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Basic Gates and

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CHAPTER 2

Basic Gates

This module gives a quick review of Basic Logic Gates, Integrated Circuits along with its working and
truth table. Introduction to combinational circuits will be given and circuits will be designed.
Simplification methods such as k-map and Quine-mcClusky method is all discussed in detail. This
module will also introduce to Hardware Description Language(HDL)

1
SECTION 1

Introduction to Logic Gates

Figure 2.1 Quick review of all logic gates

Above figure shows symbolic representation of logic gates used in circuit design. Further details about each gate is discussed in further section

✴ A logic gate is a digital circuit with 1 or more input voltages but only 1
output voltage.
✴ Logic gates are the fundamental building blocks of digital systems.
✴ By connecting the different gates in different ways, we can build circuits
that perform arithmetic and other functions associated with the human
brain.
✴ Because the circuits simulate mental processes, gates are often called
logic circuits. NOT, OR & AND gates are the basic types of gates.
✴ The inter-connection of gates to perform a variety of logical operations is
called logic design.
✴ The operation of a logic gate can be easily understood with the help of
" t r u t h t a b l e " .


2
THE BASIC GATES - NOT, OR, AND EXAMPLE 2.1

N O T G A T E ( I N V E R T E R )
 A 1-kHz square wave drives pin 1 of a 7404 (see Fig. 2.3). What does the
• It is a gate with only 1 input and a complemented output (Figure 2.2).
 voltage waveform at pin 2 look like?
• 7 4 0 4 I C i s c a l l e d a h e x i n v e r t e r ( F i g u r e 2 . 3 ) .

• 7 4 0 4 I C c o n t a i n s s i x i n v e r t e r s .

• After applying +5 V dc (the supply voltage for all TTL devices) to pin
14 and grounding pin 7, you can connect any inverters to other TTL
d e v i c e s .

• For example, if you only need one inverter, you can connect an input EXAMPLE 2.2
signal to pin 1 and take the output signal from pin 2.
If a 500-Hz square wave drives pin 3 of a 7404(see Fig. 2.2), what is the
waveform on pin 4?

Figure 2.3 Timing Diagram of (a) example 2.1 (b) example 2.2

Figure 2.2 Pin Diagram of 7404 IC(Hex Inverter)

3
OR GATE EXAMPLE 2.3

• It is a gate with 2 or more inputs. Work out the truth table for below figure

• The output is HIGH when any input is HIGH (Figure 2.4).

• In Boolean equation form, we write: Y = A + B.
• The '+' sign represents logic operation OR.


7432 IC

• 7432 IC is a TTL quad 2-input OR gate (Figure 2.7).

• 7432 contains four 2-input OR gates inside a 14-pin DIP.

• After connecting a supply voltage of +5 V to pin 14 and a ground to pin
7, you can connect one or more of the OR gates to other TTL devices.

Figure 2.4 Input OR Gate

a) 2-Input OR Gate Symbol

b) Truth Table

AND GATE

• It is a gate with 2 or more inputs (Figure 2.10).


• The output is HIGH only when all inputs are HIGH.

• In Boolean equation form, we write: Y = A.B

• The '.' sign here represents logic operation AND.

7 4 0 8

• 7408 IC is a TTL quad 2-input AND gate (Figure 2.8).

• 7408 contains four 2-input AND gates inside a 14-pin DIP.

Figure 2.5 Pinout diagram of Figure 2.6 Timing Diagram of
7432 2-input OR gate

4
• After connecting a supply voltage of +5 V to pin 14 and a ground to pin EXAMPLE 2.4
7, you can connect one or more of the AND gates to other TTL devices.
Work out the truth table for below figure

Figure 2.9 a)
2-Input AND
Gate Symbol b)
Truth Table

Figure 2.8 Pin out diagram of 7408 IC

EXAMPLE 2.5

What is the Boolean equation for the logic circuit given below

Figure 2.7 Timing diagram of 2-input AND gate

5
 UNIVERSAL LOGIC GATES - NOR, NAND

• Any logic function can be realized using only NAND gates or only
NOR gates. For this reason, AND & NOR gates are called universal
g a t e s .

N O R G A T E

• This represents an OR gate followed by an inverter (fig 2.10a)
EXAMPLE 2.6
• 7402 IC is a quad 2-input NOR gate in a 14-pin DIP (fig 2.10 d)
Write the Boolean equation for below figure
• Bubbles on the inputs are a reminder of inversion that takes place
before AND operation

• fFg 2.10c represents the IEEE symbol of NOR gate

• Fig 2.12 represents the truth table of NOR gate

EXAMPLE 2.7

EXAMPLE 2.7

What is the logic circuit whose Boolean equation is Y=A’BC+AB’C

Figure 2.10 NOR logic gate basics

Figure a) Intermediate, (b) Final logic circuit of Example 2.7

6
 Note: NOR gate is equivalent to Bubbled OR gate. Click below image
for further information.

Figure 2.12 Truth table of NOR gate

De Morgan's First Theorem

• It says the complement of a sum equals the product of the complements. Video Tutorial

Universality of NOR Gate

Movie 2.1 Video Tutorial on NOR gate Universality
• Realization of other gates using only NAND gates (Figure 2.11).

Click on above video to know more about NOR gate

EXAMPLE 2.8
Figure 2.11 Universality of NOR gate (a)NOT from NOR
A 7402 is a quad 2-input NOR gate. This TTL IC has four 2-input NOR
(b)OR from NOR (c)AND from NOR
gates in a 14-pin DIP. What is the Boolean equation for the output of
below figure (a)?

7
 EXAMPLE 2.10

What is the truth table for the NOR-NOR circuit of above figure?

Table 2.1 Sample Truth Table

EXAMPLE 2.9

Prove that below fig. c is logically equivalent to Fig. a.

EXAMPLE 2.11

Convert Table 2.1 into a

timing diagram.

8
NAND GATE

• This represents an AND gate followed by an inverter (fig 2.13a) De Morgan's Second Theorem

• 7400 is a quad 2-input NAND gate in a 14-pin DIP(fig 2.13d) • It says the complement of a product equals the sum of the complements.

• Bubbles on the inputs are a reminder of inversion that takes place Universality of NAND Gate
before OR operation
Interactive 2.1 Image showing equivalence between NAND and
• fig 2.13c represents the IEEE symbol of NAND gate
Bubbled OR gate

Bubble OR gate

Figure 2.15 Realization of basic gates using

NAND gates

NAND GATE
A & B input are passed to
NAND gate which
produces (AB)`

Figure 2.13 NAND Gate Logic

Figure 2.14
Truth Table of 1 2
NAND Gate

9
 Review 2.1 Review questions on Logic Gates
Movie 2.2 Video Lecture on universality of NAND gate
Question 1 of 3
The output will be a LOW for any case when one or more
inputs are zero in a(n)

A. OR gate

B. NOT gate

C. AND gate

D. NAND gate

Click above video for more explanation on NAND gate Check Answer

10
 SECTION 2

Positive and Negative Logic

POSITIVE AND NEGATIVE LOGIC

We know that, in binary logic, two voltage levels represent the two
binary digits, 1 and 0.
In positive logic, the lower voltage level is assigned binary 0 & higher
voltage level is assigned binary 1
In positive logic representation Bit 1 represents Logic high and Bit 0
represent a Logic low as shown in
High is represented by +5 Volts and low is represented by -5 Volts or 0
Volts.HIGH=1 LOW=0

11
 

• In negative logic, the lower voltage level is assigned binary 1 & higher
voltage level is assigned binary 0. So, we can convert table 2.3 to table
2.4. HIGH=0 and LOW=1

Positive and Negative Logic

We know that, in binary logic, two voltage levels represent the two binary
digits, 1 and 0.
Table 2.4 Negative Logic Truth Table

Gates in Positive Logic are Equivalent to Gates in Negative logic. Click

on the below link for further informatio

Gallery 2.1 Images on equivalence of positive logic

gates with negative logic gates
Table 2.3 Sample Truth Table

In positive logic, the lower voltage level is assigned binary 0 & higher
voltage level is assigned binary 1. So, we can convert table 2.3 to table
2.2.

Equivalence of Gates based on Positive and Negative Logic

Table 2.2 Truth table in positive logic

12
ASSERTION LEVEL

• To activate, if an input line has a bubble on it, you assert the input by
making it low. If there is no bubble, you assert the input by making it
high. This is called as Assertion level.

• It means that you draw chips with the kind of input that causes
something to happen, or with the kind of output that indicates
something has happened.

• If a low input signal turns on a chip, you show a bubble on that input

• If a low output is a sign of chip action, you draw a bubble on that

output. Once you get used to assertion-level logic, you may prefer
d r a w i n g l o g i c c i r c u i t s t h i s w a y .


What happens when the inputs are asserted?



• A n i n p u t i s a s s e r t e d w h e n i t i s a c t i v e .

• This means it may be low or high, depending on whether it is an
a c t i v e - l o w o r a c t i v e - h i g h i n p u t .

• For instance, given a positive AND gate, all inputs must be asserted
( h i g h ) t o g e t a h i g h o u t p u t .

• As another example, the STROBE input of a TTL multiplexer must be
a s s e r t e d ( l o w ) t o t u r n o n t h e m u l t i p l e x e r .

• In short, you can equate the word assert with activate.

• You assert, or activate, the inputs of a gate or device to get something
to happen.

13
SECTION 3

Combinational Logic Circuits

Figure 2.16 Block Diagram

Combinational circuit is a circuit in which we combine the different
gates in the circuit, for example encoder, decoder, multiplexer and
demultiplexer.
Some of the characteristics of combinational circuits are following
The combinational circuit do not use any memory. The previous state
of input does not have any effect on the present state of the circuit.
A combinational circuit can have an n number of inputs and m number
of outputs.

The output of combinational circuit at any instant of time,depends

only on the levels present at input terminals.

14
Types of Combinational Circuits

Figure 2.17 ANDing two variables and their complements

Table 2.6 Fundamental Products for two inputs

SUM OF PRODUCTS METHOD

The fundamental products are also called minterms (Figure: 2.17 &
2.18).
Figure 2.18 Fundamental Products for three inputs
Product-terms are represented as follows (Table: 2.6):

➡ A'B → m0 Table 2.5 ANDing three variables and their

➡ A'B → m1 complements

➡ AB' → m2

➡ AB → m3

• For 'n' variable, there can be 2n number of minterms. Example:

➡ For 2 variable, there are 4 minterms.

➡ For 3 variable, there are 8 minterms (Table: 2.5).

15
S U M O F P R O D U C T S E Q U A T I O N
 • Y=F(A,B,C) means Y is a function of 3 boolean variables A,B and C.
• Sum-of-products equation means the logical sum of fundamental
p r o d u c t s t h a t p r o d u c e o u t p u t 1 s i n t h e t r u t h t a b l e .
 • To get the sum of products equation, we have to OR the minterms.
• Each product-term is called minterm. Y = F ( A , B , C ) = A ' B C + A B ' C + A B C ' + A B C

For example, A.B, A.B.C, A.B.C.D etc Y=F(A,B,C)=m3+m5+m6+m7 where minterm is denoted by mi
Y=F(A,B,C)=Σm(3,5,6,7) where ∑ denotes summation i.e. OR
• Here, we have to locate output 1 in the truth table and write down the operation
minterm.
• This kind of representation of a truth table is also known as canonical
sum form.

• The corresponding logic circuit is either click

→ AND-OR circuit or NAND-NAND Circuit

→ NAND-NAND circuit.

Figure 2.19
Table 2.7 Fundamental Products AND-OR
solution

• Consider truth table: Table 2.7

✤First output 1 appears for an input A=0, B=1 and C=1. The
corresponding minterm is A'BC.

✤Second output 1 appears for A=1, B=0 and C=1. The corresponding
minterm is AB'C.

✤Third output 1 appears for A=1, B=1 and C=0. The corresponding
minterm is ABC’.

✤Fourth output 1 appears for A=1, B=1 and C=1. The corresponding
minterm is ABC.

16
 Figure 2.20 EXAMPLE 2.13
NAND-NAND
solution for the Simplify the following Boolean equation and describe the logic circuit.
above Sum of Y=A’B’C’ +A’BC’ +AB’C’ +ABC’
products
expression

EXAMPLE 2.12

Suppose a three-valuable truth table has a high output for these input
conditions: 000, 010, 100, and 110. What is the sum-of-products circuit? TRUTH TABLE TO Karnaugh Map (KMAP)

A Karnaugh map (K-map) is a pictorial method used to minimize

Boolean expressions without having to use Boolean algebra theorems and
equation manipulations.

A K-map can be thought of as a special version of a truth table

In Table 2.8

i) The first output 1 appears for A=1 and B=0. The minterm for this input
condition is AB'.

➡ enter 1 into cell of kmap identified by row A and column B'.

ii) Similarly, enter 1 into cell identified by row A and column B.

iii) Finally, enter 0s in the remaining cells.

17
 Table 2.8 Figure 2.22 K-Map for the above logic equation
Sample Truth
Table

Figure 2.21 Constructing a K map

Four Variable K-Maps
• Kmap for logic equation Y=F(A,B,C,D)=∑m(2,6,7,14) is shown in
Figure 2.23

• Table 3.7 gives truth table for given logic equation.

Three-Variable K-Maps
Figure 2.23 4 variable K-Map for the
• Table 2.9 gives truth table for logic equation Y=F(A,B,C)=∑m(2,6,7) above logic equation
and k-map is shown in fig 2.22

Table 2.9 Truth table for above equation

18
Table 2.10 Truth Table for the 4 variable
expression given above • Entered variable map for Table: 2.11 is constructed as follows.

Table 2.11 Truth table for a sample equation

ENTERED VARIABLE MAP (EVM)

•Entered variable map is an alternative to Kmap.
•Here, one of the input variables is placed as output variable inside the
kmap. This is done separately noting how an input variable is related to
the output variable.
Figure 2.24 Entered Variable Map for the above truth table
1) For AB=00, we find Y=0 and is not dependent on C (Figure: 2.24
(a)).
2) For AB=01, we find Y is complement of C thus we can write Y=C' .

•This reduces the kmap size by 1 degree. 3) For AB=10, Y=0.

4) For AB=11, Y=1.

•This technique is particularly useful for mapping problems with more
t h a n 4 i n p u t v a r i a b l e s .
 Figure 2.24(b) shows the EVM after second level of simplification
.Similarly any variable can be taken as a Entered variable map as shown
in figure 2.24(c) where ‘a’ is taken EVM.
•

19
PAIRS, QUADS AND OCTETS

• Pair means two horizontally or vertically adjacent 1s on a Kmap. It
eliminages 1 variable and its complement

KARNAUGH SIMPLIFICATIONS

In given kmap (Figure 2.25), we have


• Quad means four horizontal, vertical, or rectangular 1s on a Kmap. It
eliminates 2 variables and their complements
1) The pair which represents A’B’D.

2) The lower quad which represents AC’.

3) The quad on the right which represents CD’.
• By ORing these simplified products, we get the Boolean equation
corresponding to the entire Kmap: Y=A’B’D+AC’+CD’

Figure 2.25 Encircling pairs and quads

• Octet means eight adjacent 1s in a 2 x 4 shape on a Kmap.

• It eliminates three variables and their complements . For ex, A, C,

D,A’, D` & C’ are eliminated.

20
Overlapping Groups Rolling the Map

• Overlapping groups means using the same 1(minterm) more than once
when grouping the 1s of a Kmap.

Figure 2.27 Rolling the Map

• Visualize picking up the Kmap and rolling it so that the left side
touches the right side.
Figure 2.26 Overlapping groups • If you are visualizing correctly, you will realize the two pairs actually
form a quad.

• In Figure 2.26 (a) ,you can find an octet and a pair grouping. The
simplified equation for the overlapping groups is Y=A+BC’D
• In Figure 2.26(b) you can find an octet and a single 1(minterm).The
simplified equation for the groups is Y=A+A`BC’D which requires
more no. of gates compared to the above expression. Therefore , it is
suggested to opt for the bigger grouping. i.e., grouping done as in fig
2.26(b) is not recommended
• So, always overlap groups if possible. That is, use the 1s more than
once to get the largest groups you can.
• In figure 2.27(a) two pairs are being identified which would be wrong.
Instead, we choose figure 2.27(b) where the quad has the equation
Y=BD’.
• Thus, 1s on the edges of a Kmap can be grouped with ls on opposite
edges.
Rolling and Overlapping
• In Figure. 2.29(b), rolling as well as overlapping is being applied; thus
the Boolean equation is Y= C’+BD’

21
 KMAP METHOD FOR SIMPLIFYING BOOLEAN EQUATIONS

1. Enter a 1 on map for each fundamental product that produces a 1

output in truth table. Enter 0s elsewhere.

2. Encircle the octets, quads and pairs.

3. If any isolated 1s remain, encircle each.

4. Eliminate any redundant group.

Figure 2.29 Rolling and Overlapping
5. Write boolean equation by ORing the products corresponding to the
encircled group.
Eliminating Redundant Groups
EVM METHOD FOR SIMPLIFYING BOOLEAN EQUATIONS
•Redundant group means a group of 1s on a kmap that are all part of
Here, we make use of following identities:
o t h e r g r o u p s .

• Yo u c a n e l i m i n a t e a n y r e d u n d a n t g r o u p .

•After you have finished encircling groups, eliminate any redundant
i) 1=1+C'
group. This is a group whose 1s are already used by other groups.
ii)1=1+C

iii) 1=C+C'

Figure 2.30 Simplification of entered variable

map

Case (i): Example for using 1=1+C'

• As shown in Figure. 2.30(a) C' is grouped with 1 to get a larger group

as 1 can be written as 1=1+C'. Next, the product-term representing each
Figure 2.28 Identification and elimination of redundant groups
group is obtained by including map entered variable in the group as an
additional ANDed term.

• Here, Group-1 gives B.(C')=BC' and Group-2 gives AB.(1)=AB Thus,

Y=BC'+ AB.

22
Case (ii): Example for using 1=1+C DON’T CARE CONDITION (X)
• As shown in Figure. 2.30(B), A is grouped with 1 to get a larger group • This is an input-output condition that never occurs during normal
as 1 can be written as 1=1+A. • Here, operation.
Group-1 gives B.(A)=AB and Group-2 gives BC'.(1)=BC' Thus, Y=BC'+ • Since the condition never occurs, you can use an ‘X’ on the Kmap
AB. (Table: 3.8).
Case (iii): Example for using 1=C+C' • This X can be a 0 or a 1, whichever you prefer (Table 2.12)
• As shown in Figure. 2.30(c) EVM

→ has only two product-terms and

→ doesn't need a separate coverage of 1.

• This is because one can write 1=C+C' and C is included in one group
while C' in other. • Here,

Group-1 gives B.(C')=BC' and Group-2 gives A.(C)=AC Thus, Y =AC+

BC'.

Example 2.14

What is the simplified Boolean equation for the following logic equation
expressed by minterms? Y=F(A,B,C,D)=Σm(7,9, 10, 11, 12, 13, 14, 15)

Table 2.12 Truth Table with Dont care conditions

23
How to use Don’t Care conditions(X) in KMAP Click on below image gallery for some of wrong grouping examples in K MAP

simplification

Gallery 2.2 Examples of K-Map invalid groupings

Figure 2.31 Don’t Care conditions in Kmap

1)Given the truth table, draw a kmap with 0s, 1s and don't cares.

2) Encircle the actual 1s on the kmap in the largest groups you can find by
t r e a t i n g t h e d o n ' t c a r e s a s 1 s .

3) After the actual 1s have been included in groups, discard the remaining
don't cares by visualizing them as 0s.
Other Study Material
EXAMPLE 2.15 Web Link for online k-map calculator
Give the simplest logic circuit for following logic equation where d
represents don't-care condition for following locations.
F(A,B,C,D)=Σm(7)+d(10,11,12,13,14,15)

24
SECTION 4

Hardware Description Language

HDL (HARDWARE DESCRIPTION LANGUAGE) is a specialized
computer language used to describe the structure and behavior of
electronic circuits, and most commonly, digital logic circuits.
✴A hardware description language enables a precise, formal description
of an electronic circuit that allows for the automated analysis and
simulation of an electronic circuit.
✴ To describe large complex design requiring hundreds of logic gates in
a convenient manner.
✴ To use software test-bench to detect functional error and correct it
(called simulation)
✴ To get hardware implementation details (called synthesis).

25
 

Currently, there are 2 widely used HDLs:
• The symbol '//' is used
- Verilog
→ to put comments &
- VHDL (Very high speed integrated circuit Hardware Description
→ to improve readability for a human.
Language).

In this section ,we will be discussing on Verilog Code • The module-body describes the logic within the black box which
→ acts on the inputs a, b, c and
VERILOG HDL
→ generates output x, y.
• This describes a digital system as a set of modules.

• In a digital circuit, there are a set of inputs and a set of outputs which • Semicolon ';' is used to indicate end the statement.
are called as ports. Writing module body

There are 3 different models of writing module body in Verilog HDL.

They are:

1) Structural model

2) Data flow modeling &

3) Behavioral modeling.

Figure 2.32 Verilog code for a sample circuit
Figure 2.32 shows Input/output definition in Verilog HDL for logic
circuit described within black-box testckt
Each model has its own advantage and suited for certain kind of design.
Sample Verilog Code
1. Write a verilog for following gate using Structural Model

Describing input/output

• module and endmodule are the keywords.

• Module describes a design-entity with a name or identifier selected by
user (here, testckt) followed by input-output port-list.

26
 module or_gate(A,B,Y); PREPARATION OF TEST BENCH

input A,B; output Y; • Here, we write a verilog code for simulating a OR gate
and g1(Y,A,B);
• .The test bench creates an input in the form of a timing waveform and
endmodule passes this to OR gate module through a function or procedural call
2. Write a verilog for following circuit using Structural Model
• .To generate timing waveform, we use time delay available in the
//defines two input port //define one output port //represents OR gate form of #n where n=number in decimal that gives delay in
nanoseconds.

• Input values to a variable can be provided through syntax m'tn where

m=number of digits, t=type of number and n=value to be provided

• The keyword 'reg' is used to hold value of a data object in a

procedural assignment.

module fig2_24(A,B,C,D,Y) • The keyword 'initial' ensures sequential execution of codes following
it, but once.
input A,B,C,D;

output Y;

• The keyword 'always' is used for sequential execution but for infinite
wire op1,op2;
time.
and g1(op1,A,B); and g2(op2,C,D); or g3(Y,op1,op2);
Below figure shows simulation of 2 input OR gate with 20ns gate
endmodule delay

//g1 represents upper AND gate //g2 represents lower AND gate

//g3 represents the OR gate

//internal connections

27
28
SECTION 5

Product of Sums method

Figure 2.33 Product of sum derivation

Canonical Expression

A boolean expression consisting entirely either of minterm or maxterm is Following is a canonical expression consisting of minterms
called canonical expression. Different Forms of Canonical Expression
XY + X’Y’ and
Sum of Products (SOP)
Following is a canonical expression consisting of maxterm
Product of Sums (POS)
(X+Y) . (X’ + Y’)
If we have two variables X and Y then,

29
Product-of-sums equation means the logical product of those fundamental
s u m s t h a t p r o d u c e o u t p u t 0 s i n t h e t r u t h t a b l e .

• Each sum-term is called maxterm.

For example,

(A+B), (A+B+C), (A+B+C+D) etc

• Here, we have to locate output 0 in the truth table and write down the Table 2.13 Fundamental sums for three inputs
maxterm

Figure 2.34 NOR-NOR CIRCUIT Figure 2.35 AND-OR CIRCUIT

• Consider Table 2.13,

1.First output 0 appears for an input A=0, B=0 and C=0. The
corresponding maxterm is A+B+C.

2.Second output 0 appears for A=0, B=1 and C=1. The

corresponding maxterm is A+B’+C’.

3.Third output 0 appears for A=1, B=1 and C=0. The corresponding
maxterm is A’+B’+C.

• This kind of representation of a truth table is also known as canonical

• Y=F(A,B,C) means Y is a function of 3 boolean variables A,B and C.

product form.
• To get the product-of-sums equation, we have to AND the maxterms.
• The logic circuit for Y is shown in Figure: 2.34 and 2.35
Y=F(A,B,C)=(A+B+C).(A+B'+C').(A'+B'+C)

Y=F(A,B,C)=M0.M3.M6 where maxterm is denoted by Mi. • The corresponding logic circuit is

Y=F(A,B,C)=∏M(0,3,6) where ∏ denotes product, i.e. AND → OR-AND circuit (FIGURE 2.35)or

operation → NOR-NOR circuit (Figure 2.34).

30
STEPS TO CONVERT BETWEEN STANDARD SOP & POS LIMITATIONS (OR DRAWBACKS) OF KMAP
FORM
1) The map method depends on the user's ability to identify patterns that
1) Identify complementary locations. gives largest size.

2) Changing minterm to maxterm or reverse. 2) The map method becomes difficult to adapt for simplification of 5 or
more variables.
3) Changing summation by product or reverse.
PRODUCT-Of-SUMS SIMPLIFICATION
• This is known as conversion between canonical forms. For example,
• Procedure to simplify boolean equation in product-of-sums form:

If Y=F(A,B,C)=A'BC'+AB'C+A'B'C' then Y'=F’(A,B,C)=(A+B'+C).
(A'+B+C').(A+B+C) 1) Convert the truth table into a Kmap.

2) Complement the Kmap i.e. interchange 0 and 1.

If Y=F(A,B,C)=∏M(0,3,6) then Y’=F’(A,B,C)=Σm(1,2,4,5,7) 3) Group the 1s, write the sum-of-products equation for Y’.

4) Using duality theorem, convert the sum-of-products equation to
EXAMPLE 2.14
equivalent product-of-sums equation.
Suppose a truth table has a low output for the first three input conditions:
000, 001, and 010. If all other outputs are high, what is the EXAMPLE 2.15
product-of-sums circuit? • Consider truth table: Table 2.14

Figure 2.36
using only NOR
gate

Table 2.14 Truth table for a logical

expression
31
1 ) Convert the truth table into a Kmap as shown in 2.37.
 EXAMPLE 2.16
2) Complement the Kmap i.e. interchange 0 and 1 as shown in Fig.
Show the sum-of-products and product-of-sums circuits for the Kmap
2.37(b).

3) After grouping the 1s, we have the sum-of-products equation Y’.

Y’=A’B+AB’C’

4) Using duality theorem, the sum-of-products equation is converted to

equivalent product-of- sums equation as follows:

Y=(A+B’).(A’+B+C)

Figure 2.37 Deriving the product-of-sums circuit

• The logic circuit for Y is shown in Figure: 2.38 


EXAMPLE 2.17

Figure 2.38 Logic circuit for Y Give simplest POS form of Kmap shown in below figure by grouping
zeros.

32
Review 2.2 Logic Gates

Question 1 of 6
The output of an AND gate with
three inputs, A, B, and C, is HIGH
when ________.

A. A = 1, B = 1, C = 0

B. A = 0, B = 0, C = 0

C. A = 1, B = 1, C = 1

D. A = 1, B = 0, C = 1

Check Answer

33
SECTION 6

Static and Dynamic Hazard

A static hazard is the situation where, when one input variable changes, Static Hazards
the output changes momentarily before stabilising to the correct value.
• Static-1 Hazard: the output is currently 1 and after the inputs change,
There are 2 types of Hazards, namely
the output momentarily changes to 0,1 before settling on 1.
- Static Hazards • Static-0 Hazard: the output is currently 0 and after the inputs changes,
- Dynamic Hazards the output momentarily changes to 1,0 before settling on to 0

34
In properly formed two-level AND-OR logic based on a Sum Of Products
expression, there will be no static-0 hazards. Conversely, there will be no
static-1 hazards in an OR-AND implementation of a Product Of Sums
expression.

Static-0 hazard
In a combinational circuit, if output goes momentarily 1 when it should
r e m a i n a 0 , t h e h a z a r d i s k n o w n a s s t a t i c - 0 h a z a r d

• Static-0 hazard occurs when
→ Y=AA' type of situation appears in a logic circuit.
→ ‘A‘ makes a transition 0 1.
• Here is how static-0 hazard occurs:
An AA' condition should always generate 0 at the output, i.e. static-0.
But the NOT gate output takes finite time to become 0 following 0 1
transition of A.
Thus for AND gate, there are 2 ones appearing at its input for the
small duration, resulting a 1 at its output.
The width of this zero is in nanosecond order and is called a glitch.
Figure 2.40 Static-0 hazard Figure 2.41 Hazard free circuit
C o n s i d e r K m a p s h o w n i n F i g . 2 . 4 0

• Minimally, the Kmap is represented by output Y=(B+C)(A+C')

• T h e c o r r e s p o n d i n g c i r c u i t i s s h o w n i n F i g . 2 . 4 0 ( b )

• A s s u m e , i n p u t A = 0 , B = 0 .

• When C makes a transition 0-->1, there will be static-0 hazard occurring
at output.
Example for circuit with hazard cover
• Consider another grouping for the Kmap in Fig.2.41.

• This includes one additional term (A+ B) and now output
Y=(B+C)(A+C')(A+B)

• T h e c o r r e s p o n d i n g c i r c u i t i s s h o w n i n F i g . 2 . 4 1

Example for circuit with static-0 hazard
• T h i s c i r c u i t i s h a z a r d f r e e .

• • This circuit requires more hardware than minimal representation.

• The additional term (A + B) ensures Y=0 for A=0, B=0.

• A 0--> 1 transition at C does not affect output.

Figure 2.39 Static-0 Hazard

35
STATIC -1 HAZARD DYNAMIC H A Z A R D

• Dynamic hazard occurs when circuit output makes multiple transitions
A static 1 hazard may occur in a two level sum of products (SOP)
before it settles to a final value while the logic equation asks for only one
implementation. Consider an AND-OR SOP implementation with the
following characteristics: t r a n s i t i o n .

• When this hazard occurs, an output transition designed as
1 For the current input conditions only one AND gate has a 1--> 0 may give 1-->-->1-->0
logic '1' output. This causes the output of the OR to be '1'.
0-->1 may give 0-->1-->0-->1
2 A single input variable changes which "simultaneously" 

causes the first AND gate output to a logic '0' and causes another AND • The output of logic equation in dynamic hazard degenerates into
gate output to go to a logic '1'.
Y = A + A ' . A o r Y = ( A + A ' ) .

If the first AND gate changes before the second, the OR will have two '0' • A kind of relations for certain combinations of the other input variables.

inputs for a short time and an output glitch will occur. • Dynamic hazard occur in multilevel circuits having implicit static-1
and/or static-0 hazards.
For example, consider the function f(A,B,C) = A'B+AC implemented in
this minimized SOP form. • By providing covers to each one of them, dynamic hazard can be
prevented.
In this case R=A'B and S=AC so f(A,B,C)=R+S.

When the inputs change from ABC=111 to ABC=011, a glitch as

described above can occur. If it does not occur on this transition, it will
occur on the reverse transition from ABC=011 to ABC=111.

36
SECTION 7

Quine McClusky Method

Figure 2.42 Quine McClusky method for simplification

SIMPLIFICATION BY QUINE MCCLUSKY METHOD

The Quine–McCluskey algorithm (or the method of prime implicants) It is functionally identical to Karnaugh mapping, but the tabular form
is a method used for minimization of Boolean functions. makes it more efficient for use in computer algorithms, and it also gives
a deterministic way to check that the minimal form of a Boolean function
It is sometimes referred to as the tabulation method. has been reached.

37
The method involves two steps: iii) This means corresponding variable is not required to represent those
members.
1 Finding all prime implicants of the function.
Stage 3
2 Use those prime implicants in a prime implicant chart to find
the essential prime implicants of the function, as well as other prime i) We combine members of different groups of stage 2 in a similar way.

implicants that are necessary to cover the function. ii) Now it will have two '-' elements in each combination.

iii) This means each combination requires 2 literals to represent it.

PROCEDURE USED FOR DETERMINING ESSENTIAL PRIME
iv) There is no stage 4 for this problem. This completes process of
IMPLICANTS determination of prime implicants.
Consider a 4-variable simplification problem for Table 2.15 Figure 2.43
shows prime implicant determination table for the problem.

Stage 1
Table 2.15 Truth table
i) We find out all the terms that gives output 1 from truth table (Table
2 . 1 5 ) .

ii) We put them in different groups depending on how many 1 i/p variable
combinations have.

For example,
- First group has no 1 in input combination.
- Second group has only one 1.
- Third group has two 1s.
- Fourth group has three 1s.
- Fifth group has four 1s.
iii) We also write decimal equivalent of each combination to their right
for convenience.

Stage 2

i) We first try to combine first and second group of stage 1, on a member

t o m e m b e r b a s i s .

ii) The rule is to see if only one binary digit is differing between two
m e m b e r s a n d w e m a r k t h a t p o s i t i o n b y ' - ' .


38
Figure 2.43 Quine McClusky method of simplification

Table 2.16 Finding Prime Implicants

• Selection of essential prime implicants from this table is done in the

SELECTION OF PRIME IMPLICANTS
• Next step is to select essential prime implicants and remove duplication
a m o n g t h e m .

• For this, we prepare a table as shown in Table 2.16 that along the row
lists all the prime implicants and along columns lists all minterms.

• The cross-point of a row and column is ticked if the term is covered by
c o r r e s p o n d i n g p r i m e i m p l i c a n t .

• For example,
f o l l o w i n g w a y :

i) We find minimum number of prime implicants that covers all the
m i n t e r m s .

ii) We find A'B' and AB cover terms that are not covered by others and
t h e y a r e e s s e n t i a l p r i m e i m p l i c a n t s .

iii) B'C and AC among themselves cover 10,11 which are not covered
by others. So, one of them has to be included in the list of essential
prime implicants making it three. And the simplified representation of
truth table given in Table 2.16 is one of the following
Y=A'B'+B'C+AB or Y=A'B'+AC+AB
EXAMPLE 3.13
Simplification by Quine-McClusky method for below figure

Te r m s 0 a n d 1 a r e c o v e r e d b y A ' B '

Terms 2 and 3 are covered by both A'B and B'C'. Thus, the
c o r r e s p o n d i n g c r o s s - p o i n t s a r e t i c k e d .

This way we complete the table for rest of the terms.

39
To know more simplification examples using Quine Mcclusky method ,
click below weblink

40
Canonical

In mathematics and computer science, a canonical, normal, or standard form of a

mathematical object is a standard way of presenting that object as a mathematical
expression. The distinction between "canonical" and "normal" forms varies by subfield.

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Chapter 2 - Combinational Logic Circuits

Digital

Expressed as series of the digits 0 and 1, typically represented by values of a physical

quantity such as voltage or magnetic polarization.

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Chapter 2 - Introduction to Logic Gates

Function

In mathematics, a function was originally the idealization of how a varying quantity

depends on another quantity. For example, the position of a planet is a function of time.

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Chapter 2 - Introduction to Logic Gates

HAZARD

A hazard is an agent which has the potential to cause harm to a vulnerable target. The terms
"hazard" and "risk" are often used interchangeably. However, in terms of risk assessment,
they are two very distinct terms.

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Chapter 2 - Static and Dynamic Hazard

HDL

In computer engineering, a hardware description language (HDL) is a specialized computer

language used to describe the structure and behavior of electronic circuits, and most
commonly, digital logic circuits.

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Inverters

A power inverter, or inverter, is an electronic device or circuitry that changes direct current
(DC) to alternating current (AC).

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Chapter 2 - Introduction to Logic Gates

Karnaugh map

The Karnaugh map (KM or K-map) is a method of simplifying Boolean algebra expressions.
Maurice Karnaugh introduced it in 1953 as a refinement of Edward Veitch's 1952 Veitch
chart,which actually was a rediscovery of Allan Marquand's 1881 logical diagram aka
Marquand diagram but with a focus now set on its utility for switching circuits.

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Chapter 2 - Combinational Logic Circuits

Multiplexer

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line.

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Chapter 2 - Positive and Negative Logic

Quine-McClusky

The Quine–McCluskey algorithm (or the method of prime implicants) is a method used for
minimization of Boolean functions that was developed by Willard V. Quine and extended by
Edward J. McCluskey.

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Chapter 2 - Quine McClusky Method

Simulate

Simulation is the imitation of the operation of a real-world process or system. The act of
simulating something first requires that a model be developed; this model represents the
key characteristics, behaviours and functions of the selected physical or abstract system or
process.

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Chapter 2 - Introduction to Logic Gates

SOP

In boolean logic, a disjunctive normal form (DNF) is a standardisation (or normalisation) of

a logical formula which is a disjunction of conjunctive clauses; it can also be described as an
OR of ANDs, a sum of products, or (in philosophical logic) a cluster concept. As a normal
form, it is useful in automated theorem proving

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Chapter 2 - Static and Dynamic Hazard

Verilog

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to

model electronic systems. It is most commonly used in the design and verification of digital
circuits at the register-transfer level of abstraction.

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