Pyxis Quickstart PDF

A Quick Start Guide for the Pyxis
Custom Design Platform
Software Version 10.2x
© 2012-2015 Mentor Graphics Corporation

All rights reserved.
This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
document may duplicate this document in whole or in part for internal business purposes only, provided that this entire
notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable
effort to prevent the unauthorized use and distribution of the proprietary information.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make
changes in specifications and other information contained in this publication without prior notice, and the
reader should, in all cases, consult Mentor Graphics to determine whether any changes have been
made.
The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in
written agreements between Mentor Graphics and its customers. No representation or other affirmation
of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor
Graphics whatsoever.
MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.
MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR
CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)
ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,
EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at
private expense and are commercial computer software and commercial computer software
documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to
FAR 48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S.
Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in
the license agreement provided with the software, except for provisions which are contrary to applicable
mandatory federal laws.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of
Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior
written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third-
party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to
indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’
trademarks may be viewed at: www.mentor.com/trademarks.
The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of
Linus Torvalds, owner of the mark on a world-wide basis.
Mentor Graphics Corporation

8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777
Telephone: 503.685.7000
Toll-Free Telephone: 800.592.2210
Website: www.mentor.com
SupportNet: supportnet.mentor.com/
Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form

Table of Contents
Chapter 1
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IC Design Flow with the Pyxis Custom Design Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Installing the Pyxis Quick Start Example Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Using the /solutions Project Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Global Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IC Design Flow Documentation Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 2
Front-End Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Creating a Logic Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Importing HDL Files into a Logic Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Regenerating Circuit Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Validating Registered Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Creating a Schematic Sheet from a Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Creating a Simulation Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Setting Up and Performing an ADMS Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Adding Properties to a Design Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Creating a New Project and Attaching a PDK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Creating a Transistor-Level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Setting Up and Running a Transistor-Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 3
Back-End Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Creating a Layout Cell View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Setting Up Compatibility Mode For Performing Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Creating Geometries in a Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Setting Up Schematic Driven Layout (SDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Generating a Cell Layout from a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Generating a Top-Level Layout with Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Running Calibre nmDRC for Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Running Calibre nmLVS for Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Performing Parasitic Extraction for a Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Appendix A
CAD Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
How to Start Pyxis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
How to Start the Calibre, Eldo, and EZwave Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Pyxis Binary File Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Pyxis Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Pyxis Custom Design Project Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
A Quick Start Guide for the Pyxis Custom Design Platform, 10.2x 3
Table of Contents
Data Management in the Pyxis Custom Design Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Project Data Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Appendix B
Pyxis Quick Reference Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Pyxis Schematic Quick Reference Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Pyxis Layout Quick Reference Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Third-Party Information
End-User License Agreement
4 A Quick Start Guide for the Pyxis Custom Design Platform, 10.2x
List of Figures
Figure 1-1. Pyxis Custom Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 1-2. IC Front-End Design Flow (Netlist and Schematic Capture) . . . . . . . . . . . . . . . 14
Figure 1-3. IC Back-End Design Flow (Physical Layout and Verification) . . . . . . . . . . . . . 15
Figure 1-4. Automated Layout Flow with Pyxis Custom Router . . . . . . . . . . . . . . . . . . . . . 16
Figure 1-5. Opening the solutions Design Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2-1. Front-End Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2-2. Project Navigator Before Creating a New Logic Library . . . . . . . . . . . . . . . . . . 30
Figure 2-3. Enter New Logic Library Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2-4. myDesign Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 2-5. Import HDL with the Pyxis Language Interface. . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 2-6. Import HDL Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 2-7. Registered Inverter Circuit in the myDesign Library . . . . . . . . . . . . . . . . . . . . . 34
Figure 2-8. Expanded nand2 Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 2-9. Register Model from Source for Symbol Regeneration . . . . . . . . . . . . . . . . . . . 36
Figure 2-10. Symbol Layout Changes for nand2 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 2-11. nand2 Symbol Opened in Pyxis Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 2-12. Create Sheet Dialog Box for delay_block Schematic . . . . . . . . . . . . . . . . . . . . 39
Figure 2-13. Schematic for delay_block Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 2-14. Add Wires to the Test Bench Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 2-15. Add Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 2-16. Completed delay_block Test Bench Schematic . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 2-17. Set Up a New Design Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-18. Enter Simulation Mode Dialog Box Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-19. Simulation Environment in Pyxis Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 2-20. Parameter and Value Fields in the Setup Simulation Window . . . . . . . . . . . . . 49
Figure 2-21. Parameter List for sim_delay_block Test Bench . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 2-22. Analysis Selection in the Setup Simulation Window . . . . . . . . . . . . . . . . . . . . 49
Figure 2-23. Defined PULSE Sources for the tb_ain and tb_enable Signals . . . . . . . . . . . . 51
Figure 2-24. Changing DELAY_BLOCK1 Model to BLACKBOX for Simulation . . . . . . 51
Figure 2-25. Plot of tb_ain and tb_enable Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 2-26. Populate the Converter Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 2-27. Converter Values in the Setup Simulation Window . . . . . . . . . . . . . . . . . . . . . 53
Figure 2-28. Simulation Results for Verilog Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-29. Simulation Results with Schematic Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-30. Setup Simulation Window for tpHL Parameters . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 2-31. Summary of Analysis Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 2-32. Setup for the p_delay_block Sweep Parameter. . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-33. Annotated Schematic for sim_delay_block Test Bench . . . . . . . . . . . . . . . . . . 60
Figure 2-34. Sweep Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 2-35. Plots of TPHL and TPLH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
List of Figures
Figure 2-36. Selecting the generic13 PDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 2-37. PDK in the Project Navigator Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2-38. Checking the generic13 PDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2-39. Attaching a PDK to myProject . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 2-40. Attaching External and Logic Libraries to myProject . . . . . . . . . . . . . . . . . . . 66
Figure 2-41. Adding myDesign and Standard Libraries to myProject. . . . . . . . . . . . . . . . . . 66
Figure 2-42. Adding the myChip Design Library to myProject . . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-43. Copying Cells from the myDesign Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2-44. Pasting Cells into the myChip Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2-45. Creating a New Schematic View for inv1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 2-46. Device Symbol List for generic13 PDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 2-47. Editing Object Properties for nmos Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 2-48. inv1 Transistor-Level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 2-49. Adding Net Name for Implicit vdd_imp Power Pin . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-50. Creating Implicit Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-51. nand2 Transistor-Level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 2-52. Selecting delay_block from Open Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 2-53. Adding Implicit Nets to delay_block Schematic . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 2-54. Entering the Implicit Pin Names in Project Registration Options . . . . . . . . . . 77
Figure 2-55. Registration Preview Window for myProject . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 2-56. Circuit Hierarchy for DELAY_BLOCK1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 2-57. Setting Up Sources for vdd_imp and vss_imp . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-58. Adding Implicit Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-59. Importing Eldo Simulation Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 2-60. Selecting the Typical Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 2-61. Reviewing a Scenario Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 2-62. Transistor-Level Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 3-1. Back-End Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 3-2. Opening the myChip Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 3-3. Creating a New Category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 3-4. Creating a New Layout Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 3-5. Pyxis Layout Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 3-6. Setup Preferences Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 3-7. Setting Up Display Options for Compatibility Mode . . . . . . . . . . . . . . . . . . . . . 89
Figure 3-8. Setting Up Editing Options for Compatibility Mode . . . . . . . . . . . . . . . . . . . . . 89
Figure 3-9. Setting Up Behavior Options for Compatibility Mode . . . . . . . . . . . . . . . . . . . . 90
Figure 3-10. Setting Up Selection Options for Compatibility Mode. . . . . . . . . . . . . . . . . . . 90
Figure 3-11. Starting the logicCell Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 3-12. Expanding a Palette. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 3-13. Drawing P-Well and N-Well Areas for logicCell Template. . . . . . . . . . . . . . . 95
Figure 3-14. Placing Power Rails in the logicCell Template. . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 3-15. Selecting the Easy Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 3-16. Selecting N-well contacts for N-well Region of logicCell Template . . . . . . . . 97
Figure 3-17. Completed logicCell Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 3-18. Finalizing the logicCell Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
List of Figures
Figure 3-19. Setting up SDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 3-20. Setting Up the Pyxis Layout Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-21. Selecting the logicCell Template for Placement in inv1 Layout . . . . . . . . . . . 104
Figure 3-22. Flatten Object Prompt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 3-23. DLA Palette. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 3-24. Placing Devices in the inv1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 3-25. Placing the pmos Device in inv1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 3-26. Placing Ports in the inv1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 3-27. All Ports for inv1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-28. Editing Port Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 3-29. Stretching vdd_imp and vss_imp Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 3-30. IRoute Prompt in Pyxis Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 3-31. Routing the Ain Signal with IRoute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 3-32. Accessing Options While Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-33. Placing Gate Poly Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-34. Completing the Route to pmos Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-35. Completed inv1 Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-36. Adding Text to Ports for LVS Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-37. Browsing for Cells in Pyxis Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-38. Placing Cells in the delay_block Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-39. Configuring the Layer Palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 3-40. Simplified View of delay_block Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 3-41. Abutting Cells in the delay_block Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-42. Removing Connections in the nand2_mgc Cell . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 3-43. Adding Connections in the nand2_mgc Cell . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 3-44. Final Layout for the delay_block Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 3-45. Running Calibre nmDRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 3-46. Calibre Interactive - nmDRC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 3-47. Viewing DRC Summary Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 3-48. Reviewing DRC Results with Calibre RVE . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 3-49. Setting up Selections for Calibre nmDRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 3-50. Simple View of Check Selection Recipe Editor Window . . . . . . . . . . . . . . . . 128
Figure 3-51. Running Calibre nmLVS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 3-52. Calibre Interactive - nmLVS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 3-53. Viewing LVS Report File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 3-54. Reviewing LVS Results with Calibre RVE . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 3-55. Creating an Error in the nand2_mgc Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 3-56. Reviewing LVS the Report File for Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 3-57. Finding Discrepancies in the nand2_mgc Layout. . . . . . . . . . . . . . . . . . . . . . . 134
Figure 3-58. Identifying LVS Errors in the Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 3-59. Viewing the Differences Between the Layout and Schematic . . . . . . . . . . . . . 135
Figure 3-60. Highlighting Error in nand2_mgc Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 3-61. Running Calibre PEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 3-62. Setting up a Calibre PEX Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 3-63. Setting up Inputs for Calibre PEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
List of Figures
Figure 3-64. Extracted Transistor-Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 3-65. Reviewing Detailed Parasitics on the Zout Net . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure A-1. Project Data Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure A-2. Pyxis Project File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
List of Figures
List of Tables
Table 1-1. Quick Start Guide Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 1-2. Files in the Pyxis_qs_ekit Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 1-3. Contents in the /qsg_solutions Sub-directory . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-4. IC Design Flow Tool Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2-1. Parameter Value Pairs for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 2-2. Parameter Values for PULSE Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 2-3. Parameters and Values for tpHL Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table A-1. Command-line Invocation for Pyxis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table A-2. Command-line Invocation for non-Pyxis Tools . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 1
Before You Begin
The purpose of this document and the example design data is to introduce you to the Pyxis
Custom Design Platform and demonstrate how to perform IC design.
The procedures quickly introduce some of the basic functions of the Pyxis design tools. The
topics in this document are organized as follows:
• Front-end Design Topics (Schematic and Netlist) — includes information on

commonly performed tasks such as schematic tool invocation, schematic capture
(including placing, moving, and connecting devices), setting up and running analog and
mixed-signal simulations, and viewing results.
• Back-end Design Topics (Physical Layout and Verification) — includes information
on commonly performed tasks such as layout tool invocation, layout capture (including
placing, moving, copying, connecting, and modifying shapes and devices), routing, and
physical verification (DRC/LVS).
Short appendixes introduce CAD topics relevant to this manual, including software installation,
environment setup, tool invocation, project organization, and data management.
Tip: In the PDF version of this document, to return back to a previous page press the Alt
+ Left Arrow keys.
Table 1-1 shows the organization of this manual by chapter. Each chapter contains several
procedures and discussion topics. Each procedure briefly describes a specific task and how to
perform it. The data for each procedure are provided with the software installation package.
Table 1-1. Quick Start Guide Chapter Organization

Chapter Topic Related Tools
2 Front-End Design Pyxis Project Manager
Pyxis Language Interface
Pyxis Schematic
Eldo
Questa ADMS
3 Back-End Design Pyxis Layout
Calibre nmDRC/nmDRC-H
Calibre nmLVS/nmLVS-H
Calibre xRC
Appendix A CAD Topics
Before You Begin
Table 1-1. Quick Start Guide Chapter Organization

Chapter Topic Related Tools
Appendix B Pyxis Quick Reference Cards
IC Design Flow with the Pyxis Custom Design Platform. . . . . . . . . . . . . . . . . . . . . . . . . 13

Installing the Pyxis Quick Start Example Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Using the /solutions Project Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Global Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IC Design Flow Documentation Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Before You Begin
IC Design Flow with the Pyxis Custom Design Platform
IC Design Flow with the Pyxis Custom Design

Platform
The following figure is a high-level view of the Pyxis Custom Design environment, showing
how different stages in the design flow interact.
Figure 1-1. Pyxis Custom Design Environment
Pyxis Project Manager
Design Verification High-Level Design and Verification

ADiT, Eldo, EZwave, Pyxis Language Interface
Questa ADMS Compile and Register HDL
Mixed Signal
Analog Schematic Design Floorplanning and

Pyxis Schematic Assembly
RF Pyxis Custom Router,
Hierarchical Schematics
Pyxis Layout
Parasitic Modeling Design Configuration Area Estimation
Physical Verification Physical Layout Implementation

Calibre Tools Pyxis Custom Router, Pyxis Layout
DRC, DFM, LVS, PEX Full Custom Layout Automated Layout
Figure 1-2 and Figure 1-3 show high-level front-end design and back-end design flows,
respectively. While design flows can vary, the main steps shown here represent common stages
in design. Each stage in the flow links to procedures containing more detailed information,
demonstrating specific tools in the Pyxis Custom Design Platform.
Figure 1-3 shows two possible paths for physical design. The Manual Layout Flow places
emphasis on using the Pyxis Layout tool. Figure 1-4 shows the physical design flow for the
Automated Layout Flow, which emphasizes using the Pyxis Custom Router tool.
Note
The Pyxis Custom Router includes an advanced set of integrated tools for global and
detail routing, assisted routing, supporting combinations of devices, cells, and blocks. It
provides an environment for developing correct-by-construction layouts. For more details
about using this tool, please refer to the Pyxis Custom Router User’s Manual.
Before You Begin
Figure 1-2. IC Front-End Design Flow (Netlist and Schematic Capture)
IC Specification
Pyxis Project Manager Create Design Library
Pyxis Language Interface Initial Behavioral

Questa-ADMS Design and Simulation
Cell Schematic and

Pyxis Schematic Symbol Capture
Questa-ADMS Cell Functional

Eldo Simulation
No Results
OK?
Yes
Circuit
Optimization
Finalize and Verify Cell

Questa-ADMS Behavioral Design
Pyxis Schematic Top-Level Schematic

Questa-ADMS Capture and Simulation
Front-End Design
Complete
Before You Begin
Figure 1-3. IC Back-End Design Flow (Physical Layout and Verification)
Front-End Design
Manual Layout Flow Automated Layout

with Pyxis Layout Flow with Pyxis
Custom Router
Perform Automated
Floorplan Cell/Block Custom Layout
See Figure 1-4
IRoute Cell/Block Layout
Calibre Physical Physical

Verification Verification
Eldo Parasitic
Resimulation
No Results
OK?
Yes
Top-Level Layout
Final Chip-Level
Calibre Physical Verification Layout Verification
Back-End Design
Complete
Before You Begin
Figure 1-4. Automated Layout Flow with Pyxis Custom Router
Front-End Design
Floorplan Design
Place Devices
Generate Pre-Wires
Set Router
Constraints
Route
Pyxis Custom Router
Shield Nets
Run DFM
Run Net Parasitic

Extraction
Run Timer
Final Chip-Level
Calibre Physical Verification Layout Verification
Back-End Design
Complete
Optional Step
Before You Begin
Installing the Pyxis Quick Start Example Data

Learn how to install example data to use with the procedures contained in this quick start guide.
Prerequisites
• You have downloaded the Pyxis_qs_ekit_10.2x.tgz file containing the design data from
Mentor Graphics SupportNet:
Procedure
1. In a UNIX or Linux terminal window, browse to or create the directory from which you
will run the Pyxis design environment for the Quick Start design data.
2. Copy the Pyxis_qs_ekit_10.2x.tgz file to this directory.
3. Uncompress the Pyxis_qs_ekit_10.2x.tgz file using one of these commands:
gtar -xzf Pyxis_qs_ekit_10.2x.tgz
gunzip < Pyxis_qs_ekit_10.2x.tgz | tar xvf -
4. Change to the example directory:

cd Pyxis_qs_ekit
5. List the contents of the example directory:

ls -al Pyxis_qs_ekit
There are several subdirectories and files in a project. Take a few minutes to explore the
directory hierarchy and become familiar with the contents.
Table 1-2 shows the major directories and contents of the directory.
Table 1-2. Files in the Pyxis_qs_ekit Directory

Directory or File Description
open_Pyxis_QSG_solutions C-shell script that opens Pyxis Project Manager and sets up the
solutions project for viewing.
pyxis_quickstart.pdf This document.
qsg_solutions/ Directory containing solutions for the procedures detailed in
this document.
qsg_tech/ Directory containing the generic13 technology kit used in
procedures.
README ASCII text file describing the contents of the directory.
setup_Pyxis_QSG C-shell script that starts the Pyxis Project Manager and sets up
the environment for starting the design project used in the
procedures.
Before You Begin
Table 1-2. Files in the Pyxis_qs_ekit Directory (cont.)

source_files/ Directory for logic cell Verilog files.
As you perform each procedure, Pyxis Project Manager will automatically open the
project hierarchy for your design. Any generated output from running the examples is
placed within the design directory.
6. In the Pyxis_qs_ekit directory, run the project initialization script as follows:
./setup_Pyxis_QSG
This sets up the design environment and opens the Pyxis Project Manager tool.
If you are planning to proceed to the first front-end procedure, “Creating a Logic
Library” on page 29, then leave the tool open. If not, close the tool by selecting
MGC > Exit.
7. Before you start using the procedures, be sure to review the items listed in “Global
Prerequisites.” It may also be helpful to review the procedures before executing them so
that you become familiar with any prerequisites or special considerations.
8. Optional — To maintain your working design data accessed throughout this document,
create a new sub-directory inside the Pyxis_qs_ekit directory, that is descriptive of your
work, for example:
mkdir ./qsg_projects
In the Creating a Logic Library and Creating a New Project and Attaching a PDK
procedures, specify this location when instructed to create a logic library or project.
Before You Begin
Using the /solutions Project Directory

The Pyxis Quick Start data package includes a solutions project which can be used as a
reference or starting point for performing the procedures in this manual.
This project is found in the qsg_solutions directory.Table 1-3 shows the directory organization.
Table 1-3. Contents in the /qsg_solutions Sub-directory
qsgLogicLib/ A completed logic library, identical to the myDesign logic
library detailed in “Creating a Logic Library” on page 29. This
library contains imported Verilog files for the standards cells, as
well as symbols for each cell.
solutions/ The project directory containing the Front_End and Back_End
libraries.
solutions/Front_End/ The design library containing all schematics, symbols, and
simulation views created in the myChip design library.
solutions/Back_End/ The design library containing layout, schematic, and symbol
views created in the myChip design library.
mgc_location_map, *.attr, ASCII text files used by Pyxis tools. Do not modify these files.
*.pref, *.bak files
Caution
Do not modify or rename any of the files or sub-directories in the /qsg_solutions
directory. Modifying any of the content may result in unusable design data.
Prerequisites
• Access to Pyxis Project Manager (dmgr_ic).
• Existing logic library or design library.
Procedure
1. Change locations to the /Pyxis_qs_ekit directory.
2. Run the C-shell script that opens the solutions project:
./open_Pyxis_QSG_solutions
This opens the Pyxis Project Manager and displays the solutions project and its content.
See Figure 1-5.
Before You Begin
Figure 1-5. Opening the solutions Design Project
3. Explore the contents of the solutions project. Refer to “Project Data Organization” on
page 150 for a brief description of project data.
The Front_End library contains only schematics and symbols, along with a simulation
schematic for the delay_block circuit.
The Back_End library contains layout views for the cells in the design in addition to the
schematic and symbol views.
The qsgLogicLib logic cell library contains the Verilog and symbol views for the
standards digital cells used in the design.
The other default libraries are included with the Pyxis installation tree.
4. Optional — To copy a cell from the qsgLogicLib, Front_End, or Back_End libraries to a
library in your project, follow the directions given in Step 5 of “Creating a New Project
and Attaching a PDK” on page 63.
Related Topics
Creating a Transistor-Level Schematic
Before You Begin
Global Prerequisites
Global Prerequisites
All procedures in this document require the following items to be installed and properly
configured:
• A Mentor Graphics software tree must be installed with the $MGC_HOME and
$CALIBRE_HOME environment variables set to the correct versions of the Pyxis tools,
Eldo simulator, and Calibre tools.
• The Pyxis documentation must be installed and the appropriate variables must be set.
• Software licenses must be installed and license variables must be set.
Contact your Mentor Graphics sales representative or application engineer for configuration and
licensing information.
Before You Begin
IC Design Flow Documentation Reference

The following table lists the Mentor Graphics tools associated with performing IC design.
Information about related documentation is also provided. The table does not list all of the
documents. For a complete list of products and references please visit:
http://supportnet.mentor.com/overview/index.cfm?fa=overview.productlist
Table 1-4. IC Design Flow Tool Reference

Tool Description Related Documentation
IC Design Capture
Pyxis™ Custom Router Includes an advanced set of • Pyxis Custom Router Command
integrated tools for global and Property Reference Manual
and detail routing, assisted
routing, supporting any • Pyxis Custom Router User’s
combination of devices, Manual
cells, and blocks.
Pyxis Design Allows a downstream tool • Pyxis Design Viewpoint User’s
Viewpoint (such as a simulator) to and Reference Manual
view a source schematic as
fully evaluated data,
enabling several team
members to work on a
schematic simultaneously.
Pyxis Project Manager Provides the hardware • Pyxis Project Manager User’s
description language (HDL) Manual
and SPICE support for
Pyxis Project Manager’s
Project Navigator
hierarchies; primarily
serves as an integration tool
for using ADvanced Mixed-
Signal (ADMS), Questa,
and Eldo simulation tools.
Before You Begin
Table 1-4. IC Design Flow Tool Reference (cont.)

Pyxis Layout Custom IC environment • Pyxis Layout Reference Manual
including Schematic Editor,
Layout Editor, and Pyxis • Pyxis Layout User’s Manual
Project Manager; the tool
environment integrates with
Questa ADMS, Eldo, Eldo
RF, and ADiT for
simulations; and Calibre
nmDRC, Calibre nmLVS,
Calibre PERC, and Calibre
xRC for physical
verification and parasitic
extraction.
Pyxis Netlister Translates data between • Pyxis Netlister User’s and
Pyxis Custom Design Reference Manual
applications.
Pyxis Plot Formats designs for • Pyxis Plot User’s and Reference
plotting. Manual
Pyxis Project Manager Provides a structured • Pyxis Project Manager Reference
framework for creating, Manual
organizing, accessing, and
managing a design. • Pyxis Project Manager User’s
Manual
Pyxis Schematic Provides the environment to • Pyxis Schematic Reference
create, simulate, and debug Manual
custom analog or digital,
RF, and mixed-signal • Pyxis Schematic User’s Manual
circuits.
Pyxis Schematic Produces schematics and • Pyxis Schematic Generator User’s
Generator symbols from connectivity and Reference Manual
information supplied by
other applications.
Pyxis common Commonly used documents • AMPLE for Pyxis Reference
documents for Pyxis tools and Manual
applications; use as
necessary. • AMPLE for Pyxis User’s Manual
• Pyxis Common User Interface

Reference Manual
• Pyxis Common User Interface

User’s Manual
Before You Begin

IC Design Simulation
ADiT™ A Fast-SPICE simulator • ADiT User’s and Reference
which targets analog and Manual
mixed-signal transistor-
level applications.
Eldo® An analog simulator which • Eldo Reference Manual
is the core component of
several analog and mixed- • Eldo User’s Manual
signal simulators, including
Eldo RF, Questa ADMS, • Eldo RF User’s Manual
and ADMS-ADiT.
• Eldo Verilog-A User’s Manual
EZwave™ Provides a graphical display • EZwave User’s and Reference
of data produced by Manual
simulators, allowing for
loading and displaying
analog, digital, and mixed-
signal waveforms in a
single environment.
Questa® ADMS™ Simulation system which • Questa ADMS Command
integrates ADiT, Eldo Reference
(including Eldo RF), and
Questa SIM simulation • Questa ADMS User’s Manual
engines, providing an
efficient means for
simulating mixed-language
designs inside one
environment.
IC Design Verification
Calibre® DESIGNrev™ Layout viewer used for full- • Calibre DESIGNrev Layout
chip design viewing and Viewer User’s Manual
basic editing.
• Calibre DESIGNrev Reference
Manual
Calibre Interactive™ GUI for DRC, LVS, PERC, • Calibre Interactive and Calibre
PEX, and DFM. Also calls RVE User’s Manual
Calibre RVE.
Before You Begin

Calibre nmDRC™/ Performs design rule • Calibre Verification User’s
Calibre nmDRC-H™ checking of integrated Manual
circuit layout designs.
• Calibre Solutions for Physical
Verification
• Standard Verification Rule

Format (SVRF) Manual
Calibre nmLVS™/ Performs layout-versus- • Calibre Verification User’s
Calibre nmLVS-H™ schematic comparison and Manual
netlist extraction.
• Calibre Solutions for Physical
Verification
• Standard Verification Rule

Format (SVRF) Manual
Calibre xACT Performs fieldsolver • Calibre xACT User’s Manual
capacitance extraction
(xACT 3D) and digital
design parasitic extraction
(xACT SOC).
Calibre xRC™ Performs parasitic • Calibre xRC User’s Manual
extraction, generating user-
specified output formats
including SPICE, Eldo,
Spectre, LEF/DEF, and so
forth.
Calibre RealTime™ Integrates flat Calibre • Calibre RealTime User’s Manual
nmDRC with supported
layout design tools allowing
Calibre nmDRC to be run
directly from the design
tool.
Calibre RVE™ GUI used to view and • Calibre Interactive and Calibre
debug results output from RVE User’s Manual
Calibre tools.
• Calibre DRC RVE Quick
Reference
• Calibre LVS RVE Quick Reference
Before You Begin
Chapter 2
Front-End Design
The front-end design flow and procedures for the Pyxis Custom Design Platform are as follows:
Creating a Logic Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Importing HDL Files into a Logic Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Regenerating Circuit Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Validating Registered Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Creating a Schematic Sheet from a Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Creating a Simulation Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Setting Up and Performing an ADMS Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Adding Properties to a Design Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Creating a New Project and Attaching a PDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Creating a Transistor-Level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Setting Up and Running a Transistor-Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 2-1 shows the front-end design flow and how these topics connect with specific design
stages.
Note
Before proceeding with any of the schematic capture procedures in this chapter, review
the Pyxis Schematic Quick Reference Card, found in Appendix B. This overview of
common Pyxis Schematic commands, palettes, project structure, and key bindings is
helpful in selecting how to perform an operation. For example, to copy a device symbol,
you have an option to use a key binding, a menu button, or a Pyxis Stroke. Select methods
that are comfortable and fit within your work flow.
Front-End Design
Figure 2-1. Front-End Design Flow
IC Specification
• Creating a Logic
Library
Create Design Library
• Creating a New Project
and Attaching a PDK
• Importing HDL Files Initial Behavioral

into a Logic Library
Design
• Regenerating Circuit
Symbols
Cell Schematic and • Validating Registered

Symbol Capture Models
• Creating a Simulation
Test Bench • Creating a Schematic
Sheet from a Symbol
• Setting Up and
Performing an ADMS Cell Functional • Creating a Transistor-
Simulation Simulation Level Schematic
• Setting Up and
Running a Transistor-
Level Simulation No Results
OK?
Yes
Circuit • Adding Properties to a

Optimization Design Configuration
Finalize and Verify Cell

Behavioral Design
Top-Level Schematic
Capture and Simulation
Front-End Design
Complete
Front-End Design
Creating a Logic Library

Use this procedure to create a new logic library when you have not selected the process
technology for your design. This is helpful when the focus is behavioral design work, especially
for capturing digital logic circuits.
Keep in mind the following limitations:
• Do not open the Pyxis Project Manager (dmgr_ic) inside an existing project hierarchy.
Doing so causes problems with location map files as you proceed.
• Ensure that the new logic library directory is completely empty.
Prerequisites
• Disk space for your new logic library.
Procedure
1. Start the Pyxis Project Manager from your home directory:
% dmgr_ic
Caution
Do not start Pyxis Project Manager from inside an existing hierarchical design directory,
such as a project, external library, logic library, technology library, or any location where
there is an existing mgc_location_map file. Starting the Pyxis Project Manager this way
results in errors inside location map files.
Figure 2-2 shows the Pyxis Project Manager after it has been started, before creating a
new project. Notice that there is no content in any of the windows.
Front-End Design
Figure 2-2. Project Navigator Before Creating a New Logic Library
2. To create a new logic library, select File > New > Logic Library. This opens the New
Logic Library dialog window.
3. In the New Logic Library window, enter the path to the logic library in the Library
path field, naming it “myDesign”, as shown in Figure 2-3. Click OK to create the new
library, including the myDesign directory.
This also opens the Manage External/Logic Libraries window.
Figure 2-3. Enter New Logic Library Name
Note
Figure 2-3 shows the myDesign logic library path included in the Pyxis_qs_ekit directory.
The /qsg_projects location is recommended to be used for storing the myDesign, and
later, myProject design objects. See “Using the /solutions Project Directory” on page 19,
Step 8, for creating the qsg_projects subdirectory.
Front-End Design
4. In the Manage External/Logic Libraries window, click the Add Standard Libraries
button. This fills the form in the window with predefined standard libraries for IC
devices, generic standard cells, and any other external libraries defined for your design
environment.
Click OK to exit and close the window.
5. Review the Project Navigator window. Clicking the plus icon (+) next to myDesign
expands the library hierarchy, as shown in Figure 2-4.
Figure 2-4. myDesign Hierarchy
6. You may close Pyxis Project Manager (MGC > Exit) or leave it open for the next stage.
This ends the procedure.
Related Topics
Creating a New Project and Attaching a PDK
Importing HDL Files into a Logic Library
Front-End Design Flow
Front-End Design

This procedure is for importing HDL circuit descriptions into a logic library or an existing
design. The design may or may not be attached to a process technology.
Prerequisites
• Access to Pyxis Project Manager.
• Access to the design data (see “Installing the Pyxis Quick Start Example Data” on
page 17).
• Successful completion of “Creating a Logic Library” on page 29.
Procedure
1. If the Pyxis Project Manager is open, proceed to Step 2. Otherwise, start the tool as
follows:
% dmgr_ic
You should see the myDesign project under the first Object column.
Note
When you start the Pyxis Project Manager, the myDesign project automatically appears in
the Project Navigator pane. The Pyxis Project Manager tool maintains the previous
project you opened. To start the tool without referencing any projects, you must close the
working project hierarchy (File > Close Hierarchy) before exiting the tool.
2. Right-click the myDesign logic library and select Open > Language Interface. This
opens the Pyxis Language Interface window.
3. Select myDesign in the Project Area pane (it is highlighted by default when you open the
tool).
4. Select File > Import > HDL, as shown in Figure 2-5. This opens the Import HDL
window.
Front-End Design
Figure 2-5. Import HDL with the Pyxis Language Interface
5. In the HDL Source field, enter the path to the inv1.v file, the Verilog model for an
inverter. Type the path and filename or browse to it by clicking the browse icon on the
right and click OK, as shown in Figure 2-6.
Figure 2-6. Import HDL Dialog Box
This file is found in the source_files directory. See “Installing the Pyxis Quick Start
Example Data” on page 17 for the data directory structure.
6. Do not change the default settings and Click OK. This compiles the model, creates a
symbol for the model, and registers the compiled model to the symbol. Depending on
your system, this may take a few moments.
Once completed, the new circuit appears in the myDesign hierarchy, in the Project Area
of the Pyxis Language Interface, as shown in Figure 2-7.
Status messages are written to the Message Area. Review the messages to understand
the information related to importing a circuit.
Front-End Design
Figure 2-7. Registered Inverter Circuit in the myDesign Library
7. Repeat Step 3 through Step 6 for the nand2.v and delay_block.v circuits, also found in
the source_files directory.
Once completed, you should see the new models in the myDesign hierarchy, similar to
the inv1 model.
8. Close the Pyxis Language Interface by selecting MGC > Exit.
Related Topics
Regenerating Circuit Symbols
Validating Registered Models
Front-End Design

This procedure shows how to regenerate symbols for imported HDL models. For example,
instead of using the default box symbol, you can regenerate the nand2 symbol to use the
standard NAND logic symbol.
Prerequisites
• Access to the design data (see “Installing the Pyxis Quick Start Example Data” on
page 17).
• Successful completion of “Importing HDL Files into a Logic Library” on page 32.
Procedure
follows:
% dmgr_ic
You should see the myDesign project under the first Object column.
2. Right-click the myDesign logic library and select Open > Language Interface. This
opens the Pyxis Language Interface window with the myDesign project highlighted.
3. Under myDesign, do the following:
a. Select the nand2 cell and click the plus (+) icon on the left side.
b. Select the nand2 Verilog model view. Figure 2-8 shows the available model views
(symbol and Verilog).
Figure 2-8. Expanded nand2 Cell
Front-End Design
4. Right-click the nand2 Verilog view and select Register Model. This opens the Register
Model from Source window.
5. In the Register Model from Source window, enable the Regenerate Symbol checkbox.
This activates the Symbol Layout Options button, as shown in Figure 2-9.
Figure 2-9. Register Model from Source for Symbol Regeneration
6. Modify the symbol by clicking the Symbol Layout Options button. This opens the
Symbol Layout Properties window. Do the following:
a. From the Shape dropdown list, select And Gate.
b. For the Zout pin, enable the Bubble checkbox. Figure 2-10 shows the modified
configuration for the Symbol Layout Properties window.
Figure 2-10. Symbol Layout Changes for nand2 Model
c. Click OK in the Symbol Layout Properties window to close it.
Front-End Design
d. Click OK in the Register Model from Source window to close it. The symbol
regeneration may take a few moments.
7. Right-click the symbol view for the nand2 cell ( ) and select Open. This opens the
Pyxis Schematic window for the nand2 symbol, shown in Figure 2-11.
Review the symbol and close the Pyxis Schematic tool by selecting MGC > Exit.
Figure 2-11. nand2 Symbol Opened in Pyxis Schematic.
8. Repeat steps 3 to 7 for the inv1 cell, with the following changes:
• Select Buffer from the Shape dropdown list.
• Enable the bubble checkbox for the output pin, Zout.
Keep the Pyxis Language Interface window open if you are proceeding to the next
procedure. This ends the procedure.
Related Topics
Front-End Design

This procedure shows how to validate a registered model prior to performing simulations or
other activities.
If the Pyxis Language Interface tool is still open, and myDesign is selected, proceed to Step 4.
Otherwise, begin with Step 1.
Prerequisites
• Successful completion of “Importing HDL Files into a Logic Library” on page 32.
Procedure
follows:
% dmgr_ic
You should see the myDesign logic library under the first Object column.
2. Right-click the myDesign logic library and select Open > Language Interface.
3. Make sure that myDesign is selected in the Object area of the Pyxis Language Interface
window (it should be highlighted).
4. Click the Check Language Models button ( ). It may take a few moments to
complete the checks.
Review the Message Area in the Pyxis Language Interface window. When models are
checked successfully, the following message appears:
Note: Selected objects pass check.
Validate all imported models before running downstream applications, such as

simulators. Any errors in HDL models (for example, syntax errors) are reported after
running Check Language Models.
5. Close the Pyxis Language Interface by selecting MGC > Exit.
Related Topics
Creating a Schematic Sheet from a Symbol
Front-End Design

This procedure shows how to create a schematic sheet from an existing symbol.
Prerequisites
• The project myDesign contains correctly imported and registered models for inv1,
nand2, and delay_block circuits.
Procedure
1. Open Pyxis Project Manager:
% dmgr_ic
2. Under the myDesign logic library, select the delay_block design object. This shows the
Verilog and symbol views in the right window pane.
3. Right-click the delay_block symbol and select Open > Schematic Editor. This opens
the symbol in edit mode. You are not going to edit the symbol.
4. With the delay_block symbol open in the Pyxis Schematic tool, do the following:
a. Select File > Create Sheet. This opens the Create Sheet dialog box, Figure 2-12.
Figure 2-12. Create Sheet Dialog Box for delay_block Schematic
b. Do not change the Schematic name or Sheet name fields. Click OK to create the new
schematic sheet.
A new tab opens in the workspace area of Pyxis Schematic. The schematic has ports
placed in it, matching the names and approximate locations of those found in the
symbol.
5. Place instances of the nand2 and inv1 cells in the schematic and connect with wires. The
final schematic is shown in Figure 2-13.
To complete the schematic, do the following:
a. Click the Add Instance icon ( ), or use the keyboard short cut by typing I. This
brings up the File Browser window.
Front-End Design
b. In File Browser, select the nand2 cell and click OK. The cell appears inside the
schematic and is free to move with the cursor.
c. Left-click within the schematic to place the nand2 cell.
d. Repeat Steps a through c for the inv1 cell.
Notice that the inv1 stays attached to the cursor after you place the first instance.
Place two more instances, then press the Esc key to clear the cell.
To unselect all of the instances, left-click anywhere in the schematic.
e. Move the pre-placed ports to the locations shown in Figure 2-13. Do this by left-
clicking to select each port, then dragging it while holding down the left-mouse-
button to the shown location.
Tip: To move multiple objects at the same time, begin by drawing a selection box around
the objects to be moved. Press M on the keyboard to move the selected objects. The
selections follow your mouse cursor. Place the objects by left-clicking.
f. Press F to fit the schematic view to the available workspace area. You may also use
the View All button ( ).
g. To make the wiring connections, left-click a pin (from instance NAND21/Zout) and,
while holding the left-mouse-button down, drag it to another pin (to instance
INV11/Ain). Complete the wiring as shown in Figure 2-13.
An open pin has a small diamond indicating that the pin is unconnected. Once a wire
is attached, the diamond disappears.
Figure 2-13. Schematic for delay_block Circuit
Front-End Design
6. Save the schematic by clicking the Check/Save icon ( ). A new tab opens, presenting
a report of warning and errors found during the operation.
Review this information. If there are errors, determine the cause. You may ignore any
warning messages. If there are no errors, this procedure is finished.
Related Topics
Creating a Simulation Test Bench
Front-End Design

Creating a simulation test bench is similar to creating a circuit schematic.
Prerequisites
• The project myDesign contains correctly imported and registered models for inv1,
• Successful completion of “Creating a Schematic Sheet from a Symbol” on page 39.
Procedure
1. Open Pyxis Project Manager:
% dmgr_ic
2. Select the delay_block cell under the myDesign logic library.

3. Right-click the schematic view of the delay_block in the right pane of the Project
Navigator window and select Open > Schematic Editor, or double-click the schematic
view.
4. In the Pyxis Schematic tool, select File > New > Schematic to start a new schematic for
the simulation test bench.
5. In the New Schematic window, do the following:
a. Click the Create button ( ). From the submenu, select the New Cell option. The
New Object dialog box opens.
b. In the Object Name field, enter the test bench schematic name sim_delay_block.
Note
Although all standard ASCII characters are allowed for object names in the Pyxis Custom
Design tools, avoid using any non-alphanumeric characters, such as a space, which other
downstream tools may not accept. For example, although the object name “sim delay
block” (with spaces) is acceptable in the Pyxis design environment, it may not work in
downstream simulation tools.
The New Object dialog box closes and the sim_delay_block cell object appears in
the New Schematic window.
c. Click OK to close the New Schematic window. This opens a new tab for the
sim_delay_block circuit in the Pyxis Schematic tool.
Front-End Design
6. Create the schematic for the delay_block test bench:

a. Select the Add Instance button ( ). This opens the File Browser window. Do the
following:
i. Make sure that the myDesign library is selected in the Object pane. The contents
of myDesign are displayed in the right pane of this window.
ii. Select the delay_block and click OK. The File Browser window closes and the
delay_block symbol appears in the sim_delay_block schematic, free to move
with the cursor.
iii. Place the delay_block symbol by left-clicking the mouse in the schematic,
preferably in the center of the workspace.
b. Select the Add Instance button again to place a capacitor:
i. Select device_lib in the Object column.
ii. Find the ideal_capacitor in the right pane, select it, and click OK.
iii. Place the ideal_capacitor symbol close to the Zout pin of the DELAY_BLOCK1
instance.
iv. Press Escape to exit the Add Instance operation.
c. Connect the capacitor to delay_block by left-clicking the ideal_capacitor top pin
and, while holding the left-mouse-button down, dragging it to Zout pin of
DELAY_BLOCK1.
d. Add more wires, using the Add Wire button (refer to Figure 2-14):
i. Click the Add Wire button ( ), or use the W hotkey. This changes the cursor
to a plus sign and opens the ADD WI prompt in the schematic space.
ii. Add a wire to the bottom pin of the capacitor and terminate it (double-click) to
the left of the capacitor symbol.
iii. Add an unconnected wire close to the capacitor wire.
iv. Add wires to the unconnected Enable and Ain pins of DELAY_BLOCK1.
Front-End Design
Figure 2-14. Add Wires to the Test Bench Schematic
7. Add net names to the wires (refer to Figure 2-15):

a. Select the wire connecting the Zout pin and the capacitor. When you select the wire,
its color changes to white. Make sure the wire is selected.
b. Click the Add Net Name button ( ). This opens the ADDPRTH prompt.
Figure 2-15. Add Net Names
When the ADDPRTH prompt appears, the wire color changes back to the default.
However, a selection indicator (shown in Figure 2-15) appears.
c. In the Property Value field, enter the net name tb_zout, leave the other fields
unchanged, and click OK. The new net name appears on the net.
Front-End Design
d. Follow steps a through c for the remaining nets. Add the following net names,
corresponding to the net numbers shown in Figure 2-15:
• Net 1 — tb_enable
• Net 2 — tb_ain
• Net 3 — VDD
• Net 4 — VSS
The final schematic is shown in Figure 2-16.
Tip: You can also modify net names by selecting the net, pressing the Q hotkey to open
the Edit Properties form, and modifying the Net Name field.
8. Save the schematic by clicking the Check/Save button ( ). A new tab opens, reporting
any generated warnings and errors.
Review this information. If there are errors, determine the cause. There may be a few
warnings; you can ignore these. If there are no errors, this procedure is finished.
Figure 2-16. Completed delay_block Test Bench Schematic
Related Topics
Setting Up and Performing an ADMS Simulation
Front-End Design
Setting Up and Performing an ADMS

Simulation
This procedure shows how to setup and run an ADMS simulation. Setting up the environment
and performing the simulation are done within the Pyxis design environment.
The flow for setting up and running an ADMS simulation is as follows:
• Set up the simulation configuration.
• Set up the global parameters for the simulation run.
• Set up the analysis types.
• Set up the input signal sources.
• Verify the input signals for correctness.
• Modify the A2D/D2A settings for the simulation.
• Run the simulation.
• Review results.
Prerequisites
• The myDesign logic library contains correctly imported and registered models for inv1,
• Successful completion of “Creating a Simulation Test Bench” on page 42.
Procedure
1. If Pyxis Project Manager is already open along with the sim_delay_block schematic,
proceed to Step 4, otherwise start Pyxis Project Manger:
% dmgr_ic
2. In the myDesign logic library, select the sim_delay_block design object.

3. In the right window pane of the Project Navigator, right-click the sim_delay_block
schematic view and select Open > Schematic Editor, or double-click the schematic
view to open it.
Note
If you are starting from a session that is already open, make sure that all open symbol
views are closed in the Pyxis Schematic session. This is a requirement for setting up and
running a simulation.
Front-End Design
4. To set up the simulation configuration, do the following:

a. Click the Enter Simulation Mode button ( ) to start the simulation environment.
This brings up the Entering Simulation Mode dialog box.
b. In the Entering Simulation Mode dialog box, click the New Design Configuration
button ( ).
c. Enter ADMS_0 for the Name field and select ADMS for Simulation type. See
Figure 2-17. Click OK to close this dialog box.
Figure 2-17. Set Up a New Design Configuration
d. In the Entering Simulation Mode window, make sure the ADMS option is selected
under Simulation type and click OK. See Figure 2-18.
Figure 2-18. Enter Simulation Mode Dialog Box Setup
Closing the Entering Simulation Mode dialog box with the newly defined
configuration changes the Pyxis Schematic tool environment. This is in preparation
for running simulations. The new environment is shown in Figure 2-19.
Front-End Design
Figure 2-19. Simulation Environment in Pyxis Schematic
5. Set up the simulation parameters for the circuit as follows:

a. In the schematic window, type P to open the Setup Simulation window.
b. Refer to Figure 2-20. In the Parameter and Value fields, enter the parameter and
value pairs from Table 2-1. Press Return or click Add after entering each pair.
Table 2-1. Parameter Value Pairs for Simulation

Parameter Value
p_vdd 1
p_vss 0
p_tdelay 4n
p_tperiod 20n
p_trise 100p
p_tfall 100p
p_tend {2*p_tperiod + p_tdelay}
p_vth {(p_vdd - p_vss)/2}
Front-End Design
Figure 2-20. Parameter and Value Fields in the Setup Simulation Window
After entering the parameters, the lower part of the Setup Simulation window looks
like Figure 2-21, showing the parameter names, nominal values, and other possible
arguments for each parameter. Do not change any other arguments.
c. Review the parameters. If there are no errors in the values, click Apply. Notice that
the Apply button becomes inactive.
Figure 2-21. Parameter List for sim_delay_block Test Bench
6. Set up the simulation analysis as follows:

a. From the Simulation Panel, select Analysis. The window layout changes and the
Analysis Selector sub-panel opens. See Figure 2-22.
Figure 2-22. Analysis Selection in the Setup Simulation Window
Front-End Design
b. In the Analysis Selector, unselect the OP (operating point) option and select the
TRAN (transient) option.
c. Set the Start Time field to 0. Set the Stop Time field to p_tend, the user-defined
parameter. Do not change any other fields.
d. Click Apply.
7. Set up the input signals for the simulation as follows:
a. Select Forces from the Simulation Panel. Notice that the Selection from Schematic
and Source Type panes appear.
b. Click within the schematic workspace to make it active.
c. Select the tb_ain signal connected to the Ain pin of DELAY_BLOCK1. Notice that
the signal name appears in the Selection from Schematic pane in the Setup
Simulation window. Also notice that the wire color changes to indicate that it is
highlighted.
d. Go back to the Setup Simulation window.
e. Select PULSE from the Source Type list and specify the parameter values as follows
(the parameters are defined in Table 2-2):
i. Enter the value for Initial Value (p_vss).
ii. To move to the next field, press Tab. Do not use the Return key at this point; this
applies all of the default values to the PULSE source parameters.
iii. Enter all of the parameter values for tb_ain and click the Add button ( ).
f. Select the tb_enable signal connected to the Enable pin of the DELAY_BLOCK1.
Repeat steps d and e to set up the PULSE source for this signal. Figure 2-23 shows
the bottom of the Setup Simulation window once both sources have been defined.
Table 2-2. Parameter Values for PULSE Sources

Parameter tb_ain tb_enable
Initial Value (V/A) p_vss p_vss
Pulsed Value (V/A) p_vdd p_vdd
Delay (s) p_tdelay {p_tdelay+(3*p_tperiod/4)}
Rise Time (s) p_trise p_trise
Fall Time (s) p_tfall p_tfall
Pulse Width (s) {(p_tperiod/4)- p_trise} {10*p_tend}
Period (s) {p_tperiod/2} {20*p_tend}
Front-End Design
Figure 2-23. Defined PULSE Sources for the tb_ain and tb_enable Signals
g. Click the Apply button ( ) at the bottom of the form. This does not close the
window.
h. Close the Setup Simulation window by clicking the Cancel button ( ) at the
bottom of the form.
8. In the sim_delay_block schematic view, select the DELAY_BLOCK1 cell and right-
click to select Change Model > BLACKBOX. See Figure 2-24.
Doing this enables you to verify the simulation stimulus setup without actually running
the full simulation.
9. Click the Start Simulation button ( ) to begin the stimulus verification run. The Log
panel opens in the Pyxis Schematic window and shows the run progress. Review the log
information for warnings and errors.
Figure 2-24. Changing DELAY_BLOCK1 Model to BLACKBOX for Simulation
Front-End Design
10. Plot the tb_ain and tb_enable signals to verify that are set up correctly. To do this:
a. Left-click the tb_ain wire. Notice that it is highlighted.
b. Press the Control key and at the same time left-click the tb_enable wire. Both signals
are selected and highlighted in schematic workspace.
c. Click the Cross Probe Selected Items button ( ). This opens the EZwave
application and plots the tb_ain and tb_enable signals, shown in Figure 2-25.
Review the signal plot and verify that it matches the PULSE source specifications.
After reviewing, in the EZwave window select File > Exit to close the application.
Figure 2-25. Plot of tb_ain and tb_enable Signals
11. With the input signals verified, set up the analog-to-digital and digital-to-analog signal
converters for the simulation. Do this as follows (refer to Figure 2-26):
a. In the sim_delay_block schematic, press P to bring up the Setup Simulation window.
b. Under the Simulation Panel heading, select Converters. This brings up the Model
options.
c. Under the Model heading, select Std_logic (standard logic).
d. In the top of the Converters form, select the Builtin and A2D options.
e. In the parameter column, enter the following values:
o str: STRONG (the default)
o vth: {(p_vdd - p_vss)/2} or p_vth
Front-End Design
f. Click the Add button ( ). Notice that the A2D model is now added to the list of
models at the bottom of the window. See Figure 2-27.
g. Select the D2A option at the top of the Converters form.
h. In the parameter column, set the following values:
o vhi = p_vdd
o vlo = p_vss
o trise = p_trise
o tfall = p_tfall
i. Click the Add button. The D2A is now added to the model list.
Figure 2-26. Populate the Converter Fields
Figure 2-27. Converter Values in the Setup Simulation Window
j. Click the Apply button ( ) at the bottom of the form to apply the changes to
the simulation setup. Click the Cancel button ( ) to exit the window.
12. In the sim_delay_block schematic, left-click the DELAY_BLOCK1 cell to select, then
right-click to select Change Model > VERILOG.
Front-End Design
13. Click the Run Simulator button ( ). The simulation runs with the Verilog model for
the delay_block. Review the Log window for warning and error messages.
14. Select the tb_enable, tb_ain, and tb_zout signals.
15. Click the Cross Probe Selected Items button ( ). This starts the EZwave application
and then plots the selected signals. See Figure 2-28.
Figure 2-28. Simulation Results for Verilog Model
Notice that there are two waveforms plotted for each signal. Zoom-in on the area that
contains the low-to-high signal transition in the tb_enable signal by left-clicking and
selecting the area around the signal level change.
The new view shows that there are two plotted signals: one showing an ideal transition
(the ideal signal) and one showing a sloped transition (the simulated signal).
16. Explore the waveform information in EZwave. When finished, click File > Exit to close
the application.
17. In the sim_delay_block schematic view, select the DELAY_BLOCK1 cell and right-
click to select Change Model > SCHEMATIC.
18. Click the Run Simulator button ( ). The simulation runs with the schematic model
for the delay_block. Review the Log window for warning and error messages.
19. Plot the tb_enable, tb_ain, and tb_zout signals by first selecting the signals and then
clicking the Cross Probe Selected Items button. See Figure 2-29 for the expected
results.
Front-End Design
Note
If you did not close the previous simulation session, the signals of interest are
automatically plotted in EZwave once the simulation is completed. Note that the results
are presented in the same state which EZwave was closed with. To see the complete
waveforms in EZwave, select View > View All. This resets the x and y axis, making
complete waveforms visible.
Figure 2-29. Simulation Results with Schematic Model
Notice that for the tb_zout signal, the initial output is different that previous results. This
is due to the initial conditions of nets inside the schematic model at the beginning of the
simulation run.
20. Close the EZwave window by selecting File > Exit. Close the Pyxis Schematic tool by
selecting MGC > Exit. You can keep the Pyxis Project Manager session open or close it
by selecting MGC > Exit.
Related Topics
Adding Properties to a Design Configuration
Setting Up and Running a Transistor-Level Simulation
Front-End Design

With a parametrized simulation test bench, it is possible to sweep the circuit under test and
calculate design performance metrics. This is done by measuring attributes from simulated
signals.
In this procedure, you set up properties in the simulation configuration to measure propagation
delay for the delay_block circuit. Do this by setting up transition edge-to-edge time
measurements while varying the p_delay_block parameter.
The flow for setting up and running a sweep simulation is as follows:
• Select signals to be measured.
• Set up required calculations based on measured signals.
• Add the necessary sweep parameters to the simulation configuration.
• Annotate the sweep parameters for the required cells.
• Run the simulation.
• Review results.
Prerequisites
• The myDesign logic library contains correctly imported and registered models for inv1,
nand2, delay_block, and sim_delay_block circuits.
• Successful completion of “Setting Up and Performing an ADMS Simulation” on
page 46.
Procedure
1. Start Pyxis Project Manager and open the ADMS_0 view for the sim_delay_block
object.
2. Press P in the sim_delay_block schematic view to open the Setup Simulation window.
3. From the Simulation Panel list, select Measures.
4. In the sim_delay_block schematic, select both the tb_ain and tb_zout signals. Do this by
first selecting the tb_ain signal, then press the Ctrl key while left-clicking the tb_zout
signal.
Notice that both signals are highlighted and appear in the Selection from Schematic pane
of the Setup Simulation window.
Front-End Design
5. In the Setup Simulation window, set up the falling-edge to falling-edge, or high-to-low

transition measurement (tpHL). To do this:
a. Select both the tb_ain and tb_zout signals from the Selection from Schematic list.
Use shift-left-click to select both.
b. In the Label field, enter tpHL.
c. Select TRAN from the Analysis dropdown list.
d. Select Tpddd from the Function dropdown list.
e. Make sure Voltage is indicated from Measure dropdown list (this is the default
value).
f. Refer to Figure 2-30. Enter the corresponding Value for each Parameter using the
information shown in Table 2-3.
Table 2-3. Parameters and Values for tpHL Measurement

Parameter Value
occurrence 1
after {p_tdelay+(3*p_tperiod/4)}
vthout (leave blank)
before p_tend
vth p_vth
vthin (leave blank)
g. Click the Add button ( ). The new analysis expression appears in the bottom of
the Setup Simulation window.
Figure 2-30. Setup Simulation Window for tpHL Parameters
Front-End Design
6. Set up the rising-edge to rising-edge, or low-to-high transition measurement (tpLH). To

do this:
a. Select both the tb_ain and tb_zout signals from the Selection from Schematic list.
These should be selected from the previous step.
b. In the Label field, enter tpLH.
c. Select TRAN from the Analysis dropdown list.
d. Select Tpduu from the Function dropdown list.
e. Select Voltage from the Measure dropdown list (this is the default).
f. Enter the corresponding Value for each Parameter using the information shown in
Table 2-3.
g. Click the Add button. Both tpHL and tpLH definitions appear in the expression
summary area. See Figure 2-31.
Figure 2-31. Summary of Analysis Expressions
7. Click the Apply button ( ) to add these measurement statements to the

simulation configuration.
8. Add a new parameter, p_block_delay, for performing an incremental sweep (see
Figure 2-32). To do this:
a. In the Setup Simulation window, select the Params/Sweeps option under Simulation
Panel list.
b. In the Parameter field, enter p_block_delay.
c. In the Value field, enter 1n (one nanosecond).
d. Define the sweep by clicking the Enabled checkbox under in the Sweeps section.
Also, select the Range option.
e. Enter the following values for these fields in the Sweeps section:
i. Range = Increment (default)
ii. Start = 0.6n
iii. Stop = 1.4n
Front-End Design
iv. Increment by = 0.2n

f. Click the Add button ( ). The new parameter appears in the parameter list.
Figure 2-32. Setup for the p_delay_block Sweep Parameter
9. Click the Apply button ( ) at the bottom of the form to apply the changes to the
simulation setup. Click the Cancel button ( ) to exit the window.
10. Select the DELAY_BLOCK1cell in the schematic view and right-click to select Change
Model > Verilog.
11. Annotate the user-defined tPHL and tPLH properties to the DELAY_BLOCK1 cell. To
do this:
a. Select the DELAY_BLOCK1 cell and press Q to open the Edit Object window.
b. Change the value for tPHL and tPLH to p_block_delay. With the changed model
view and the new annotation, the test bench schematic should resemble Figure 2-33.
Front-End Design
Figure 2-33. Annotated Schematic for sim_delay_block Test Bench
12. Click the Run Simulator button ( ) to start the simulation. The Log window opens if
this is a new simulation session.
Several simulation runs complete, each one corresponding to a point in the defined
sweep variable, p_delay_block. Review the Log window for warnings or errors.
13. Plot the tb_ain and tb_zout signals by first selecting the signals and hen clicking the
Cross Probe Selected Items button ( ). Figure 2-34 shows a zoomed-in portion of
the output results.
Notice that there are several results plotted for the tb_zout (lower plot). Each output
signal corresponds to a sweep value.
Figure 2-34. Sweep Simulation Results
Front-End Design
14. In the EZwave application, if the Waveform List panel on the left side of the plot
window is not open, then select View > Waveform List to open this view.
15. Refer to Figure 2-35. In the Waveform List panel, under the Currently Open Databases,
click the plus (+) icon next to sim_delay_block_ADMS_0 to open the waveform tree.
16. Select the EXT folder. This refers to “Extracted” results, those defined with the Measure
and Analysis options in the Setup Simulation window.
17. Under the Name heading, in the lower pane of the Waveform List panel, double-click
the TPHL and THLH waveforms to plot these results.
Figure 2-35. Plots of TPHL and TPLH
18. Review the plotted results. When you are satisfied, select File > Exit in the EZwave
window to close the application.
19. In the Pyxis Schematic window, click the Save button ( ) to save your work. Select
MGC > Exit to close the schematic and simulation session.
Front-End Design
Related Topics
Front-End Design

This procedure shows how to create a new project, attach a process design kit (PDK), and copy
existing cells in to the project.
The Quick Start data is arranged so that you can either use the generic13 PDK data or a locally
installed and Pyxis-compatible PDK. The steps below assume that you will be using the
generic13 PDK. With minor changes to the instructions, you can use a company-specific Pyxis
PDK.
Prerequisites
• Access to the Quick Start generic13 PDK or other locally installed PDK.
• Successful completion of the following procedures:
o Creating a Logic Library
o Importing HDL Files into a Logic Library
o Regenerating Circuit Symbols
o Validating Registered Models
• Disk space for creating a new project.
Procedure
1. Start the Pyxis Project Manager:
% dmgr_ic
2. Find and open the PDK in the Pyxis Project Manager. Follow these steps:
a. Click the Open button ( ) to start the Open window.
b. Navigate to the path for the generic13 PDK, <qsg_installation_path>/qsg_tech. Do
this by typing the path in the Look in field. Figure 2-36 shows the Open window.
Figure 2-36. Selecting the generic13 PDK
Select the PDK and click OK. The PDK appears in the Object column of the Project
Navigator tab (Figure 2-37).
Front-End Design
Figure 2-37. PDK in the Project Navigator Tab
c. Check the references in the generic13 PDK by selecting Edit > Check References.
This checks that the PDK components are properly referenced. When the check is
completed, the Change/Fix References window opens showing the components of
the PDK with a green check mark next to each entry that has a clean reference
(Figure 2-38).
Figure 2-38. Checking the generic13 PDK
Verify that all of the components are clean. This is indicated by a green check mark
to the left of each entry. Click OK at bottom of the window.
Front-End Design
3. Start a new project and attach a technology to it. Refer to Figure 2-39 and follow these
steps:
a. In the Pyxis Project Manager, click the New Project button ( ). This opens the
New Project dialog window.
b. In the Project Path field, enter the path to your project, including the project name.
In this case, the project name is myProject.
c. In the Technology section of the New Project window, do the following:
i. Use the Browse button ( ) next to the Library field to navigate to the
generic13 PDK location, or enter the path to the PDK in the Library field by
typing:
<qsg_installation_path>/qsg_tech/generic13
Since the PDK was just added, a virtual path ($GENERIC13) appears in the
Library field. If it does not, then enter the path manually.
ii. Do not make any changes to the Configuration field.
iii. Click OK at the bottom of the window. This opens the Manage External/Logic
Libraries window.
Figure 2-39. Attaching a PDK to myProject
d. Refer to Figure 2-40. In the Manage External/Logic Libraries window, do the

following:
i. Click the browse icon ( ). This opens the File Browser window.
Front-End Design
ii. In the File Browser window navigate to the path for the myDesign library.
iii. Select myDesign from the list and click the OK button. This adds the myDesign
library to the project and returns the focus to the Manage External/Logic
Libraries window.
iv. At the bottom of the window, click the Add Standard Libraries button. This
adds any standard libraries that are native to your specific Pyxis design
environment. Click OK.
Figure 2-40. Attaching External and Logic Libraries to myProject
e. Refer to Figure 2-41. Review the content of the Manage External/Logic Libraries
window. When you are satisfied, click OK.
Figure 2-41. Adding myDesign and Standard Libraries to myProject
Front-End Design
4. In myProject, add a new chip library for transistor-level schematics and layouts. Follow
these steps:
a. In the Project Navigator tab of the Pyxis Project Manage, make sure myProject is
selected.
b. Click the New Library button ( ). This opens the New Library dialog box.
c. Enter the new design name, myChip, in the Library name field and click OK.
d. Refer to Figure 2-42. Review the Project Navigator tab of the Pyxis Project
Manager. In the Object column, the myChip library is added to myProject. Notice
also that the generic13 and myDesign libraries are part of myProject.
Figure 2-42. Adding the myChip Design Library to myProject
5. Add the cells from myDesign to myChip in preparation for drawing transistor-level
schematics and completing layout. Follow these steps:
a. Select the myDesign library in the Project Navigator tab. The right-side pane
displays the contents of the library.
b. Refer to Figure 2-43. In the right-side pane, select the delay_block, inv1, nand2, and
sim_delay_block cells and right-click to select Copy.
c. Refer to Figure 2-44. Select the myChip library and right-click to select Paste. After
a few moments, the copied cells appear in the myChip library (right-side pane).
Front-End Design
Figure 2-43. Copying Cells from the myDesign Library
Figure 2-44. Pasting Cells into the myChip Library
6. Optional — After copying data from one library to another and setting up the project,
you may wish to clean up the object list in the Project Navigator tab. To do this:
a. Select myDesign in the Object column of the Project Navigator tab.
b. Right-click and select Close Hierarchy. This does not remove any of the data from
disk. It simply removes the object from the displayed hierarchies.
c. Repeat for the generic13 library.
Front-End Design
Related Topics
Front-End Design

This procedure shows how to capture a transistor-level schematic for the inv1 and nand2 cells.
You can create a new schematic by starting with a new cell or adding it to an existing cell that
may have a behavioral view.
Prerequisites
• Successful completion of Creating a Schematic Sheet from a Symbol.
Procedure
1. Start the Pyxis Project Manager:
% dmgr_ic
2. Expand the myChip library in the Object pane and select the delay_block cell. In the
right-side pane of the Project Navigator tab, several available views for this cell are
displayed.
3. From the view list, right-click the schematic view and select Open > Schematic Editor.
This opens the circuit schematic captured in “Creating a Schematic Sheet from a
Symbol” on page 39. You can also double-click the schematic view to open it.
4. Click the INV11 symbol and right-click to select Open Down > Choose Model (this is
found at the bottom of the popup). This opens the Open Down window, shown in
Figure 2-45.
5. Review the contents of the Open Down window. Notice that the different views for the
inv1 cell are listed in the Unit Type column. The schematic view is missing.
6. Enable the New sheet radio box and click OK. This opens a new schematic sheet in new
tab in the Pyxis Schematic tool. The cell’s ports are placed in the schematic.
Figure 2-45. Creating a New Schematic View for inv1
Front-End Design
7. Place MOSFET transistors in the schematic as follows:

a. Click the Add Instance button ( ). This opens the File Browser window.
b. In the File Browser window, scroll down the Object list and select the generic13
technology library (this should be the last entry under myProject). When you select
the PDK, the contents appear in the right pane.
c. In the right window pane, double-click the symbols sub-folder ( ). This opens
the sub-folder and shows its contents. There are a few devices listed. See Figure 2-
46.
Figure 2-46. Device Symbol List for generic13 PDK
d. Select the nmos symbol and click OK. This closes the File Browser window,
changes the focus back to the schematic sheet, and shows an nmos symbol which
moves with the cursor.
e. Place the nmos device close to the Ain pin.
f. Press Escape to exit the device placement mode.
g. With the nmos highlighted, type Q to open the Edit Object window. See Figure 2-47.
Change the value of the Width field to 1.3u from the default, press Return, and click
OK.
Front-End Design
Figure 2-47. Editing Object Properties for nmos Device
h. Repeat steps a to f for placing a pmos transistor.

i. Use step g to change the Width value for the pmos transistor to 2.6u.
8. Complete the wiring for the circuit, as shown in Figure 2-48. You may use the Add
Wire button ( ) to add wires, or you may click each diamond shape on a device pin
and drag the cursor to connect to other pins.
Figure 2-48. inv1 Transistor-Level Schematic
Front-End Design
9. Add net names to the power and ground nets, as follows:

a. Select the unnamed net connected to the pmos device (connecting the source and
bulk pins). This highlights the net.
b. Click the Set Net Name button ( ). This opens the ADDPRTH prompt.
c. Refer to Figure 2-49. Enter the name vdd_imp (implicit power) in the Property Value
field and click OK.
Figure 2-49. Adding Net Name for Implicit vdd_imp Power Pin
d. Using steps a to c, add the vss_imp net name to the unnamed net connected to the
nmos device (connecting the source and bulk pins). The schematic should resemble
Figure 2-48.
e. After creating the implicit power and ground nets, create the implicit pins as follows:
i. From the pulldown menu, select Add > Create Implicit Pins. This opens the
Create Implicit Pins window, shown in Figure 2-50.
ii. Enable both pins by selecting both checkboxes, then click OK to close the
window and return to the schematic.
Figure 2-50. Creating Implicit Power and Ground Pins
f. Click the Check/Save button ( ). This opens a report window which shows any
errors or warning found during the schematic checking process.
10. Use steps 4 through 9 to complete the transistor-level schematic for the nand2 cell. The
schematic should resemble Figure 2-51.
Use the same Width values from the inv1 cell (nmos width of 1.3u, pmos width of 1.3u
with fingers set to 2). Save the schematic using the Check/Save button ( ).
Front-End Design
Figure 2-51. nand2 Transistor-Level Schematic
11. In the Pyxis Schematic tool, select the delay_block schematic from the available tabs.
See Figure 2-52.
Figure 2-52. Selecting delay_block from Open Schematics
12. In the delay_block schematic, select all cell instances of both the nand2 and inv1 cells.
Do this by selecting the area around the cells with your mouse or use Shift-Left-Click to
select the instances individually.
Front-End Design
13. From the pulldown menu, select Edit > Update > Auto. This updates the delay_block
schematic, showing the implicit power and ground pins associated with each cell.
Figure 2-53.
14. Add two wires to the delay_block schematic to represent the implicit power (vdd_imp)
and ground (vss_imp) nets. Use the Add Wire ( ) and Set Net Name ( ) buttons to
do this. Figure 2-53.
Figure 2-53. Adding Implicit Nets to delay_block Schematic
15. Save the delay_block schematic by clicking the Check/Save button. Review the report
that opens. There are 2 warnings indicating that vss_imp and vdd_imp are dangling nets.
This is expected because these nets are not connected yet.
Close the Pyxis Schematic tool by selecting MGC > Exit. If a prompt opens, indicating
unsaved work, click OK to save.
Related Topics
Front-End Design
Setting Up and Running a Transistor-Level

Simulation
This procedure shows how to set up an Eldo ADMS simulation for the sim_delay_block circuit.
In “Setting Up and Performing an ADMS Simulation” on page 46, you used logic cell Verilog
views for simulating the circuit. In this procedure, you will use the schematic views while using
the same setup.
Much of the setup for this procedure is dependent on prior procedures. Be sure to complete
those listed below before running this simulation.
Prerequisites
• Successful completion of the following procedures:
o Creating a Simulation Test Bench
o Setting Up and Performing an ADMS Simulation
o Adding Properties to a Design Configuration
o Creating a Transistor-Level Schematic
Procedure
1. Start the Pyxis Project Manager, if it is not open.
2. In the Project Navigator tab select myProject.
3. For this procedure, the cell views have to be registered again. This is due to the changes
made in the symbols as well as capturing the schematics.
Right-click myProject and select Open > Language Interface. This opens the Pyxis
Language Interface window.
4. In the Project Area of the Pyxis Language Interface, select myProject.
5. From the pulldown menu, select Edit > Registration Options. This opens the Project
Registration Options window.
6. In the Additional Symbol Pins section, enter the implicit pin names for inv1 and nand2,
vdd_imp and vss_imp, and enable the Implicit checkbox for both. See Figure 2-54.
Click OK after entering in the pin names.
Front-End Design
Figure 2-54. Entering the Implicit Pin Names in Project Registration Options
7. Click the Register All Models button ( ). This opens the Registration Preview
window. Click the plus sign (+) next to each entry listed in the Design Units pane to see
the contents, as shown in Figure 2-55.
Review the Message Area at the bottom of the Pyxis Language Interface window. A
“Registration complete” message indicates that the symbols are correctly registered.
Figure 2-55. Registration Preview Window for myProject
8. Select MGC > Exit to close the Pyxis Language Interface window.
9. In the Project Navigator tab of the Pyxis Project Manager, select the sim_delay_block
object from the myChip library under myProject.
Front-End Design
10. Two views appear in the right-hand pane: ADMS_0 and schematic. Double-click the
schematic view to open it.
11. When the schematic view opens, click the Enter Simulation Mode button ( ). This
opens the Entering Simulation Mode window.
12. In the Entering Simulation Mode window, select ADMS_0 under the Design
Configuration column and click OK. This changes the Pyxis Schematic tool window
configuration in preparation for running simulations.
13. In the schematic sheet, click the DELAY_BLOCK1 cell to select it, then right-click and
select Change Model > SCHEMATIC.
14. From the icons on the left side of the window, click the Hierarchy Navigator button
( ). Verify that the value in the Language column is set to SCHEMATIC for the
INV11, INV12, INV13, and NAND21 cells.
Explore the circuit hierarchy under DELAY_BLOCK1. To open a hierarchy branch,
click the plus sign (+) to the left of the object. See Figure 2-56.
Figure 2-56. Circuit Hierarchy for DELAY_BLOCK1
Leave the Hierarchy Navigator open or close it by clicking on the X at the upper-right
corner of the pane.
Front-End Design
15. New voltage sources are necessary for the transistor-level circuit. To add the implicit
power supplies, do the following:
a. Click the Simulation Setup button ( ) to open the Setup Simulation window.
b. In the Simulation Panel column, select Forces.
c. In the sim_delay_block schematic view, double-click the DELAY_BLOCK1 cell to
open the schematic.
d. In the DELAY_BLOCK1 schematic, select the vdd_imp and vss_imp wires together
(click vdd_imp to select it, then shift-left-click vss_imp to select both). The nets also
appear in the Selection from Schematic pane of the Setup Simulation window.
e. Select the X_DELAY_BLOCK1.VDD_IMP net in the Selection from Schematic
column. To see the full name of the object, hover the mouse over the wire for a few
moments.
f. In the Source Type column, select DC.
g. In the Magnitude (V/A) field, type in p_vdd and click the Add button ( ). See
Figure 2-57.
h. Select the X_DELAY_BLOCK1.VSS_IMP net, set the DC source value to p_vss,
and click the Add button.
Figure 2-57. Setting Up Sources for vdd_imp and vss_imp
The new sources are added to the Instance name column at the bottom of the
window. See Figure 2-58.
Figure 2-58. Adding Implicit Sources
Front-End Design
i. To complete the implicit source setup, click Apply at the lower-right corner of the
window. Do not close the Setup Simulation window.
16. Select the transistor models necessary for running the Eldo ADMS simulation. Do this
as follows:
a. In the Setup Simulation window, select Libraries in the Simulation Panel column
and click the Import Library button ( ) found below the Model
Scenario pane. This opens the Import Library window.
b. Navigate to the model directory. Do this by typing “$GENERIC13/models” in the
Look in field found at the top of the Import Library window. See Figure 2-59.
c. From the list of files, select lib.eldo.
d. Set the Type to Spice, and click OK. This opens the Edit Model Scenario window.
Figure 2-59. Importing Eldo Simulation Models
e. Review the contents of the Edit Model Scenario window. Enable the checkboxes
shown in Figure 2-60. This activates the typical simulation corner. Click OK to
close the window.
When the Edit Model Scenario window closes, a new entry appears
(default_scenario) in the Scenario Name column of the Model Scenario area in the
Setup Simulation window. See Figure 2-61.
f. Click Cancel in the Setup Simulation window to close it.
Front-End Design
Figure 2-60. Selecting the Typical Simulation Models
Figure 2-61. Reviewing a Scenario Name
17. With the setup complete, run the transistor-level simulation by clicking the Run
Simulator button ( ). The simulation may take a few moments to complete.
18. In the sim_delay_block schematic, use the cursor and Shift key to select the following
nets: tb_enable, tb_ain, and tb_zout.
19. Click the Cross Probe Selected Items button ( ) to view the simulation results. The
results are shown in Figure 2-62.
Using the zooming functions in EZwave, explore the output data. Notice that the
simulations results for the output (tb_zout) are slightly different than results from the
behavioral simulations.
Specifically, in the transition regions (from low to high and high to low), there are
overshoot and undershoot artifacts. These are due to using the transistor models,
showing a non-ideal response.
Close the EZwave application by selecting File > Exit.
20. Close Pyxis Schematic and Pyxis Project Manager selecting MGC > Exit in each
window.
Front-End Design
Figure 2-62. Transistor-Level Simulation Results
Related Topics
Back-End Design Flow
Chapter 3
Back-End Design
The back-end design flow and procedures for the Pyxis Custom Design Platform are as follows:
Creating a Layout Cell View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Setting Up Compatibility Mode For Performing Layout. . . . . . . . . . . . . . . . . . . . . . . . . 88
Creating Geometries in a Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Setting Up Schematic Driven Layout (SDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Generating a Cell Layout from a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Generating a Top-Level Layout with Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Running Calibre nmDRC for Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Running Calibre nmLVS for Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Performing Parasitic Extraction for a Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 3-1 shows the back-end design flow and how these topics connect with specific steps.
Note
Before proceeding with any of the layout procedures in this chapter, review the Pyxis
Layout Quick Reference Card, found in Appendix B. This overview of common Pyxis
Layout commands, palettes, and keybindings is helpful in selecting how to perform an
operation. For example, to copy a polygon, you have an option to use a keybinding, a
menu button, or a Pyxis Stroke. Select methods that are comfortable and fit within your
work flow.
Back-End Design
Figure 3-1. Back-End Design Flow
Front-End Design
Complete
• Creating a Layout Cell

View
• Setting Up Floorplan Cell/Block
• Creating Geometries in
Compatibility Mode For
a Layout
Performing Layout
• Setting Up Schematic
Driven Layout (SDL) Cell/Block Layout
• Generating a Cell • Running Calibre
Layout from a nmDRC for Layouts
Schematic
Physical • Running Calibre
nmLVS for Layouts
Verification
• Performing Parasitic
Extraction for a Layout
Parasitic
Re-simulation
No Results
OK?
Yes
• Generating a Top-
Top-Level Layout Level Layout with Cells
Top-Level Physical
Verification
Create MEBES
Database
Back-End Design
Complete
Back-End Design
Creating a Layout Cell View

This procedure describes how to create a layout cell view, prior to drawing layout objects.
It is possible to create a layout view for a cell or as a stand-alone design object. In this
procedure, you create a new category for organizing layout templates, then add a logic cell
layout template for future use.
Prerequisites
• Disk space for your new logic library.
Procedure
1. Start the Pyxis Project Manager from your home directory:
% dmgr_ic
Caution
Do not start Pyxis Project Manager from inside an existing hierarchical design directory,
such as a project, external library, logic library, technology library, or any location where
there is an existing mgc_location_map file. Starting the Pyxis Project Manager this way
results in errors inside location map files.
2. If you have completed the procedures in “Front-End Design” on page 27, then proceed
to Step 4. Otherwise, start with Step 3.
3. If you are only interested in physical layout and verification topics, then navigate to the
correct directory, as follows:
a. In the Pyxis Project Manager, click the Open button ( ).
b. In the Look in field, type the path to the layout portion of the project:
<quick_start_path>/layout_start/
c. Click OK to close the Open window. The myProject hierarchy appears in the Project
Navigator tab of the Pyxis Project Manager.
4. In the myProject hierarchy, select the myChip library. See Figure 3-2.
Back-End Design
Figure 3-2. Opening the myChip Design Library
5. Click the New Category button ( ). This opens the New Category window.
6. In the Category name field, type myTemplates and click OK. A new category icon
appears in the myChip library hierarchy, shown in Figure 3-3. Select the myTemplates
category.
Figure 3-3. Creating a New Category
7. Click the New Layout button ( ). This opens the New Layout window.
8. In both the Layout name and Cell name fields, type logicCell and click OK. See
Figure 3-4.
Figure 3-4. Creating a New Layout Cell
9. The Pyxis Layout window opens once you click OK in the New Layout window.
Additionally, a different New Layout window opens, showing cell information and other
options. See Figure 3-5.
Back-End Design
Figure 3-5. Pyxis Layout Tool
Review the information in the Cell Information section of the New Layout window. Do
not make any changes. Click OK to close it. The logicCell layout opens in the Pyxis
Layout tool.
This ends the procedure. If you are proceeding to “Creating Geometries in a Layout” on
page 92, do not close this layout view.
If you are stopping at this point, click the Save Layout button ( ). Once the layout has
been saved, from the pulldown menu MGC > Exit to close and exit Pyxis Layout.
Related Topics
Setting Up Compatibility Mode For Performing Layout
Creating Geometries in a Layout
Back-End Design
Setting Up Compatibility Mode For Performing

Layout
Use this procedure to set up Compatibility Mode in Pyxis Layout. The compatibility mode
makes it possible to use keyboard shortcuts and mouse strokes found in other layout editors.
Prerequisites
• Successful completion of “Creating a Layout Cell View” on page 85, or an open session
of Pyxis Layout.
Procedure
1. If you closed the logicCell layout view, do the following:
a. Start the Pyxis Project Manger.
b. Select myProject > myChip > myTemplates > logicCell and double-click the layout
view to open it. This opens the cell in the Pyxis Layout tool.
2. Select MGC > Setup from the pulldown menu to open the Setup Preferences window,
shown in Figure 3-6. The Display, Editing, Behavior, and Selection options are
modified for Compatibility Mode.
Figure 3-6. Setup Preferences Window
Back-End Design
3. Click the Display icon. In the Objects tab of the Display pane, enable the Text Origin
option, shown in Figure 3-7.
Figure 3-7. Setting Up Display Options for Compatibility Mode
4. Click the Editing icon and disable Selection-based editing, Auto select, and
Split MOS devices on move, as shown in Figure 3-8.
Figure 3-8. Setting Up Editing Options for Compatibility Mode
Back-End Design
5. Refer to Figure 3-9. Click the Behavior icon. In the General tab of the pane, do the
following:
a. Enable the Target Object, Start commands at cursor (in-fix), Repeat last
command, and Automatically resync data when peeking options.
b. Disable Popup menu (RMB).
Figure 3-9. Setting Up Behavior Options for Compatibility Mode
6. Click the Selection icon and enable the Point inside option, shown in Figure 3-10.
Figure 3-10. Setting Up Selection Options for Compatibility Mode
Back-End Design
7. Click OK at the bottom of the Setup Preferences window to apply the changes and exit
the form.
Related Topics
Setting Up Schematic Driven Layout (SDL)
Back-End Design

This procedure demonstrates how to use basic layout functions, such as placing and modifying
polygon shapes, to create a logic cell template for future use. The logicCell layout view from
the previous procedure is used as the starting point.
Prerequisites
• Successful completion of “Creating a Layout Cell View” on page 85.
Procedure
1. If you closed the logicCell layout view, do the following:
a. Start the Pyxis Project Manger.
b. Select myProject > myChip > myTemplates > logicCell and double-click the layout
view to open it. This opens the cell in the Pyxis Layout tool.
2. Enlarge the Pyxis Layout window by clicking the lower-right-hand corner of the
window and dragging it. See Figure 3-11.
Review the Pyxis Layout window. On the left side of the layout area are several buttons
for editing the layout. On the right side of the layout area are several palettes: Layer
Palette, Layer Appearance, Layer Attributes, Select Filter, and IC Palettes.
To expand a palette for viewing, hold the cursor over the palette title, as shown in
Figure 3-12.
The plus marker (+) in the middle of the layout drawing area is the origin (0, 0).
Note
The layout-related steps in this and subsequent procedures use the compatibility editing
mode. Keyboard shortcuts and mouse operations are presented using this mode. Ensure
that you have enabled compatibility mode, using “Setting Up Compatibility Mode For
Performing Layout” on page 88.
Back-End Design
Figure 3-11. Starting the logicCell Layout
Figure 3-12. Expanding a Palette
Back-End Design
3. Begin drawing the logic cell template by adding well implants. Do this as follows:
a. From the editing buttons, click the Add Rectangle button ( ). The cursor in the
layout area changes to a pencil icon ( ).
b. In the Layer Palette, select the PW (p-well) layer.
c. In the layout area, draw a rectangle by left-clicking at the origin and dragging the
cursor up and to the right to draw the shape.
Notice that the dimensions of the rectangle appear as you draw the shape. Draw the
rectangle to be 2.0 um wide by 5.0 um high.
Tip: After drawing the rectangle, select it and type Q at the keyboard. This opens the Edit
Object window. In the Attribute column, review the Width and Height values. Make any
changes to the dimensions and click OK.
The rectangle will still be selected (highlighted) when you have finished drawing it.
d. With the rectangle still selected, type C to copy the rectangle in place. Move the
cursor off the original shape. You should see a new copy of the rectangle moving
with the cursor.
e. On the keyboard, type V to turn on automatic alignment and move the new rectangle
so that the lower-left corner is aligned with the upper-left corner of the original
rectangle.
f. With the copied rectangle still selected (highlighted), type Q to open the Edit Object
window.
g. In the Attributes column, find Layer Name and change the value to NW (n-well).
Click OK when done. This closes the Edit Object window and changes the copied
rectangle from PW layer to NW layer. See Figure 3-13.
Back-End Design
Figure 3-13. Drawing P-Well and N-Well Areas for logicCell Template
4. Add power supply rails to the cell template as follows:

a. In the Layer Palette, select the M1 layer. You may need to scroll down the layer list.
b. Click the Add Rectangle button ( ). Align the cursor with the top-left corner of
the n-well rectangle and draw an M1 rectangle.
Draw the M1 rectangle as wide as the n-well region and 0.5u high. Type V on the
keyboard to turn on automatic alignment and place the rectangle.
As necessary, use the Edit Object window (type Q) to edit the size of the M1
rectangle.
c. Using the method in Step 3, copy and place another M1 rectangle in the lower
portion of the p-well region. Refer to Figure 3-14 for its placement.
Back-End Design
Figure 3-14. Placing Power Rails in the logicCell Template
5. Place well connections in the p-well and n-well region as follows:

a. In IC Palettes, click the Easy Edit button, shown in Figure 3-15. This changes the
palette name to Easy Edit and shows a set of editing buttons.
Figure 3-15. Selecting the Easy Edit Menu
b. Select the M1 rectangle drawn in the n-well region.

c. In the Easy Edit palette, scroll to the Via button and select Via > Fill Selected. This
opens the ICdevice Shape Via window, shown in Figure 3-16.
d. From the list of options, select m1nwell. Do not change the Subtype or Overlap
type fields. Click OK.
Back-End Design
Figure 3-16. Selecting N-well contacts for N-well Region of logicCell Template
e. Select the M1 shape in the p-well area. Use steps c and d to place p-well contacts
(m1psub in the ICdevice Shape Via window).
The completed logicCell layout is shown in Figure 3-17. To view all of the layers in
the layout, type Shift+F (show hierarchy). To hide the hierarchy, type Control+F.
Figure 3-17. Completed logicCell Template
Back-End Design
6. Optional — Refer to Figure 3-18. The n-well area associated with the placed well
contacts extends over the edge of the n-well region and alters the bounding box for the
cell. To clean up the cell layout, you can do the following:
a. In the pulldown menu, click Select > Select > Edge. This opens the SEL ED prompt
and enables selection of edges on polygons.
b. Select the right edge of the n-well rectangle.
c. Type S (stretch) on the keyboard to begin stretching the selected edge.
d. Align the left edge of the n-well rectangle with the left edge of the n-well area
associated with the placed contacts.
e. Repeat steps a through d for the right edge.
f. Notice that you must now align the left and right edges of the p-well region with the
left and right edges of the n-well region. Follow steps a through e to complete this.
The final layout is shown in Figure 3-18.
Figure 3-18. Finalizing the logicCell Layout
7. Save the layout by clicking the Save Layout button ( ).
Back-End Design
8. Before closing the layout, run Calibre nmDRC to ensure the cell has been drawn
correctly. Follow the instruction in “Running Calibre nmDRC for Layouts” on
page 123.
9. If necessary, make any corrections to the layout and save it again. Complete a final DRC
run to ensure the cell is clean.
10. Close the layout by selecting MGC > Exit. This closes the Pyxis Layout tool. Use the
logicCell template when drawing the layout for the nand2 and inv1 cells.
This completes the procedure.
Related Topics
Back-End Design

This procedure briefly describes how to configure Schematic Driven Layout (SDL) for
performing assisted layout.
For a detailed description of SDL operations and capabilities, refer to Schematic Driven Layout
Editing Operations in the Pyxis Layout User’s Manual.
Prerequisites
• Successful completion of “Creating a Transistor-Level Schematic” on page 70.
Procedure
1. Start the Pyxis Project Manager and navigate to myProject > myChip > inv1.
2. Select the inv1 cell in the Project Navigator tab.
3. Click the New Layout button ( ). This opens the New Layout window.
4. Click OK to accept the values for Layout name and Cell name. The Pyxis Layout
window opens first, followed by a different New Layout window which shows cell
information and available options.
Click OK in this window to accept the default settings and close it. The inv1 schematic
and a blank layout open.
5. On the pulldown menu, select Setup > SDL. This opens the Setup SDL window.
Back-End Design
6. For this step, refer to Figure 3-19 and do the following:
Figure 3-19. Setting up SDL
a. In the Setup SDL window, click the Prompt user radio box.
b. In the Setup Values selection list, scroll to and select SDL Port Styles, then click
Setup. This opens the Set Active Port Style window.
c. In the Set Active Port Style window, select the M1 layer.
d. In the Width and Height fields, enter 0.26 (for 0.26 um). This sets the size of the
names ports when you place them in the layout.
e. Click OK in the Set Active Port Style window to save the size settings and close the
window.
f. Click OK in the Setup SDL window to complete the setup process.
This ends the procedure. If you are proceeding to “Generating a Cell Layout from a
Schematic” on page 102, leave the inv1 cell layout open in the Pyxis Layout window.
Related Topics
Back-End Design
Generating a Cell Layout from a Schematic

This procedure shows how to complete a cell layout using Schematic Driven Layout (SDL) for
the inv1 logic cell.
The flow for completing the layout is:
• Import the logicCell template.
• Flatten the template in preparation for editing.
• Place instances of devices.
• Place ports and edit implicit ports as necessary.
• Use IRoute to connect devices and nets.
• Perform physical verification.
Prerequisites
• Successful completion of “Setting Up Schematic Driven Layout (SDL)” on page 100.
Procedure
1. If you have not done so, complete Setting Up Schematic Driven Layout (SDL).
2. In the Pyxis Layout workspace, two windows are open in the workspace:
• /Inv1 — The schematic window.
• IC 0: Inv1 > Inv1… — The layout window.
You may need to move and resize the windows in the workspace to make both of them
visible. For ease of use, modify the workspace to look like Figure 3-20.
Once you have set up the windows as shown, you can resize the Pyxis Layout window.
The sub-windows will automatically resize.
Note
When SDL is invoked, the objects in the schematic and layout windows are coupled. That
is, if you select a device, net, or pin in the schematic, it is also highlighted in the layout
window.
Back-End Design
Figure 3-20. Setting Up the Pyxis Layout Window
3. Click the Add Instance button ( ). This opens the File Browser window.
4. Refer to Figure 3-21. In the File Browser window, navigate to myProject > myChip >
myTemplates and select the logicCell layout view. Click OK to prepare for placing the
logicCell template in the inv1 layout view.
Back-End Design
Figure 3-21. Selecting the logicCell Template for Placement in inv1 Layout
5. In the inv1 layout view, the outline of the logicCell appears and moves with the cursor.
Place the lower-left corner of the cell on the origin and left-click the mouse, then type
Esc to disable further placements.
You may need to zoom in to place the cell directly on the origin coordinate (0, 0). Zoom
in around the origin by using the default Pyxis Strokes. See the Pyxis Layout Quick
Reference Card card found in Appendix B.
You can also zoom in by using the scroll-wheel on your mouse (if it has one).
6. Select the logicCell instance and in the pulldown menu, select Edit > Flatten. This
opens the FLA prompt, shown in Figure 3-22. Accept the default settings by clicking
OK.
Figure 3-22. Flatten Object Prompt
Note
The logicCell template is used as a starting point for the inv1 and nand2 layouts. Maintain
the via structures as they are to be able to stretch and modify them as necessary. Do not
completely flatten the template layout.
7. Click within the schematic workspace. Notice that the palette area changes and the DLA
Logic palette appears, shown in Figure 3-23.
Back-End Design
Figure 3-23. DLA Palette
8. With the schematic window selected, click the Inst button ( ) in the DLA palette.
Notice that several things happen in preparation for placing a device in the layout (refer
to Figure 3-24):
• The focus changes to the layout window.
• The first placed device in the schematic, M1 (nmos) is highlighted.
• An nmos device layout appears in the layout window, ready for placement.
Figure 3-24. Placing Devices in the inv1 Layout
Place the nmos device in the p-well area by left-clicking, as shown in Figure 3-24.
Back-End Design
9. After the nmos device is placed, the pmos device is highlighted in the schematic window
and the equivalent layout view appears in the layout window.
Left-click within the n-well region to place the pmos device. Notice that there are
highlighted lines (fly lines) that virtually connect the gates and drains of both devices,
shown in Figure 3-25.
Figure 3-25. Placing the pmos Device in inv1 Layout
10. Click within the schematic window, then click the Port button ( ) in the DLA
Logic palette.
Notice that several things happen in preparation for placing ports in the layout (refer to
Figure 3-26):
• The focus changes to the layout window.
• The vss_imp net is highlighted in the schematic.
• The nmos device is highlighted.
Back-End Design
• A port named vss_imp appears in the layout window, virtually attached to the nmos
device. For the port, M1 stands for the “metal 1” layer.
Tip: You can switch the port layer by pressing the Spacebar key.
Figure 3-26. Placing Ports in the inv1 Layout
11. Refer to Figure 3-27 and do the following:

a. Place the vss_imp port on top of the lower rail, near the nmos. Left-click to place the
port.
b. The vdd_imp port appears in the layout after you place the vss_imp port. Left-click
to place this port on the top rail, near the pmos.
c. The Ain and Zout ports appear. Place these as shown in Figure 3-27.
Notice that all of the ports are generated with the M1 layer. Also, each port is
virtually connected to device pins.
Note
During port placement, device pins that are connected to a port are highlighted until the
port is placed. This visual cue helps you see the connections between device pins and the
placed ports. Once the port is placed, the highlighting moves to the next set of
connections until all ports are placed.
Back-End Design
Figure 3-27. All Ports for inv1 Layout
12. Edit the ground and power port names as follows:

a. Select the vss_imp pin.
b. From the pulldown menu, select Connectivity > Port > Make Port:. This opens the
Make Port window.
c. In the Attributes column, find Port Name row. The current value is /vss_imp.
Remove the forward-slash (/) from the port name.
d. Refer to Figure 3-28. Click the dropdown list in the Port Type & Direction row.
Change the value from Signal In to Ground In and click OK.
Note
Editing the vss_imp and vdd_imp port definitions is necessary because they are implicit
ports. This is not necessary if ports are explicitly defined in the schematic (that is,
associated with port symbols).
Back-End Design
Figure 3-28. Editing Port Definitions
e. Repeat steps a through d for the vdd_imp port in the layout. Remove the forward
slash (/) and change the Port Type and Direction to Power In.
13. For easier routing in the layout, modify the vss_imp and vdd_imp ports in the layout.
Stretch each port to cover the well contact areas. Refer to Creating Geometries in a
Layout, Step 6 to learn how to select and stretch edges of a polygon. The modified and
highlighted port shapes are shown in Figure 3-29.
Figure 3-29. Stretching vdd_imp and vss_imp Ports
Back-End Design
14. Click within the layout window and from the pulldown menu, select Tools > IRoute.
This opens the IRO prompt in Pyxis Layout, shown in Figure 3-30.
Figure 3-30. IRoute Prompt in Pyxis Layout
Additionally, the following happens:

• In the layout window, the cursor changes to show a small square of M1 layer. If you
hover the cursor over one of the ports, the port name appears automatically.
• An IRoute message appears in the Message Area indicating that you can begin
routing:
Note: Use left mouse button to start routing.
You can exit IRoute by typing Esc at any time. After you exit, restart IRoute by
selecting Tools > IRoute.
15. With IRoute started, route the nets in the layout as follows:
a. In the layout window, move the cursor on top of the pmos transistor gate pin. Notice
that the cursor now shows the associated net name and a routing layer.
b. If the routing layer is not POLYG, press Spacebar until the label next to the cursor
changes to POLYG.
c. See Figure 3-31. Left-click the pmos gate pin and drag the mouse to the gate of the
nmos transistor. Left-click to complete the route with IRoute.
Figure 3-31. Routing the Ain Signal with IRoute
Back-End Design
d. Refer to Figure 3-32. Move the cursor to the Ain pin. If necessary, press the
Spacebar to switch to the M1 drawing layer and do the following:
i. Left-click the Ain pin to start the route.
ii. Drag the cursor to the right of the pin and right-click. This opens a menu window
showing routing options.
iii. Select the Set Wire Width (w) option. This opens the Set Wire Width dialog
box.
iv. In the Net width field enter 0.26 (0.26 um). This matches the width of the Ain
pin. Click OK and notice that the width of the drawn path changes to match the
port width.
Figure 3-32. Accessing Options While Routing
e. Refer to Figure 3-33. Prepare the Ain net for routing to the POLYG net connecting
the pmos and nmos transistors gates as follows:
i. Extend the cursor just beyond the Ain port.
ii. Type V on the keyboard to turn on the via generator.
iii. Press the Spacebar until the via type changes to M1-POLYG.
Figure 3-33. Placing Gate Poly Contact
Back-End Design
f. See Figure 3-34. Drag the M1-POLYG via next to the POLYG net connecting the
two gates until a check mark appears. This is a visual cue, indicating that the via is
placed correctly according to DRC rules.
Left-click to place the via and complete the route.
Figure 3-34. Completing the Route to pmos Gate
g. Refer to Figure 3-35. Using steps a through f, complete the remaining connections
for the inv1 layout. Keep in mind the following:
• Use the Set Width option to set path widths to 0.26 um.
• Use M1 layer for routing. Other layers are not necessary.
• Remember that the check marks appear when a path is routed correctly.
Do not change any of the default values. Click OK to apply the text to ports and
close the window.
Back-End Design
Figure 3-35. Completed inv1 Layout
h. Complete the layout by adding text to ports. Do this by selecting Add > Text on
Ports from the pulldown menu. This opens the Add Text on Ports window, shown in
Figure 3-36.
Figure 3-36. Adding Text to Ports for LVS Checking
Back-End Design
Note
In the Add Text On Ports window, the default values are defined by settings in the Pyxis
PDK. If default values are not defined, then provide them.
Also, if text that is already placed is moved or modified, a new Add > Text on port or
$add_text() command will completely replace the old placement.
16. Click the Save Layout button ( ) to save the layout.

17. Complete physical verification checks (DRC and LVS) as discussed in “Running
Calibre nmDRC for Layouts” on page 123 and “Running Calibre nmLVS for Layouts”
on page 129.
18. If the verification results are clean, save the layout again and exit by selecting MGC >
Exit.
19. Optional — A layout for the nand2 circuit is included in the project data in myProject >
myChip > nand2 > layout_mgc. Optionally, you may wish to perform its layout using
the steps shown in this procedure.
Related Topics
Back-End Design
Generating a Top-Level Layout with Cells

This procedure shows how to complete a layout by placing existing cells. Steps are also
included for editing a cell in place, as it may be necessary in some instances.
Prerequisites
• Successful completion of “Generating a Cell Layout from a Schematic” on page 102.
• A completed nand2 cell layout or access to the nand2_mgc layout in the project data.
Procedure
1. Start the Pyxis Project Manager and navigate to myProject > myChip > delay_block.
2. With the delay_block cell selected in the Project Navigator tab, click the New Layout
button ( ). This opens the New Layout dialog window.
3. Accept the default Layout name and Cell name values in the New Layout dialog
window by clicking OK. This opens the Pyxis Layout window with another New
Layout dialog window, showing cell information.
4. Accept the default values in the New Layout window by clicking OK.
5. Start the Setup SDL window by clicking the Setup SDL button ( ).
6. Set up the SDL options as shown in Step 6 of Setting Up Schematic Driven Layout
(SDL).
7. Set up the Pyxis Layout window environment with the schematic and layout windows
placed side-by-side, as shown in Figure 3-20 on page 103.
8. Click within the schematic window and notice that the DLA Logic palette appears in the
palette area.
9. With the schematic window selected, click the Inst button ( ) in the DLA palette.
10. Refer to Figure 3-37. Place the layouts of cells as follows:
Note
From this point, the procedure uses the nand2_mgc layout that is included with project
data. If you have laid out the nand2 cell as part of using the Quick Start data, then use that
layout.
If you are using your own nand2 cell layout, be aware that Pyxis Layout may issue a
warning message that no instances are placed. To avoid this, ensure that the project
directory containing the inv1 and nand2 layout views is specified in your SDL search
path. To set the search path select Setup > SDL and modify the Search Path field as
necessary.
Back-End Design
a. In the schematic window, left-click the nand2 cell. This opens the Create/Browse for
Cell window. Click the Browse for cell button. This changes the content of the
Create/Browse for Cell window.
b. Click the Browse button next to the Cell Name field in the Create/Browse for Cell
window. This opens the Cell Navigator window.
c. In the Cell Navigator window, browse to the nand2_mgc layout and click OK to
close the window.
d. In the Create/Browse for Cell window, click OK to close the window. In the layout
window the outline of the cell appears.
e. Place the nand2_mgc cell in the delay_block layout by left-clicking within the layout
space (this step is not annotated in Figure 3-37).
Figure 3-37. Browsing for Cells in Pyxis Layout
Back-End Design
11. When the nand2_mgc layout is placed, two things happen:

• In the schematic window, one of the inv1 instances is highlighted.
• The Create/Browse for Cell window opens again.
In the Create/Browse for Cell window, click the Browse button ( ) and navigate to the
layout view for the inv1 cell.
This occurs two more times, once for each remaining instance of the inv1 cell. Place the
cells according to the order in which they appear in schematic. The initial cell placement
is shown in Figure 3-38.
12. Place the input and output ports as follows:
a. Click within the schematic view.
b. In the DLA Logic palette, click the Port button ( ). In the schematic window,
the Zout pin is highlighted, and a corresponding pin appears in the layout window in
the M1 layer.
c. To place the pin, click within the layout window, next to the output of the last inv1.
The next pin automatically appears in the layout space.
d. Place the Enable and Ain pins as they become active in the layout. The initial pin
placement is shown in Figure 3-38.
Figure 3-38. Placing Cells in the delay_block Layout
13. Abut the cells next to each other as follows:

a. Type Shift-F to view the full cells.
b. In the Layer Palette, type D to show only the drawn layers in the layer list.
Back-End Design
c. In the V column (layer visibility) of the Layer Palette, turn off all layers except OD
and M1. The new Layer Palette configuration is shown in Figure 3-39.
Figure 3-39. Configuring the Layer Palette
The resulting layout view is shown in Figure 3-40.
Figure 3-40. Simplified View of delay_block Layout
d. Using the Move command (select an instance and type M on the keyboard), abut the
cells together so that the diffusion regions (OD layer) are touching. The resulting
layout is shown in Figure 3-41. For clarity, the M1 layer has been turned off in the
Layer Palette.
Back-End Design
Figure 3-41. Abutting Cells in the delay_block Layout
14. Using the Layer Palette, turn on all drawn layers by clicking the corresponding
checkboxes in the V column or by clicking the dash icon (-) at the top of the V column.
15. Optional — With the cells abutted, the power and ground connections are aligned. Most
of the circuit’s output to input connections are also aligned. However, the connection
from the nand2_mgc output to first inv1 input may not be aligned. To modify this, you
can edit the nand2_mgc cell layout in place as follows:
a. Select the nand2_mgc cell in the layout and type X on the keyboard. This changes
the scope of the layout view to the nand2_mgc cell and allows edits inside the cell.
You cannot make edits in the rest of the delay_block layout.
Note
Visual cues in the Pyxis Layout window show the active, editable context of a layout. For
example, if you examine the window banner for the Pyxis Layout tool, the title indicates
that you are editing the nand2_mgc cell in the delay_block circuit (“IC 0: delay_block >
nand2_mgc …”).
Back-End Design
b. Remove the nets connecting the Ain and Bin pins to the poly gate connections. Also
remove the poly contacts.
c. Swap the locations for the Ain and Bin pins.
d. Remove the Zout net attached to the drain pin of the nmos and pmos devices.
e. Move the Zout pin to the cell’s edge and align it with the Ain pin of the inv1 layout.
f. To change the pin name locations, from the pulldown menu select
Connectivity > Ports > Add Text On Ports and click OK in the Add Text On Ports
window. See Figure 3-42. The Zout pin of the nand2_mgc cell is superimposed on
the Ain pin of the inv1 cell, making it difficult to see.
Figure 3-42. Removing Connections in the nand2_mgc Cell
g. Select Tools > IRoute > IRoute from the pulldown menu.
h. Complete the connections in the cell as shown in Figure 3-43. For details about
using IRoute, refer to Step 15 of “Generating a Cell Layout from a Schematic”.
Figure 3-43. Adding Connections in the nand2_mgc Cell
Back-End Design
i. Save the nand2_mgc layout by clicking the Save Layout button ( ) and type
Shift-B to return to the delay_block context for editing layout.
16. Refer to Figure 3-44. Add power and ground nets as follows:
a. Draw a rectangle in the M1 layer that overlays the vdd_imp rails of the nand2_mgc
and inv1 cells. Extend the left and right edges of the rectangle beyond the outer
boundaries of the cells.
b. Copy the rectangle and place it on top of the vss_imp rail.
17. Use IRoute to complete the remaining net routing for the delay_block layout. For details
about using IRoute, refer to Step 15 of “Generating a Cell Layout from a Schematic”.
Figure 3-44. Final Layout for the delay_block Cell
18. Complete the layout by adding text to ports. Do this by selecting Add > Text on Ports
from the pulldown menu. This opens the Add Text on Ports window, shown in Figure 3-
36. Click OK to reposition port names, in preparation for LVS checks.
19. Complete physical verification checks (DRC and LVS) as discussed in “Running
Calibre nmDRC for Layouts” on page 123 and “Running Calibre nmLVS for Layouts”
on page 129.
20. If the verification results are clean, save the layout and exit by selecting MGC > Exit.
Back-End Design
Related Topics
Back-End Design
Running Calibre nmDRC for Layouts

This procedure shows how to complete the Design Rule Checks (DRC) using Calibre nmDRC.
Steps are also included for excluding certain checks, as this may be necessary in some
instances.
This procedure uses the nand2_mgc layout. You can substitute another layout as necessary.
Note
If you are using a different technology than the generic13 PDK, which accompanies the
Quick Start, specify the Calibre nmDRC rule file in the DRC Rules File field, accessible
by clicking the Rules button in the Calibre Interactive nmDRC window. Refer to Step 4
of this procedure.
Prerequisites
• A Calibre nmDRC/nmDRC-H license.
• Access to an existing layout, or successful completion of either “Generating a Cell
Layout from a Schematic” on page 102 or “Generating a Top-Level Layout with Cells”
on page 115.
Procedure
1. Start the Pyxis Project Manager (dmgr_ic).
2. Navigate to myProject > myChip > nand2 and open the nand2_mgc layout. This opens
the layout in the Pyxis Layout tool.
3. From the Pyxis Layout window pulldown menu, select Tools > Calibre > Run DRC.
This starts a Calibre Interactive nmDRC session. See Figure 3-45.
Note
It is also possible to run Calibre nmDRC and other Calibre tools in command-line or
batch mode. However, throughout this document, all Calibre-related procedures use
Calibre Interactive, accessible through the Pyxis Layout tool.
Back-End Design
Figure 3-45. Running Calibre nmDRC
4. Refer to Figure 3-46 and review the Calibre Interactive - nmDRC interface.
Figure 3-46. Calibre Interactive - nmDRC Interface
Back-End Design
A detailed discussion of Calibre Interactive functionality is not presented in this

document. Please refer to the Calibre documentation sources cited in Table 1-4 on
page 22. However, please note the following areas in the interface:
1 — Control what is presented in the main pane with these buttons. For example,
since the Rules button is selected, fields for entering DRC rules and the DRC run
directory are shown.
2 — Specify the Calibre nmDRC rules file in this field. You can also control turning
on and off rule checks in this area.
3 — Specify the Calibre nmDRC run directory in this field.
5. Click the Inputs, Outputs, and Run Control buttons and review the contents of each
pane.
In the Outputs pane, the Show Results in RVE box is selected. This means that when
the DRC run is complete, the results browser (Calibre RVE) opens automatically.
6. When you are satisfied with the setup, click the Run DRC button. When the Calibre
nmDRC run is completed, the DRC Summary Report and Calibre RVE windows open.
7. Review the DRC results as follows:
a. Refer to Figure 3-47. Review the contents of the DRC Summary Report. Scroll
through the report to view basic statistics about the verification run. The summary of
the completed checks and generated results (DRC errors) for this layout show one
error.
Figure 3-47. Viewing DRC Summary Results
Back-End Design
b. Review the Calibre RVE window and note the following areas marked in Figure 3-
48:
1 — Use these icons to navigate to the highlighted errors in the layout.
2 — Note the number of errors reported.
3 — Select the type of DRC error from this list. In this case, the rule name
PO.R.2 refers to a poly density check.
4 — View the errors in the layout by clicking the numbers listed in this pane.
5 — Review the rule definitions from the DRC rules file.
Figure 3-48. Reviewing DRC Results with Calibre RVE
c. In the Calibre RVE window, select the forward arrow button ( , in area 1), or click
the highlighted 1 (area 4) to identify the error location in the layout. For this error,
the entire cell is highlighted in the Pyxis Layout window.
The poly density rule checks for a certain level of density in the layout. In this case,
it is best to disable this check.
8. Close the Calibre RVE and DRC Summary Report windows by selecting File > Exit in
both windows.
Back-End Design
9. Disable the density checks for the DRC run as follows:
Note
If you do not have access to a version of Calibre Interactive that includes recipe editing,
you may use the SELECT CHECK SVRF statement in a Calibre nmDRC rule file to
control which checks are executed. For more information, see the Standard Verification
Rule Format (SVRF) Manual.
a. Go to the Calibre Interactive nmDRC window and click the Rules button, if it is not
selected.
b. Click the Edit button to the right of the Check Selection Recipe field. This opens
the Check Selection Recipe Editor window. For the next three steps, refer to
Figure 3-49.
Figure 3-49. Setting up Selections for Calibre nmDRC
c. In the Check Selection Recipe Editor window, click the New button. This opens the
Check Selection New Recipe dialog box.
d. In the New recipe name field, type in a unique recipe name that identifies the DRC
checks without density rules. For example, type in no_density in the field.
e. Click OK to accept the name and close the dialog box.
In the Check Selection Recipe Editor window, the Recipe field changes to
no_density, the custom checking recipe.
Back-End Design
f. At the bottom of the Check Selection Recipe Editor, click the Advanced button.
This collapses the form and presents a more simple view. The resulting view is
shown in Figure 3-50.
Figure 3-50. Simple View of Check Selection Recipe Editor Window
g. In the Exclude section, enable the Checks with density checkbox. This excludes all
density checks from the Calibre nmDRC run.
h. Click OK to close the window. Note that in the Calibre Interactive - nmDRC
window, the text in the Check Selection Recipe field has changed to no_density (or
the user-defined name you have selected).
10. Click the Run DRC button to start the Calibre nmDRC run. Review the results to see
that a poly density violation is no longer reported.
11. If you are satisfied with the DRC results, close the Calibre nmDRC session by selecting
File > Exit in all Calibre-related windows.
Related Topics
Running Calibre nmLVS for Layouts
Calibre DRC RVE Quick Reference
Calibre Interactive and Calibre RVE User’s Manual
Calibre Solutions for Physical Verification
Calibre Verification User’s Manual
Standard Verification Rule Format (SVRF) Manual
Back-End Design

This procedure shows how to complete Layout Versus Schematic (LVS) checks using Calibre
nmLVS.
This procedure uses the nand2_mgc layout. You can substitute another layout as necessary.
Note
Quick Start, specify the Calibre nmLVS rule file in the LVS Rules File field, accessible
by clicking the Rules button in the Calibre Interactive nmLVS window. Refer to Step 4.
Prerequisites
• A Calibre nmLVS/nmLVS-H license.
• Access to an existing layout, or successful completion of either “Generating a Cell
Layout from a Schematic” on page 102 or “Generating a Top-Level Layout with Cells”
on page 115.
Procedure
2. Navigate to myProject > myChip > nand2 and open the nand2_mgc layout. This opens
3. From the Pyxis Layout window pulldown menu, select Tools > Calibre > Run LVS.
This starts a Calibre Interactive nmLVS session. See Figure 3-51.
Note
It is also possible to run Calibre nmLVS and other Calibre tools in command-line or
batch mode. However, throughout this document, all Calibre-related procedures use
Calibre Interactive, accessible through the Pyxis Layout tool.
Back-End Design
Figure 3-51. Running Calibre nmLVS
4. Refer to Figure 3-52 and review the Calibre Interactive - nmLVS interface.
Figure 3-52. Calibre Interactive - nmLVS Interface
A detailed discussion of Calibre Interactive functionality is not presented in this

document. Refer to the Calibre documentation sources cited in Table 1-4 on page 22.
However, please note the following areas in the interface:
Back-End Design
1 — Control what is presented in the main pane with these buttons. For example,
since the Rules button is selected, fields for entering LVS rules and the LVS run
directory are shown.
2 — Specify the Calibre nmLVS rules file in this field.
3 — Specify the Calibre nmLVS run directory in this field.
5. Click the Inputs, Outputs, and Run Control buttons and review the contents of each
pane. Make changes to locations or options as required or accept the current default
values.
In the Outputs pane, the View Report after LVS finishes box is selected. This means
that when the LVS run is complete, the results browser (Calibre RVE) opens
automatically.
6. When you are satisfied with the setup, click the Run LVS button. When the Calibre
nmLVS is completed, the LVS Report File and Calibre RVE windows open.
7. Review the LVS results as follows:
a. Review the contents of the LVS Report File. Scroll through the report to view basic
statistics about the verification run. See Figure 3-53.
Scroll to the bottom of the file to find a summary of matched devices and nets. If
there are any errors in your layout, they will appear as unmatched devices or nets.
b. Review the results shown in the Calibre RVE window. See Figure 3-54. Note the
comparison results are marked with an icon that indicates the checks were
successful. If there are errors, the comparison results will indicate it.
Back-End Design
Figure 3-53. Viewing LVS Report File
Back-End Design
Figure 3-54. Reviewing LVS Results with Calibre RVE
8. To show the effects of an error in the layout while performing LVS, do the following:
a. Close the Calibre RVE and Calibre Interactive windows by selecting File > Exit.
b. In the nand2_mgc layout, remove the vdd_imp connection to the source pin of the
M4 pmos transistor. See Figure 3-55.
c. Save the layout by clicking the Save Layout button ( ).
Figure 3-55. Creating an Error in the nand2_mgc Layout
9. Start Calibre nmLVS by selecting Tools > Calibre > Run LVS in the Pyxis Layout
window pulldown menu.
Back-End Design
10. In the Calibre Interactive nmLVS window, click the Run LVS button. Dialog boxes
prompt you to overwrite the GDS output file and the netlist file. Click OK in both dialog
boxes to generate the new files.
11. Review the LVS Report File. In the INFORMATION AND WARNINGS section at the
bottom of the file, notice the device and net discrepancies. See Figure 3-56.
Figure 3-56. Reviewing LVS the Report File for Errors
12. In the Calibre RVE window, review the Comparison Results tab, shown in Figure 3-57.
Click the expand icon (+) next to the nand2_mgc cell name to expand the comparison
results. Click all of the expand icons to see the complete set of discrepancies.
Figure 3-57. Finding Discrepancies in the nand2_mgc Layout
Back-End Design
13. Click Discrepancy #1 under the Incorrect Nets category. In the lower pane, the details of
the error is reported: missing net. See Figure 3-58.
Figure 3-58. Identifying LVS Errors in the Layout
14. Click Net 5 under the LAYOUT NAME column in the Comparison Results tab. This
changes the configuration of the Calibre RVE window and highlights the problem area
in the nand2_mgc layout view. See Figure 3-59 and Figure 3-60.
Figure 3-59. Viewing the Differences Between the Layout and Schematic
Back-End Design
Figure 3-60. Highlighting Error in nand2_mgc Layout
15. Review the other discrepancies in Calibre RVE and see how they map to the layout
view.
16. Close Calibre RVE and Calibre Interactive, make the correction to the layout to fix the
LVS error, and run Calibre nmLVS again to verify your work.
17. If you are satisfied with the LVS results, close the Calibre nmLVS session by selecting
File > Exit in all Calibre-related windows.
Related Topics
Calibre LVS RVE Quick Reference
Calibre Solutions for Physical Verification
Calibre Verification User’s Manual
Back-End Design
Performing Parasitic Extraction for a Layout

This procedure shows how to complete a parasitic extraction run using Calibre xRC through
Calibre Interactive.
This procedure uses the delay_block layout. You can substitute another layout as necessary.
Note
Quick Start, specify the Calibre xRC rule file in the PEX Rules File field, accessible by
clicking the Rules button in the Calibre Interactive PEX window. Refer to Step 4.
Prerequisites
• A Calibre xRC license.
• One of the following:
o Access to an existing layout that is DRC and LVS clean, or successful completion of
either Generating a Cell Layout from a Schematic or Generating a Top-Level Layout
with Cells.
o A DRC and LVS clean layout for the delay_block cell.
Procedure
2. Navigate to myProject > myChip > nand2 and open the delay_block layout. This opens
3. From the Pyxis Layout window pulldown menu, select Tools > Calibre > Run PEX.
This starts a Calibre Interactive PEX session. See Figure 3-61.
Note
It is also possible to run Calibre PEX (Calibre xRC or Calibre xACT) and other Calibre
tools in command-line or batch mode. However, throughout this document, all Calibre-
related procedures use Calibre Interactive, accessible through the Pyxis Layout tool.
Back-End Design
Figure 3-61. Running Calibre PEX
4. Running parasitic extraction run requires several setup items. A detailed discussion of
Calibre Interactive for parasitic extraction setup is not presented in this document.
Please refer to the Calibre documentation sources cited in Table 1-4 on page 22.
To set up the run for the delay_block layout, refer to Figure 3-62 and do the following:
Figure 3-62. Setting up a Calibre PEX Run
Back-End Design
a. Click the Rules button. Verify that the PEX Rules File and PEX Run Directory
fields are populated with valid paths to the generic13 PEX rules and your run
directory, respectively.
b. In the PEX Rules File area, click the Load button ( ) to load the parasitic
extraction rule file. Notice that the Inputs button changes from red to green text.
c. Click the Inputs button. Refer to Figure 3-63 and do the following:
Figure 3-63. Setting up Inputs for Calibre PEX
i. Click the Layout tab and do the following:

a. In the File field, type the file name for the layout output: delay_block.gds.
b. Make sure the Format selection list is set to GDSII.
c. Make sure that Export from layout viewer option is selected. This
generates a new GDS file from the latest layout.
d. In the Top Cell field, type in delay_block. If you are using another cell, enter
the top cell name here.
ii. Click the Netlist tab and notice that the Files field shows a file name in red. This
indicates the file is not found or does not exist. Do the following:
a. In the Files field, type the netlist file name: delay_block.spi.run.
b. Make sure that the Export from schematic viewer option is selected. This
generates a new source netlist from the latest schematic.
c. In the Top Cell field, type in delay_block. If you are using another cell, enter
the top cell name here.
iii. Do not make changes in the H-Cells, Blocks, or Probes tabs.
d. Click the Outputs button. Review values for the Extraction Mode and Extraction
Type fields. Maintain the defaults for the initial setup.
Optionally, you may change these later as you experiment with parasitic extraction
runs.
The View netlist after PEX finishes option is turned on. This automatically opens
the extracted transistor-level netlist when the parasitic extraction run is successfully
completed.
e. Make the following changes in the Outputs pane:
i. In the Format selection list, select the ELDO option radio button.
Back-End Design
ii. In the Use Names From selection list, select the SCHEMATIC radio button.
With this option, device names from the schematic view are used in the output
netlist.
iii. Select the SVDB tab and enable the Start RVE after PEX selection box.
f. Click the Run Control button. Do not change any values in this pane. However,
review the tabs to become familiar with the information.
5. When you are satisfied with the setup, click the Run PEX button. When the Calibre
PEX run is completed, the extracted netlist (net.dist) opens in the PEX Netlist File
window. Calibre RVE also opens.
6. Refer to Figure 3-64 and review the extracted transistor-level netlist. Two include
statements in the netlist point to the files for the extracted parasitics.
Figure 3-64. Extracted Transistor-Level Netlist
The two files in the .include statements are defined as follows:

• net.dist.pex — Contains circuit models composed of resistors and capacitors that
represent the interconnect nets between devices and cells in the layout. Each net
model is defined in a .subckt block.
• net.dist.DELAY_BLOCK.pxi — Contains extracted coupled capacitors and
instances of the net models defined in the net.dist.pex file.
For the Quick Start data, these files are found in the following location:
<qsg_install_path>/myProject/myChip/delay_block/delay_block.cal
7. Refer to Figure 3-65. To explore the extracted net parasitics do the following:
a. Select the Parasitic heading under the Navigator pane of Calibre RVE and select one
of the listed nets. In this example, Zout is selected.
Back-End Design
b. Right-click the selected net to open the popup menu showing options for viewing the
information for the net.
c. From the popup menu, click Show Detailed Parasitics.
Figure 3-65. Reviewing Detailed Parasitics on the Zout Net
The lower pane shows the extracted parasitic devices for the net. Click the column
headings to sort the data in ascending or descending order.
d. Left-click a parasitic device from the list and right-click to select Highlight Selected
Parasitics. The device is highlighted in the open layout window.
8. Explore the parasitic data. When you have completed the review, close Calibre RVE and
Calibre Interactive PEX by selecting File > Exit from the pulldown menu in each
window.
Back-End Design
Related Topics
Calibre xACT User’s Manual
Calibre xRC User’s Manual
Appendix A
CAD Topics
The follow topics describe how to invoke Pyxis tools and other tools used in the IC design flow
as well as brief introductions for configuration management and project setup.
How to Start Pyxis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
How to Start the Calibre, Eldo, and EZwave Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Pyxis Binary File Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Pyxis Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Pyxis Custom Design Project Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Data Management in the Pyxis Custom Design Platform . . . . . . . . . . . . . . . . . . . . . . . . 149
Note
The topics in this appendix are written for a CAD/EDA engineer who is responsible for
setting up the Pyxis Design Platform. Some of the content may be useful for design and
layout engineers. Please address any questions related to your company’s specific tool
installation practices and tool setup issues to your local CAD team first.
CAD Topics
How to Start Pyxis Tools
How to Start Pyxis Tools

For most users, starting the Pyxis Project Manager is sufficient for accessing and editing a
design.
All design components and design tools, including simulation and physical verification tools,
can be accessed from the Pyxis Project Manager and subsequently through schematic, netlist,
and layout views.
Occasionally, you may need to access a specific tool directly from a UNIX or Linux shell.
Table A-1 shows the command-line invocations for the Pyxis tools presented in this document.
The $MGC_HOME environment variable is set to the location for the executable versions of
the tools.
Note
Unless you are troubleshooting a project-related issue or have a specific purpose for
accessing a Pyxis tool through the shell command, use the Pyxis Project Manager for
accessing design components throughout the modules in this document.
Table A-1. Command-line Invocation for Pyxis Tools

Pyxis Tool Invocation
PyxisTM Custom Router Launches from within Pyxis Layout tool.
Pyxis Design Viewpoint $MGC_HOME/bin/dve_ic
Pyxis Language Interface $MGC_HOME/bin/lmrc_ic
Pyxis Layout $MGC_HOME/bin/ic
Pyxis Netlister $MGC_HOME/bin/icnet
Pyxis Plot Launches from within Pyxis Layout tool.

Pyxis Project Manager $MGC_HOME/bin/dmgr_ic
Pyxis Schematic $MGC_HOME/bin/da_ic
Pyxis Schematic Generator $MGC_HOME/bin/sg_ic
Related Topics
“IC Design Flow Tool Reference” on page 22.
CAD Topics
How to Start the Calibre, Eldo, and EZwave Tools
How to Start the Calibre, Eldo, and EZwave

Tools
It is a best practice to start the simulation and physical verification tools from the appropriate
Pyxis tool.
Occasionally, you may need to access a specific tool directly from a UNIX or Linux shell.
Table A-1 shows the command-line invocations for the Pyxis tools presented in this document.
The $MGC_AMS_HOME and $CALIBRE_HOME environment variables are set to the
location for the executable versions of these tools.
Table A-2. Command-line Invocation for non-Pyxis Tools
Tool Invocation
ADiTTM $MGC_AMS_HOME/bin/adit <inpfile>
Eldo® $MGC_AMS_HOME/bin/eldo cir_filename.cir
EZwaveTM $MGC_AMS_HOME/bin/ezwave
Questa® ADMSTM For details, please refer to the Questa ADMS User’s
Manual
Calibre® DESIGNrevTM $CALIBRE_HOME/bin/calibredrv <options>
Calibre InteractiveTM $CALIBRE_HOME/bin/calibre -gui
Calibre Physical Verification $CALIBRE_HOME/bin/calibre <options>

(nmDRC, nmLVS, xRC, DFM,
Pattern Matching)
Calibre PERCTM $CALIBRE_HOME/bin/calibre -perc <options>
Calibre Query Server $CALIBRE_HOME/bin/calibre -perc <options>
Calibre RealTimeTM Launched from within Pyxis Custom Router.

Calibre RVETM $CALIBRE_HOME/bin/calibre -rve <options>
Related Topics
Pyxis Binary File Locations

All necessary Pyxis Custom Design Platform binary files are located in the $MGC_HOME
location.
Typically, this environment variable is set up by the CAD/EDA engineering team. Executable
locations can be added to the UNIX or Linux PATH variable.
CAD Topics
Pyxis Software Installation
Consult with your CAD/EDA engineering group to set the paths to correct locations.
Related Topics
Pyxis Software Installation

All Mentor Graphics products require licensing to be installed and configured properly before
invoking and operating them. You must install licenses before installing the applications.
A detailed list of tools for the IC design flow is listed in Table 1-4 on page 22. For more
installation and licensing information, refer to the Download tab of the SupportNet tool page.
To access SupportNet, go to:
http://supportnet.mentor.com/
Access to SupportNet requires a valid username and password.
Related Topics
Pyxis Custom Design Project Configuration

A Pyxis design configuration is a collection of design objects that meet the criteria of a set of
rules.
For example, you may want to set up a design that is configured to follow these criteria:
1. Project paths are based the current home directory.

2. Project contains the current version of two design objects and the previous version of
another.
Design configuration in the Pyxis design environment is done with the Configuration Window,
accessed through the Pyxis Project Manager. You can also write scripts that directly access
configuration management toolkit functions.
The details of project configuration are beyond the scope of this document. Please refer to the
Related Topics section for further details and example of how to set up a design configuration.
CAD Topics
Setting Environment Variables
Related Topics
“Configuration Management Toolkit Functions” in Pyxis Project Manager Reference
Manual.
“Configuration Management Toolkit Examples” in Pyxis Project Manager Reference
Manual.

Several environment variables are necessary for running the Pyxis Design Platform. These
variables point to the various tools used within the design environment.
You can include environment variable definitions in a login startup file, a project-specific
script, or set them manually in a shell window prior to starting your design session.
This procedure shows how to set the basic environment variables for proper operation in a
project-specific script. The software versions used may not match your specific installation.
Note
Mentor Graphics software is compatible with several hardware configurations. To access
the correct software version for your particular hardware, contact your CAD or EDA
team.
Prerequisites
• IC design tools have been installed, including Pyxis, Eldo, and Calibre.
Procedure
1. Navigate to your home directory.
2. Using an ASCII editor, open a new file called pyxis_qsg_startup. This will be a c-shell
script.
If you prefer another shell type, make the necessary adjustments to the example script
shown in Step 3.
3. In pyxis_qsg_startup, include the following script code lines:
#!/bin/csh -f
# Mentor Graphics license location

setenv $MGLS_LICENSE_FILE <license_file server>
# pyxis design platform

setenv MGC_HOME \
<pyxis_path>/icstation10.3_p.aol/v10.3_linux_x86_64/pyxis_home
# calibre physical verification
CAD Topics
setenv CALIBRE_HOME <calibre_path>/2013.x_nn/ixl_cal_2013.x_nn.mm
# AMS simulation
setenv MGC_AMS_HOME <ams_path>ams12.1_1.aol
# Set the $path variable. Notice that the MGC_AMS_HOME entries occur
# at the top of the stack.
set path = ($MGC_AMS_HOME/bin \
$MGC_AMS_HOME/modeltech/bin \
$CALIBRE_HOME/bin \
$MGC_HOME/bin \
$path )
4. Save the pyix_qsg_startup file.
Related Topics
Pyxis Project Manager User’ Guide
CAD Topics
Data Management in the Pyxis Custom Design Platform
Data Management in the Pyxis Custom Design

Platform
The Pyxis Project Manager manages designs by providing a framework for creating and
organizing a design project.
A project is composed of a collection of data, a directory structure, and a set of default or user-
defined options.
A design object is the basic unit in the Pyxis Project Manager. Design objects are design files
and directories.
For example, a schematic design object in a project is composed of several files organized in
one directory. However, the schematic directory and files are treated as one design object in the
project.
Figure A-1 shows a high-level presentation of how multiple projects might be organized in the
Pyxis Custom Design platform.
Figure A-1. Project Data Organization
Reference Libraries
Technology Standard Cell Pad Cell Analog Cell
Design Kit Library Library Library
Project One Project Two

Design Library: Digital Design: Design Library: Digital Design:
Digital Analog DSP ADC/DAC
Design Library: Design Library: Design Library: Design Library:

Test Benches Stimulus Files RF Simulations
Related Topics
“The Pyxis Project Manager tool” in Pyxis Project Manager User’ Guide
“Integrated Design Management (iDM)” in Pyxis Project Manager User’s Guide
CAD Topics
Project Data Organization
Project Data Organization

The Pyxis project file structure is organized as follows:
Figure A-2. Pyxis Project File Structure
Related Topics
Pyxis Project Manager User’ Guide
Appendix B
Pyxis Quick Reference Cards
There are two quick reference cards available in the Pyxis documentation suite.
Pyxis Schematic Quick Reference Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Pyxis Layout Quick Reference Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Pyxis Schematic Quick Reference Card
Pyxis Layout Quick Reference Card
Third-Party Information
For third-party information, refer to Third-Party Software for Pyxis Products.
End-User License Agreement
The latest version of the End-User License Agreement is available on-line at:
www.mentor.com/eula
IMPORTANT INFORMATION
USE OF ALL SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THIS LICENSE
AGREEMENT BEFORE USING THE PRODUCTS. USE OF SOFTWARE INDICATES CUSTOMER’S COMPLETE
AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT.
ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY.
END-USER LICENSE AGREEMENT (“Agreement”)
This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively “Products”)
between the company acquiring the Products (“Customer”), and the Mentor Graphics entity that issued the corresponding
quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (“Mentor Graphics”). Except for license
agreements related to the subject matter of this license agreement which are physically signed by Customer and an authorized
representative of Mentor Graphics, this Agreement and the applicable quotation contain the parties’ entire understanding
relating to the subject matter and supersede all prior or contemporaneous agreements. If Customer does not agree to these
terms and conditions, promptly return or, in the case of Software received electronically, certify destruction of Software and all
accompanying items within five days after receipt of Software and receive a full refund of any license fee paid.
1. ORDERS, FEES AND PAYMENT.
1.1. To the extent Customer (or if agreed by Mentor Graphics, Customer’s appointed third party buying agent) places and Mentor
Graphics accepts purchase orders pursuant to this Agreement (each an “Order”), each Order will constitute a contract between
Customer and Mentor Graphics, which shall be governed solely and exclusively by the terms and conditions of this Agreement,
any applicable addenda and the applicable quotation, whether or not those documents are referenced on the Order. Any
additional or conflicting terms and conditions appearing on an Order or presented in any electronic portal or automated order
management system, whether or not required to be electronically accepted, will not be effective unless agreed in writing and
physically signed by an authorized representative of Customer and Mentor Graphics.
1.2. Amounts invoiced will be paid, in the currency specified on the applicable invoice, within 30 days from the date of such invoice.
Any past due invoices will be subject to the imposition of interest charges in the amount of one and one-half percent per month
or the applicable legal rate currently in effect, whichever is lower. Prices do not include freight, insurance, customs duties, taxes
or other similar charges, which Mentor Graphics will state separately in the applicable invoice. Unless timely provided with a
valid certificate of exemption or other evidence that items are not taxable, Mentor Graphics will invoice Customer for all
applicable taxes including, but not limited to, VAT, GST, sales tax, consumption tax and service tax. Customer will make all
payments free and clear of, and without reduction for, any withholding or other taxes; any such taxes imposed on payments by
Customer hereunder will be Customer’s sole responsibility. If Customer appoints a third party to place purchase orders and/or
make payments on Customer’s behalf, Customer shall be liable for payment under Orders placed by such third party in the event
of default.
1.3. All Products are delivered FCA factory (Incoterms 2010), freight prepaid and invoiced to Customer, except Software delivered
electronically, which shall be deemed delivered when made available to Customer for download. Mentor Graphics retains a
security interest in all Products delivered under this Agreement, to secure payment of the purchase price of such Products, and
Customer agrees to sign any documents that Mentor Graphics determines to be necessary or convenient for use in filing or
perfecting such security interest. Mentor Graphics’ delivery of Software by electronic means is subject to Customer’s provision
of both a primary and an alternate e-mail address.
2. GRANT OF LICENSE. The software installed, downloaded, or otherwise acquired by Customer under this Agreement, including any
updates, modifications, revisions, copies, documentation and design data (“Software”) are copyrighted, trade secret and confidential
information of Mentor Graphics or its licensors, who maintain exclusive title to all Software and retain all rights not expressly granted
by this Agreement. Mentor Graphics grants to Customer, subject to payment of applicable license fees, a nontransferable, nonexclusive
license to use Software solely: (a) in machine-readable, object-code form (except as provided in Subsection 5.2); (b) for Customer’s
internal business purposes; (c) for the term of the license; and (d) on the computer hardware and at the site authorized by Mentor
Graphics. A site is restricted to a one-half mile (800 meter) radius. Customer may have Software temporarily used by an employee for
telecommuting purposes from locations other than a Customer office, such as the employee’s residence, an airport or hotel, provided
that such employee’s primary place of employment is the site where the Software is authorized for use. Mentor Graphics’ standard
policies and programs, which vary depending on Software, license fees paid or services purchased, apply to the following: (a)
relocation of Software; (b) use of Software, which may be limited, for example, to execution of a single session by a single user on the
authorized hardware or for a restricted period of time (such limitations may be technically implemented through the use of
authorization codes or similar devices); and (c) support services provided, including eligibility to receive telephone support, updates,
modifications, and revisions. For the avoidance of doubt, if Customer provides any feedback or requests any change or enhancement to
Products, whether in the course of receiving support or consulting services, evaluating Products, performing beta testing or otherwise,
any inventions, product improvements, modifications or developments made by Mentor Graphics (at Mentor Graphics’ sole discretion)
will be the exclusive property of Mentor Graphics.
3. ESC SOFTWARE. If Customer purchases a license to use development or prototyping tools of Mentor Graphics’ Embedded Software
Channel (“ESC”), Mentor Graphics grants to Customer a nontransferable, nonexclusive license to reproduce and distribute executable
files created using ESC compilers, including the ESC run-time libraries distributed with ESC C and C++ compiler Software that are
linked into a composite program as an integral part of Customer’s compiled computer program, provided that Customer distributes
these files only in conjunction with Customer’s compiled computer program. Mentor Graphics does NOT grant Customer any right to
duplicate, incorporate or embed copies of Mentor Graphics’ real-time operating systems or other embedded software products into
Customer’s products or applications without first signing or otherwise agreeing to a separate agreement with Mentor Graphics for such
purpose.
4. BETA CODE.
4.1. Portions or all of certain Software may contain code for experimental testing and evaluation (which may be either alpha or beta,
collectively “Beta Code”), which may not be used without Mentor Graphics’ explicit authorization. Upon Mentor Graphics’
authorization, Mentor Graphics grants to Customer a temporary, nontransferable, nonexclusive license for experimental use to
test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics. Mentor Graphics may
choose, at its sole discretion, not to release Beta Code commercially in any form.
4.2. If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code under normal
conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customer’s use of the
Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customer’s evaluation and testing,
Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths, weaknesses and
recommended improvements.
4.3. Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code, including the methods and
concepts utilized therein, solely to those employees and Customer location(s) authorized by Mentor Graphics to perform beta
testing. Customer agrees that any written evaluations and all inventions, product improvements, modifications or developments
that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly on
Customer’s feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, title and
interest in all such property. The provisions of this Subsection 4.3 shall survive termination of this Agreement.
5. RESTRICTIONS ON USE.
5.1. Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include all notices
and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All copies shall
remain the property of Mentor Graphics or its licensors. Customer shall maintain a record of the number and primary location of
all copies of Software, including copies merged with other software, and shall make those records available to Mentor Graphics
upon request. Customer shall not make Products available in any form to any person other than Customer’s employees and on-
site contractors, excluding Mentor Graphics competitors, whose job performance requires access and who are under obligations
of confidentiality. Customer shall take appropriate action to protect the confidentiality of Products and ensure that any person
permitted access does not disclose or use Products except as permitted by this Agreement. Customer shall give Mentor Graphics
written notice of any unauthorized disclosure or use of the Products as soon as Customer becomes aware of such unauthorized
disclosure or use. Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local
law, Customer shall not reverse-assemble, reverse-compile, reverse-engineer or in any way derive any source code from
Software. Log files, data files, rule files and script files generated by or for the Software (collectively “Files”), including without
limitation files containing Standard Verification Rule Format (“SVRF”) and Tcl Verification Format (“TVF”) which are Mentor
Graphics’ trade secret and proprietary syntaxes for expressing process rules, constitute or include confidential information of
Mentor Graphics. Customer may share Files with third parties, excluding Mentor Graphics competitors, provided that the
confidentiality of such Files is protected by written agreement at least as well as Customer protects other information of a
similar nature or importance, but in any case with at least reasonable care. Customer may use Files containing SVRF or TVF
only with Mentor Graphics products. Under no circumstances shall Customer use Products or Files or allow their use for the
purpose of developing, enhancing or marketing any product that is in any way competitive with Products, or disclose to any
third party the results of, or information pertaining to, any benchmark.
5.2. If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct software
errors and enhance or modify the Software for the authorized use. Customer shall not disclose or permit disclosure of source
code, in whole or in part, including any of its methods or concepts, to anyone except Customer’s employees or on-site
contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code in
any manner except to support this authorized use.
5.3. Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense, or otherwise transfer the
Products, whether by operation of law or otherwise (“Attempted Transfer”), without Mentor Graphics’ prior written consent and
payment of Mentor Graphics’ then-current applicable relocation and/or transfer fees. Any Attempted Transfer without Mentor
Graphics’ prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics’ option, result in the
immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms of this Agreement,
including without limitation the licensing and assignment provisions, shall be binding upon Customer’s permitted successors in
interest and assigns.
5.4. The provisions of this Section 5 shall survive the termination of this Agreement.
6. SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer with updates and
technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor Graphics’ then
current End-User Support Terms located at http://supportnet.mentor.com/supportterms.
7. LIMITED WARRANTY.
7.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly installed,
will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not
warrant that Products will meet Customer’s requirements or that operation of Products will be uninterrupted or error free. The
warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. Customer must
notify Mentor Graphics in writing of any nonconformity within the warranty period. For the avoidance of doubt, this warranty
applies only to the initial shipment of Software under an Order and does not renew or reset, for example, with the delivery of (a)
Software updates or (b) authorization codes or alternate Software under a transaction involving Software re-mix. This warranty
shall not be valid if Products have been subject to misuse, unauthorized modification, improper installation or Customer is not
in compliance with this Agreement. MENTOR GRAPHICS’ ENTIRE LIABILITY AND CUSTOMER’S EXCLUSIVE
REMEDY SHALL BE, AT MENTOR GRAPHICS’ OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON
RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF THE
PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY. MENTOR GRAPHICS MAKES NO WARRANTIES
WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA CODE; ALL OF
WHICH ARE PROVIDED “AS IS.”
7.2. THE WARRANTIES SET FORTH IN THIS SECTION 7 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS
LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY
DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
8. LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID
OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE
LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING LOST PROFITS OR
SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVEN IF MENTOR GRAPHICS
OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL MENTOR
GRAPHICS’ OR ITS LICENSORS’ LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT RECEIVED FROM
CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR SERVICE GIVING RISE TO THE CLAIM. IN THE CASE
WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY
DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 8 SHALL SURVIVE THE TERMINATION OF THIS
AGREEMENT.
9. HAZARDOUS APPLICATIONS. CUSTOMER ACKNOWLEDGES IT IS SOLELY RESPONSIBLE FOR TESTING ITS

PRODUCTS USED IN APPLICATIONS WHERE THE FAILURE OR INACCURACY OF ITS PRODUCTS MIGHT RESULT IN
DEATH OR PERSONAL INJURY (“HAZARDOUS APPLICATIONS”). EXCEPT TO THE EXTENT THIS EXCLUSION OR
RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL
MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION
WITH THE USE OF MENTOR GRAPHICS PRODUCTS IN OR FOR HAZARDOUS APPLICATIONS. THE PROVISIONS OF
THIS SECTION 9 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
10. INDEMNIFICATION. CUSTOMER AGREES TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS
LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE OR LIABILITY, INCLUDING ATTORNEYS’ FEES,
ARISING OUT OF OR IN CONNECTION WITH THE USE OF MENTOR GRAPHICS PRODUCTS IN OR FOR HAZARDOUS
APPLICATIONS. THE PROVISIONS OF THIS SECTION 10 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
11. INFRINGEMENT.
11.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product acquired
by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics
will pay costs and damages finally awarded against Customer that are attributable to such action. Customer understands and
agrees that as conditions to Mentor Graphics’ obligations under this section Customer must: (a) notify Mentor Graphics
promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to settle or defend the
action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action.
11.2. If a claim is made under Subsection 11.1 Mentor Graphics may, at its option and expense: (a) replace or modify the Product so
that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return of the
Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
11.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with any
product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the use of
other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a product that
Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided by Mentor
Graphics’ licensors who do not provide such indemnification to Mentor Graphics’ customers; or (h) infringement by Customer
that is deemed willful. In the case of (h), Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other
costs related to the action.
11.4. THIS SECTION 11 IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS, AND CUSTOMER’S SOLE AND EXCLUSIVE REMEDY, FOR DEFENSE,
SETTLEMENT AND DAMAGES, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.
12. TERMINATION AND EFFECT OF TERMINATION.
12.1. If a Software license was provided for limited term use, such license will automatically terminate at the end of the authorized
term. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon
written notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement
upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of this Agreement
or any license granted hereunder will not affect Customer’s obligation to pay for Products shipped or licenses granted prior to
the termination, which amounts shall be payable immediately upon the date of termination.
12.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination, Customer shall ensure that all use of the affected Products ceases, and shall return hardware and
either return to Mentor Graphics or destroy Software in Customer’s possession, including all copies and documentation, and
certify in writing to Mentor Graphics within ten business days of the termination date that Customer no longer possesses any of
the affected Products or copies of Software in any form.
13. EXPORT. The Products provided hereunder are subject to regulation by local laws and United States (“U.S.”) government agencies,
which prohibit export, re-export or diversion of certain products, information about the products, and direct or indirect products thereof,
to certain countries and certain persons. Customer agrees that it will not export or re-export Products in any manner without first
obtaining all necessary approval from appropriate local and U.S. government agencies. If Customer wishes to disclose any information
to Mentor Graphics that is subject to any U.S. or other applicable export restrictions, including without limitation the U.S. International
Traffic in Arms Regulations (ITAR) or special controls under the Export Administration Regulations (EAR), Customer will notify
Mentor Graphics personnel, in advance of each instance of disclosure, that such information is subject to such export restrictions.
14. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. The parties agree that all Software is
commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to U.S. FAR 48
CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. government or a U.S.
government subcontractor is subject solely to the terms and conditions set forth in this Agreement, which shall supersede any
conflicting terms or conditions in any government order document, except for provisions which are contrary to applicable mandatory
federal laws.
15. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and
other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
16. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during
Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customer’s
software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customer’s
compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FlexNet (or successor
product) report log files that Customer shall capture and provide at Mentor Graphics’ request. Customer shall make records available in
electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of
any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information
gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights
under this Agreement. The provisions of this Section 16 shall survive the termination of this Agreement.
17. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual
property licensed under this Agreement are located in Ireland and the U.S. To promote consistency around the world, disputes shall be
resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of
Oregon, U.S., if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or
South America. All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of the courts
of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when the laws of Ireland apply. Notwithstanding the foregoing,
all disputes in Asia arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a single arbitrator
to be appointed by the chairman of the Singapore International Arbitration Centre (“SIAC”) to be conducted in the English language, in
accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be incorporated by
reference in this section. Nothing in this section shall restrict Mentor Graphics’ right to bring an action (including for example a motion
for injunctive relief) against Customer in the jurisdiction where Customer’s place of business is located. The United Nations
Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
18. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or
illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect.
19. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all prior
or contemporaneous agreements. Some Software may contain code distributed under a third party license agreement that may provide
additional rights to Customer. Please see the applicable Software documentation for details. This Agreement may only be modified in
writing, signed by an authorized representative of each party. Waiver of terms or excuse of breach must be in writing and shall not
constitute subsequent consent, waiver or excuse.
Rev. 140201, Part No. 258976

Pyxis Quickstart PDF

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Pyxis Quickstart PDF

Caricato da

Copyright:

Formati disponibili

A Quick Start Guide for the Pyxis

Custom Design Platform

Software Version 10.2x

© 2012-2015 Mentor Graphics Corporation

Mentor Graphics Corporation

Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form

Data Management in the Pyxis Custom Design Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 1-1. Pyxis Custom Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2-36. Selecting the generic13 PDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 3-19. Setting up SDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 3-64. Extracted Transistor-Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 1-1. Quick Start Guide Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

• Front-end Design Topics (Schematic and Netlist) — includes information on

Table 1-1. Quick Start Guide Chapter Organization

Table 1-1. Quick Start Guide Chapter Organization

IC Design Flow with the Pyxis Custom Design Platform. . . . . . . . . . . . . . . . . . . . . . . . . 13

IC Design Flow with the Pyxis Custom Design

Figure 1-1. Pyxis Custom Design Environment

Pyxis Project Manager

Design Verification High-Level Design and Verification

Analog Schematic Design Floorplanning and

Physical Verification Physical Layout Implementation

DRC, DFM, LVS, PEX Full Custom Layout Automated Layout

Figure 1-2. IC Front-End Design Flow (Netlist and Schematic Capture)

Pyxis Project Manager Create Design Library

Pyxis Language Interface Initial Behavioral

Cell Schematic and

Questa-ADMS Cell Functional

Finalize and Verify Cell

Pyxis Schematic Top-Level Schematic

Figure 1-3. IC Back-End Design Flow (Physical Layout and Verification)

Manual Layout Flow Automated Layout

IRoute Cell/Block Layout

Calibre Physical Physical

Figure 1-4. Automated Layout Flow with Pyxis Custom Router

Pyxis Custom Router

Run Net Parasitic

Installing the Pyxis Quick Start Example Data

4. Change to the example directory:

5. List the contents of the example directory:

Table 1-2. Files in the Pyxis_qs_ekit Directory

Table 1-2. Files in the Pyxis_qs_ekit Directory (cont.)

Using the /solutions Project Directory

Figure 1-5. Opening the solutions Design Project

IC Design Flow Documentation Reference

Table 1-4. IC Design Flow Tool Reference

Table 1-4. IC Design Flow Tool Reference (cont.)

• Pyxis Common User Interface

• Pyxis Common User Interface

Table 1-4. IC Design Flow Tool Reference (cont.)

Table 1-4. IC Design Flow Tool Reference (cont.)

• Standard Verification Rule

• Standard Verification Rule

• Calibre LVS RVE Quick Reference

Figure 2-1. Front-End Design Flow

• Importing HDL Files Initial Behavioral

Cell Schematic and • Validating Registered

Circuit • Adding Properties to a

Finalize and Verify Cell

Creating a Logic Library

Figure 2-2. Project Navigator Before Creating a New Logic Library

Figure 2-3. Enter New Logic Library Name

Figure 2-4. myDesign Hierarchy