Institut für Integrierte Systeme

Integrated Systems Laboratory

Department of Information Technology and Electrical Engineering

VLSI II:
Design of Very Large Scale Integration Circuits
227-0147-00L

Exercise 7

Power Distribution
Prof. L. Benini
F. Gürkaynak

Last Changed: 2019-03-28 20:30:37 +0100

Reminder:
With the execution of this training you declare that you understand and accept the regulations about using
CAE/CAD software installations at the ETH Zurich. These regulations can be read anytime at
http://eda.ee.ethz.ch/index.php/Regulations.
1 What You Will Learn
In the previous exercises, you were taught how to perform a power analysis of a digital circuit. Unfortunately,
not every chip design can build on such a well-established power design flow like you were provided in the
previous exercise. Therefore, a designer must consider a number of power-related issues when doing an
analysis of the power network:
• How to locate excessive voltage losses in power and ground networks.
• How to detect excessive current densities in power and ground networks.
• How to improve power and ground distribution networks where necessary.
The required CAE tools throughout this exercise are M ENTOR G RAPHICS M ODELSIM and I NNOVUS. You will
use the former in order to perform a post-layout simulation as you have learned in the previous exercise.
I NNOVUS will be used in order to prepare and manipulate the power and ground nets of a sample design as
well as for IR drop analysis and current density estimations.

2 Ground Bounce, Supply Droop, and Electromigration

During the development of an adequate power distribution strategy, a designer has to determine the width, the
position, the layers, and the number of vertical and horizontal stripes for both ground and supply nets. These
properties affect the power distribution across the design and will determine whether the final chip actually
works at the designated maximum frequency or not.
In order to analyze the power consumption of a design, we will use the Rail Analysis of I NNOVUS. The rail
analyzer can show the current density, ground bounce, and supply droop across the power lines in a chip. This
allows us to evaluate whether or not the current power distribution is adequate for the design. In I NNOVUS the
ground bounce and supply droop are called IR Drop.
During the design of the power nets, it is important to keep in mind two different problems:
IR Drop: Since the metal exhibits a natural resistance (R), current (I) flowing through such a connection will
create a voltage drop. This in turn will reduce the supply voltage of any cell, which is at the detriment
of its performance (e.g., increased propagation time). Additionally, excessive supply droop and ground
bounce may violate noise margins leading to a malfunction of the chip.1 Depending on process voltage
temperature (PVT) variations, this leads to immediate influences of the correct behavior of the chip.
Electromigration: Thermally agitated metal ions are washed away by flowing electrons, thereby reducing the
cross section of the metal. As a final result, an interruption of a power line can occur, which destroys the
chip. This phenomenon depends on the current density J.
IR drop is a problem that has an immediate effect on the chip’s operation, while electromigration is a slow
process, which may show its negative impact after months or even years during which the IC has been working
correctly. The positive side effect of designing the supply wires sufficiently wide with respect to electromigration
is that fusing due to high current densities is prevented. That is, constraints for preventing electromigration are
much tighter than those for preventing fusing.
Fortunately, I NNOVUS features efficient rail analysis tools that show the IR drop along the supply lines and the
current density therein graphically. Basically, there are two versions of the Rail Analysis available:
Early Rail Analysis: Is a simplified analysis that can be used after floorplanning.
Rail Analysis: A more accurate analysis, that can also take into account the power distribution within macros
such as I/O pads and memories.
The Early Rail Analysis can be used for first investigations of the quality of the power distribution. Throughout
this exercise, we will use the more precise Rail Analysis.

1 For a detailed discussion, refer to chapter 11.3 of the VLSI II script.

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3 The Test Vehicle
Throughput this exercise, we will use an AES (Advanced Encryption Standard) design as our test vehicle. AES
is one of the most important block ciphers these days and has been standardized by the National Institute
of Standards and Technology (NIST). Figure 1 shows a simplified overview of the top-level design. For our
exercise, we use the AES algorithm based on a 128-bit wide secret key (also known as the cipherkey), which
is usually referred to as AES-128. A description of the I/Os of the design is provided in Table 1.

ACLK_CI aes128Top
ARESET_RBI 128
aes128 6
ScanEn_TI Cipherkey Debug_TO
EncrBusy_TO

8 8
TDATA_DI Ser2Par Par2Ser TDATA_DO

128
128

Ciphertext
AES-128
Plaintext 128 128

RAM

RAM
TVALID_SI
TREADY_SO TVALID_SO
TID_SI
TDEST_SI
4 Main FSM TREADY_SI
TUSER_SI

Figure 1: The test vehicle being used.

The main components of the architecture are the actual encryption engine, two RAMs storing the plaintext
to be encrypted and the resulting ciphertext, and an FSM which controls the interfaces and the encryption
process. The AES-128 architecture is trimmed for high throughput and can provide 128 bits of ciphertext within
each clock cycle once its pipeline is full. The encryption module has ten pipeline stages as well as input and
output registers. Therefore, the AES-128 block has an overall latency of 12 clock cycles. The architecture by
itself might be part of a larger microprocessor design or the like in order to provide fast encryption, which is
usually an important requirement these days. Basically, the design works as follows:
• First, the 8-bit wide AXI streaming interface is used in order to write the cipherkey and the plaintext byte-
by-byte into the Cipherkey register and the Plaintext RAM, respectively. Due to the limited number of I/O
pins of our package, the AXI input interface offers only a data bus of eight bits. Since our plaintext RAM
uses a word width of 128 bits, we use a serial-to-parallel shift register (denoted by Ser2Par in Figure 1)
in order to collect 16 plaintext bytes and once the Ser2Par register is full, the plaintext block is written
into the RAM.
• Once the data to be encrypted has been written into the Plaintext RAM (32kB at a maximum), the encryp-
tion process starts and all the 128-bit wide plaintext blocks are encrypted and stored in the Ciphertext
RAM.
• As soon as the whole encryption process is completed, the 8-bit output AXI interface is used in order to
provide the computed ciphertext to its environment.
Note: The provided AES architecture has solely been designed for academic purposes and does not represent
a secure design from a cryptographic point of view.

3.1 Installation and Preparation Work

The test vehicle can be installed as follows:
Student Task 1:
1. Open a Unix shell window.
2. From your root directory, install the test vehicle using:

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 Table 1: Pinout of the AES-128 design.
Port Name Direction Size Description
ACLK CI Input 1 System clock
ARESET RBI Input 1 Asynchronous, active-low reset
ScanEn TI Input 1 Scan-chain enable
TDATA DI Input 8 Data port of AXI input interface
TVALID SI Input 1 AXI input interface valid signal; indicates that the AXI master is driving
valid input data
TREADY SO Output 1 AXI input interface ready signal; indicates that the AXI slave can accept
the input data in the current clock cycle
TID SI Input 1 Determines the type of the input data; 0. . . plaintext byte; 1. . . cipherkey
byte
TDEST SI Input 4 Address of the cipherkey byte; TID SI must be 1
TUSER SI Input 1 Starts the encryption; has to be set when transmitting the last input byte
Debug TO Output 6 Some debug outputs
EncrBusy TO Output 1 Determines whether the encryption is currently busy
TDATA DO Output 8 Data port of the AXI output interface
TVALID SO Output 1 AXI output interface valid signal; indicates that the AXI master is driving
valid output data
TREADY SI Input 1 AXI output interface ready signal; indicates that the AXI slave can accept
the output data in the current clock cycle

sh > /home/vlsi2/ex07/install.sh

3. Start the cockpita :

sh > cd ex07
sh > icdesign umcL65 -update all &

a Note that you only need the -update all option if you start the cockpit the first time.

Afterwards, load the already prepared design in I NNOVUS.

Student Task 2:
1. Start I NNOVUS.
2. Navigate to File→Restore Design, select Innovus as the data type and choose
aes128Chip_final.enc from the save directory.
3. Press OK and change to the Physical view of the design once it is loaded. (Button on the right side)
4. Change the number of CPUs to 4. You can find it in Tools→Set Multiple CPU Usage below
the Basic tab and Local Machine.

For the present design, a full backend has already been accomplished for you. Before you can proceed with
the actual rail analysis, you need to perform a post-layout simulation as you have learned in the previous
exercise.
Student Task 3:
• Use the provided script templates in the ./modelsim directory in order to create a compile and a
simulation script for the post-layout simulation as you have learned in the previous exercise. The
netlist you should use for your compile script is located at ./encounter/out/aes128Chip.v\
and the two testbench-specific files are ./sourcecode/tb_util.vhd and ./sourcecode/\

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 aes128Chip_tb.vhd. When adapting the simulation script template to your needs, you need to
specify an additional library (fse0k a memaker verilog), since our design uses some RAM macro
cells. The SDF file you should use for the simulation can be found at ./encounter/out/\
aes128Chip.sdf.gz.

Note: Make sure that you have the correct permissions in order to run the shell scripts. You
may change them using the chmod tool.

• When starting the simulation, you will encounter a large number of warnings regarding the supply
connections of the design. You can ignore those messages.
• Before you actually generate the VCD file, analyze the behavior of the test vehicle using the sim-
ulation and the source code and determine meaningful start/stop times for your VCD recording.
Assuming that we want to analyze the actual encryption process and not the I/O transfers of the
design, what are suitable start/stop times for the VCD file generation?
Start time: Start time:

How did you determine the start/stop times (discuss your results with an assistant)? If you do not
determine the interval for the VCD file generation correctly, your power figures and the following rail
analyses will result in meaningless numbers.
• Depending on the complexity of the analyzed design, the resulting VCD file may become quite large.
Hence, you should consider saving it on your local hard drive (mounted under /scratch/). If you
have chosen the start/stop times in the previous section adequately, the simulation time for which
the VCD file will be generated should be rather short (and therefore, the resulting VCD file not too
large). Hence, you may store your VCD file within your home directory as well, for instance, under
./modelsim/vcd/aes128.vcd.

Note: Assure that you only generate the VCD file for the interval for which we want to perform
the IR drop analysis later on. Otherwise, your resulting VCD file might become too large and
you would waste a lot of hard disk space unnecessarily.

Now that you have generated the VCD file, you should be ready for the actual rail analysis. Close QuestaSim
and switch back to I NNOVUS. Some power-specific information is required to start the rail analysis, which can
be gained from the power analysis as follows:

Student Task 4:
• Navigate to Power→Power Analysis→Setup... and switch to the Basic tab. Enter the nets
VDDIO VSSIO into the Switched-off or Power-up Nets box as shown in Figure 2 and click OK.
• In order to run a power analysis choose Power→Power Analysis→Run.... Activate the Activity
File option and choose the VCD file you have generated previously. The Scope of the design
should be aes128chip tb/aes128Chip 1 and insert the start/stop times you determined during the
VCD generation. Do not forget to click the A DD button. Enter ./reports/power as the Results
Directory and press OK.

Note: Remember that the Scope field is case-sensitive and it is of utmost importance to set
it correctly in order to obtain meaningful power results. You may doublecheck the scope by
opening the respective VCD file and look-out for the $scope lines. For the present example you
will encounter that even though our testbench is called aes128Chip tb, QuestaSim generates
a VCD file with an all lower-case scope for the testbench hierarchy (i.e., aes128chip tb).

• Watch the output within the I NNOVUS shell and check whether the coverage of the node activity file
reaches 100%. If this is not the case, your power results as well as the upcoming rail analyses

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 will be meaningless. Talk to an assistant if you encounter problems setting up the power simulation
yourself.

Figure 2: Power Analysis Setup.

The power analysis should report a total power consumption of about 70.5 mW. If your personal result deviates
significantly, make sure that you have followed our instructions correctly.

4 Rail Analysis
Now that we have obtained the required power-specific information, we can start with the actual rail analysis.
Like for the power analysis, we first need to do some initial configurations.

4.1 Rail Analysis Setup

Student Task 5:
• From the menu select Power→Rail Analysis→Setup Rail Analysis.... In the B ASIC tab,
set the Accuracy to HD (High definition) and add all three libraries located at
./encounter/tech/cl to the PowerGrid Libraries.
• Select the EM Analysis Models option and choose the file
./encounter/tech/qrc_8m1t0f1u.em_model.
• Compare the settings to Figure 3. If all is correct, save the settings by using S AVE (this is useful to
load the config again if something crash) and then press the OK button.

4.2 IR Drop Threshold

In order to perform an IR drop analysis, we need to fix a threshold that indicates the worst acceptable voltage
level in the design. The threshold voltage can be extracted from the I/O databook (located at
./docs/io_library_b04_databook.pdf):

Student Task 6: Look for the electrical specifications in the I/O cell databook and report the following
values for an I/O voltage of 2.5 V:

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 Figure 3: UI of the rail analysis setup.

VDD core voltage: VDD minimal core voltage:

At first sight, a good threshold value might be the minimal voltage of the standard cells (i.e., the minimal core
power supply). However, we need to take into account that the IR drop analysis is done for VDD and ground
separately, that is the maximal IR drop is the sum of VDD and ground drops.

Student Task 7: Taking into account the above hints, determine an appropriate threshold level for the IR
drop on the power nets and discuss your results with an assistant:
Threshold:

4.3 Rail Analysis Run

If you have determined the thresholds correctly, you should now be ready for the actual rail analysis:

Student Task 8:
• Open the Run Rail Analysis window choosing
Power→Rail Analysis→Run Rail Analysis and enter VDD as the power net and an appro-
priate Voltage and Threshold value.
• In the Power Data section choose the Current Files option and then select the instance current file
that was generated previously during the power simulation, i.e., static_VDD.ptiavg for the net
VDD (located in the ./reports/power directory).

I NNOVUS does not really know how the power signal will enter the chip. You can provide this information using
the Power Pads definition. One way to create this information is to select XY File and then click C REATE.

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 Figure 4: Rail analysis settings.

Within the Edit Pad Location window, enter VDD as the Net Name and click F ETCH. The Pad Location
List should be updated with all the VDD supplies. Save the obtained information using the S AVE button under
./encounter/save/aes128Chip.VDD.pp. Repeat this procedure for the net VSS and save the file under
./encounter/save/aes128Chip.VSS.pp. Return to the Run Rail Analysis window by pressing the
C ANCEL button.
Back to the Run Rail Analysis window, you have to load the pad location list that you have just created by
selecting it within the File textbox. Enter the correct net name (i.e., VDD or VSS) and press the A DD button.

Note: The presented way of defining the pad locations is not really accurate. Hence, we have already
prepared some templates for the QFN40 package, which we will use in this exercise.

Student Task 9:
• In the Run Rail Analysis window select XY File for the Power Pads, choose the file located at
./encounter/src/qfn40.VDD.pp and enter VDD as the Net Name. Do not forget to press the
A DD button in order to add the pad location information.
• After providing the results directory ./reports/rail, the GUI should look similar to Figure 4.
Press the A PPLY button.

If the rail analysis succeeded, the I NNOVUSshell should display an output similar to the following:

Rail Analysis completed successfully.

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 Figure 5: IR drop of the original design

4.4 View Rail Analysis Result

Once the rail analysis is completed, you have to open a new window, named Power & Rail Results to be
able to see the results.

Student Task 10:

• Go to the menu Power→Report→Power & Rail Result.
• On the left side, a new side bar is opened. Select Basic and change Type to Rail.
• Now, we need to define which rail analysis files should be used, for this click on DB Setup and
change the Rail Database to reports/rail/VDD_25C_avg_1. Press the OK.

Note: The trailing number of the result files directory (i.e., ’1’ in the aforementioned example) gets in-
cremented each time you run a new rail analysis. Thus, when you want to view the results of a new rail
analysis, you need to load the state from the new result directory. The tool will allow you to visualize
different features like the IR Drop or the Current Density directly on your chip.

IR Drop Analysis: As a first step, we will analyze the IR Drop map of the chip.

Student Task 11: Select ir - IR Drop from the Drop Down menu, and click on Apply. Make sure that the
option Auto Apply in the Action field is checked. Otherwise you will have to press the A PPLY button in
order to show the results. This will give you a color-coded map of the IR drop as an overlay of our test
vehicle. The highest drop will be colored dark red.

By default, the tool will automatically determine the color ranges based on the provided thresholds. You can
change this if you want by clicking on the arrow on the right side of color scheme. The power distribution in
our design looks pretty good. There are only minor drops within the RAM macro cells, but none of those are
actually critical.
Resistor Current Analysis: In the Power & Rail Results window select rc - Resistor Current to show
the plot of the current flowing across the wires.
Resistor Current Density Analysis: The resistor current density plot (rj - Resistor Current Density option)
computes the ratio J/Jmax for every wire of the chip. More precisely, J corresponds to the actual chip current
density and Jmax is the maximal allowed current density of the selected metal. A ratio greater than 1 means
that the current density limit of the segment is violated. This is an important aspect since for critical values of
J/Jmax , your chip could suffer from the problems described in Section 2.

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5 Power Distribution Techniques
The test vehicle used so far provides a well-designed power distribution network. Unfortunately, you do not
always know in advance how much power your design requires exactly and therefore, you may encounter
different kind of problems when analyzing the power budget of it. Hence, in this part of the exercise, we will
look at different power distribution networks for our test vehicle and will use the previously learned analysis
methods to identify potential weaknesses.
Although the errors in all of the designs have been inserted intentionally, they may also happen during the
backend design by coincidence and are usually neither detectable by a post-layout simulation nor an adequate
Layout Versus Schematic (LVS) check.
During the remainder of this section, you should complete Table 2 for each of the different power distribution
network variants. The first empty column of the table should contain the maximum IR drop within the design,
whereas the second column should be completed using the number of nets, which violate the IR drop thresh-
old. Other weaknesses, which can be discovered using the techniques presented in the previous section,
should be described briefly in the third empty column.

Student Task 12: As a first step, take the numbers you obtained for the original design during the previous
section and complete the first row of Table 2. For the number of nets below threshold use the Result
Browser as showed in Figure 6.

Figure 6: Result Browser

5.1 Design: aes128Chip final 1.enc

So far we have analyzed a well-designed power network. Next, you will be asked to analyze the same design,
created with different power distribution networks. Since we are using the same design, we do not have to redo
the power analysis over and over again. Instead, you can proceed immediately with the rail analysis once you
have loaded the new design.

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 Table 2: Power distribution network variants

Design Max. IR Nets Below Other

Drop [mV] Threshold Weaknesses

aes128Chip final.enc None

aes128Chip final 1.enc

aes128Chip final 2.enc

aes128Chip final 3.enc

aes128Chip final 4.enc

aes128Chip final 5.enc

Student Task 13:

• Clear the current design using the following command from within the I NNOVUS command shell:
enc > freeDesign

• Next, load the design located at ./encounter/save/aes128Chip_final_1.enc as done pre-

viously for the original design.
• Perform the analysis techniques you were taught in the previous sections. Are there any nets, which
are violating the threshold set earlier? If so, how many?

• What is wrong within the present power distribution network?

• Do you expect the design to work properly from a functional point of view? If not, why?

• Complete the respective row in Table 2.

5.2 Design: aes128Chip final 2.enc

Proceed with design ./encounter/save/aes128Chip_final_2.enc as you did in the previous section.

Student Task 14:

• Are there any violating nets?

• Do you expect the design to function properly? If not, what is the problem?

• Complete the respective row in Table 2.

5.3 Design: aes128Chip final 3.enc

Proceed with design ./encounter/save/aes128Chip_final_3.enc as you did in the previous section.

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 Student Task 15:
• Are there any violating nets?

• Do you expect the design to function properly? If not, what is the problem?
• Complete the respective row in Table 2.

You should have encountered that in the present design one of the power pads is not correctly connected to
the rest of the power distribution network. Therefore, you should have observed a continuous increase of the
power drop from one side of the design to the other. To correct this problem, you can use the Special Route
functionality as follows:

Student Task 16:

• First, investigate the problematic area in the layout (i.e., zoom to the location where there should
actually be a connection between the power pad and the core power network).
• Next, navigate to Route→Special Route... and enter VDD in the Net(s) textbox.
• Make sure that you have only ticked the Pad Pins check box. Clicking the OK button should create
the missing power network connections.
• Make sure that the power network now works as intended by re-running a rail analysis.

5.4 Design: aes128Chip final 4.enc

Open design ./encounter/save/aes128Chip_final_4.enc and analyze it as done previously.

Student Task 17:

• Are there any violating nets?

• Do you expect the design to function properly? If not, what is the problem?

• Complete the respective row in Table 2.

5.5 Design: aes128Chip final 5.enc

Open design ./encounter/save/aes128Chip_final_5.enc and analyze it as done previously.

Student Task 18:

• Are there any violating nets?

• Do you expect the design to function properly? If not, what is the problem?

• Complete the respective row in Table 2.

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5.6 Concluding remarks
The quality of a power distribution network cannot be detected by only considering the worst case IR Drop.
Rather, try to build your network in a way such that almost all components (standard cells, macro blocks, etc.)
are provided with the same supply voltage. This includes that you should not simply stop your efforts as soon
as all nets do not violate the initially set threshold anymore, but try to achieve a balanced power distribution.
Some of the problems in the designs might be much easier to detect by using further analysis methods of the
rail analysis, which we have not mentioned in this training. Feel free to try the other analysis methods besides
IR Drop and Current Density.

Present the results to an assistant and discuss any open questions. Finally
E follow the instructions in Section 5.7 to tidy up your workspace. E
5.7 Tidy up your workspace
During this exercise a lot of temporary data was produced which are used for the analysis (e.g. the rail analysis
has created about 1.5 GB). They are not needed any more after this exercise and can easily be reproduced if
needed later again. We encourage you to use the DZ tool llama to delete all unneeded files.

Student Task 19:

• Open llama (DZ tools) through the icdesign gui.
• Delete all temporary files.

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