ELECTRICAL SPECIALISATION

COURSE
O-149

Project Report On

Design and implementation of FPGA based

musical fountain

Guide: Syndicate:
Lt Cdr Kulveer Singh Lt NR Karunaratne
Lt PU Prabhu
Lt Nitish Awasthi

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Design and implementation of FPGA based musical fountain
 Acknowledgement

1. We sincerely thank our project guide Lt Cdr Kulveer Singh who guided us in
carrying out project successfully. His knowledge on the subject helped us to cross
many hurdles, which we faced time to time during the completion of the project.

2. We convey our gratitude to the staff of FTP, LES who directly or indirectly
helped in successful completion of this project. A special word of thanks is rendered
to SI FTP who motivated us to achieve the newer horizons in the project.

Lt NR Karunaratne Lt PU Prabhu Lt Nitish Awasthi

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Design and implementation of FPGA based musical fountain
 Certificate of Merit

This is to certify that under mentioned officers of ‘O’-149 have successfully completed
the project “Design and implementation of FPGA based musical fountain” and have
been able to achieve the desired results as a partial fulfillment of requirements for ‘L’
specialisation at INS Valsura.

(a) Lt NR Karunaratne - NRL 1752

(b) Lt PU Prabhu - 52198 F
(c) Lt Nitish Awasthi - 52196A

The project report compiled by them is an indication of the successful completion of the
project under my guidance.

(Kulveer Singh)
Lieutenant Commander
Project Guide

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Design and implementation of FPGA based musical fountain
 CONTENTS

CHAPTER INDEX

1. Scope of the project

2. Introduction

3. General Block diagram

4. Musical Intensity Divider circuit

5 . Interfacing LM3914 to FPGA

6. Introduction to FPGA – SPARTAN 3E Kit

7 . Introduction to VHDL Programming

8. VHDL Program to Control the Pumps

9. Interfacing FPGA to MOSFET

1O. Conclusion

Appendix :
1. Wiring diagram

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Design and implementation of FPGA based musical fountain
 CHAPTER 1

SCOPE OF THE PROJECT

SCOPE OF THE PROJECT

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Design and implementation of FPGA based musical fountain
 The scope of this project is to design and implement FPGA based musical
fountain. The fountain varies its pattern according to the musical note. FPGA acts
as the controller of the fountain. To achieve this a VHDL programme has been
written. The programe is activated by the output from the musical intensity
divider circuit which is connected to the musical source.

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Design and implementation of FPGA based musical fountain
 CHAPTER 2

INTRODUCTION

INTRODUCTION

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Design and implementation of FPGA based musical fountain
 The various units of the system are

1. Audio unit
2. Musical Intensity Divider unit
3. FPGA Controller unit
4. Interfacing unit
5. Pumps

Audio unit consists of a musical player which acts as main input for control unit.

The fountain controller unit consists FPGA. Musical intensity divider circuit is
used to determine the intensity of incoming audio signal and output is given to FPGA.
FPGA controls the pumps

The fountain control unit is capable of controlling the water performance. The
fountain control system includes variable speed pumps which are used to control the flow
of water through the discharge conduits and ultimately the height of the stream of water
projected by the discharge outlet. The fountain control system is capable of varying the
speed of the pumps in accordance with an audio input signal and thereby control the
height of the stream of water. The fountain control system has the added ability of
providing a unique performance based on different pieces of music without the need of
reprogramming.

Fountain consists of pumps and piping arrangements. The pumps are controlled
by control unit.

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Design and implementation of FPGA based musical fountain
 CHAPTER 3

GENERAL BLOCK DIAGRAM

GENERAL BLOCK DIAGRAM

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Design and implementation of FPGA based musical fountain
 Musical Musical FPGA
player intensity Controller
divider circuit Unit

Fountain Pumps MOSFET

The main function of the musical fountain is that the fountain pattern has
to change according to the musical intensity of the musical note.

The function of the of the musical intensity divider circuit is to sort the
musical intensity of note into various level and give the output of the maximum intensity
at the particular instantaneous time.

The brain of the project is the FPGA. The function of the FPGA is to
generate pulses which run the pumps through MOSFET’s . The pulses are generated
according to the intensity of the musical note. The programming of the FPGA is done in
such a way that according to a particular intensity of the musical note a set of pulses is
given to run the pumps. For each intensity a particular code will be executed.

The fountain consists of three pumps.

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Design and implementation of FPGA based musical fountain
 CHAPTER 4

MUSICAL INTENSITY DIVIDER CIRCUIT

MUSICAL INTENSITY DIVIDER CIRCUIT

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Design and implementation of FPGA based musical fountain
 The function of the of the musical intensity divider circuit is to sort the musical
intensity of note into various level and give the output of the maximum intensity at the
particular instantaneous time.

The LM3914 is a monolithic integrated circuit that senses analog voltage

levels and drives 10 LEDs, providing a linear analog display. A single pin changes the
display from a moving dot to a bar graph. Current drive to the LEDs is regulated and
programmable, eliminating the need for resistors. This feature is one that allows operation
of the whole system from less than 3V.

The circuit contains its own adjustable reference and accurate 10-step
voltage divider. The low-bias-current input buffer accepts signals down to ground, or V-,
yet needs no protection against inputs of 35V above or below ground. The buffer drives
10 individual comparators referenced to the precision divider. Indication non-linearity can
thus be held typically to 1/2%, even over a wide temperature range.

Versatility was designed into the LM3914 so that controller, visual alarm,
and expanded scale functions are easily added on to the display system. The circuit can
drive LEDs of many colors, or low-current incandescent lamps. Many LM3914s can be
“chained” to form displays of 20 to over 100 segments. Both ends of the voltage divider
are externally available so that 2 drivers can be made into a zero-center meter.

The LM3914 is rated for operation from 0°C to +70°C.

The output of the LM3914 is given to the FPGA.

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Design and implementation of FPGA based musical fountain
 13
Design and implementation of FPGA based musical fountain
 CHAPTER 5

INTERFACING LM3914 TO FPGA

INTERFACING LM3914 TO FPGA

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Design and implementation of FPGA based musical fountain
 The interfacing of LM3914 to FPGA is done through Optocoupler F817.
Optocoupler acts as an isolator. The optocoupler has a LED inside it which is supplied by
output of LM3914. The LED provides the gate signal to the transistor inside F817 which
gives the required the required voltage to the FPGA pin.
The output of the LM3914 is given to the J2 6pin accessory header to the pins F7,
E7, B6.

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Design and implementation of FPGA based musical fountain
 CHAPTER 6

INTRODUCTION TO FPGA –SPARTAN 3E KIT

INTRODUCTION TO FPGA –SPARTAN 3E KIT

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Design and implementation of FPGA based musical fountain
Key Components and Features

The key features of the Spartan-3E Starter Kit board are:

o Xilinx XC3S500E Spartan-3E FPGA

o Up to 232 user-I/O pins
o 320-pin FBGA package
o Over 10,000 logic cells
o Xilinx 4 Mbit Platform Flash configuration PROM
o Xilinx 64-macrocell XC2C64A CoolRunner™ CPLD
o 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
o 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
o FPGA configuration storage
o MicroBlaze code storage/shadowing
o 16 Mbits of SPI serial Flash (STMicro)
o FPGA configuration storage
o MicroBlaze code shadowing
o 2-line, 16-character LCD screen
o PS/2 mouse or keyboard port
o VGA display port
o 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
o Two 9-pin RS-232 ports (DTE- and DCE-style)
o On-board USB-based FPGA/CPLD download/debug interface
o 50 MHz clock oscillator
o SHA-1 1-wire serial EEPROM for bitstream copy protection
o Hirose FX2 expansion connector
o Three Digilent 6-pin expansion connectors
o Four-output, SPI-based Digital-to-Analog Converter (DAC)
o Two-input, SPI-based Analog-to-Digital Converter (ADC) with
programmable-gain
o pre-amplifier
o ChipScope™ SoftTouch debugging port
o Rotary-encoder with push-button shaft
o Eight discrete LEDs
o Four slide switches
o Four push-button switches
o SMA clock input
o 8-pin DIP socket for auxiliary clock oscillator

Slide Switches

Locations and Labels

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Design and implementation of FPGA based musical fountain
 The Spartan®-3E FPGA Starter Kit board has four slide switches, as shown in
Figure .The slide switches are located in the lower right corner of the board and are
labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-
most switch.

SW3 SW2 SW1 SW0

(H18) (N17) (L14) (L13)

Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic
High.When DOWN or in the OFF position, the switch connects the FPGA pin to ground,
a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is
no active debouncing circuitry, although such circuitry could easily be added to the FPGA
designprogrammed on the board.

Clock Sources Overview

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Design and implementation of FPGA based musical fountain
As shown in Figure , the Spartan®-3E FPGA Starter Kit board supports three primary
clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E
logo.

• The board includes an on-board 50 MHz clock oscillator.

• Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA
can generate clock signals or other high-speed signals on the SMA-style connector.

• Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket.

Bank 0, Oscillator Voltage 8-Pin DIP Oscillator Socket

Controlled by Jumper JP9 CLK_AUX: (B8)

On-Board 50 MHz Oscillator

CLK_50MHz: (C9)

Programming the FPGA, CPLD, or Platform Flash PROM via USB

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Design and implementation of FPGA based musical fountain
 The Spartan-3E Starter Kit includes embedded USB-based programming logic
and an USB endpoint with a Type B connector. Via a USB cable connection with the host
PC, the iMPACT programming software directly programs the FPGA, the Platform Flash
PROM, or the on-board CPLD. Direct programming of the
parallel or serial Flash PROMs is not presently supported.

Connecting the USB Cable

The kit includes a standard USB Type A/Type B cable, similar to the one shown
in Figure .

USB Type B Connector

Connects to Starter Kit's USB connector

USB Type A Connector

Connects to computer's USB connector

Expansion Connectors
The Spartan®-3E FPGA Starter Kit board provides a variety of expansion
connectors for easy interface flexibility to other off-board components. The board
includes the following I/O expansion headers.

• A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins, including
up to 15 differential LVDS I/O pairs and two Input-only pairs

• Three 6-pin Peripheral Module connections

• Landing pads for an Agilent or Tektronix connectorless probe

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Design and implementation of FPGA based musical fountain
 Jumper JP9, I/O Bank 0
Voltage
Default is 3.3V, set to Hirose 100-pin FX2 Connector, J3
2.5V for differential I/O 43 I/O connections, high-performance

J1 6-pin Accessory Header

J2 6-pin Accessory Header

J6 Probe Landing Pads

Connectorless logic analyzer probes

J4 6-pin Accessory Header

Hirose 100-pin FX2 Edge Connector (J3)

A 100-pin edge connector is located along the right edge of the board . This
connector is a Hirose FX2-100P-1.27DS header with 1.27 mm pitch. Throughout the
documentation, this connector is called the FX2 connector. 43 FPGA I/O pins interface to
the FX2 connector. All but five of these pins are true, bidirectional I/O pins capable of
driving or receiving signals. Five pins, FX2_IP<38:35> and FX2_IP<40> are Input-only
pins on the FPGA. These pins are highlighted in light green in Table 15-1 and cannot
drive the FX2 connector but can receive signals.

Six-Pin Accessory Headers

The 6-pin accessory headers provide easy I/O interface expansion using the
various Digilent Peripheral Modules. The location of the 6-pin headers is provided in
Figure.

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Design and implementation of FPGA based musical fountain
Header J1

The J1 header, shown in Figure is the top-most 6-pin connector along the right
edge of the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J1
header,FX2_IO<4:1>. These four signals are also shared with the Hirose FX2 connector.
The board supplies 3.3V to the accessory board mounted in the J1 socket on the bottom
pin.
J1
Spartan-3E FPGA
FX2 101
B4
FX2 102
A4

3.3V
FX2 103
D5
FX2 104
C5

GND

3.3 V

Header J2

The J2 header, shown in Figure is the bottom-most 6-pin connector along the right
edge of the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J2
header, FX2_IO<8:5>. These four signals are also shared with the Hirose FX2 connector.
The board supplies 3.3V to the accessory board mounted in the J2 socket on the bottom
pin.

J2
Spartan-3E FPGA
FX2 105
A6
FX2 106
B6

3.3V
FX2 107
E7
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B7and implementation of FPGA based musical fountain
Design
 FX2 108

GND

3.3 V

Header J4

The J4 header, shown in Figure 15-10, is located immediately to the left of the J1 header.
It uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect
to the J4 header, FX2_IO<12:9>. These four signals are also shared with the Hirose FX2
connector. The board supplies 3.3V to the accessory board mounted in the J4 socket on
the bottom pin.

J4
Spartan-3E FPGA
FX2 109
D7
FX2 110
C7

3.3V
FX2 111
E8
FX2 112
F8

GND

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Design and implementation of FPGA based musical fountain
 3.3 V

CHAPTER 7
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Design and implementation of FPGA based musical fountain
 INTRODUCTION TO VHDL
PROGRAMMING

INTRODUCTION TO VHDL
PROGRAMMING

VHDL (VHSIC hardware description language) is commonly used as a design-

entry language for field-programmable gate arrays and application-specific integrated
circuits in electronic design automation .

VHDL is a fairly general-purpose language, and it doesn't require a simulator on

which to run the code. There are a lot of VHDL compilers, which build executable
binaries. It can read and write files on the host computer, so a VHDL program can be
written that generates another VHDL program to be incorporated in the design being
developed. Because of this general-purpose nature, it is possible to use VHDL to write a
testbench that verifies the functionality of the design using files on the host computer to
define stimuli, interacts with the user, and compares results with those expected. This is
similar to the capabilities of the Verilog language.] for a long time. Both languages make
it relatively easy for an inexperienced developer to produce code that simulates
successfully but that cannot be synthesized into a real device, or is too large to be
practicable. One particular pitfall in both languages is the accidental production of
transparent latches rather than D-type flip-flops as storage elements

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Design and implementation of FPGA based musical fountain
 VHDL is not a case sensitive language. One can design hardware in a VHDL IDE
(such as Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After
that, the generated schematic can be verified using simulation software (such as
ModelSim) which shows the waveforms of inputs and outputs of the circuit after
generating the appropriate testbench. To generate an appropriate testbench for a particular
circuit or VHDL code, the inputs have to be defined correctly. For example, for clock
input, a loop process or an iterative statement is required.

The key advantage of VHDL when used for systems design is that it allows the
behavior of the required system to be described (modeled) and verified (simulated) before
synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system

(many parts, each with its own sub-behavior, working together at the same time). VHDL
is a Dataflow language, unlike procedural computing languages such as BASIC, C, and
assembly code, which all run sequentially, one instruction at a time.

A final point is that when a VHDL model is translated into the "gates and wires"
that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is
the actual hardware being configured, rather than the VHDL code being "executed" as if
on some form of a processor chip.

CHAPTER 8

VHDL PROGRAM TO CONTROL THE PUMP

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Design and implementation of FPGA based musical fountain
 VHDL PROGRAM TO CONTROL THE PUMP
The program to control the speed of the pumps is written in VHDL.

The program is so designed that the PWM signals are varied according to the
intensity of the incoming audio signal. The PWM signals are sent to the ports of header J1
and J2 pins A6,C5,D5. The following program is executed when the FPGA receives the
input signal.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sp3etest is
Port ( clk : in std_logic;
key : in std_logic_vector(3 downto 0);
bits : in std_logic_vector(2 downto 0);
led : out std_logic_vector(2 downto 0);
Pump : out std_logic_vector(2 downto 0));
end sp3etest;

architecture Behavioral of sp3etest is

type pwma is array(0 to 2) of std_logic_vector(7 downto 0);
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Design and implementation of FPGA based musical fountain
signal clk_scaler :std_logic_vector(25 downto 0);
signal Pwm_Clk : std_logic;
signal Dly : std_logic;
signal pwm_count : std_logic_vector(7 downto 0);
signal Pump_Val : pwma;
begin

process(clk,clk_scaler)
begin
if clk = '1' and clk' event then
clk_scaler <= clk_scaler + '1';
end if;
end process;

Pwm_Clk <= clk_scaler(11);

dly <= clk_scaler(25);
process (Pwm_Clk,pwm_count) -- 8 bit PWM Counter

begin
if Pwm_Clk = '1' and Pwm_Clk' event then
pwm_count <= pwm_count + 1;
end if;
end process;

process (pwm_count,Pump_Val) -- PWM Output

begin
for i in 0 to 2 loop
if(pwm_count < Pump_Val(i)) then
Pump(i) <= '1';
led(i) <= '1';
else
Pump(i) <= '0';
led(i) <= '0';
end if;
end loop;
end process;

process (key,bits,Pump_Val,dly)
begin
if dly = '1' and dly' event then
if key(3) = '1' then
if key = "1000" then
Pump_Val(0) <= "00000000";
Pump_Val(1) <= "00000000";
Pump_Val(2) <= "00000000";
elsif key = "1001" then

Pump_Val(0) <= "01111111"; --50%

Pump_Val(1) <= "00111111"; --25%

Pump_Val(2) <= "01111111"; --50%

elsif key = "1010" or key = "1011" then

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Design and implementation of FPGA based musical fountain
 Pump_Val(0) <= "10111111"; --75%

Pump_Val(1) <= "01111111"; --50%

Pump_Val(2) <= "00111111"; --25%

elsif key = "1100" or key = "1111" then

Pump_Val(0) <= "11111111"; --100%

Pump_Val(1) <= "01111111"; --50%

Pump_Val(2) <= "10111111"; --75%

end if;

else
if bits = "111" then

Pump_Val(0) <= "00000000";

Pump_Val(1) <= "00000000";

Pump_Val(2) <= "00000000";

elsif bits = "110" then

Pump_Val(0) <= "11111111"; --100%

Pump_Val(1) <= "00000000"; --0%

Pump_Val(2) <= "01111111"; --50%

elsif bits = "101" or bits = "100" then

Pump_Val(0) <= "00000000"; --0%

Pump_Val(1) <= "01111111"; --50%

Pump_Val(2) <= "11111111"; --100%

elsif bits = "011" or bits = "000" then

Pump_Val(0) <= "01111111"; --50%

Pump_Val(1) <= "00000000"; --0%

Pump_Val(2) <= "11111111"; --100%

end if;
end if;
end if;
end process;
end Behavioral;

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Design and implementation of FPGA based musical fountain
 CHAPTER 9

INTERFACING FPGA TO MOSFET

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Design and implementation of FPGA based musical fountain
 INTERFACING FPGA TO MOSFET

The output of the FPGA is given to the J2 6pin accessory pin A6 and J1 6pin
accessory header to the pins C5,D5.

The interfacing of FPGA to MOSFET is done through Optocoupler F817.

Optocoupler acts as an isolator. The optocoupler has a LED inside it which is supplied by
output of FPGA. The LED provides the gate signal to the transistor inside F817 which
gives the required the required voltage to the MOSFET gate.
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Design and implementation of FPGA based musical fountain
 The output of the FPGA is given to three MOSFETS which can run a pump each.
The discharge of the pumps are varied according to the musical intensity

CHAPTER 1O
CONCLUSION

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Design and implementation of FPGA based musical fountain
 Conclusion

The aim of this project to design and implement FPGA based musical fountain has
been acheived. The pump varies its speed according to the musical note. FPGA acts as the
controller of the fountain and it is achieved by VHDL programme. Three pumps can be
controlled using the FPGA

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Design and implementation of FPGA based musical fountain
 APPENDIX

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Design and implementation of FPGA based musical fountain
 Wiring Diagram

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Design and implementation of FPGA based musical fountain
 36
Design and implementation of FPGA based musical fountain