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Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-1

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-1

LECTURE 05 - PN JUNCTIONS AND CMOS TRANSISTORS

LECTURE ORGANIZATION

Outline pn junctions

• MOS transistors

• Layout of MOS transistors

• Parasitic bipolar transistors in CMOS technology

• High voltage CMOS transistors

• Summary

CMOS Analog Circuit Design, 3 rd Edition Reference Pages 33-46 and 644-652

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-2

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-2

PN JUNCTIONS How are PN Junctions used in CMOS?

PN junctions are used to electrically isolate one semiconductor region from another

PN diodes

• ESD protection

• Creation of the thermal voltage for bandgap purposes

• Depletion capacitors – voltage variable capacitors (varactors)

Components of a pn junction:

1.) p-doped semiconductor a semiconductor having atoms containing a lack of electrons (acceptors). The concentration of acceptors is N A in atoms per cubic centimeter. 2.) n-doped semiconductor a semiconductor having atoms containing an excess of electrons (donors). The concentration of these atoms is N D in atoms per cubic centimeter.

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-3

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-3

Abrupt PN Junction

Metal-semiconductor junction pn junction Metal-semiconductor junction + p semiconductor n semiconductor Depletion
Metal-semiconductor junction
pn junction
Metal-semiconductor junction
+
p
semiconductor
n semiconductor
Depletion Region
060121-02
W
+
p
semiconductor
n semiconductor
x
0
W
1
W 2
W 1 = Depletion width on p side
W 2 = Depletion width on n side

1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.

2. As these fixed atoms lose their free carriers, they build up an electric field, which opposes the diffusion mechanism.

3. Equilibrium conditions are reached when:

Current due to diffusion = Current due to electric field

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-4

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-4

Influence of Doping Level on the Depletion Regions

Intuitively, one can see that the depletion regions are inversely proportional to the doping level. To achieve equilibrium, equal and opposite fixed charge on both sides of the junction are required. Therefore, the larger the doping the smaller the depletion region on that side of the junction.

The equations that result are:

and

W 1 =

W 2 =

junction. The equations that result are: and W 1 = W 2 = 2( o -v
2( o -v D ) 1   N N A  A qN A
2( o -v D )
1
N
N
A
A
qN A  1 +
N
D
  N N A  A qN A  1 +   N D
2( o -v D ) 1    N D qN D  1
2( o -v D )
1
N
D
qN D  1 + N D
N
A
N A = 10 15 N D = 10 17 9.1nm 910nm N A =
N A = 10 15
N D = 10 17
9.1nm
910nm
N A = 10 19
N D = 10 17
91nm
0.91nm
p-side
n-side
140310-01

Assume that v D = 0, o = 0.637V and N D = 10 17 atoms/cm 3 . Find the p-side depletion region width if N A = 10 15 atoms/cm 3 and if N A = 10 19 atoms/cm 3 :

For N A = 10 15 atoms/cm 3 the p-side depletion width is 0.90 µm. For N A = 10 19 atoms/cm 3 the p-side depletion width is 0.9 nm.

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-5

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-5

Graphical Characterization of the Abrupt PN Junction Assume the pn junction is open-circuited. Cross-section of an ideal pn junction:

x d x p x n p + semiconductor n semiconductor i D + v
x
d
x
p
x
n
p + semiconductor
n semiconductor
i
D
+
v
D
-

060121-03

Symbol for the pn junction:

Built-in potential, o :

N

A

N D

o = V t ln

n

i 2

where

V t = kT

q

,

i D

+ - v D i D + - v D Fig. 06-03
+
-
v
D
i
D
+
-
v D
Fig. 06-03

n i is the intrinsic concentration of silicon.

CMOS Analog Circuit Design

Impurity Concentration (cm -3 ) N D x 0 N A Impurity Concentration (cm -3
Impurity Concentration (cm -3 )
N
D
x
0
N
A
Impurity Concentration (cm -3 )
qN D -W 1 x 0 W 2 -qN A Electric Field ( V/cm) x
qN D
-W 1
x
0
W
2
-qN A
Electric Field ( V/cm)
x
E
0
Potential ( V)
y
o
x
x
d
060121-04
© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-6

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-6

Reverse-Biased PN Junctions Depletion region:

and

x d = x p + x n = W 1 + W 2

x p = W 1

v D i D v R v R
v D
i D
v R
v R
v R
v R

x n = W 2

060121-05

Breakdown voltage (BV):

In the reverse direction the current can be written as, -I R

i D =

v

R

1 - BV

n

CMOS Analog Circuit Design

x d - v R = 0V +
x
d
-
v R = 0V
+

Influence

of v R on

depletion

region width

x d - v R > 0V +
x
d
-
v R > 0V
+
i D BV v D Reverse Forward Bias Bias 060121-06
i D
BV
v D
Reverse
Forward
Bias
Bias
060121-06

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-7

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-7

Breakdown Voltage as a Function of Doping It can be shown that :

BV si (N A + N D ) 2qN A N D

2

E max

where E max = 3x10 5 V/cm for silicon.

An example:

Assume that N D = 10 17 atoms/cm 3 .

Find BV if N A = 10 15 atoms/cm 3 and if N A = 10 19 atoms/cm 3 :

N A = 10 15 atoms/cm 3 :

If N A << N D, then BV

N A = 10 19 atoms/cm 3 :

If N A >> N D, then BV

si

max = 1.04x10 -12 ·9x10 2·1.6x10 -19 ·10

2

10

15

2qN A E

si

max = 1.04x10 -12 ·9x10 2·1.6x10 -19 ·10

2

10

17

2qN D E

= 291V

= 2.91V

P. Allen and D. Holberg, CMOS Analog Circuit Design, 3 rd ed., Oxford University Press, 2012

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-8

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-8

Depletion Capacitance Physical viewpoint of the depletion capacitance:

C j =

si A

si A

d = W 1 +W 2

x d W 1 W 2
x d
W 1
W 2

d

= si A  si A  d = W 1 + W 2 x d
- + - + - + - + - + - + + v D
- +
- +
- +
- +
- +
- +
+ v D
-

060204-01

si A

= 2 si ( o -v D )  N  N D N A
=
2 si ( o -v D )
N
N D
N A +
A
q(N D +N A ) 
N
D
 si qN A N D
1
= A
2(N A +N D )
 o -v D

=

C j0 1 - v D  o
C j0
1 - v D
 o
C j Ideal C j0 Gummel- Poon Effect Reverse Bias v D 0 y o
C
j
Ideal
C j0
Gummel-
Poon Effect
Reverse Bias
v D
0
y o
060204-02

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-9

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-9

Forward-Biased PN Junctions

When the pn junction is forward-biased, the potential barrier is reduced and significant current begins to flow across the junction. This current is given by:

D

V t

v

i D = I s exp

- 1

Dppno

L

p

where I s = qA

+ D n n po

L

n

  qAD

L

n

i 2

N

-V

GO

= KT 3 exp

V

t

Graphically, the i D versus v D characteristics are given as:

the i D versus v D characteristics are given as: CMOS Analog Circuit Design ln(i D

CMOS Analog Circuit Design

ln(i D /I s ) Decade current change/60mV or Octave current change/18mV v D 0V
ln(i D /I s )
Decade current
change/60mV
or
Octave current
change/18mV
v D
0V
060204-03

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-10

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-10

Graded PN Junctions In practice, the pn junction is graded rather than abrupt.

Impurity

Concentration Impurity profile approximates a p + constant slope + n p + Intrinsic Concentration
Concentration
Impurity profile
approximates a
p +
constant slope
+
n
p +
Intrinsic
Concentration
x
x
Junction
0 Surface
060204-04

The previous expressions become:

Depletion region widths-

2

si (o -v D )N D

W 1 =

qN A (N A +N D )

m

2

si (o -v D )N A

W 2 =

qN D (N A +N D )

m

CMOS Analog Circuit Design

W

1

N

m

Depletion capacitance-

si qN A N D

C j = A 2(N A +N D )

C

j0

=

1 - v D

o

m

m

where 0.33 m 0.5.

1

o -v D

m

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-11

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-11

Metal-Semiconductor Junctions

Ohmic Junctions: A metal-semiconductor junction formed by a highly doped semiconductor and metal.

Energy band diagram

IV Characteristics

I

1 Contact Resistance
1
Contact
Resistance

V

140809-02

Vacuum Level Tunneling qf m qf s qf B
Vacuum Level
Tunneling
qf
m
qf s
qf B
V 140809-02 Vacuum Level Tunneling qf m qf s qf B n -type metal E E

n-type metal

E

E

C

F

E

V

Highly doped n-type

semiconductor

Schottky Junctions: A metal-semiconductor junction formed by a lightly doped semiconductor and metal.

E F

CMOS Analog Circuit Design

Energy band diagram

IV Characteristics

Current flow by thermionic emission

qf B
qf B

E C (Forward Bias)

E C (Thermal Equilibrium)

E C (Reverse Bias)

E V (Forward Bias)

E V (Thermal Equilibrium)

E V (Reverse Bias)

I 140809-01
I
140809-01

n-type metal

Low Doped n-type semiconductor

V

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-12

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-12
MOS TRANSISTORS Physical Structure of MOS Transistors in an n-well Technology Substrate Salicide Substrate Salicide
MOS TRANSISTORS
Physical Structure of MOS Transistors in an n-well Technology
Substrate Salicide
Substrate Salicide
Well Salicide
W
W
+
+
+
+
p
+
n + +
+
p
n n
n
L
n n
L
Shallow
Shallow
Trench
Trench
n-well
Isolation
Isolation
p-well
Substrate
070322-02
Gate Ox Oxide
Gate Ox
Oxide
+ p
+
p
p
p
- p
-
p
- n
-
n
n
n
+ n
+
n
Poly
Poly
Salicide Polycide Metal
Salicide
Polycide
Metal

Width (W) of the MOSFET = Width of the source/drain diffusion Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions Note that the MOSFET is isolated from the well/substrate by reverse biasing the resulting pn junction

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-13

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-13

Enhancement MOSFETs The channel of an enhancement MOSFET is formed when the proper potential is applied to the gate of the MOSFET. This potential inverts the material immediately below the gate to the same type of impurity as the source and drain forming the channel.

V GS =0V V S G D Cutoff
V GS =0V
V
S G
D
Cutoff

DS <V DS (sat)

V DS

0V< V GS <V T V S G D Weak Inversion
0V< V GS <V T
V
S G
D
Weak Inversion

DS <V DS (sat)

V DS

V GS >V T V DS <V DS (sat) S G D V DS Strong
V GS >V T
V
DS <V DS (sat)
S G
D
V DS
Strong Inversion
060205-06

V T = Gate-bulk work function (MS ) + voltage to change the surface potential (-2F ) + voltage to offset the channel-bulk depletion charge (-Q b /C ox ) + voltage to compensate the undesired interface charge (-Q ss /C ox )

V T = MS -2F -

Q

Q

- Q b - Q b0

C

ox

b0

ss

C ox -

C

ox

 

|-2F + v SB | -

= V T0 +

 |-2 F |  
|-2 F |

where V T0 = MS - 2F -

CMOS Analog Circuit Design

Q b0

C ox

-

Q

ss

C ox , =

2q si N A C ox
2q si N A
C ox

and

Q b

ss C o x ,  = 2q si N A C ox and Q b

2qN A si (|-2F +v SB |)

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-14

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-14

Depletion Mode MOSFET The channel is diffused into the substrate so that a channel exists between the source and drain with no external gate potential.

the source and drain with no external gate potential. The threshold voltage for a depletion mode

The threshold voltage for a depletion mode NMOS transistor will be negative (a negative gate potential is necessary to attract enough holes underneath the gate to cause this region to invert to p-type material).

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-15

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-15

Weak Inversion Operation

Weak inversion operation occurs when the applied gate voltage is below V T and occurs when the surface of the substrate beneath the gate is weakly inverted.

0V<V GS <V T <V DS (sat) V DS G S D V DS Diffusion
0V<V GS <V T
<V DS (sat)
V DS
G
S
D
V DS
Diffusion
Current
Weak Inversion
060205-07

Regions of operation according to the surface potential, S .

S < F :

F < S < 2F :

2F < S :

Substrate not inverted

Channel is weakly inverted (diffusion current)

Strong inversion (drift current)

Drift current versus diffusion current in a MOSFET:

log i D

10 -6

10 -12

Diffusion Current Drift Current V GS 0 V T
Diffusion Current
Drift Current
V GS
0
V T

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-16

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-16
LAYOUT OF MOS TRANSISTORS Layout of a Single MOS transistor: L STI L Well/Bulk Well/Bulk
LAYOUT OF MOS TRANSISTORS
Layout of a Single MOS transistor:
L
STI
L
Well/Bulk
Well/Bulk
Drain
Drain
W
W
n-well
p-well
Gate Source
Gate Source
060223-01

Comments:

• Make sure to contact the source and drain with multiple contacts to evenly distribute the current flow under the gate.

• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-17

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-17

Diffusion and Etch Effects

• Poly etch rate variation – use dummy elements to prevent etch rate differences.

Dummy

Gate

dummy elements to prevent etch rate differences. Dummy Gate Dummy Gate 041027-03 • Do not put

Dummy

Gate

041027-03

• Do not put contacts on top of the gate for matched transistors.

• Be careful of diffusion interactions for diffusions near the channel of the MOSFET

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-18

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-18

Thermal and Stress Effects

• Oxide gradients – use common centroid geometry layout

• Stress gradients – use proper location and common centroid geometry layout

• Thermal gradients keep transistors well away from power devices and use common centroid geometry layout with interdigitated transistors Examples of Common Centroid Interdigitated transistor layout:

S A /S B S A /S B D A D B D A A
S A /S B
S A /S B
D A
D B
D A
A
B
B
A
G A
G B
G B
G A
Dummy Gate
Dummy Gate

Interdigitated, common centroid layout

041027-04

CMOS Analog Circuit Design

D A

S A /S B

D B

A B G G B A G G B A B A Dummy Gate Dummy
A
B
G
G
B
A
G
G
B
A
B
A
Dummy Gate
Dummy Gate

D B

S B /S A

D A

Cross-Coupled Transistors

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-19

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-19

MOS Transistor Layout Photolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI comes from optical interactions between the UV light and the masks.

Simple illustration of PLI:

Source/Drain Implant Photo- Photo- resist resist 140810-01
Source/Drain Implant
Photo-
Photo-
resist
resist
140810-01

Examples of the layout of matched MOS transistors:

1.) Examples of mirror symmetry and photolithographic invariance.

CMOS Analog Circuit Design

and photolithographic invariance. CMOS Analog Circuit Design Mirror Symmetry Photolithographic Invariance 120328-02 ©
and photolithographic invariance. CMOS Analog Circuit Design Mirror Symmetry Photolithographic Invariance 120328-02 ©

Mirror Symmetry

invariance. CMOS Analog Circuit Design Mirror Symmetry Photolithographic Invariance 120328-02 © P.E. Allen - 2016
invariance. CMOS Analog Circuit Design Mirror Symmetry Photolithographic Invariance 120328-02 © P.E. Allen - 2016

Photolithographic Invariance

120328-02

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-20

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-20

MOS Transistor Layout - Continued 2.) Two transistors sharing a common source and laid out to achieve both photolithographic invariance and common centroid.

both photolithographic invariance and common centroid. Metal 2 Metal 1 Via 1 120328-03 CMOS Analog Circuit
Metal 2 Metal 1 Via 1 120328-03
Metal 2
Metal 1
Via 1
120328-03

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-21

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-21

MOS Transistor Layout - Continued 3.) Compact layout of the previous example.

- Continued 3.) Compact layout of the previous example. Metal 2 Via 1 Metal 1 120328-04
Metal 2 Via 1 Metal 1 120328-04
Metal 2
Via 1
Metal 1
120328-04

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-22

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-22

PARASITIC BIPOLAR TRANSISTORS IN CMOS TECHNOLOGY A Lateral Bipolar Transistor n-well CMOS technology:

• It is desirable to have the lateral collector current much larger than the vertical collector current.

• Lateral BJT generally has good matching.

• The lateral BJT can be used as a photodetector with reasonably good efficiency.

• Triple well technology allows the current of the vertical collector to avoid the substrate.

VC

B

LC

E

LC

+ + + p + p n p STI STI n-well Substrate
+
+
+
p
+
p
n
p
STI
STI
n-well
Substrate
060221-01 Vertical STI Lateral Collector Collector Emitter Base
060221-01
Vertical
STI
Lateral Collector
Collector
Emitter
Base

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-23

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-23

A Field-Aided Lateral BJT Use minimum channel length to enhance beta:

ß F 50 to 100 depending on the process

CMOS Analog Circuit Design

B LC E LC VC + + + + + p p p p n
B
LC
E
LC
VC
+
+
+
+
+
p
p
p
p
n
Keeps carriers from
STI
STI
flowing at the surface
and reduces 1/f noise
n-well
Substrate
060221-02
Vertical
STI
Lateral Collector Emitter
Collector
Base

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-24

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-24

HIGH VOLTAGE CMOS TRANSISTORS Extended Voltage MOSFETS The electric field from the source to drain in the channel is shown below.

Electric

Field

E max

0

Area = V d

x p Pinch-off region x d
x p
Pinch-off region
x d
Field E max 0 Area = V d x p Pinch-off region x d Area =
Area = V p
Area = V p

Distance, x

Source n +

Channel

Drain n +

Substrate depletion region

p - substrate

Source

depletion

region

Drain

depletion

region

p - substrate Source depletion region Drain depletion region 040920-01 The voltage drop from drain to

040920-01

The voltage drop from drain to source is, V DS = V p + V d = 0.5(E max x p + E max x d ) = 0.5E max (x p + x d ) E max and x p are limited by hot carrier generation and channel length modulation requirements whereas these limitations do not exist for x d . Therefore, to get extended voltage transistors, make x d larger.

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-25

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-25

High Voltage Architectures The objective is to create a lightly doped, extended drain region where the high voltage of the drain can drop down to a level that will not cause the gate oxide to breakdown. LOCOS Architecture:

DSM Architecture:
DSM Architecture:
© P.E. Allen - 2016
© P.E. Allen - 2016

CMOS Analog Circuit Design

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-26

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-26

Lateral DMOS (LDMOS) Using LOCOS CMOS Technology The LDMOS structure is designed to provide sufficient lateral dimension and to prevent oxide breakdown by the higher drain voltages. One possible implementation using LOCOS technology:

One possible implementation using LOCOS technology: • Structure is symmetrical about the source/bulk contact

• Structure is symmetrical about the source/bulk contact

• Channel is formed in the p region under the gates

• The lightly doped n region between the drain side of the channel and the n + drain contact (x d ) increases the depletion region width on the drain side of the channel/drain pn junction resulting in larger values of v DS .

• Drain voltage can be 20-100V depending on the spacing and doping.

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-27

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-27

Lateral DMOS (LDMOS) Using DSM CMOS Technology Cross-section of an NLDMOS using DSM technology:

Technology Cross-section of an NLDMOS using DSM technology: Differences between an NLDMOS and NMOS: • Asymmetry

Differences between an NLDMOS and NMOS:

• Asymmetry

• Non-uniform channel

• Current flow (not all at the surface)

• No self-alignment (larger drain-gate overlap capacitance)

• Note the extended drift region on the drain side of the channel

= 0V > V > 0 V S V G T V D Poly STI
= 0V
> V
> 0
V S
V G
T
V D
Poly
STI
STI
Depletion
region
120624-03

CMOS Analog Circuit Design

© P.E. Allen - 2016

Lecture 05 PN Junction and CMOS Transistors (8/5/14)

Page 05-28

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-28

SUMMARY

pn junction usage in CMOS include:

- Electrical isolation, pn diodes, ESD protection, depletion capacitors

• Depletion region widths are inversely proportional to the doping

• Depletion region widths are proportional to the reverse bias voltage

• Ohmic metal-semiconductor junctions require a highly doped semiconductor

• MOSFETs can be:

- Enhancement the applied gate voltage forms the channel

- Depletion the channel is physically constructed in fabrication

• The threshold voltage of MOSFETs consists of the following components:

- Gate bulk work function (MS )

- Voltage to change the surface potential (-2F )

- Voltage to offset the channel-bulk depletion charge (-Q b /C ox )

- Voltage to compensate the undesired interface charge (-Q ss /C ox )

• Weak inversion is MOSFET operation with the gate-source voltage less than the threshold voltage

• Layout of the MOSFET is important to its performance and matching capabilities

Extended drain regions lead to higher voltage capability MOSFETs

CMOS Analog Circuit Design

© P.E. Allen - 2016