Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-1

LECTURE 05 - PN JUNCTIONS AND CMOS TRANSISTORS

LECTURE ORGANIZATION
Outline
• pn junctions
• MOS transistors
• Layout of MOS transistors
• Parasitic bipolar transistors in CMOS technology
• High voltage CMOS transistors
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 33-46 and 644-652

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-2

PN JUNCTIONS
How are PN Junctions used in CMOS?
• PN junctions are used to electrically isolate one semiconductor region from another
• PN diodes
• ESD protection
• Creation of the thermal voltage for bandgap purposes
• Depletion capacitors – voltage variable capacitors (varactors)

Components of a pn junction:
1.) p-doped semiconductor – a semiconductor having atoms containing a lack of
electrons (acceptors). The concentration of acceptors is NA in atoms per cubic
centimeter.
2.) n-doped semiconductor – a semiconductor having atoms containing an excess of
electrons (donors). The concentration of these atoms is ND in atoms per cubic
centimeter.

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-3

Abrupt PN Junction
Metal-semiconductor junction pn junction Metal-semiconductor junction

p+ semiconductor n semiconductor

Depletion Region
W 060121-02

p+ semiconductor n semiconductor
W1 0 x
W2
W1 = Depletion width on p side W2 = Depletion width on n side

1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-4

Influence of Doping Level on the Depletion Regions

Intuitively, one can see that the depletion regions are inversely proportional to the doping
level. To achieve equilibrium, equal and opposite fixed charge on both sides of the
junction are required. Therefore, the larger the doping the smaller the depletion region
on that side of the junction.
NA = 1015 ND = 1017
The equations that result are: 9.1nm
2(o -vD) 1
W1 =  910nm
 NA  NA
qNA1 + N 
 D
NA = 1019 ND = 1017
and
2(o -vD) 1 91nm

ND 
W2 = 0.91nm
 ND
qND1 +  p-side n-side
 N A 140310-01

Assume that vD = 0, o = 0.637V and ND = 1017 atoms/cm3. Find the p-side depletion
region width if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
For NA = 1015 atoms/cm3 the p-side depletion width is 0.90 µm.
For NA = 1019 atoms/cm3 the p-side depletion width is 0.9 nm.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-5

Graphical Characterization of the Abrupt PN Junction

Assume the pn junction is open-circuited. Impurity Concentration (cm -3)
ND
Cross-section of an ideal pn junction: x
xd 0
xp
xn NA
Impurity Concentration (cm -3)
qND
p+ semiconductor n semiconductor -W1
x
iD
0 W2
+ vD - -qNA
060121-03

Symbol for the pn junction: Electric Field (V/cm)

iD
Built-in potential, o: x
NAND +v -
o = Vt ln 2  , D E0
 ni  iD
Potential (V)
where
+v -
kT D Fig. 06-03 yo
Vt = q x

xd
ni is the intrinsic concentration of silicon. 060121-04

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-6

Reverse-Biased PN Junctions
Depletion region: xd
xd = xp + xn = W1 + W2 Influence
vD of vR on
xp = W1  vR depletion
iD region width
and - vR = 0V +
vR xd
xn = W2  vR

060121-05
- vR > 0V +
Breakdown voltage (BV):
In the reverse direction the current iD
can be written as,
-IR BV
iD = vD
 vR n Reverse Forward
1 - BV
  Bias Bias

060121-06

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-7

Breakdown Voltage as a Function of Doping

It can be shown that†:
si(NA + ND) 2
BV ≈ Emax
2qNAND
where Emax = 3x105 V/cm for silicon.
An example:
Assume that ND = 1017 atoms/cm3.
Find BV if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
NA = 1015 atoms/cm3:
si2 1.04x10-12·9x1010
If NA << ND, then BV ≈ E = = 291V
2qNA max 2·1.6x10-19·1015
NA = 1019 atoms/cm3:
si2 1.04x10-12·9x1010
If NA >> ND, then BV ≈ E = = 2.91V
2qND max 2·1.6x10-19·1017

†
P. Allen and D. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-8

Depletion Capacitance
Physical viewpoint of the depletion capacitance:
d
xd
- +
- +
- +
- +
- +
- +
W1 W2 060204-01 + vD -
siA siA
Cj = d = W +W
1 2
siA Cj
=
2si(o-vD)  ND NA  Ideal
 
q(ND+NA)  NA + ND  Cj0 Gummel-
siqNAND 1 Poon Effect
=A 2(NA+ND) o-vD Reverse Bias
Cj0
=
v
yo D
vD 0
1-
o 060204-02

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-9

Forward-Biased PN Junctions
When the pn junction is forward-biased, the potential barrier is reduced and significant
current begins to flow across the junction. This current is given by:
 vD  Dppno Dnnpo qAD ni2 -VGO
iD = Isexp V  - 1 where Is = qA L + L  ≈ L N = KT exp V  3
  t   p n   t 
Graphically, the iD versus vD characteristics are given as:

ln(iD/Is)

Decade current
change/60mV
or
Octave current
change/18mV
vD
0V 060204-03

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-10

Graded PN Junctions
In practice, the pn junction is graded rather than abrupt.
Impurity
Concentration Impurity profile
approximates a
p+
constant slope
n+ p+
Intrinsic
x Concentration
x
0
Surface Junction
060204-04

The previous expressions become:

Depletion region widths- Depletion capacitance-
2si(o-vD)NDm   siqNAND m 1
W1 =  qN (N +N )   C j = A  
 A A D   1 m
2(NA+ND) o-vDm
2si(o-vD)NAm
 W  N
 

W2 =  qN (N +N )  
Cj0
D A D  

=
 v D m
1 - 
 o
where 0.33 m  0.5.

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-11

Metal-Semiconductor Junctions
Ohmic Junctions: A metal-semiconductor junction formed by a highly doped
semiconductor and metal.
Energy band diagram IV Characteristics
I

Vacuum Level 1

qfm Tunneling
Contact
qfs
qfB EC Resistance
EF V
EV
n-type metal Highly doped n-type 140809-02
semiconductor

Schottky Junctions: A metal-semiconductor junction formed by a lightly doped

semiconductor and metal.
Energy band diagram IV Characteristics
Current flow by thermionic emission
I

qfB EC (Forward Bias)

EF EC (Thermal Equilibrium)
EC (Reverse Bias)
EV (Forward Bias) V
EV (Thermal Equilibrium)
EV (Reverse Bias) 140809-01
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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-12

MOS TRANSISTORS
Physical Structure of MOS Transistors in an n-well Technology
Substrate Salicide Substrate Salicide

Well Salicide

W W
n+ p+ p+ nn++ nnn+++
L L
Shallow Shallow
Trench Trench
Isolation n-well Isolation
p-well

Substrate 070322-02

Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal

Width (W) of the MOSFET = Width of the source/drain diffusion

Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions
Note that the MOSFET is isolated from the well/substrate by reverse biasing the
resulting pn junction

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-13

Enhancement MOSFETs
The channel of an enhancement MOSFET is formed when the proper potential is applied
to the gate of the MOSFET. This potential inverts the material immediately below the
gate to the same type of impurity as the source and drain forming the channel.
VGS=0V 0V<VGS<VT V <V (sat) VGS>VT
VDS<VDS(sat) DS DS VDS<VDS(sat)
S G D S G D S G D
VDS VDS VDS

Cutoff Weak Inversion Strong Inversion

060205-06

VT = Gate-bulk work function (MS) + voltage to change the surface potential (-2F)
+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)
+ voltage to compensate the undesired interface charge (-Qss/Cox)
Qb0 Qss Qb - Qb0
VT = MS -2F - C - C - C = VT0 +   |-2F + vSB| - |-2F|
ox ox ox
where Qb0 Qss 2qsiNA
VT0 = MS - 2F - C - C ,  = and Qb ≈ 2qNAsi(|-2F+vSB|)
ox ox Cox
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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-14

Depletion Mode MOSFET

The channel is diffused into the substrate so that a channel exists between the source and
drain with no external gate potential.

The threshold voltage for a depletion mode NMOS transistor will be negative (a negative
gate potential is necessary to attract enough holes underneath the gate to cause this
region to invert to p-type material).

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-15

Weak Inversion Operation

0V<VGS<VT VDS<VDS(sat)
Weak inversion operation occurs when the applied
gate voltage is below VT and occurs when the surface S G D
VDS
of the substrate beneath the gate is weakly inverted.

Regions of operation according to the surface Diffusion

potential, S. Current
Weak Inversion
S < F : Substrate not inverted 060205-07

F < S < 2F : Channel is weakly inverted (diffusion current)

2F < S : Strong inversion (drift current)
Drift current versus
log iD
diffusion current
Diffusion Current
in a MOSFET: Drift Current
10-6

10-12 VGS
0 VT

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-16

LAYOUT OF MOS TRANSISTORS

Layout of a Single MOS transistor:

L STI L
Well/Bulk Well/Bulk
Drain Drain

W W

n-well p-well

Gate Source Gate Source

060223-01

Comments:
• Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.
• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-17

Diffusion and Etch Effects

• Poly etch rate variation – use dummy elements to prevent etch rate differences.
Dummy Dummy
Gate Gate

041027-03

• Do not put contacts on top of the gate for matched transistors.

• Be careful of diffusion interactions for diffusions near the channel of the MOSFET

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-18

Thermal and Stress Effects

• Oxide gradients – use common centroid geometry layout
• Stress gradients – use proper location and common centroid geometry layout
• Thermal gradients – keep transistors well away from power devices and use common
centroid geometry layout with interdigitated transistors
Examples of Common Centroid Interdigitated transistor layout:
DA SA/SB DB
DA SA/SB DB SA/SB DA

A B

Dummy Gate
Dummy Gate

Dummy Gate

Dummy Gate
A B B A GA GB
GB GA

B A

GA GB GB GA
Interdigitated, common centroid layout
DB SB/SA DA
041027-04
Cross-Coupled Transistors

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-19

MOS Transistor Layout

Photolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI
comes from optical interactions between the UV light and the masks.
Source/Drain Implant
Simple illustration of PLI:
Photo- Photo-
resist resist
140810-01

Examples of the layout of matched MOS transistors:

1.) Examples of mirror symmetry and photolithographic invariance.

Mirror Symmetry Photolithographic Invariance

CMOS Analog Circuit Design 120328-02 © P.E. Allen - 2016
Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-20

MOS Transistor Layout - Continued

2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.

Metal 2 Metal 1
Via 1

120328-03

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-21

MOS Transistor Layout - Continued

3.) Compact layout of the previous example.

Metal 2

Via 1

Metal 1

120328-04

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-22

PARASITIC BIPOLAR TRANSISTORS IN CMOS TECHNOLOGY

A Lateral Bipolar Transistor VC B LC E LC
n-well CMOS technology: n+ p+ p+ p+
• It is desirable to have the lateral
STI STI
collector current much larger than the
vertical collector current. n-well

• Lateral BJT generally has good Substrate

060221-01
matching.
• The lateral BJT can be used as a Vertical STI Lateral Collector
Collector
photodetector with reasonably good
efficiency. Emitter
• Triple well technology allows the
current of the vertical collector to
avoid the substrate.
Base

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-23

A Field-Aided Lateral BJT

Use minimum channel length to VC B LC E LC

enhance beta:
ßF  50 to 100 depending on the n+ p+ p+ pp++
Keeps carriers from
process STI flowing at the surface STI
and reduces 1/f noise
n-well
Substrate
060221-02

Vertical STI Lateral Collector Emitter

Collector

Base

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-24

HIGH VOLTAGE CMOS TRANSISTORS

Extended Voltage MOSFETS
The electric field from the source to drain in the channel is shown below.
Electric
Field
Emax

Area = Vp Area = Vd
0
Distance, x
Pinch-off region xp xd

Channel
Source n+ Drain n+
Source Drain
depletion depletion
region region
Substrate depletion region
p - substrate
040920-01

The voltage drop from drain to source is,

VDS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)
Emax and xp are limited by hot carrier generation and channel length modulation
requirements whereas these limitations do not exist for xd.
Therefore, to get extended voltage transistors, make xd larger.

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-25

High Voltage Architectures

The objective is to create a lightly doped, extended drain region where the high voltage
of the drain can drop down to a level that will not cause the gate oxide to breakdown.
LOCOS Architecture:

DSM Architecture:

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-26

Lateral DMOS (LDMOS) Using LOCOS CMOS Technology

The LDMOS structure is designed to provide sufficient lateral dimension and to prevent
oxide breakdown by the higher drain voltages.
One possible implementation using LOCOS technology:

• Structure is symmetrical about the source/bulk contact

• Channel is formed in the p region under the gates
• The lightly doped n region between the drain side of the channel and the n+ drain
contact (xd) increases the depletion region width on the drain side of the channel/drain
pn junction resulting in larger values of vDS.
• Drain voltage can be 20-100V depending on the spacing and doping.
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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-27

Lateral DMOS (LDMOS) Using DSM CMOS Technology

Cross-section of an
NLDMOS using DSM
technology:

Differences between an NLDMOS and NMOS:

VS = 0V VG > VT VD > 0
• Asymmetry
Poly
• Non-uniform channel
STI STI
• Current flow (not all at the surface) Depletion
• No self-alignment (larger drain-gate overlap region
capacitance)
• Note the extended drift region on the drain side of the
channel 120624-03

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Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-28

SUMMARY
• pn junction usage in CMOS include:
- Electrical isolation, pn diodes, ESD protection, depletion capacitors
• Depletion region widths are inversely proportional to the doping
• Depletion region widths are proportional to the reverse bias voltage
• Ohmic metal-semiconductor junctions require a highly doped semiconductor
• MOSFETs can be:
- Enhancement – the applied gate voltage forms the channel
- Depletion – the channel is physically constructed in fabrication
• The threshold voltage of MOSFETs consists of the following components:
- Gate bulk work function (MS)
- Voltage to change the surface potential (-2F)
- Voltage to offset the channel-bulk depletion charge (-Qb/Cox)
- Voltage to compensate the undesired interface charge (-Qss/Cox)
• Weak inversion is MOSFET operation with the gate-source voltage less than the
threshold voltage
• Layout of the MOSFET is important to its performance and matching capabilities
• Extended drain regions lead to higher voltage capability MOSFETs
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