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System On Chip Design

HW SW Codesign


P.Jayakrishnan Assistant Professor (Sr.)

Department of Micro & Nano Electronics

School of Electronics Engineering VIT University, Vellore

HW SW Co-Design

The word system refers to any functional device

implemented in hardware, software, or combinations of the two.

When it is a combination of hardware and software, we normally call it Hardware and software codesign.






software codesign.




System design begins with specifying the required


System design is to transform the system functionality into an architecture.

The design process or methodology is the set of design tasks that transform an abstract specification model into an architectural model.


The overall process of system design (codesign) begins

with identifying the system requirements.

They are the required functions, performance, power, cost, reliability, and development time for the system.

These requirements form the preliminary specifications often produced by the development teams and marketing professionals

HW SW Codesign Methodology

HW SW Codesign Methodology 5


Given the high-level model, software and hardware partitions is done based

on functions performed by the hardware and what should be achieved by the software applications.

Once the hardware and software partitions have been determined, a

behavioral model of the hardware is created together with a working prototype of the software.

The cosimulation of hardware and software allows these components to be refined and to develop an executable model with fully functional specs.

Some of the major hardware design considerations in this process are clock

tree, clock domains, layout, floor planning, buses, verification, synthesis, and interoperability issues.


A number of research groups have developed tools for codesign.

Single processor architecture: Cosyma

Multiprocessor architecture: Chinook

COSYMA (co-synthesis for embedded microarchitecture)

Cosyma is an experimental system for design space exploration for hardware and software codesign.

The target architecture of Cosyma consists of a standard RISC

processor, RAM, and an automatically generated application-

specific coprocessor.

For ASIC development using these components, the peripheral

units are required to be put in by the ASIC designer.

The host processor and coprocessor communicate via shared memory.

Cosyma Design flow

Cosyma Design flow 9


Design Methodology for Logic cores

In design flow, although the architectural design is based on hardware and software codevelopment, the VLSI design requires simultaneous analysis and optimization of area, performance, power.

Because SoC may also contain embedded software, the design methodology also requires that the both hardware and software be developed concurrently to ensure correct functionality.

The first part in this design process consists of recursive development and verification of a set of specifications until it is

detailed enough to allow RTL implementation.

Architecture of the Present-Day SoC

In all SoC designs, predesigned cores are the essential

components. A system chip may contain combinations of cores for on-chip functions such as microprocessors, DSP

functions, and so on.

These cores are generally available in either synthesizable high-level description language (HDL) form such as in Verilog/VHDL, or optimized transistor-level layout such as GDSII.

The flexibility in the use of cores also depends on

the form in which they are available. Subsequently, soft, firm, and hard cores are defined as follows:

Soft cores: These are reusable blocks in the form of

a synthesizable RTL description or a netlist of

generic library elements. This implies that the user of soft core (macro) is responsible for the actual

implementation and layout.

Firm cores: These are reusable blocks that have been

structurally and topologically optimized for performance and area through floor planning and placement, perhaps

using a range of process technologies. These exist as

synthesized code or as a netlist of generic library elements.

Hard cores: These are reusable blocks that have been

optimized for performance, power, and size, and mapped to a specific process technology. These exist as a fully placed

and routed netlist and as a fixed layout such as in GDSII