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CONTENTS
VTU (OCB and CBCS) Syllabus for Basic Electronics (18ELN14/24) iii
1. Semiconductor Diodes and Applications

1.1 PN junction diode 2
1.2 Equivalent circuit of diode 7
1.3 Zener Diode 9
1.4 Zener diode as a voltage regulator 11
1.5 Rectification
1.5.1 Half wave rectifier 14
1.5.2 Full wave rectifier 15
1.5.3 Bridge rectifier 16
1.5.4 Capacitor filter circuit 21
1.6 Photo diode 22
1.7 LED 23
1.8 Photo coupler 24
1.9 78XX series, 7805 Fixed IC voltage regulator 25
Solved Examples 26
Exercise 27
Tutorial Questions 28
Multiple Choice Questions 28
Key Answers 31
2. FET and SCR

2.1 Introduction 33
2.2 JFET: Construction and operation 33
2.3 JFET Drain Characteristics and Parameters 35
2.4 JFET Transfer Characteristic, Square law
expression for ID, Input resistance RDS 37
2.5 MOSFET: Depletion and Enhancement type 38
2.6 MOSFET- Construction, Operation 39
2.7 Characteristics and Symbols 40
2.8 CMOS Circuits 42
2.9 Silicon Controlled Rectifier (SCR) – Two- transistor model 43
2.10 SCR Characteristics 45
2.11 Phase control Application 46
Exercise 47
Solved Examples 48
Key Answers 53
3. Operational Amplifiers and Applications

3.1 Introduction to Op-amp 55
3.2 Op-Amp Parameters 55
3.3 Op-Amp Input Modes 58
3.4 Applications of Op-Amp
3.4.1 Inverting amplifier 59
3.4.2 Non-Inverting amplifier 60
3.4.3 Summer 61
3.4.4 Voltage Follower 62
3.4.5 Differentiator 63
3.4.6 Integrator 64
3.4.7 Comparator 65
Exercise 65
Problems 66
4. BJT Applications, Feedback Amplifiers and Oscillators

4.1 Introduction 72
4.2 BJT as an amplifier 72
4.3 BJT as a switch 74
4.4 Transistor switch circuit to switch ON/OFF an LED and a lamp
in a power circuit using a relay 74
4.5 Feedback Amplifiers – Principle 76
4.6 Properties and advantages of Negative Feedback 78
4.7 Types of feedback 76
4.8 Voltage series feedback 79
4.9 Gain stability with feedback 80
4.10 Oscillators – Barkhaunsen's criteria for oscillation 80
4.11 RC Phase Shift oscillator 81
4.12 Wien Bridge oscillator 83
4.13 IC timer 555 84
4.14 Astable Oscillator using 555 85
Appendix – A Analysis of RC Phase shift Oscillator 88
Exercise 91
5. Digital Electronics Fundamentals

5.1 Introduction 94
5.2 Difference between analog and digital signals 95
5.3 Number System - Binary, Hexadecimal, Conversion - Decimal to
binary, Hexadecimal to decimal and vice-versa 97
5.4 Boolean algebra 100
5.5 Basic and Universal Gates 102
5.6 Half and Full adder 107
5.7 Multiplexer 109
5.8 Decoder 110
5.9 SR and JK flip-flops 111
5.10 Shift register 113
5.11 Basic Communication System 115
5.12 Principle of operation of Mobile phone 115
Exercise 117
ii
[As per Out Come Based (OCB) and Choice Based Credit System (CBCS) scheme]
SEMESTER – I/II CIA Marks: 40 SEE Marks: 60 Credits – 03
Total Number of Lecture Hours: 40 (08 Hours per Module) Exam Hours : 03
Course objectives: This course will enable students to:
transistors, field effect transistors, SCRs and operational amplifiers in electronic circuits.
ntal building blocks of digital
circuits.
Module-1: Semiconductor Diodes and Applications
PN junction diode,
Equivalent circuit of diode,
Zener Diode, Zener diode as a voltage regulator,
Rectification-Half wave rectifier, Full wave rectifier, Bridge rectifier, Capacitor filter circuit
Photo diode, LED, Photocoupler.
78XX series and 7805 Fixed IC voltage regulator. RBT Levels - L1, L2, L3
Module-2: FET and SCR
Introduction JFET: Construction and operation,

JFET Drain Characteristics and Parameters, JFET Transfer Characteristic, Square law expression
for ID, Input resistance,
MOSFET: Depletion and Enhancement type MOSFET- Construction, Operation, Characteristics
and Symbols, CMOS.
Silicon Controlled Rectifier (SCR) – Two-transistor model, Switching action, Characteristics,
Phase control application. RBT Levels - L1, L2, L3
Module-3: Operational Amplifiers and Applications
Introduction to Op-Amp, Op-Amp Input Modes, Op-Amp Parameters-CMRR, Input Offset

Voltage and Current, Input Bias Current, Input and Output Impedance, Slew Rate.
Applications of Op-Amp -Inverting amplifier, Non-Inverting amplifier, Summer, Voltage
follower, Integrator, Differentiator, Comparator. RBT Levels - L1, L2, L3
Module-4: BJT Applications, Feedback Amplifiers and Oscillators
BJT as an amplifier, BJT as a switch, Transistor switch circuit to switch ON/OFF an LED and a
lamp in a power circuit using a relay.
Feedback Amplifiers – Principle, Properties and advantages of Negative Feedback, Types of
feedback, Voltage series feedback, Gain stability with feedback.
Oscillators – Barkhaunsen's criteria for oscillation, RC Phase Shift oscillator, Wien Bridge
oscillator.
IC 555 Timer and Astable Oscillator using IC 555. RBT Levels - L1, L2, L3
iii
Module-5: Digital Electronics Fundamentals
Difference between analog and digital signals,

Number System- Binary, Hexadecimal, Conversion- Decimal to binary, Hexadecimal to decimal
and vice-versa,
Boolean algebra, Basic and Universal Gates,
Half and Full adder, Multiplexer, Decoder,
SR and JK flipflops, Shift register, 3 bit Ripple Counter.
Basic Communication system, Principle of operations of Mobile phone. RBT Levels - L1, L2
Course Outcomes: After studying this course, students will be able to:
· Describe the operation of diodes, BJT, FET and Operational Amplifiers.

· Designand explainthe construction of rectifiers, regulators, amplifiers and oscillators.
· Describe general operating principles of SCRs and its application.
· Explain the working and design of Fixed voltage IC regulator using 7805 and Astable oscillator
using Timer IC 555.
· Explain the different number system and their conversions and construct simple combinational
and sequential logic circuits using Flip-Flops.
· Describe the basic principle of operation of communication system and mobile phones.
Proposed Activities to be carried out for 10 marks of CIE:
Students should construct and make the demo of the following circuits in a group of 3/4 students:
1. +5v power supply unit using Bridge rectifier, Capacitor filter and IC 7805.
2. To switch on/off an LED using a Diode in forward/reverse bias using a battery cell.
3. Transistor switch circuit to operate a relay which switches off/on an LED.
4. IC 741 Integrator circuit/ Comparator circuit.
5. To operate a small loud speaker by generating oscillations using IC 555.
Question paper pattern:

Examination will be conducted for 100 marks with question paper containing 10 full questions,
each of 20 marks.
· Each full question can have a maximum of 4 sub questions.
· There will be 2 full questions from each module covering all the topics of the module.
· Students will have to answer 5 full questions, selecting one full question from each module.
· The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Books:
1. D.P.Kothari, I.J.Nagarath, “Basic Electronics”, 2nd edn, McGraw Hill, 2018.
2. Thomas L. Floyd, “Electronic Devices”, Pearson Education, 9th edition, 2012.
Reference Books:
1. D.P.Kothari, I.J.Nagarath, “Basic Electronics”, 1st edn, McGraw Hill, 2014.
2. Boylestad, Nashelskey, “Electronic Devices and Circuit Theory”, Pearson Education, 9th
Edition, 2007/11th edition, 2013.
3. David A. Bell, “Electronic Devices and Circuits”, Oxford University Press, 5th Edition, 2008.
4. Muhammad H. Rashid, “Electronics Devices and Circuits”, Cengage Learning, 2014.
iv
Basic Electronics (18ELN14/24)
Module – 1 Semiconductor Diodes and Applications
1.1 PN junction diode

1.2 Equivalent circuit of diode
1.3 Zener Diode
1.4 Zener diode as a voltage regulator
1.5 Rectification
1.5.1 Half wave rectifier
1.5.2 Full wave rectifier
1.5.3 Bridge rectifier
1.5.4 Capacitor filter circuit
1.6 Photo diode
1.7 LED
1.8 Photocoupler
1.9 78XX series
1.10 7805 Fixed IC voltage regulator
Easwara M 1
1.1 PN Junction Diode

When P-type and N-type semiconductors are joined together, at that instant PN junction is formed. This
is also called as PN junction diode. Diode is a two terminal device which allows current to flow only in
one direction, offering less resistance. The structure and the circuit symbol are as shown in the fig.1.1.
Fig.1.1 structure and circuit symbol of the PN junction Diode
Diode has an arrow head symbol (►) indicating the conventional direction of current flow in Forward
Bias condition.
Unbiased Diode : When no external DC voltage is applied between Anode and Cathode, it is said to
be unbiased Diode. The instant, P-type and N-type semiconductors are joined; the following
phenomenon takes place immediately.
(i) The majority electrons from N-side diffuse (spread) into P-side and the majority holes from
P-side diffuse into N-side. It is as shown in the fig.1.2 (a).
(ii) The free electron – hole recombination creates a pair of ions. Fixed positive ions on N-side
and fixed negative ions on P-side. It is as shown in the fig.1.2 (b).
Fig.1.2 (a) Holes from P-Type diffuse into N-Type and Electrons from N-Type diffuse into P-Type
Fig.1.2 (b) Holes and electrons recombined across the PN junction causes depletion region
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The region of positive ions on N-side and negative ions on P-side at the junction is called the depletion
region.
(iii) An electric potential is developed due to the immobile positive and negative ions (known as
barrier potential, VB) that stops further re-combination of electrons and holes.
(iv) This barrier potential, VB, causes the movement of minority charge carriers in opposite
direction. This is called drift current (very small in magnitude in terms of µA or ɳA).
(v) In equilibrium state, the net current across the junction is zero.
Types of Diode Biasing
Biasing is the process of applying external DC voltage across the device to bring it into the operating
condition. There are two types of biasing:
1. Forward Biasing (FB) and
2. Reverse Biasing (RB)
Forward Biasing: Diode is said to be Forward Biasing, if P-side is connected to positive (+) and N-
side is connected to negative (-) of the battery, VF as shown in the fig.1.3.
(a) (b)
Fig.1.3 (a) Diode under Forward Biasing condition (depletion width decreases)
(b) Practical diode circuit acts like a closed switch
Let VF be the forward voltage applied across the terminals of the diode D and VB be the barrier potential
developed across the PN junction. When FB is applied across the diode; the following points are
observed.
(i) If VF < VB, diode does not conduct and no current flows through the diode (i.e, ID = 0). Because, the
depletion width will not decrease. That means, electrons cannot gain enough energy to cross over the
depletion region and move towards P-region. Same applies to holes in the opposite.
(ii) If VF > VB, diode conducts and current flows in the circuit. This is because, holes of P-region are
repelled by (+) and electrons of N-region are repelled by (-) of the battery, VF. As a result, depletion
width reduces. It is as shown in the fig.1.3 (a).
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(iii) If VF >> VB and since, forward biased diode offers less resistance, current rises sharply. It is desired
an external series resistance R, to limit the diode current ID, as shown in fig. 1.3(b).
Example 1: Find the value of series resistance R, required to driving a forward current of 1.25mA
through a Germanium diode from a 4.5V battery. Write the circuit diagram showing all the values.
VTU (14ELN15/25) June/July 2015
Solution: Given IF = 1.25mA,
V = 4.5V,
VD = 0.3V
Using Ohm’s law, V = IF R and from fig Ex 1
(4.5 – 0.3) = 1.25 x 10-3 R
R = 4.2 / (1.25 x 10-3) = 3.36 K Ω
R = 3.36K Ω Fig. Ex 1
[NOTE: The amount of energy required by electrons to cross the junction is

equal to the barrier potential, VB (0.3V for Germanium diode and 0.7V for
Silicon). This means, when diode is FB, voltage drop across the diode ≡ 0.7V
for (Si) and 0.3V for (Ge)]
Reverse Biasing: Diode is said to be reverse biasing, if P-side is connected to negative (-) and N-side
is connected to positive (+) of the battery, VR as shown in the fig. 1.4(a).
When RB is applied across the diode; the following phenomena occur.
(i) Quickly, electronics of N-side are attracted towards the positive (+) and holes of P-side are attracted
towards the negative (-) of the battery. This reduces the number of majority carriers on either side of the
regions and depletion width increases. It is as shown in the fig.1.4 (a). Additional more positive and
negative immobile ions are created across the junction. This increases the resistance of the crystal. As a
result, diode does not conduct and current ID due to the majority carriers is zero (ID = 0).
(a) (b)
Fig.1.4 (a) Diode under Reverse Bias condition (increase in the depletion width).
(b) Practical diode circuit acts like a open switch.
Easwara M 4
(ii) Electrons of P- region and holes of N-region (minority charge carriers) are pushed towards the PN
junction by the respective battery terminals. This constitutes a very small reverse current called reverse
saturation current IS. The magnitude is in terms of µA or ɳA.
V I – Characteristics of Diode
V I means, Volt – Ampere, is an experimental study to analyze graphically the electrical behavior
(relationship between voltage and current) of the device. V I – Characteristics of the Diode (shown in
fig.1.5) is non-linear (not straight line), because its resistance is not constant.
1. Forward Characteristics
This is ON mode of diode. P-side is connected to positive (+) and N-side is connected to negative (-) of
the battery. From the fig. 1.5(a) the following point are observed.
(i) The current in this mode is called forward current, IF, only due to majority carriers.
(ii) At VF = 0, diode does not conduct, hence there is no forward current (i.e., IF = 0).
(iii) With gradual increase in the forward voltage VF, forward current IF increases.
(iv) Continuing increase of VF, causes rapid increase of IF, because diode offers less resistance.
(vi) The knee voltage, at which diode current starts to increase rapidly (0.3V for Germanium diode
and 0.7V for Silicon). Above knee voltage, the diode current is almost exponential growth.
(vii) Dynamic resistance of the diode, rD = Ω
VBR(Si) VBR(Ge)
(a) (b)
Fig.1.5 V-I characteristics of diode: (a) Forward Biased characteristics (b) Reverse Biased characteristics of Silicon
and Germanium diodes
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Comparison of VI characteristics between Silicon and Germanium diode is illustrated in the fig. 1.5.
Parameter Silicon (Si) Germanium (Ge)
1. ICBO at 25°C 0.01 µA to 1µA 2 to 15 µA.
2. variation of ICBO with ICBO  doubles with each 8 to 10°C ICBO  doubles with each 12°C
temperature rise rise
3. working temperature operated up to 150°C operated up to 70°C
4. potential barrier 0.7V 0.3V
5. PIV ratings 1000V close to 400V
Example 2: The incremental change in the voltage and the current is found to be 0.19 V and 37.6 mA
respectively from the forward characteristics of the diode. Determine the AC resistance of the
junction. VTU (11ELN15/25) Jan 2013
Solution: Given ΔIF = 37.6 mA,

ΔVF = 0.19 V
AC resistance = Dynamic resistance of the diode,
= Ω
i.e., slope of fig Ex 2 =
= = 5.05 Ω
= 5.05 Ω Fig. Ex 2
2. Reverse Characteristics
This is OFF mode of diode. P-side is connected to positive (+) and N-side is connected to negative (-) of
the battery. From the fig. 1.5 (b), the following points are observed.
(i) The majority carrier current is blocked, but very small reverse current called reverse saturation
current IS flows due to minority charge carriers (see fig. 1.5 (b)).
(ii) At a point called break down voltage, VBR, reverse current IR sharply increases. This is not normal
mode of operation. That means, if IR exceeds the maximum rating, diode will get damage.
(iii) Break down voltage depends on doping level, set by the manufacturer.
Diode parameters or Specifications

Diode specifications are the ratings of diodes important in circuit design and component selection. The
list below provides a summary of some of the more widely used diode specifications, with their
meanings.
1. Forward Voltage (VF): Forward voltage is the voltage drop across a PN junction diode during
forward biased condition. It is due to the majority carriers, measured in volts.
2. Forward Current (IF): It is a current flowing through forward biased diode (due to the majority
carriers), measured in milli ampere (mA).
3. Reverse Current (IR): It is a current flowing through reverse biased diode (due to the minority
carriers), measured in µA or ɳA.
Easwara M 6
4. Reverse Break down Voltage (VBR) or Peak Inverse Voltage (PIV): It is a maximum reverse
voltage that a diode can withstand without damage, measured in volts.
5. Power Dissipation (PD): It is the product of diode voltage, VD and diode current, ID.
i.e., PD = VD ID, measured in watts.
1.2 Diode Equivalent Circuit

Diode equivalent circuits or approximations describe the behavior of diode circuit. It is useful in the
analysis of the device. In the approximation, the equivalent circuit involves voltage cells and resistors.
There are three diodes approximations demonstrated below.
Approximation Equivalent circuit Characteristics curve
1st Approximation
(Ideal diode)
Acts like a perfect
Observation: Diode starts
switch with zero
conducting instantly without
resistance.
any voltage drop, when it is
forward biased.
 In forward bias, diode is like a closed switch, hence R = 0, in turn conducts heavily even if VD = 0
 In reverse bias, diode is like a open switch, hence R = ∞ Ω, in turn does not conduct ,therefore ID = 0
2nd Approximation
(Real or practical
diode)
Assume the diode
drop voltage, VK. Battery VK (0.7V for Si)
indicates voltage drop across
diode.
Observation: Diode starts conducting well after voltage drop VK, when it is
forward biased.
 In forward bias, diode starts conducting well after voltage drop VK offering R = 0
 In reverse bias, diode offers R = ∞ Ω, in turn does not conduct, therefore ID = 0
3rd Approximation
(Piece wise linear)
Assume the diode
drop voltage, VK
and bulk resistance R = dynamic resistance
f
RD. Observation: Curve is formed by two straight
= Ω lines. One, along x-axis, indicates diode does not
VD = VK + IDRf (linear equation) conduct up to VK . Two, slope = =
 In forward bias, diode starts conducting well after voltage drop VK offering low resistance, Rf
 In reverse bias, diode offers very high resistance, but R ≠ ∞ Ω.
Easwara M 7
Diode Relationship
The current and the voltage relationship of the PN-junction diode is exponential. It is described by
Shockley’s ideal diode equation, mathematically expressed as,
…………………………………….. (1)
Where,
ID and VD are the diode current and voltage, respectively
q = charge on the electron, 1.602 x 10-19 C
n = ideality factor or emission coefficient n = 1 for Si, n = 2 for Ge
K = Boltzmann’s constant, 1.38 x 10-23 J / K
T = temperature in Kelvin, KT/q is also known as the thermal voltage. At 300K (room
temperature), KT/q = 25.9 mV
Eqn (1) is applicable for unbiased, forward biased and reverse biased condition of the diode.
1. For Unbiased Diode:

Diode voltage VD = 0
2. Forward biased Diode:

Diode voltage VD = + VF
mA
3. Revesse biased Diode:

Diode voltage VD = - VR
µA
NOTE: 1) Eqn (1) is applicable for unbiased, forward biased and reverse biased condition of the diode
but not applicable for VD > VBreakdown
2) Ideal Forward curve passes through the origin.
3) Is increases as T increases; the rise is 7%/ºC for both Si and Ge and approximately doubles
for every 10ºC rise in temperature.
4) Barrier voltage (VB) is also dependent on temperature it decreases by 2mV/ºC for Ge and Si.
Example 3: A Germanium diode is used in a rectifier circuit and is operating at a temperature of 25oC
with a reverse saturation current of 100 µA. Calculate the value of forward current, if it is
forward biased by 0.22 V. Assume n = 1. VTU - Feb 2005
Solution: Given, IS = 100 µA, VF = 0.22 V, T = 25 + 273K = 298 oK, n = 1,
K = 1.38 x 10 -23 J/K, q = 1.602 x 10 -19 C
Easwara M 8
Diode current equation is given by,
Let, VT = KT/q = (1.38 x 10-23 x 298)/1.602 x 10-19

VT = 25mV,
Then above eqn, is written as,
ID = 0.6633A ID = 0.6633 A
Applications of Diodes
 Voltage regulators, Signal rectifiers and Clippers and clampers
Example-4 : Determine the output Vo of the circuit given in the
fig. Ex-4.
Solution: Given Si =0.7V, Vi =10V, R1 = R2 = 1KΩ.

Modifying the given circuit
Apply KVL to find current, I.
Vi = VD +I (R1 + R2)
10V = 0.7 + I (1K+1K) Fig.Ex-4
I = 9.3/ 2x103 = 4.65mA
Output Vo is determined as:
Current flowing through R2
Vo = I R2 = 4.65x10-3x1 x103
Vo = 4.65V
1.3 Zener Diode
Zener diode is a highly doped PN junction diode, designed to operate in Zener Breakdown Voltage (Vz)
in the reverse biased condition. In the forward bias direction, the zener diode behaves like an ordinary
diode. In the reverse bias direction, there is practically no reverse current flow until Vz is reached. When
Vz occurs there is a sharp increase in reverse current (Iz). Varying amount of reverse current (IR) can
pass through the zener diode without damaging it. The breakdown voltage or zener voltage (Vz) across
the diode remains relatively constant. The maximum IR is limited, by the wattage rating of the diode.
The depletion region formed in the zener diode is very thin (< 1 µm) and the electric field is very
high (about 500 kV/m) even for a small reverse bias voltage of about 5 V, allowing electrons to tunnel
from the valence band of the p-type material to the conduction band of the n-type material.
Circuit symbol and approximated model of zener diode is shown in fig. 1.6.
Fig.1.6 Circuit symbol, Ideal and Practical Approximated models of zener diode
Easwara M 9
PN Junction Breakdown
Electrical break down of any material (say metal, conductor, semiconductor or even insulator) can occur
due to two different phenomena.
1) Zener breakdown and
2) Avalanche breakdown
Differences between Zener breakdown and Avalanche breakdown
Zener breakdown Avalanche breakdown

1. The Zener breakdown occurs in heavy doping 1. The avalanche breakdown occurs in low
& thin junction diodes. doping diodes.
2. Depletion layer is narrow. 2. Depletion layer is large.
3. A strong electric field is produced. 3. Electric field is not so strong.
4. Vz occurs earlier than VBR. 4. VBR occurs later than Vz.
5. Electron-hole pairs acquire energy from the 5. Electron-hole pairs acquire energy from the
electric field generated by depletion region. applied potential.
6. Temperature coefficient is negative; therefore, 6. Temperature coefficient is positive; therefore,
Vz decreases as junction temperature increases. VBR increases as junction temperature increases
7. V I characteristics is very sharp 7. V I characteristics is not so sharp
V I characteristics of Zener diode
Typical V I characteristics of Zener diode is shown in fig. 1.7 (a).

Observations from the graph:
1. In the forward bias condition, the zener diode behaves like an ordinary diode.
(a) (b)
Fig.1.7 (a) VI characteristics of zener diode (b) Zener diode as voltage regulator
Easwara M 10
2. In the reverse bias condition, there is practically no reverse current flow until the breakdown
voltage (VZ) is reached. When VZ occurs there is a sharp increase in reverse current (IZ).
3. For voltages VR < VZ, zener diode acts as an open switch, except a negligible leakage current
called reverse saturation current (Io).
4. For voltages VR > VZ, zener diode acts as a constant voltage regulator between IZ(min) and IZ(max).
5. Since, the zener reverse characteristics is not exactly vertical, it possess resistance called zener resistance
RZ. It is given by RZ = Ω. RZ defines how VZ varies with respect to IZ.
1.4 Zener diode as voltage regulator

The circuit diagram of the zener diode as a simple voltage regulator is shown in fig. 1.8. The resistor, RS
is connected in the circuit to limit the current flow through the zener diode with the input voltage source,
Vin. The stabilized output voltage Vo ( = Vz) is taken from across the zener diode. The zener diode is
operating in the breakdown region when it is reverse biased by connecting with its cathode terminal to
the positive of the supply Vin.
 As long as Vin > VZ, the zener operates in the breakdown region and maintains constant voltage
across the load, irrespective changes in load current or input voltage.
Case 1) : Under No load condition

 Load current IL = 0
 IS passes through RS and the zener diode which in
turn dissipates its maximum power
 PD(max) = VZ Iz (max)
 Zener diode works as voltage regulator as long as
Iz < Iz (max).
Fig. 1.8
Case 2) : Under load condition
(a) Line regulation
 RS and RL are fixed
 Only input voltage Vin ( > desired Vo) is varied
 As current I varies, the voltage drop across RS and
Iz varies, but output voltage (Vo = Vz) would remain
constant as long as Vin is maintained above a
Vo = Vin – I RS
minimum value.
(b) Load regulation
 Vin (must be > desired Vo) and RS are fixed
 Only RL is varied
 As IL varies, Iz varies and IS is constant, but output
voltage (Vo = Vz) would remain constant as long as
RL is maintained above a minimum value.
 Maximum current is IZ(max)=PZ / VZ.

 Zener diodes are available from 2.4 to 200 volts as voltage regulators, with power ratings of 0.25,
0.4, 0.5, 1, 2, 3, and 5 watts.
Easwara M 11
Conditions for proper operation of Zener regulator
1. The zener must operate in the breakdown region or regulating region, i.e. between IZ(max) and
IZ(min).
2. The zener should not be allowed to exceed maximum dissipation power otherwise it will be
destroyed due to excessive heat.
Applications for Zener Diodes:

1. Voltage stabilizers or regulators (in shunt mode)
2. Surge suppressors for device protection
3. Peak clippers
4. Switching operations
5. Reference elements and in meter protection applications
Design: If the voltage across the Zener diode exceeds a certain value it would draw excessive current
from the supply. The series resistor RS value is designed so that when the input voltage is at VINmin and
the load current is at ILmax that the current through the Zener diode is at least IZmin . That means, to fix the
current through the Zener diode, Rs is introduced whose value is chosen from the following equation
Series Resistor value (ohms) = (Vi – Vz) / (Zener current + load current).
Then for all other combinations of input voltage, Vi and load current, IL, the Zener diode conducts the
excess current (Iz (max)) thus maintaining a constant output voltage Vo, across the load. The Zener diode
conducts the least current (Iz (min)) when the load current (IL) is the highest and it conducts the most
current when the load current is the lowest. The power dissipation of Zener diode is described as:
Total current I is calculated from the input loop, Vi = IRs +Vz or from KCL, I = Iz + IL
Example-5: In a zener regulator output is maintained at 5V, 20mA. Assume Iz (min) and Iz (max) are
5mA and 80mA, respectively. Design a zener regulator if input DC is 10V 20%. VTU Mar 1999
Solution: Given data

Vo = Vz = 5V
Io = IL = 20 mA
Vi = 10V ∓ 20%
Vi(min) = 10 – 2 (- 20%) = 8V
Vi(max) = 10 + 2 (-+20%) = 12V
∴ Vi = (8V to 12V)
(i) To find RL:
Easwara M 12
(ii) To find R(min) and R(max):

RL = 250 Ω
Rmin = 70 Ω
Rmax = 120 Ω
Example-6: A 24V, 600mW zener diode is used for providing a 24 V stabilized supply to a variable
load. If the input is 32V, calculate (i) the series resistance required (ii) diode current when the load
is 1.2KΩ.
Solution: Given data

Vo = Vz = 24V, Vi = 32V
Note that load is variable: IL
Total current I is determined by applying KVL to the input loop, Vi = IR +Vz

Iz(min) = 5 mA Iz (max) = 25 mA
Iz(min) =I – IL → Iz(min) =25 – 20 = 5 mA
Rs(min) = 320 Ω
Silicon Vs Germanium
Parameter Silicon (Si) Germanium (Ge)
1. IS at 25°C 0.01 µA to 1µA 2 to 15 µA.
2. variation of IS with
IS  doubles with each 8 to 10°C rise IS  doubles with each 12°C rise
temperature
3. working temperature operated up to 150°C operated up to 70°C
4. potential barrier, VB 0.7V 0.3V
5. PIV ratings (VBR) 50V to 1000V 100V to 400V
1.5 Rectification
Many electronic types of equipments need DC voltage. Therefore, AC is required to convert into DC.
The process of converting AC to DC (rippled) is called rectification. The following are the common
types of rectifier circuits.
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1. Half-wave rectifier – uses only one diode and ordinary power transformer.
2. Full-wave rectifier – there are two types:
 Center Tapped full wave rectifier - uses two diodes and center tapped power transformer.
 Bridge full wave rectifier - uses four diodes and ordinary power transformer.
1.5.1 Half-wave rectifier
Half wave rectification is carried out by a step-down transformer and a diode as shown in fig. 1.9(a).
During positive half cycle of the secondary voltage Vm:
 Diode is forward biased and offers low resistance RF, hence it acts like a closed switch.
 Therefore, it conducts for 0 ≤ t ≤ π. See fig. 1.9(b).
 Then, diode current ID flows through the load resistance RL. Therefore, output voltage Vo = ID RL.
During negative half cycle of the secondary voltage Vm:

 Diode is reverse biased and offers very high resistance Rr, acts like a open switch.
 Therefore, it does not conduct for π ≤ t ≤ 2π.
 Then, diode current ID = 0. Therefore, output voltage Vo = 0.
 The cycle repeats over time axis.
(a) (b)
b
Fig. 1.9 (a) Half wave rectifier circuit (b) input-output voltage wave forms
A half wave rectifier is rarely used in practice, because it conducts only for positive half cycle of the
input signal. It is never preferred as the power supply of an audio circuit due to its high ripple factor.
Advantage: Half wave rectifier is cheap, simple and easy to construct.

Disadvantage:
1. Ripple factor is high at the output.
2. Rectification efficiency is quite low, that means, power is delivered only during one half
cycle of the input alternating voltage.
3. Transformer utilization factor is low.
Example 7: A diode with VF = 0.7V is connected as a half wave rectifier, the load resistance is
600 Ω and AC input is 24V(r m s). Determine (i) output voltage, (ii) load current
and diode peak reverse voltage.
Solution: Given VF = 0.7V,
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RL = 600 Ω,
Vrms = 24V
To find Vm : Vm = x 24 = 33.94V
(i) Output voltage, Vdc = = =10.8 V
(ii) Load current, IL =
i.e., VL = Vm – VF, since, VF = 0.7V,

VL = 33.94 – 0.7 = 33.24V
Vdc = 10.8 V
IL = = = 0.0554A IL = 0.0554A
(iii) Diode peak reverse voltage = PIV = Vm = 33.94V PIV = 33.94V
1.5.2 Center tapped full-wave rectifier

Two diodes D1 and D2 are used in this circuit. They feed a common load resistor RL, with the help of a
center tapped transformer as shown in the fig. 1.10.
Fig.1. 10 Center tapped full wave rectifier circuit
During +ve half cycle of upper secondary voltage Vm / -ve half cycle of lower secondary voltage Vm :
 Diode D1 is forward biased; it offers low resistance RF1, acts like a closed switch.
 Hence, it conducts for 0 ≤ t ≤ π. Then, diode current ID1 flows through the load resistance RL.
Therefore, output voltage Vo = ID1 RL = IL RL
 While, Diode D2 is reverse biased, it offers very high resistance Rr, acts like a open switch.
 Hence, it does not conduct for 0 ≤ t ≤ π. Therefore, diode current ID2 = 0. But, Vo = ID1 RL= IL RL.
During -ve half cycle of upper secondary voltage Vm / +ve half cycle of lower secondary voltage Vm :
 Diode D2 is forward biased, it offers low resistance RF2, acts like a closed switch.
 Hence, it conducts for π ≤ t ≤ 2π. Thern, diode current ID2 flows through the load resistance RL.
Therefore, output voltage Vo = ID2 RL = IL RL
 While, Diode D1 is reverse biased, it offers very high resistance Rr, acts like a open switch.
 Hence, D1 does not conduct for π ≤ t ≤ 2π. Therefore, diode current ID1 = 0. But, Vo = ID2RL= IL RL.
The cycle repeats. The complete input-output waveform of the Center tapped full-wave rectifier is
shown in fig.1.11.
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Fig. 1.11 The complete input-output waveform of center tapped full wave rectifier
[ NOTE: Output voltage Vo = IDRL, flows in the same direction for both (+ ve) and (- ve) half cycles.]
Disadvantages
 Since, each diode uses only one-half of the transformers secondary voltage, the DC output is
comparatively small.
 It is difficult to construct and locate the center-tap on secondary winding of the transformer.
 The diodes used must have high PIV.
1.5.3 Bridge full-wave rectifier

Bridge full wave rectifier employs four diodes, but the center tapped transformer is not required. It is as
shown in fig. 1.12(a).
Fig.1. 12. (a) Bridge full wave rectifier circuit

(b) The complete input-output voltage
waveform of Bridge full wave rectifier
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During positive half cycle of the secondary voltage Vm:
 Diodes D1D2 are forward biased, they offer low resistance, and hence, they conduct for 0 ≤ t ≤ π.
Then, current I flows through the load resistance RL. Therefore, Vo = I RL.
 While, Diodes D3D4 are reverse biased, they offer very high resistance, and hence, they do not
conduct for 0 ≤ t ≤ π. Therefore, no current I flows through the load resistance RL. But, Vo = I RL
During negative half cycle of the secondary voltage Vm:
 Diodes D3D4 are forward biased, they offer low resistance, and hence, they conduct for π ≤ t ≤ 2π.
Then, current I flows through the load resistance RL. Therefore, Vo = I RL.
 While, Diodes D1D2 are reverse biased, they offer very high resistance, and hence, they do not
conduct for π ≤ t ≤ 2π.
The complete input-output voltage waveform of the Bridge full wave rectifier is shown in fig. 1.12(b).
Advantages:
1. Need for center-taped transformer is eliminated.
2. Output is twice when compared to center-tapped full wave rectifier for the same secondary voltage.
3. The PIV is one-half (1/2) compared to center-tapped full wave rectifier
Disadvantage:
It requires four diodes, the use of two extra diodes cause an additional voltage drop thereby reducing
the output voltage.
1.5.4 Performance measures of rectifiers

The following are the important performance measures of the rectifiers
1. Output current or DC current or Average current (Idc)/ DC output voltage (Vdc)
2. Root Mean Square (RMS) value of current and output voltage (Irms) / (Vrms)
3. Ripple Factor (γ)
4. Rectification Efficiency (ɳ)
5. Peak Inverse Voltage (PIV)
Performance measures of Half Wave rectifier
Fig. 1.13 Output voltage wave forms of half wave rectifier for one complete cycle
It is observed from the fig.1.13 that the output voltage waveform of a half wave rectifier for one
complete cycle (from 0 to 2π) is
for 0 ≤ ωt ≤ π ……………………………………… (2)
IL = 0 for π ≤ ωt ≤ 2π
That means, only one (+ve) half cycle is present between 0 ≤ ωt ≤ π and the signal is absent between π ≤
ωt ≤ 2π. This cycle repeats for the next cycle. Positive (+) half cycle at the output contains AC and DC
components. This variation is called ripple.
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1. Average current (Idc)/ DC Output Voltage (Vdc)

To obtain only DC value, the signal is to be integrated over one complete cycle (0 ≤ ωt ≤ 2π).
Where  (= 2f = 2/T) is the angular frequency in radian/sec.
Sine wave as current or voltage signal is mathematically represented and DC current (or load current)
through the load resistance is evaluated by,
π
Idc = ……………………………… (3)
π
Idc =
Presence of signal Absence of signal
between between
π
Idc = = – = – = =
Using Ohm’s law
Im =
where, = Resistance of the load, Average current of HWR
Resistance of secondary windings of transformer and Idc =
= forward resistance of the diode.
Therefore, Vdc = Idc·
Vdc = ·
Vdc = · For precise measurements
2. RMS Value of Load Current (Irms) / Voltage (Vrms)

RMS voltage at the load resistance can be calculated as Irms . By definition, it is the
area of one full cycle which represents the square of the function, divide by the base.
Mathematically,
0 (signal is absent)
Irms=
=
RMS Value (current) of Half
=
wave rectifier Irms =
=
RMS Value (voltage) of Half
=
wave rectifier Vrms =
=
= = = Irms =
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Ripple factor is a measure of varying components at the output of the rectifier. The pulsating output of a
rectifier consists of DC and AC component (known as ripples) as denoted in the fig. 13. It is defined as
the ratio of RMS value of AC component to the DC component in the output.
γ=
We know that, = + or = or =
γ= = = = (where, Irms = and Idc = )
γ= 1= = 1.21 Ripple factor of Half wave

rectifier γ = 1.21
Rectifier efficiency is a measure that indicates amount of input power converted into the DC output
power supplied to the circuit. It is defined as the ratio of output dc power to the total amount of input
x 100 % = =
Maximum rectifier efficiency,
ɳ= That means, in the half wave rectifier only 40.6% AC power

gets converted into DC power in the load.

The maximum reverse voltage across the diode is called peak inverse voltage (PIV). Half wave rectifier
consists of one diode and in reverse bias the total peak voltage Vm will be dropped across this diode. So,
PIV of the half wave rectifier is Vm.
PIV = Vm
1.5.5 Performance measures of Full Wave rectifier

Full wave rectification reduces the ripple factor and increases the output DC voltage level. In this
process the phase of the second half of the input wave is reversed, hence a series of positive half waves
are present. The analysis is same for both the Center Tapped and the Bridge Full Wave Rectifiers.
Fig.1. 14 Output voltage wave forms of full wave rectifier
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It is observed from the fig.1.14 that the output voltage waveform of a full wave rectifier for one
complete cycle (from 0 to 2π) is
for 0 ≤ ωt ≤ π
for π ≤ ωt ≤ 2π ……………………………………… (4)
1. Average current (Idc)/ DC Output Voltage (Vdc)
From the equation (4), it is seen that Vo = twice the Vm over one full cycle (0 ≤ ωt ≤ 2π)
Therefore, Vdc = 2 x (double that of the half wave) Average current or output
voltage of Full wave
Similarly, Idc = where,
Rectifier Idc =
2. RMS Value of Load Current (Irms) / Voltage (Vrms)
Since, 0 ≤ ωt ≤ π and π ≤ ωt ≤ 2π durations in the fig. 14 have identical pulses; Irms becomes,
Irms =
Irms =
RMS value of of Full wave

Irms =
Rectifier Irms = and Vrms =

Ripple factor of Full
γ= = = = 1= = 0.48 wave Rectifier
γ = 0.48
ɳ= x 100 % = =
Maximum rectifier efficiency,

That means, in the full wave rectifier
ɳ= x 100% ɳ=
81.2 % AC power gets converted into DC
power in the load.

Type of FWR PIV Reason
The secondary voltage Vm and voltage across the load (= 2Vm) appears
Center Tapped 2Vm across the non-conducting diode.
Sum of secondary voltage and voltage across the load = 2Vm. Since, two
diodes conduct during each half cycle this voltage is sharing by two diodes.
Bridge
Vm i.e., PIV= 2 Vm/2 = Vm
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1.5.6 Rectifier with Filter

Filters are employed in rectifier circuits for smoothing the DC output voltage, so that the undesirable AC
components (the ripples), can be minimized. Capacitor C can be used as a filtering element which
converts the rippled output of the rectifier into a smooth DC output voltage.
1. Half wave Rectifier with Capacitor Filter

Half wave rectifier with capacitor filter is as depicted in the fig. 1.15.
i) When diode D conducts for (+) half cycle in the half wave rectifier, capacitor C charges quickly to
the maximum level through the forward resistances of the diodes RF. The charge time of the
capacitor C is from t1 to t2 = RF C.
ii) When the rectified voltage starts to decrease, diode does not conduct. Capacitor C discharges slowly
through the load RL, until the next (+) half cycle is met. That means, charge stored in the capacitor is
supplied to the load during fall in the voltage cycle.
Fig. 1.15 Half wave rectifier with capacitor filter and filtered output voltage wave form
 The discharge time of the capacitor C is from t2 to t3 = RL C. It is shown in the fig. 1.16.
 This repeats for the remaining cycles.
Fig. 1.16 Filtered output voltage wave form of Half Wave Rectifier
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1.6 PHOTODIODE
A photodiode is a PN junction semiconductor device that consumes light energy to generate electric
current. It is also sometimes referred as photo-detector, photo-sensor, or light detector. Photodiodes are
specially designed to operate in reverse bias condition.
PIN (p-type, intrinsic and n-type) structure is mostly used for constructing the photodiode instead of p-n
(p-type and n-type) junction structure because PIN structure provide fast response time, used in high-
speed applications.
A photodiode has two terminals: a cathode and an anode. The symbol of photodiode is shown in the
fig.1.17 (a), contains arrows striking the diode representing the light or photons. Fig.1.17 (b) depicts its
construction.
Working: When an external light energy is supplied to the photodiode, the valence electrons in the
depletion region gains energy. Due to which the electrons from valence band jump into the conduction
band and contribute to current. In this way, the photodiode converts light energy into electrical energy.
(a) (b)
Fig.1.17 Photodiode (a) Symbol (b) Construction
The materials used for photodiode and its electromagnetic wavelength range is given in the table – I.
Table I - Materials used for photodiode and its electromagnetic wavelength range
Sl no. Material used EM wavelength range

1 Silicon (190-1100) nm
2 Germanium (400-1700) nm
3 Indium gallium arsenide (800-2600) nm
4 Mercury, cadmium Telluride (400-14000) nm
Types of photodiodes
1. PN junction photodiode
2. PIN photodiode
3. Avalanche photodiode
Among all the three photodiodes, PN junction and PIN photodiodes are most widely used.
Advantages
 Low resistance
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 Better frequency response
 Linear
 Less Noisy
 It can be used as variable resistance device.
 It is highly sensitive to the light.
 The speed of operation is very high.
Disadvantages
 Small active area (Should not exceed the working temperature limit specified by the
manufactures)
 Rapid increase in dark current and it depends on temperature.
 Require amplification at low illumination level.
 Photodiode characteristics are temperature dependent
 Poor temperature stability.
Applications Example: High speed counting
1. Light detector
2. Demodulators
3. Encoders
4. Optical communication system
5. High speed counting and switching circuits
6. Computer punching cards and tapes
7. Light operated switches
8. Sound track films
9. Electronic control circuits
1.7 Light Emitting Diode (LED)
LED is a semiconductor light source, that emits light when an electric current is passed through it. They
operate on low voltage and power. LEDs are one of the most common electronic components and are
mostly used as indicators in circuits. They are also used for luminance and optoelectronic applications.
Working Principle:
When the device is forward-biased, electrons cross the pn junction from the n-type material and
recombine with holes in the p-type material. When recombination takes place, the recombining electrons
release energy in the form of photons.
Working:
When a suitable forward biasing voltage is applied to the leads of LED, electron-holes are recombining
within the device, releasing energy in the form of photons.
LED has two terminals: a Cathode and an Anode. The symbol of LED shown in the fig.1.18 (a),
contains arrows o the diode representing the light emitting. Fig.1.18 (b) depicts its simple construction.
The light emitted from LEDs varies from visible to infrared and ultraviolet regions and LED
materials are given as in the table-II.
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(a) (b)
Fig.1.18 Light Emitting Diode (a) Symbol (b) Construction
Table-II: EM wavelength range for different LED materials
Sl no. Material used EM wavelength range

1 Indium gallium nitride (InGaN) blue, green and ultraviolet
2 Aluminum gallium indium phosphide (AlGaInP): yellow, orange and red
3 Aluminum gallium arsenide (AlGaAs red and infrared
4 Gallium phosphide (GaP): yellow and green
Advantages
- Energy efficient source of light for short distances and small areas.
- The typical LED requires only 30-60 mW to operate
- Durable and shockproof unlike glass bulb lamp types
- Reducing stray light pollution on street lights
Disadvantages
- Semiconductors are sensitive to being damaged by heat, so large heat sinks must be employed to keep
powerful arrays cool. This increases the cost.
- Shock proof requires unlike glass bulb lamp types.
Applications
 Indication lights on devices
 As small and large lamps
 Traffic lights
 Large video screens
 Street lighting (although this is still not
widespread)
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1.8 Photo-Coupler
Photo-coupler, or optical isolator, is a component that transfers electrical signals between two isolated
circuits by using light. Opto-isolators prevent high voltages from affecting the system receiving the
signal.
Fig.1.19 Schematic diagram of photocoupler
Photo-coupler contains an LED and a photodiode in a single package is shown in fig.1.19. It has a LED
on the input side and a photo-detector diode on the output side. When the current is set up in the LED,
light energy impinges on the photo-detector, and this sets up a reverse current in the output circuit. The
light detector can be a photodiode or a phototransistor.
Applications:
1. Monitor high voltage
2. Output voltage sampling for regulation
3. Micro system control for power ON/OFF
4. Signal isolation. It provides complete isolation because its input side is not electrically connected
to the output side.
1.8 78XX and 7805 based Fixed IC voltage regulator

Different parts of a robot require different DC voltage levels. Motors usually run on high voltages, like
12V or 36V. Microcontrollers run on 3.3V or 5V. Electromagnets work on even greater voltages and
currents. That means, using 78xx ICs, would decrease weight and save a lot of space, in turn,
conveniently step down to a specific voltage output.
The 78XX ICs have 3 pins (input, ground and output) and these regulators are referred to positive
voltages as shown in the fig.1.20.
Ex: 7805 chip, XX = 05 (see fig.1.20). So, the chip maintains a constant 5V across the output
terminal. The capacitors in the circuit decrease the amount of voltage fluctuations. If there is an increase
in the voltage the capacitors store it. If there is a decrease, they release their energy to maintain a
constant voltage across the output. Note that the input voltage must be greater than the required
output voltage.
Illustration: Heat generated = (input voltage – 5V) x output current.
If we have a system with input 12 volts and output current required is 0.5 amperes. We have:
(12 – 5) x 0.5 = 7 × 0.5 = 3.5 W; that means, 3.5W energy is being wasted as heat, hence an appropriate
heat sink is required to disperse this heat. On the other hand, energy actually being used is:
(5 x 0.5Amp) = 2.5W. So, 1W energy, that is actually utilized but it is wasted.
Below table describes significant details of IC 7805.
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7805 IC Pin No Function Rating
1 Input voltage Input voltage range 7V- 35V
2 Ground (0V) Current rating Ic = 1A
3 Regulated output Output voltage range VMax = 5.2V ,VMin = 4.8V
Fig.1.20 7805 IC is a fixed positive voltage regulator provides a constant 5 volts output.
Solved Examples
Example 1: Calculate the reverse saturation current for Silicon diode which passes a current of 10 mA
at 27oC for a forward bias of 700mV. VTU - June/July 2012
Solution: Given, IF = 10 mA,
VD = 700 mV,
T = 27 + 273K = 300 oK,
n = 2 (Si),
K = 1.38 x 10 -23 J/K,
q = 1.602 x 10 -19 C
Diode current equation is given by,

…………………………………(1)
Let, VT = KT/q = (1.38 x 10-23 x 300)/1.602 x 10-19 ≈ 26mV,
Then eqn(1), is written as,
= 0.014247µA
IS = 14.24 ηA
Example 2: A half wave rectifier is driven by a sinusoidal voltage v = 200 sin 250t volts.
Treating the diode as ideal and load resistance is 2 K Ω. Find (i) output voltage,
(ii) output current (iii) rms current (iv) ripple factor (vi) efficiency.
Solution: Given v = 200 sin 250t is compared with general sinusoidal voltage v = Vm sin ωt
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Vm = V ω = 250 rad/sec RL = 2 K Ω,
To find Im : Im = = = 0.1A
(i) Output voltage, Vdc = = = 63.66 V
(ii) Output current, Idc or IL = = = = 0.0318 A
(iii) RMS current Irms = = = = 0.05A
(iv) Ripple factor γ = = = 1.21
(v) Efficiency η = x 100% = 40.44%
Exercise
1. What is a PN junction Diode?
2. Explain the formation of depletion layer in PN junction Diode.
3. Discuss the behavior of PN junction Diode under:
(i) No bias (ii) Forward Bias and (iii) Reverse Bias conditions.
4. Draw and explain V-I characteristics of Silicon and Germanium diodes.
5. Define the following PN junction Diode parameters:
(i) Forward Voltage (VF) (ii) Forward Current (IF) (iii) Reverse Current (IR)
(iv) Reverse Break down Voltage (VBR) or Peak Inverse Voltage (PIV)
(v) Power Dissipation (PD) (vi) Dynamic Resistance (rD) (vii) Knee voltage (VK)
6. With appropriate diagrams discuss diode approximations.
7. What is a rectifier? Briefly discuss the common types of rectifier circuits.
8. With neat circuit diagram and waveforms explain half wave rectifier; center tapped full wave
rectifier and full wave bridge rectifiers.
9. Show that γ = 1.21, ɳ = 40.6% of a half wave rectifier. And
11. Show that γ = 0.48, ɳ = 81% of a full wave rectifier.
12. Deduce the following:
(i) Iav or IDC (ii) Irms / Vrms for half wave rectifier and full wave rectifier.
13. Discuss the need of filter circuit. Explain the operation of C – filter for half wave rectifier.
14. With neat circuit diagram and waveforms explain the operation of C – filter for full wave rectifier.
15. Explain how zener diode works as a voltage regulator.
16. Write a note on: (i) Photodiode (ii) LED (iii) Photocoupler
17. With neat circuit explain 7805 based fixed IC voltage regulator.
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Tutorial Questions
1. Determine the output Vo for the circuit given in the fig.1.
2. A zener diode has a breakdown voltage of 10V. It is supplied from voltage source varying between
20V – 40V in series with resistance of 820Ω using an ideal zener diode model obtain minimum and
maximum zener currents.
3. Design a zener diode voltage regulator to meet the following specifications: DC Vin =18V, Vo=10V,
load current=20mA, and are 10mA and 100mA, respectively.
4. A full wave rectifier is driving a load resistance of 500Ω. It is driven by a source voltage of 240V,
50Hz. Neglecting the diode resistances, determine (i) average DC voltage, (ii) average DC and (iii)
frequency of output waveform.
Multiple Choice Questions
1. In a PN junction with no external voltage, the electric field between acceptor and donor ions is called
A. Peak C. Threshold
B. Barrier D. Path
2. In a P-N junction the potential barrier is due to the charges on either side of the junction, these
charges are
A. Majority carriers C. Both (a) and (b)
B. Minority carriers D. Fixed donor and acceptor ions
3. In an unbiased PN junction
A. The junction current at equilibrium is zero as equal but opposite carriers are crossing the junction
B. The junction current is due to minority carriers only
C. The junction current reduces with rise in temperature
D. The junction current at equilibrium is zero as charges do not cross the junction
4. A forward potential of 10V is applied to a Si diode. A resistance of 1 KΩ is also in series with the
diode.
A. 10 mA C. 0.7 mA
B. 9.3 mA D. 0
5. For a P-N junction diode, the current in reverse bias may be

A. Few milliamperes C. Few micro or nano amperes
B. Between 0.2 A and 15 A D. Few amperes
6. When P-N junction is in forward bias, by increasing the battery voltage

A. Circuit resistance increases C. Current through P-N junction decreases
B. Current through P-N junction increases D. None of the above happens
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7. In a PN junction when the applied voltage overcomes the ........ potential, the diode current is large,
which is known as .............
A. Barrier, forward bias C. Resistance, reverse bias
B. Reverse, reverse bias D. Depletion, negative bias
8. As a PN junction is forward biased

A. The depletion region decreases C. The barrier tends to breakdown
B. Holes as well as electrons tend to drift away D. None of the above
from the junction
9. The main reason why electrons can tunnel through a PN junction is that
A. Barrier potential is very low C. Impurity level is low
B. They have high energy D. Depletion layer is extremely thin
10. A reverse-biased PN junctions has

A. A net electron current C. negligible current
B. A net hole current D. A very narrow depletion layer
11. The depletion layer of a PN junction diode has

A. Only free mobile holes C. Both free mobile holes as well as electrons
B. Neither free mobile electrons nor holes D. Only free mobile electrons
12. Barrier potential in a PN junction is caused by

A. Flow of drift current C. Migration of minority carriers across the
B. Diffusion of majority carriers across the junction
junction D. Thermally-generated electrons and holes
13. The diode is used in

A. Digital circuits C. Rectifiers
B. Detectors D. All of the above
14. The static VI characteristics of a junction diode can be described by the equation called
A. Child's three half-power law C. Einstein's photoelectric equation
B. Boltzmann diode equation D. Richardson-Dushman equation
15. The reverse saturation current in junction diode is independent of

A. Potential barrier C. Doping of 'P' and 'N' type region
B. Junction area D. Temperature
16. Depletion region behaves as

A. An insulator C. Conductor
B. Semiconductor D. High resistance
17. A crystal diode has forward resistance of the order of ……………

A. kΩ C. Ω
B. MΩ D. none of the above
18. The forward voltage drop across a silicon diode is about …………………
Easwara M 29
A. 0.5 V C. 1.0 V
B. 0.3 V D. 0.7 V
19. If the doping level of a crystal diode is increased, the breakdown voltage………….
A. remains the same C. is increased
B. is decreased D. none of the above
20. The current in a Zener diode is controlled by

A. Zener diode resistance C. Reverse bias voltage
B. Potential barrier D. External circuits
21. In a zener diode
A. Negative resistance characteristic exists C. Sharp breakdown occurs at low reverse voltage
B. Forward voltage rating is high D. All of the above
22. In the breakdown region, a zener diode behaves like a …………… source.
A. constant voltage C. constant resistance
B. constant current D. none of the above
23. If the a.c. input to a half-wave rectifier is an r.m.s value of 400/√2 volts, then diode PIV rating is
A. 400/√2 V C. 400 x √2 V
B. 400 V D. none of the above
24. The ripple factor of a half-wave rectifier is …………………

A. 2 C. 2.5
B. 1.21 D. 0.48
25. If the PIV rating of a diode is exceeded , ………………

A. the diode is destroyed poorly C. the diode behaves like a zener diode
B. the diode conducts D. none of the above
26. The maximum efficiency of a full-wave rectifier is ………………..

A. 40.6 % C. 82.1 %
B. 46.4% D. 81.2 %
27. The most widely used rectifier is ……………….

A. half-wave rectifier C. bridge full-wave rectifier
B. centre-tap full-wave rectifier D. none of the above
28. Forward voltage drop of an LED is greater than

A. 0.5 V C. 2.4 V
B. 1.2 V D. 5 V
29. In photodiode, when there is no incident light, the reverse current is almost negligible and is called
A. Zener current C. photo current
B. PIN current D. dark current
30. What is the possible range of current limiting resistor essential for lightening the LED in certain
applications after switched it ON?
A. 25- 55 Ω C. 110-220 Ω
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B. 55-110 Ω D. 220- 330 Ω
31. Which among the following are regarded as three-pin voltage regulator ICs?
A. Fixed voltage regulators C. Both A and B
B. Adjustable voltage regulators D. None of the above
32. The 7812 regulator IC provides
A. 5 V C. 12 V
B. –5 V D. –12 V
33. To get a maximum output current, IC regulation is provided with

A. Radiation source C. Peak detector
B. Heat sink D. None of the mentioned
34. The change in output voltage for the corresponding change in load current in a 7805 IC regulator is
defined as
A. All of the mentioned C. Load regulation

B. Line regulation D. Input regulation
35. Color of light emitted by LED depends on
A. its forward bias C. forward current

B. its reverse bias D. semiconductor material
Answers for Multiple choice Questions
1. B, 2. D, 3. A, 4. B, 5. C, 6. B, 7. A, 8. A, 9. D, 10. C, 11. B, 12. B, 13. D, 14. B, 15. B, 16. A, 17. C,

18. D, 19.B, 20.D, 21.C, 22. A, 23.B, 24. B, 25. A, 26.C, 27.C, 28.B, 29.D, 30.D, 31.A, 32.C, 33.B, 34.C, 35.D
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Module – 2 FET and SCR
2.1 Introduction
2.2 JFET: Construction and operation
2.3 JFET Drain Characteristics and Parameters
2.4 JFET Transfer Characteristic, Square law
expression for ID, Input resistance RDS
2.5 MOSFET: Depletion and Enhancement type
2.6 MOSFET- Construction, Operation
2.7 Characteristics and Symbols
2.8 CMOS
2.9 Silicon Controlled Rectifier (SCR) – Two-
transistor model
2.10 Switching action
2.11 Characteristics
2.12 Phase control application
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2.1 Introduction
A transistor is a semiconductor device that controls current with the application of a small electrical
signal. Transistors may be roughly grouped into two major families: bipolar and field-effect. BJT utilize
a small current to control a large current. But, FET utilizing a small voltage to control current.
FETs are unipolar rather than bipolar devices. That is, the main current through them is comprised
either of electrons through an N-type semiconductor (N-channel FET) or holes through a P-type
semiconductor (P-channel FET). In a JFET, the controlled current passes from Source to Drain, or from
Drain to Source as the case may be. The controlling voltage is applied between the Gate and Source.
Current flowing through this channel widely depends on the input voltage applied to its Gate terminal.
FET can be made much smaller than an equivalent BJT transistor and along with their low power
consumption and power dissipation makes them ideal for use in integrated circuits such as the CMOS
range of digital logic chips.
The FET has one major advantage over BJT, in that their input impedance, ( Rin ) is very high, (kilo
Ohms), while the BJT is comparatively low. This very high input impedance makes them very sensitive
to input voltage signals, but the price of this high sensitivity also means that they can be easily damaged
by static electricity.
FETs generally of two types :
1) JFET (Junction Field Effect Transistors) and
2) MOSFET (Metal Oxide Semiconductor Field Effect Transistors).
On a MOSFET, the metallic or poly silicon Gate is isolated from the channel by a thin layer of silicon
dioxide (SiO2). Some fundamental performance differences are there between MOSFETs and JFETS.
JFETs, by nature, operate only in the depletion mode. That is, a reverse gate bias depletes, or pinches off
the flow of channel current. A MOSFET, by virtue of its electrically-insulated gate, can be fabricated to
perform as either a depletion mode or enhancement-mode FET.
2.2 Junction Field Effect Transistor (JFET)

JFET is a voltage controlled three terminal uni-polar semiconductor device. The three terminals namely,
Source (S), Gate (G) and Drain (D). As the voltage applied to the Gate with respect to the Source (VGS),
controls the current flowing between the Drain and the Source terminals. See fig.2.1.
JFETs can be classified into two types (i) n-channel JFET and (ii) p-channel JFET, depending on
whether the current flow is due to electrons or holes, respectively.
Components of FET
1. Channel: This is the area in which majority charge carriers flow. When the majority charge
carriers are entered in FET, then with the help of this channel only they flow from source to
drain.
2. Source: Source is the terminal through which the majority charge carriers are introduced in the
FET.
3. Drain: Drain is the collecting terminal in which the majority charge carriers enter and thus
contribute in the conduction procedure.
4. Gate: Gate terminal is formed by diffusion of a type of semiconductor with another type of
semiconductor. It basically creates high impurity region which controls the flow of carrier from
source to drain.
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(a) (b)
Fig. 2.1Constructional details of (a) N-channel JFET (b) P-channel JFET
Working of n-channel JFET
Case I: No voltage is applied to the device (VDS = 0 and VGS = 0).

At this state, the device will be idle and no current flows through it (IDS = 0).
Case-II: When VDS is applied and VGS = 0
As shown in fig.2.2 (a), the two PN junctions at the sides
of the N channel establish depletion layers. The electrons
will flow from Source to Drain through a channel between
the depletion layers.
The size of the depletion layers determines the width of the
channel and hence current IDS, conduction through the bar.
Case-III: When VDS is applied and VGS = - ve

The depletion region width increases, which results in
reduces the width of conducting channel, thereby
Fig.2.2(a)
increasing the resistance of n-type bar. Consequently, the
current from Source to Drain is decreased.
If more (-VGS ) is applied, further reduces the channel
width until no current flows through the channel. At this
condition the JFET is said to be “pinched-off”. The applied
voltage at which the JFET channel is called as pinched-off
voltage, VP. At this state, the IDS current is restricted
only by the channel-resistance. However, once the pinch-
off occurs (VDS = VP), the current IDS saturates at a
particular level IDSS.
Fig.2.2(b)
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(a)
(b)
Fig. 2.3. circuit diagram of (a) N-channel JFET (b) water analogy for understanding the FET working principle
2.3 Output characteristic (Drain) V-I curves of JFET
The characteristics curves of a JFET shown in the fig.2.4, reveals four different regions of operation are
given as:
 Ohmic Region – When VGS = 0 the depletion region of the channel is very small and the JFET acts
like a voltage controlled resistor.
 Cut-off Region – This is also known as the pinch-off region were the Gate voltage, VGS is sufficient
to cause the JFET to act as an open circuit as the channel resistance is at maximum.
 Saturation or Active Region – The JFET becomes a good conductor and is controlled by the Gate-
Source voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no effect.
 Breakdown Region – The voltage between the Drain and the Source, ( VDS ) is high enough to causes
the JFET’s resistive channel to break down and pass uncontrolled maximum current.
The characteristics curves for a P-channel junction field effect transistor are the same as those above,
except that the Drain current ID decreases with an increasing positive Gate-Source voltage, VGS.
(b) The drain characteristic curve for VGS = 0 showing

Fig.2.4 (a) JFET with VGS = 0 V and a variable VDS (VDD) pinch-off voltage.
The Drain current IDS is zero when VGS = VP. For normal operation, VGS is biased to be somewhere
between VP and 0. Then we can calculate the Drain current, ID for any given bias point in the saturation
or active region as follows:
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1. Drain current in the active region
Drain current (ID) at the active region can be calculated as follows: ID lies between (pinch-off) zero to
IDSS.
2. Drain-Source channel resistance (RDS)
Similarly, if we know drain source voltage Vds and drain current Id, we can calculate the drain-source
channel resistance.
Where: gm is the “trans-conductance gain” since the JFET is a voltage controlled device and which
represents the rate of change of the ID with respect to the change in VGS.
3. Amplification factor (µ)
It is given by
Relation among JFET parameters

It can be proved from above that µ = RDS * gm
Inference:
1. As the gate to source voltage (VGS) is increased above zero, pinch off voltage is increased at a
smaller value of drain current as compared to that when VGS = 0V.
2. The value of drain to source voltage (VDS) is decreased as compared to that when VGS = 0V.
Salient Features of JFET
1. A JFET is a three-terminal voltage-controlled semiconductor device.

2. JFET is always operated with gate-source PN junction reverse biased.
3. In a JFET, the gate current is zero i.e. IG = 0.
4. Since there is no gate current, ID = IS.
5. JFET must be operated between VGS and VGS (off) . For this range of Gate-to-Source voltages, ID
will vary from a maximum of IDSS to a minimum of almost zero.
6. Because the two gates are at the same potential, both depletion layers widen or narrow down by an
equal amount.
7. JFET is not subjected to thermal runaway when the temperature of the device increases.
8. The drain current ID is controlled by changing the channel width.
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2.4 Transfer characteristics
Fig.2.5 Characteristics of JFET
The transfer characteristics can be determined by observing different values of ID with variation in VGS
provided that the VDS should be constant as shown in the fig.2.5.
Notice that the bottom end of the transfer characteristic curve is at a point on the VGS axis equal to
VGS(off), and the top end of the curve is at a point on the ID axis equal to IDSS.
This curve shows that
i) ID = 0; when VGS = VGS(off)
ii) ID = IDSS when VGS = 0
iii) The transfer characteristic curve is expressed approximately as
Hence, JFETs are often referred to as square-law devices.
Applications of JFET
 constant current source, buffer amplifier, electronic switch, phase shift oscillator,
voltage variable resistor (VVR) and chopper.
Comparision between BJT and JFET

BJT JFET
Bipolar device Uni junction transistor
Input impedance is very less Input impedance is very large
Current control device, preferred for low Voltage controlled device, preferred for low
current applications voltage applications
More noisy Less noisy
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Frequency variations effect its performance High frequency response
Temperature dependent device Better heat stability
Cheaper than FET Costly than BJT
Bigger in size than FET Smaller in size than BJT
More gain Less gain
High output impedance because of high gain Low output impedance because of less gain
High voltage gain Low voltage gain
Low current gain High current gain
Switching time is medium Switching time is fast
Consumes more power Consumes less power
2.5 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
The MOSFET, different from the JFET, has no pn junction structure; instead, the gate of the MOSFET
is insulated from the channel by a silicon dioxide (SiO2) layer shown in the fig.2.6. The MOSFET is
widely used for switching and amplifying electronic signals. Also, it is a core of ICs and it can be
designed and fabricated in a single chip because of smaller silicon chip area.
The two basic types of MOSFETs
1. Enhancement MOSFET (E-MOSFET) and
2. Depletion MOSFET (D-MOSFET). Of the two types, the enhancement MOSFET is more widely
used.
Fig.2.6 MOSFET circuit symbols
2.5.1 Depletion Mode

The depletion mode MOSFETs are generally ON at (VGS = 0V). The conductivity of the channel in
depletion MOSFETs is less compared to the enhancement type of MOSFETs. See fig. 2.7.
Case I: When there is no Gate voltage (VGS = 0), as in fig. 2.7, maximum current flows (ID = IS = IDSS).
Case II: When VGS = -ve with respect to the substrate, the Gate repels some of the electrons out of the
N-channel. This creates a depletion region in the channel, as illustrated in fig.2.8, and, therefore,
increases the channel resistance and reduces the Drain current, ID. The more negative the gate, the less
the Drain current. In this mode of operation the device is referred to as a depletion-mode MOSFET. Here
too much negative Gate voltage can pinch-off the channel.
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Fig.2.7 MOSFET in depletion mode with gate voltage zero

Case II: When VGS = -ve with respect to the substrate, the Gate repels some of the electrons out of the
N-channel. This creates a depletion region in the channel, as illustrated in fig.2.8, and, therefore,
increases the channel resistance and reduces the Drain current, ID. The more negative the gate, the less
the Drain current. In this mode of operation the device is referred to as a depletion-mode MOSFET. Here
too much negative Gate voltage can pinch-off the channel. Then device is said to be OFF.
Fig.2.8 MOSFET in depletion mode with gate voltage negative
Case III: When VGS = +ve, Gate attracts the negative charge carriers from the P-substrate to the N-
channel and thus reduces the channel resistance and increases the drain current, ID. The more positive
the Gate is made, the more Drain current flows. In this mode of operation the device is referred to as a
enhancement-mode MOSFET. This is depicted in the fig. 2.9.
Fig.2.9 MOSFET in depletion mode with gate voltage positive
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Transfer and Drain characteristic of depletion MOSFET is shown in the fig.2.10.
Transfer characteristic
Drain characteristic
Fig. 2.10 Transfer characteristic and Drain characteristic of depletion MOSFET
2.5.2 Enhancement mode
The construction of an enhancement-type MOSFET is quite similar to that of the depletion-type

MOSFET, except for the absence of an N-channel between the drain and source terminals.
The minimum value of VGS is required to form the induced N-channel, that turns the E-MOSFET ON is
called threshold voltage [VGS (th)]. For VGS below VGS (th), the drain current ID = 0.
(i) When VGS = 0 V, VDS = +ve : There is no channel induced between Source and Drain. The p-
substrate has only a few thermally produced free electrons (minority carriers) so that drain current is
almost zero. For this reason, E-MOSFET is normally OFF when VGS = 0V.
(ii) When VGS = VGS(th) = + ve, and VDS = + ve: The free electrons developed next to the SiO2 layer and
induced an N channel, as shown in the fig.2.11. Now a Drain current ID starts flowing. E-MOSFET is
turned ON. Beyond VGS (th), if the value of VGS is increased, the induced N channel becomes wider,
resulting large ID. If the value of VGS decreases not less than VGS (th), the channel becomes narrower and
ID will decrease.
Fig. 2.11 MOSFET in enhancement mode with gate voltage positive
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Since the conductivity of the channel is enhanced by the positive bias on the Gate, so this device is also
called the enhancement MOSFET or E- MOSFET.
2.6 Characteristics of E-MOSFET

Drain characteristic curves: (shown in the fig.2.12 (b)), have almost vertical and almost horizontal
parts. The vertical components of the curves correspond to the ohmic region, and the horizontal
components correspond to the saturation region (constant current). Note the following worthy points:
 ID depends on different values of VGS (from 0V to + VGS (max)).
 When VGS = 0, even for large increase in VDS, ID = 0. This is said to be cut-off region. (MOSFET off
state).
Fig. 2.12 (a) E – MOSFET circuit (b) Drain characteristic of E - MOSFET
Transfer Characteristic Curves

i) When VGS < VGS(th), then ID =0. This is because under this state, the channel will not be connecting
between the drain and the source terminals. This is called as cut-off region. (MOSFET off state). The
tranfer curves of MOSFET is shown in the fig.2.13.
ii) When VGS > VGS(th),. then ID flows through the device, initially (Ohmic region) and then saturates to
a value (saturation region). That means, ID is controlled by the Gate voltage, VGS.
iii) ID can be obtained by analytical expression:
ID = k (VGS – VGS(th))2
where A/V2
Fig.2.13 Transfer characteristic of E - MOSFET
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2.8 CMOS Circuits
The CMOS circuit consists of a combination of P-type (PMOS) and N-type (NMOS) complementary
MOSFETs. In NMOS, the majority carriers are electrons. When a high voltage is applied to the gate, the
NMOS will conduct. Similarly, when a low voltage is applied to the gate, NMOS will not conduct.
In PMOS the majority carriers are holes. When a high voltage is applied to the gate, the PMOS will not
conduct. When a low voltage is applied to the gate, the PMOS will conduct.
Fig.2.14(a) and (b) illustrate the basic operation of CMOS inverter and it can be studied by using simple
switch models.
NMOS source (S) is grounded. PMOS source (S) is connected to VDD (= +5V)
PMOS and NMOS gates (G) are shorted and taken as input (VIN).
PMOS and NMOS drain (D) are shorted and taken as output (Vout).
i) When Vin = VDD = 5V (Logic - 1):

NMOS transistor is ON, while the PMOS is OFF.
A direct path exists between Vout and the ground
node, resulting in Vout = 0 V.
This yields the equivalent circuit shown below.
9
Fig.2.14(a) Circuit for input logic 1
ii) When Vin = 0V, (Logic - 0) VDD = 5V:
PMOS transistor is ON, while the NMOS is OFF.

A direct path exists between VDD and the Vout,
resulting in Vout = 5 V.
This yields the equivalent circuit shown below.
Fig.2.14 (b) Circuit for input logic 0
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CMOS Functional Table
Vin PMOS NMOS Vout
VDD = 5V (logic 1) OFF NO 0V (logic 0)
0V (logic 0) ON OFF VDD = 5V (logic 1)
CMOS Advantages CMOS Applications

High switching speed (50ns), Computer memories, CPUs
Low power dissipation (2.5nW), Microprocessor designs
Occupies lower packing density in IC fabrication, Flash memory chip designing
To design application specific integrated circuits
(ASICs). Ex: ALU circuits, Microcontrollers, etc.
2.9 Silicon Controlled Rectifier (SCR)
An SCR is a 4-layer PNPN with three terminals: Anode, Cathode, and Gate. The upper PNP layers act
as a transistor T1, and the lower NPN layers act as a transistor T2.
The schematic symbol and basic structure of an SCR is shown in Fig.2.15.
CASE-1: Gate current is zero or the Gate terminal is open
i) When the Anode voltage is positive with respect to the Cathode, junctions J1 and J3 are forward biased
and J2 is reverse biased. The device offers high resistance. Hence, only a small leakage current (ICO)
flows from Anode to Cathode. Then the Anode current is IA = ICO. SCR is said to be in OFF state.
ii) If Anode to Cathode voltage VAK is increased to a sufficiently large value, the reverse biased junction
J2 will break. This is known as avalanche breakdown and corresponding voltage is called as forward
break over voltage VBO. Since J1 and J3 are already in forward biased, resulting in large forward current.
The device is in ON state. In this state IA is limited by an external resistance R.
iii) When Cathode voltage is larger than Anode voltage J1 and J3 are reverse biased and J2 will be forward
biased. So, SCR will be in OFF state and only leakage current flows.
(a) (b) (c) (d)
Fig. 2.15 SCR (a) Symbol (b) Basic Layout (c) Cross-sectional view and (d) Two transistor Model
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CASE-2: Transistor Logic: When positive current pulse is applied to the Gate: Switching Action
The two transistor equivalent circuit shows (see fig. 2.15 (d)) that the collector current IC1 of the NPN
transistor Q1 feeds directly into the base IB2 of the PNP transistor Q2, while the collector current IC2 of
Q2 feeds into the base IB1of Q1. In this case both transistors Q1 and Q2 turn ON (the Anode must be more
positive than the Cathode).
When a sufficient positive pulse is applied to the Gate, at first, IB1 turns on Q1, providing a conduction
path for Q2 via IB2, thus turning on Q2. The collector current IC2 of Q2 provides an additional base current
for Q1 so that Q1 stays in conduction even after the Gate pulse is removed. This regenerative action
continues until both, Q1 and Q2 drive into saturation – acts like closed switch between Anode and
Cathode. In this case, IA is limited by an external resistance R.
Turning OFF SCR (commutation)

The turn OFF process of an SCR is called commutation. The term commutation means the transfer of
currents from one path to another. So the commutation circuit does this job by reducing the forward
current to zero so as to turn OFF the SCR.
To turn OFF the conducting SCR the below conditions must be satisfied.
 The anode or forward current of SCR must be reduced to zero or below the level of holding current,
 A sufficient reverse voltage must be applied across the SCR to regain its forward blocking state.
Types of Commutation:
1) Natural commutation and 2) Forced commutation
1. Natural Commutation
In AC circuit, the current always passes through zero for
every half cycle. (Analyze one AC cycle).
If the SCR is connected to an AC supply Vs, as shown in the
fig. SCR turns off when negative voltage appears across it.
This process is called as natural commutation, since no
external circuit is required for this purpose.
2. Forced Commutation
In case of DC circuits, there is no natural current zero to turn OFF the SCR. In such circuits, forward
current or Anode current must be forced to zero to turn OFF the SCR, with an external circuit. Hence,
named as forced commutation.
This commutation circuit consist a transistor, Q and a DC supply

(V) connecting in series to the SCR as shown in the fig. When
SCR is ON, transistor is made OFF. To turn OFF the SCR, a + ve
pulse is applied to the Base of transistor to drive it into saturation.
Now, transistor acts like a closed switch. When IA < IH , SCR
turns OFF. Transistor is held ON just long enough to turn OFF the
SCR. Turn-off time of an SCR is typically 5 - 30µs.
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V-I Characteristics of SCR

The typical VI characteristic of SCR is as shown in the fig.2.16. The three basic modes of operation of
SCR are:
1. Forward Blocking mode, 2. Forward conduction mode and 3. Reverse Blocking mode
Fig. 2.16 VI Characteristics of SCR
1. Forward Blocking mode:

 When Anode is at a higher potential than Cathode, SCR is said to be forward biased,
 In this mode, a small current called forward leakage current flows from Anode to Cathode.
 From the graph, OM represents the forward blocking mode.
 SCR is treated as an open switch in the forward blocking mode.
2. Forward Conduction mode:

 When Anode to Cathode forward voltage is increased with Gate circuit open, reverse biased
junction J2 will breakdown at a voltage called forward break over voltage, VBO.
 After this breakdown, SCR gets turned ON with point 'M' at once shifting to N. Here, NK
represents the forward conduction mode.
Latching Current (IH): It is the minimum value of Anode current required to keep SCR in conducting
state even after removal of Gate pulse.
Holding Current (IL): It is defined as the minimum value of Anode current below which the SCR gets
turned off. IL > IH.
3. Reverse Blocking mode:
 When Cathode is made high potential with respect to Anode with Gate open, then the SCR is
said to be reverse biased.
 J1 and J3 are reverse biased and J2 is forward biased.
 A small current flow through the SCR, called as reverse leakage current.
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 If the reverse voltage increased, then at reverse breakdown voltage VBR, an avalanche breakdown
occurs at J1 and J3 and the reverse current increases rapidly (see in the graph points PQ).
 The SCR in the reverse blocking mode may therefore be treated as (OFF) an open switch.
2.10 Phase Control Application of SCR

SCR is turned ON by applying a short pulse to the Gate at any angle is called firing angle ( ). When
load power is controlled by varying firing angle is known as phase control. The fig.2.17 shows the single
phase half wave phase control circuit using SCR. A diode D in series with the variable resistor R is
connected to the gate which prevents reverse bias being applied to the Gate.
 During the negative half cycle of the AC input signal, SCR is reverse biased and does not conduct.
Hence, no current flows through the load RL.
 During the positive half cycle of the AC input, SCR is forward biased. But for IG = 0 (i.e, absence of
Gate signal), SCR remains OFF.
 IG is derived from AC supply and it is controlled by the variable resistance R. If the resistance R is
set to minimum value, triggering current is applied to the gate, then immediately at the beginning of
positive half cycle of input voltage the SCR is turned ON (see fig.2.17(a)). Hence the current starts
flowing to the load RL.
2.17 (a) Fig. Phase control circuit for R minimum
 If the resistance R is set to maximum value, the SCR will not turned ON until the peak value of
positive half cycle of the input voltage is reached. (see fig.2.17(b)).
2.17 (a) Fig. Phase control circuit for R minimum

 For this rectifier circuit, firing angle can be varied during the positive half cycle only.
Easwara M 46
 Therefore, by varying the firing angle or gate current (by changing the resistance R value), it is
possible to make the SCR conduct part or full positive half cycle so that the average power fed to
the load get varied.
 That means, increasing the resistance R, causing less power to be delivered to the load R L.
Decreasing the resistance R, causing more power to be delivered to the load RL.
Exercise
1. Draw the structure of JFET and discuss its working.

2. What is ‘pinch off’ voltage? How to get its value experimentally?
3. An n-JFET is operated with negative gate voltage and not with positive one. Give reasons.
4. Give the structure of depletion MOSFET (D - MOSFET). How is D - MOSFET different from
enhancement MOSFET (E - MOSFET)?
5. Draw and discuss drain characteristics for a D-MOSFET.
6. Discuss the formation of channel in E-MOSFET emphasizing the role of inversion layer.
7. How are D-MOSFET and E-MOSFET connected in a circuit to work as resistors?
8. Explain a CMOS inverter circuit.
SCR
9. Define Holding current and Latching current?
Ans. Holding current is the minimum value of anode current below which the device stops conducting
and return to its OFF state. The value is usually in millimeters.
Latching current is the minimum anode current that must flow through SCR to keep it in ON state after
the triggering pulse has been removed. Latching current is 2-3 times the holding current.
10. What is the Turn ON processes of SCR?
Ans.Following are the Turn ON processes of SCR:

a. Forward Voltage Triggering
b. Thermal Triggering or Temperature Triggering
c. dv/dt Triggering
d. Radiation or Light Triggering
e. Gate Triggering
11. What are the Gate control methods?
Ans. For gate control, a signal is applied between gate terminal and cathode terminal of the device.
There are three types of signals used for this purpose and they are as follows:
DC Signals
o A DC voltage of proper magnitude and polarity is applied between the gate and cathode terminal
in such a way that the gate becomes positive with respect to cathode
o When the applied voltage is sufficient to produce the required gate current, the device starts
conducting.
o The drawback of this scheme is that both power and control circuit is DC and there is no
isolation between them; also a continuous DC signal has to be applied to the gate causing more
gate power loss.
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AC Signals
o AC source is commonly used for the gate signal in all applications of Thyristor control. This
scheme provides proper isolation between the power and control circuit. The firing angle control
is obtained easily by changing the phase angle of the control system.
o However, the gate drive is maintained for one and a half cycle after the device is turned ON and
reverse voltage is applied between the gate and cathode terminal during the negative half cycle.
o The drawback is that a separate transformer is required to step down the AC supply which adds
to the cost.
Pulse Signals
o In this method, the gate drive consists of a single pulse appearing periodically or a sequence of
high-frequency pulses. This is also known as ‘carrier frequency gating’.
o A pulse transformer is used for isolation between main drive supply and gating signal. The main
advantage is that there is no need of applying continuous signals and hence the gate losses are
reduced.
12. What are the advantages of Gate Turn ON process?
Ans. Following are the advantages of Gate Turn ON process:

 Less Power consumption.
 It is possible to turn ON the SCR precisely at the desired value of anode to cathode voltage V AK.
 If the supply voltage is AC then it is possible to adjust the firing angle to the desired value.
 Triggering circuit is easy to design.
 Turn ON gain is very high.
 Pulse triggering circuit provides greater flexibility.
13. What are operating modes or operating regions of SCR? Explain with neat VI characteristics.
Solved Examples
2.1 The device parameters for an n-Channel JFET are: Maximum current IDSS = 10mA,
Pinch off voltage, Vp = - 4V. Calculate the drain current for (a) VGS = 0, (b) VGS = - 1.0V and
(c) VGS = - 4V
Solution: The expression for drain current ID, in the saturation region is,
(a) When VGS = 0, from Eq(1), I D= IDSS =10mA

(b) (b) When VGS = -1.0V, the drain current from Eq (1) is,
(c) When VGS = -4V = Vp, then from Eq(1),

ID=0
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2.2 A JFET produces gate current of 2nA when gate is reverse biased with 8V. Determine the
resistance between gate and source.
Solution: Since reverse gate-source voltage, VGS, of 8v produces gate current, IG of 2nA,
Therefore, gate-to-source resistance, RGS, is
2.3 The reverse gate voltage of JFET when changes from 4.4V to 4.2V, the drain current
changes from 2.2 mA to 2.6 mA. Find out the value of transconductance of the transistor.
Solution: The transconductance, gm is defined as
Where ΔID is change in drain current when change in gate-source voltage is ΔVGS.
In the given problem,
ΔID = (2.6 – 2.2) mA = 0.4 mA and,
ΔVGS = (4.4 – 4.2) V = 0.2 V
2.4 Find out the operating point current and voltage values (IDQ and VDSQ) for a self biased
JFET having the supply voltage VDD = 20V and maximum value of drain current as 12 mA.
Solution: We know that the value of drain current at Q-point may be taken as half of the maximum
current, that is
In the same way, the value of drain-source voltage at Q-point may be taken as half of
supply voltage VDD. That is,
Therefore, IDQ = 6 mA and VDSQ = 10V.

2.5 Calculate the value of source resistance RS required to self bias a n-JFET such that VGSQ
= - 3V. The n-JFET has maximum drain-source current IDSS = 12 mA, and pinch-off voltage,
Vp = - 6V.
Solution: Given, IDSS = 12 mA, VGS = -3V and Vp = -6V,

The drain current, ID, in a JFET, in the saturation region is,
RS = 333 Ω
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1. Junction Field Effect Transistors (JFET) contain how many diodes?

A. 4 C. 2
B. 3 D. 1
2. A MOSFET has how many terminals?
A. 2 or 3 C. 4
B. 3 D. 3 or 4
3. IDSS can be defined as:
A. the min. possible drain current C. the max. possible current with VGS held at 0 V
B. the max. possible current with VGS held

D. the max.drain current with the source shorted
at –4 V
4. When VGS = 0 V, a JFET is:
A. Saturated C. an open switch
B. an analog device D. cut off

5. When the JFET is no longer able to control the current, this point is called the:
A. breakdown region C. saturation point
B. depletion region D. pinch-off region
6. With a JFET, a ratio of output current change against an input voltage change is called:
A. Transconductance C. Resistivity
B. Siemens D. Gain
7. The trans-conductance curve of a JFET is a graph of:
A. IS versus VDS C. ID versus VGS
B. IC versus VCE D. ID × RDS

8. A JFET has three terminals, namely …………
A. cathode, anode, grid C. emitter, base, collector
B. source, gate, drain D. none of the above
9. A JFET is also called …………… transistor
A. unipolar C. unijunction
B. bipolar D. none of the above
10. A JFET is a ………… driven device
A. current C. both current and voltage
B. voltage D. none of the above
11. The gate of a JFET is ………… biased
A. reverse C. reverse as well as forward
B. forward D. none of the above
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12. The input impedance of a JFET is …………. that of an ordinary transistor
A. equal to C. more than
B. less than D. none of the above
13. When drain voltage equals the pinch-off-voltage, then drain current …………. with the increase in
drain voltage
A. decreases B. remains constant
C. increases D. none of the above
14. If the reverse bias on the gate of a JFET is increased, then width of the conducting channel
A. is decreased B. remains the same
C. is increased D. none of the above
15. A MOSFET has …………… terminals
A. two C. four
B. five D. three
16. A MOSFET can be operated with ……………..
A. negative gate voltage only C. positive as well as negative gate voltage
B. positive gate voltage only D. none of the above
17. A JFET has ……….. power gain
A. small C. very small
B. very high D. none of the above
18. The input control parameter of a JFET is ……………
A. gate voltage C. drain voltage
B. source voltage D. gate current
19. A common base configuration of a pnp transistor is analogous to ………… of a JFET
A. common source configuration C. common gate configuration
B. common drain configuration D. none of the above
20. A JFET has high input impedance because …………
A. it is made of semiconductor material C. of impurity atoms
B. input is reverse biased D. none of the above
21. In a JFET, when drain voltage is equal to pinch-off voltage, the depletion layers ………
A. almost touch each other C. have moderate gap
B. have large gap D. none of the above
22. In a JFET, IDSS is known as …………..
A. drain to source current C. drain to source current with gate open
B. drain to source current with gate shorted D. none of the above
23. The two important advantages of a JFET are …………..
A. high input impedance and square-law C. low input impedance and high output
property impedance
B. inexpensive and high output D. none of the above
impedance
24. Which of the following devices has the highest input impedance?
A. JFET C. Crystal diode
B. ordinary transistor D. MOSFET
25. A MOSFET uses the electric field of a ………. to control the channel current
A. capacitor C. generator
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B. battery D. none of the above
26. If the gate of a JFET is made less negative, the width of the conducting channel……….
A. remains the same C. is increased
B. is decreased D. none of the above
27. The input impedance of a MOSFET is of the order of ………..
A. Ω C. kΩ
B. a few hundred Ω D. several MΩ
28. An SCR has ………….. semi-conductor layers
A. Two C. Four
B. Three D. None of the above
29. An SCR has three terminals viz ……………
A. Cathode, anode, gate C. Anode, cathode, drain
B. Anode, cathode, grid D. None of the above
30. An SCR is sometimes called …………
A. Triac C. Unijunction transistor
B. Diac D. Thyristor
31. An SCR is made of ………….
A. Germanium C. Carbon
B. Silicon D. None of the above
32. In the normal operation of an SCR, anode is …………… w.r.t. cathode
A. At zero potential C. Positive
B. Negative D. None of the above
33. An SCR combines the features of …………..
A. A rectifier and resistance C. A rectifier and capacitor
B. A rectifier and transistor D. None of the above
34. The control element of an SCR is ………….
A. Cathode C. Anode supply
B. Anode D. Gate
35. The normal way to turn on a SCR is by ……………..
A. Breakover voltage C. Appropriate gate current
B. Appropriate anode current D. None of the above
36. An SCR is made of silicon and not germanium because silicon ………
A. Is inexpensive C. Has small leakage current
B. Is mechanically strong D. Is tetravalent
37. An SCR is turned off when …………..
A. Anode current is reduced to zero C. Gate is reverse biased
B. Gate voltage is reduced to zero D. None of the above
38. We can control a.c. power in a load by connecting …………
A. Two SCRs in series C. Two SCRs in parallel opposition
B. Two SCRs in parallel D. None of the above
39. When SCR starts conducting, then ……………. loses all control
A. Gate C. Anode
B. Cathode D. None of the above
40. CMOS inverter circuit has pair of transistors which are
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A. two PMOS C. two NMOS

B. two BJTs D. two complementary CMOS
Key Answers:
1.C, 2. D, 3. C, 4. A, 5. A, 6. A, 7. C, 8. B, 9. A, 10. B, 11. A, 12. C, 13. B, 14. A, 15. D, 16. C,
17.B, 18.A, 19.C, 20.B, 21.A, 22.B, 23.A, 24.D, 25.A, 26.C, 27.D, 28.C, 29. A, 30. D, 31. B, 32. C,
33.B, 34.D, 35.C, 36.C, 37.A, 38. C, 39.A, 40.D
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Module – 3 Operational Amplifiers and Applications
3.1 Introduction to Op-Amp

3.2 Op-Amp Parameters
3.3 Op-Amp Input Modes
3.4 Applications of Op-Amp:
3.4.1 Inverting amplifier
3.4.2 Non-Inverting amplifier
3.4.3 Summer
3.4.4 Voltage follower
3.4.5 Integrator
3.4.6 Differentiator
3.4.7 Comparator
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3.1 Introduction
 The integrated-circuit operational-amplifier is the fundamental building block for many electronic
circuits. An op-amp is a multi-stage, direct coupled, high gain negative feedback amplifier used to
amplify AC and DC input signals. It was initially used for basic mathematical operations such as
addition, subtraction, multiplication, differentiation and integration in analog computers.
 The main applications of op-amp:
Active filters, oscillators, peak detector, comparators, voltage regulators, precision rectifiers,
instrumentation and control systems, pulse generators, square wave generators etc.
 For the design of all these circuits the op-amp is manufactured with many numbers of integrated
transistors, diodes, one or two capacitors and resistors.
 By connecting external resistors, voltage gain and band width of an op-amp can be adjusted.
 The op-amp is an extremely compact; multi tasking, low cost, highly reliable and temperature stable
integrated circuit. In an ideal op-amp no current flows into either input offering infinite input
resistance. The output acts as a voltage source with a very low resistance.
 In a practical op-amp (µA 741) the input current is in the order of pico - amps (10 −12) amp, or less.
Pin Diagram of Op-amp
Pin 2: Inverting (- ve) terminal

Pin 3: Non-Inverting (+ve)
terminal
Pin 4: - ve power supply (- VEE)
Pin 5: +ve power supply (+VCC)
Pin 6: Output terminal (Vout)
Pins 1& 5: Offset null and
pin 8: not connected (NC)
Fig. 3.1 (a) Basic pin-out of Op-amp (b) circuit symbol (c) pin description
3.2 OPAMP Parameters
Ad A
1. Common-Mode Rejection Ratio: CMRR   20 log10 d (dB)
Ac Ac
It is the ability of amplifier to reject the common-mode signals (unwanted signals) while amplifying the
differential signal (desired signal).
It is defined as the ratio of differential gain to the common mode gain, measured in dB.
When both the inputs of the OPAMP has same voltages, then the output of it should be zero (Vo = V2 - V1=0;
i.e, V1 = V2) or the OPAMP should be rejecting the signal.
The function of the CMMR is used to reduce the noise on the transmission lines.
Ideal value : ∞ Practical Value: 90dB – 120dB
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2. Open-loop voltage gain, (Aol):
It is the internal voltage gain of the device and represents the ratio of output voltage to input voltage
when there are no external components.
Ideal value : ∞ Practical Value: 2 x 105
3. Input Offset Voltage:

Realistically, a small dc voltage will appear at the output when no input voltage is applied. Thus,
differential dc voltage is required between the inputs to force the output to zero volts.
Ideal value : 0 Practical Value: 2mV
4. Input Offset Current

It is the difference of input bias currents I1 and I2.
I os  I1  I 2 Vos  I1Rin  I 2 Rin  I1  I 2 Rin
Ideal value : 0 Practical Value: 20nA
5. Input Bias Current

Input bias current is the current required by the inputs of the opamp to properly operate the first stage. It
is defined as the average of both input currents I1 and I2.
Ideal value : 0 Practical Value: 80nA
6. Input Impedance: Ri :
It is the ratio of input voltage to input current and is assumed to be infinite to prevent any current
flowing from the source supply into the amplifiers inputs ( IIN = 0 ).
The ideal op-amp rules: 1. The differential input voltage is zero. Vd = V2 - V1 = 0
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2. No current flowing into the input terminals.
The larger the resistance of a device, the smaller the current that it demands. It determines the loading
effect on the previous stage.
Ideal value : ∞ Practical Value: 2MΩ
7. Output Impedance: RO
Op-amps are supposed to have zero output impedance, or very low means, the output voltage won't
change, just in case the output current changes.
The ideal op-amp acts as a perfect internal voltage source with no internal resistance. This internal
resistance is in series with the load, reducing the output voltage available to the load.
Ideal value : 0 Practical Value: 50 Ω - 100 Ω
8. Slew Rate: SR = dVo (max) /dt

Slew rate is defined as the rate of change of maximum output voltage with respect to time. The higher
the value (in V/µs) of slew rate, the faster the op-amp responds.
Slew rate describes how fast the output voltage responds to an immediate change in input voltage. It is
particularly important parameter in applications where the output is required to switch from one level to
another quickly.
The power bandwidth maximum frequency is related to the slew rate and the peak output voltage by
SR = 2 f Vp (max). Where Vp is the peak voltage of the output signal and f is its frequency in Hz.
Ideal value : ∞ Practical Value: 0.5 µV/sec
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3.3 Operation Modes of OPAMP
1. Single-ended input
 Only one input is applied with input signal while

the other is connected to ground.
 The input applied to the plus input results in an
output having the same polarity as input.
 The input applied to the minus input results in an
output being opposite in phase to the applied
signal.
2. Differential (Double-ended) input

 When signal is applied between both inputs, it is
referred to as double-ended input.
 The amplified output is in phase with the difference
between the two inputs.
 This is the reason that this mode is called
differential input.
3. Double-ended output
 The op-amp can also be operated with opposite
outputs.
 The figure shows a single-ended input with a
double-ended output.
 The signal applied to the plus input results in two
amplified output of opposite polarity.
4. Common-mode
 When the same input signals are applied to both
inputs, common-mode operation results.
 Ideally, the output is zero due to the two opposite
output components.
 This means that signals common to both inputs
will be suppressed, referred to as common-mode
rejection.
Ideal Op-Amp Properties

 Infinite input impedance (500k-2M)
 Zero output impedance (20-100 )
 Infinite open-loop gain (20k to 200k)
 Infinite bandwidth
 Zero noise contribution
 Zero DC output offset
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Concept of Virtual Ground
Fig. 3.2 (a) Illustration of virtual ground (b) Equivalent circuit of an Ideal op-amp
In an ideal Op-Amp (its equivalent circuit is shown in fig. 3.2(b)), when input voltages are equal output
will be zero. Suppose, non-inverting terminal (+) is physically grounded (VY = 0) as shown in fig.
3.2(a). Though the inverting terminal (-) is not grounded, it also stays at 0V. i.e., VX = 0V. This
phenomenon is known as virtual ground of op-amp. This is because, since the input impedances of an
ideal op-amp is infinite (Ri = ∞). There is no current flow into the two terminals. Hence, VX = VY.
Difference between open loop and closed loop

Open loop Closed loop
 No feedback connection by any type of  Fraction of the output voltage is negatively fed
components between input and output. back to the input through Rf.
 Open loop gain (AOL) is very high and  The ratio Rf / Rin controls the closed loop gain
cannot control. (ACL).
 Small difference between inputs cause op-  The ratio Rf / Rin controls output Vo of the op-
amp goes to saturation. amp go in to saturation.
 If V1 > V2 ; Vo = negative saturation,  If Rf > Rin ; ACL > 1
 If V1 < V2 ; Vo = positive saturation  If Rf < Rin ; ACL < 1
Where, V1 = inverting terminal and  If Rf = Rin ; ACL = 1
V2 = non- inverting terminal.
3.4 Op-amp Application circuits
3.4.1 Inverting operational Amplifier
The basic circuit for the inverting op-amp circuit is shown in the fig. 3.3. Input signal Vin is applied to
the inverting terminal of the circuit through Rin , and resistor RF is connected between the output and the
inverting input. The non-inverting input is connected to ground.
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 Output Vout is inverted version (180o phase shift) of input Vin, but amplified as shown in the fig. 3.3
(c). The ratio RF / Rin controls the closed loop gain (ACL).
Virtual ground concept:
1. No input current flows into the (-) terminal and
2. VX always equals to VY.
Therefore, all input current Iin flows towards the output (Vout ) through RF. See fig. 3.4.
Fig. 3.3 Inverting op amp (a) Input wave form (b) Inverting op amp circuit (c) Output wave form
Analysis: Apply KCL at node VX

Iin = IF using nodal analysis in the
direction of current flow,
= since, VX = VY = 0
Fig. 3.4 Virtual ground concept
= or = Closed Loop Gain ACL =
= = ACL = Output Voltage Vout = - Vin
[NOTE: 1. Minus (-) indicates output is inverted version of input.

2. is a scaling factor, the gain ACL depends on the selection of and values]
3.4.2 Non-inverting operational Amplifier

 The basic circuit for the non-inverting op amp circuit is shown in the fig. 3.5. Input signal Vin is
applied to the non-inverting (+) terminal of the circuit and resistor RF is connected between the
output and the inverting terminal. The inverting (-) input is connected to ground via Rin.
 Output Vout is non-inverted version (0o phase shift) of input Vin, but amplified. The ratio RF / Rin
controls the closed loop gain (ACL). Always ACL is greater than 1.

1. No current flows into the input terminal (+) and
2. VX always equals VY. Therefore, VX = VY =Vin, also current flows from output (Vout ) through RF
reaching ground. See fig. 3.6
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Fig. 3.5 Non-inverting op-amp (a) Input wave form (b) circuit (c) Output wave form
Analysis:
Apply KCL at node VY
using nodal analysis in the direction of current flow,
Iin = IF
since, VX = VY = Vin
Fig. 3.6 Virtual ground concept
Closed loop gain ACL =
3.4.3 Summing OPAMP

 The inverting summing or adder op-amp circuit NOTE: Gain, ACL will always >1
for three inputs is shown in the fig. 3.7.
 The output voltage, Vo is proportional to the
algebraic sum of the input voltages, V1, V2, V3.
Because effectively it adds individual input
voltage signals.
 Input signals V1, V2 and V3 are applied to the
inverting (-) input of the op-amp through input
Fig. 3.7 Inverting summing op-amp circuit
resistors R1, R2 and R3, respectively. Thus, I1, I2 and I3 are input currents flow through them.
 RF is connected between the Vo and the (-) input. The non-inverting input is connected to ground.
 1. No input current flows into the (-) terminal and

 2. VX always equals VY. Therefore, all input currents flow towards output (Vout ) through RF.
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Analysis: Apply KCL at node VX, using nodal analysis in the direction of current flow,
I1+ I2 + I3 = IF …………………………………………………… (1)
Where, I1 = , I2 = , I3 = and IF =
Then eqn (1) becomes, since, VX = VY = 0
Vo = - if R1 = R2 = R3 = RF = R
Vo = - (V1+V2 +V3) ≡ output voltage is proportional to the algebraic sum of the input voltages, V1, V2 ,V3.
Applications:
 Precision amplifier
 Audio mixer
 Digital to Analogue Converter (ADC), etc
3.4.4 Voltage follower OPAMP
Fig. 3.8 (a) Voltage follower op-amp (b) resembled circuit of non-inverting op-amp
 Output voltage Vout follows the input voltage Vin so the circuit is named as op-amp voltage follower.
 The output is connected directly back to the (-) inverting input so that the feedback is 100% and Vin
is exactly equal to Vout . It is shown in the fig. 3.8(a).
 If voltage Vin increases, voltage Vout increases. On the other hand, if voltage Vin decreases, voltage
Vout also decreases. It provides an effective isolation of the output from the signal source that
eliminating the loading effect of the second circuit from the first circuit. Because the input
impedance of the op amp is very high, draws very little power from the signal source, avoiding
loading effects. This circuit is useful for the first stage.
Properties of Voltage Follower
 Voltage gain = 1
 Input impedance Rin = ∞
 Output impedance Rout = 0
 Effective isolation of the output from the signal source.
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To Prove Voltage gain, = AV = 1
Voltage follower is resembles to that of non-inverting opamp, in which input impedance Rin is open
circuited (= ∞) and output impedance Rout is short circuited (= 0). See fig. 3.8(b).
= AV =
= AV =
Advantage: provides current and power gain.

Applications: The voltage follower is often used as buffers for logic circuits, impedance matching.
3.4.5 Differentiator op-amp
 Differentiator produces output voltage (Vout) is proportional to the rate of change of the input voltage
Vin. If input is a sine wave output of a differentiator is a (inverted) cosine wave. See the fig.3.9.
 A differentiator with the only RC network is called a passive differentiator, whereas a differentiator
with an op-amp is called an active differentiator.
 Advantages of active differentiator: have higher output voltage and lower output resistance than
passive RC differentiators.
 An op-amp differentiator is an inverting amplifier, which uses a capacitor C in series with the input
voltage Vin and a feedback resistor Rf is connected between Vout and inverting (-) input. The non-
inverting input terminal of the op-amp is connected to ground as shown in the fig.3.9.
 For DC input, capacitor C behaves like an open-circuit. Also, attenuates low frequency signals and
allows only high frequency signals at the output. In other words, circuit behaves like a high-pass
filter.
Input wave form

Output wave form
Fig. 3.9 Differentiator op-amp
Analysis:
From the fig.3.9, since, the node VY is at ground potential the node VX is virtually grounded.
i.e. Vx = Vy = 0.
Therefore, the current flowing into the op-amp internal circuit is zero, effectively all of the current flows
through the resistor Rf.
From the input side, the current Iin = C [d(Vin - Vx) / dt] = C [dVin / dt]…………………………(1)
From the output side, the current IF = (Vx - Vout) / Rf = - {Vout / Rf} …………………………(2)
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Equating the (1) & (2) equations Iin = IF
C{dVin / dt} = - Vout / Rf
Vout = - Rf C{dVin / dt}
The output Vout is Rf C times the differentiation of the input voltage. The product Rf C is called as the
RC time constant of the differentiator circuit. The negative sign indicates the output is out of phase by
180o with respect to the input.
Applications:
 Wave shaping circuits
 To operate on triangular and rectangular signals.
3.4.6 Integrator op-amp

 Integrator produces output voltage Vout, is proportional to the integral of the input voltage Vin. If
input is a square wave, output of an integrator is a triangular (inverted) wave. See the fig.3.10.
Integrator with the only RC network is called a passive integrator, whereas an integrator with an op-
amp is called an active integrator. Advantages of active integrator: have higher output voltage and
lower output resistance than passive RC integrators.
 An op-amp integrator is an inverting amplifier, which uses a resistor Rin in series with the input
voltage Vin and a capacitor C is connected between Vout and inverting (-) input as feedback. The non-
inverting input terminal of the op-amp is connected to ground as shown in the fig.3.10.
 For DC input, capacitor C behaves like an open-circuit. Also, attenuates high frequency signals and
allows only low frequency signals at the output. In other words, circuit behaves like a low-pass filter.
Output
Input
Square wave
Fig. 3.10 Integrator op-amp
Analysis: From the fig.3.10, since, the node VY is at ground potential the node VX is virtually grounded.
i.e. Vx = Vy = 0. Therefore, the current flowing into input terminals is zero, effectively all of the current
flows through the capacitor C.
………………………… (1)
From the output side, the current IF = C [d(VX - Vout) / dt] = - C [dVout / dt] …………………… (2)
Equating the (1) & (2) equations: Iin = IF
= - C [d(Vout)/dt] ……………………………………(3)
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The output Vout is CRin times the integration of the input voltage Vin. The product CRin is called as the
RC time constant of the integrator circuit. The negative sign indicates the output is out of phase by 180o
with respect to the input.
3.4.7 Comparator OPAMP

OPAMP voltage comparator compares the magnitudes of two voltage inputs and determines which is the
larger of the two.
 Referring the fig.3.11, assume ( VIN < VREF ).

 As the non-inverting (positive) input of the comparator is less than the inverting (negative) input, the
output will be the negative supply voltage, -Vcc resulting in a negative saturation of the output.
 When (VIN > VREF) , the output voltage rapidly switches HIGH towards the positive supply
voltage, +Vcc resulting in a positive saturation of the output.
Fig. 3.11 Voltage comparator using OPAMP
 Suppose the input voltage VIN, is decreased slightly less than VREF, the op-amp’s output switches
back to its negative saturation voltage acting as a threshold detector.
 Then it is seen that the op-amp voltage comparator is a device whose output is dependent on the
value of the input voltages.
Exercise
1. What is an op-amp? Write the pin diagram of µA 741op-amp.
2. Write the symbol of µA 741op-amp and name the terminals.
3. List and discuss the ideal and practical characteristics/parameters of op-amp.
4. With circuit diagrams explain the operation modes of op-amp.
5. With neat circuit diagram and waveforms explain how op-amp can be used as inverting and non-
inverting amplifiers.
6. Explain three input inverting type summing amplifier.
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7. Explain the working of op-amp as an integrator.
8. Explain the working of op-amp as a differentiator.
9. With neat circuit and waveforms explain the voltage follower using op-amp.
10. With neat circuit and waveforms explain the comparator using op-amp.
Problems
1. In the circuit shown below R2 = 99 kΩ. Assume that the op-amp is ideal. Determine the value
of R1 so that the magnitude of closed-loop gain, G = vO / vS is 11.
2. Calculate the voltage gain for each stage of this amplifier circuit (both as a ratio and in units
of decibels), then calculate the overall voltage gain.
Ans: Stage 1: AV = 4.3 = 12.669 dB

Stage 2: AV = 6.745 = 16.579 dB
Overall: AV = 29.002 = 29.249 dB
3. Determine both the input and output voltages in the following circuit.
Ans: Vin = -10 V Vout = 24 V
4. Calculate the output voltage if V1 = V2 = 0.15 V.
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5. Calculate the input voltage if the final output is 10.08 V.
Ans: 0.168 V
6. Calculate the output of the first-stage op-amp when V1 = 25 mV.
7. Calculate the output voltage if V1 = V2 = 700 mV.
8. Calculate IL for this circuit.
Ans: 5 mA
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Multiple choice Questions
1. How many op-amps are required to implement this equation? Vo = V1

A. 2 B. 3
C. 4 D.1
2. How many op-amps are required to implement this equation?
A. 2 B.3
C. 4 D.1
3. A differential amplifier ……………..

A. is a part of an Op-amp C. has one input and one output
B. has two outputs D. answers (1) and (2)
4. When a differential amplifier is operated single-ended, …………

A. the output is grounded C. one input is grounded and signal is applied to the other
B. both inputs are connected together D. the output is not inverted
5. In differential-mode, …………….
A. opposite polarity signals are applied to the inputs C. the gain is one
B. the outputs are of different amplitudes D. only one supply voltage is used
6. In the common mode, ……………

A. both inputs are grounded C. the outputs are connected together
B. an identical signal appears on both the inputs D. the output signal are in-phase
7. The common-mode gain is ………..

A. very high C. very low
B. always unity D. unpredictable
8. The differential gain is ………

A. very high C. very low
B. dependent on input voltage D. about 100
9. If ADM = 3500 and ACM = 0.35, the CMRR is ……….

A. 1225 C. 10,000
B. 80 dB D. answers (1) and (3)
10. With zero volts on both inputs, an OP-amp ideally should have an output ………..
A. equal to the positive supply voltage C. equal to the negative supply voltage
B. equal to zero D. equal to CMRR
11. For an Op-amp with negative feedback, the output is …….

A. equal to the input C. increased
B. fed back to the inverting input D. fed back to the noninverting input
12. The use of negative feedback ………
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A. reduces the voltage gain of an Op-amp C. makes the Op-amp oscillate
B. makes linear operation possible D. answers (1) and (2)
13. Negative feedback ………..

A. increases the input and output impedances C. increases the input impedance and bandwidth
B. decreases the output impedance and bandwidth D. does not affect impedance or bandwidth
14. A certain noninverting amplifier has Ri of 1 kΩ and Rf of 100 kΩ. The closed-loop voltage gain
is ………
A. 100,000 C. 1000
B. 101 D. 100
15. The Op-amp can amplify

A. a.c. signals only C. d.c. signals only
B. both a.c. and d.c. signals D. neither d.c. nor a.c. signals
16. The input offset current equals the ……….

A. difference between two base currents C. average of two base currents
B. collector current divided by current gain D. none of these
17. The input stage of an Op-amp is usually a ……….

A. differential amplifier C. class B push-pull amplifier
B. CE amplifier D. swamped amplifier
18. Current cannot flow to ground through …….

A. a mechanical ground C. an a.c. ground
B. a virtual ground D. an ordinary ground
19. An ideal operational amplifier has

A. infinite output impedance B. zero input impedance
C. infinite bandwidth D. All of the above
20. Another name for a unity gain amplifier is:
A. difference amplifier B. comparator
C. single ended D. voltage follower
21. Which of the following electrical characteristics is not exhibited by an ideal op-amp?
A. Infinite voltage gain B. Infinite bandwidth
C. Infinite output resistance D. Infinite slew rate
22. An ideal op-amp requires infinite bandwidth because

A. Signals can be amplified without attenuation
B. Output common-mode noise voltage is zero
C. Output voltage occurs simultaneously with input voltage changes
D. Output can drive infinite number of device
Answer: a
23. Ideal op-amp has infinite voltage gain because
A. To control the output voltage B. To obtain finite output voltage
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C. To receive zero noise output voltage D. None of the mentioned
Answer: b Explanation: As the voltage gain is infinite, the voltage between the inverting and non-
inverting terminal (i.e. differential input voltage) is essentially zero for finite output voltage.
24. How will be the output voltage obtained for an ideal op-amp?
A. Amplifies the difference between the two input voltages

B. Amplifies individual input voltages
C. Amplifies products of two input voltage
D. None of the mentioned
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Module – 4 BJT Applications, Feedback Amplifiers and Oscillators
4.1 Introduction
4.2 BJT as an amplifier
4.3 BJT as a switch
4.4 Transistor switch circuit to switch ON/OFF an
LED and a lamp in a power circuit using a relay
4.5 Feedback Amplifiers – Principle
4.6 Properties and advantages of Negative
Feedback
4.7 Types of feedback
4.8 Voltage series feedback
4.9 Gain stability with feedback
4.10 Oscillators – Barkhaunsen's criteria for
oscillation
4.11 RC Phase Shift oscillator
4.12 Wien Bridge oscillator
4.13 IC 555 Timer
4.14 Astable Oscillator using IC 555
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4.1 Introduction
Transistor means, transfer resistor. So, named because it transfers the signal from the region of low
resistance to the region of high resistance. Transistor is a three layered - two PN junction semiconductor
device. The three layers are called the emitter (E), base (B) and collector (C). It is also called as Bipolar
Junction Transistor (BJT): because, both electrons and holes contribute to current in the device. This
current controlled device is invented in 1948 by Shockley, Bardeen, and Brattain at Bell Laboratories.
BJT can act as an electrically controlled switch, or a current amplifier depending upon junction biasing
condition. There are two types of BJT: NPN and PNP. The NPN type consists of two N-regions
separated by a P-region. The PNP type consists of two P-regions separated by an N-region. The details
of three regions of the transistor can be summarized as below.
Region Function Doping level Physical Area
Emitter (E) Emits or injects the majority carriers high Moderate

Base (B) Controls the flow of the majority carriers light Thin
Collector (C) Collects the majority carriers Moderate Large
Doping level of the Emitter is made high because its function is to emit the majority carriers. Base is
thin and lightly doped because it has to control the flow of majority carriers with least recombination.
Physical area of the collector is large because it must dissipate more heat while collecting the majority
carriers. Structure and circuit symbol of PNP and NPN transistors are shown in the fig. 4.1.
Arrow head in the circuit

symbol shows the conventional
direction of current flow
(a) (b)
Fig. 4.1 (a) Structure and circuit symbol of PNP (b) Structure and circuit symbol of NPN transistor
4.2 BJT in CE mode: As a voltage Amplifier

The CE amplifier is designed so that a small change in input voltage, results large changes at the output
due to small current in the Base (ΔIB) of the transistor made large changes in the Collector current (ΔIC).
That means, the small swings in the input produce large changes in the output.
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Amplifier is the circuit that increases the strength of a
weak signal, is as shown in fig. 4.2.
Let Vin be a small AC input voltage signal applied to
the Base of the NPN transistor connected in the CE
mode in series with the bias source VBB.
 During positive half cycle of Vin: Input voltage to
the transistor is (VBB + Vin). This makes input more
forward bias. Increasing IB, causes exponential
increase in IC and it is IC =β IB.
 As IC rises, voltage drop across RC increases and VCE
drops toward ground (VCE = Vo =VCC - IC RC). As a
result, output voltage Vo (= VCE) is a negative swing.
 During negative half cycle of Vin: Input voltage to
the transistor is (VBB - Vin). This makes input less Fig. 4.2 Biased NPN transistor in CE mode as a voltage
forward bias. Decreasing IB, causes decrease in IC. Amplifier
 As IC drops, voltage drops across RC also decreases and VCE rises toward VCC (VCE = Vo =VCC - IC
RC). As a result, output voltage Vo (= VCE) is a positive swing.
 In this way small swings in the input produce large changes in the output. Since the output signal
goes negative when the input is positive, input and output signals are 180o out of phase.
 β is current gain defined as the ratio of the Collector current IC to the Emitter current IB. I
 C
Voltage gain is given by, AV = IB
Characteristics:
1. Large current gain, voltage gain and power gain 2. Voltage phase shift is about 1800
3. Moderate input and output impedance
Transistor Voltages and currents

PNP and NPN Transistor voltages and currents are described in the fig.4.3.
Fig. 4.3 PNP and NPN Transistor Voltages and currents
Table 2 Notations and meanings of PNP and NPN Transistor Voltages and currents
Transistor voltages Transistor Currents
Between transistor terminals Between terminal and Through terminals
ground
VCE = Voltage between Collector-Emitter VE = Emitter Voltage IE = Emitter Current
VCB= Voltage between Collector-Base VB = Base Voltage IB = Base Current
VEB= Voltage between Emitter-Base VC = Collector Voltage IC = Collector Current
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4.3 Transistor as a switch

A BJT works as a switch when it is alternately driven between the saturation region and cutoff regions.
A simple version of the switch is shown in fig. 4.4(a) and (b).
Cut-off Characteristics: When the input equals 0V, the BE junction is reverse biased (OFF), so no
current flows in the circuit; hence transistor works as open switch.
Saturation Characteristics: When the input equals +VBB, the BE junction is forward biased (ON), so
current flows in the circuit; hence transistor works as closed switch.
 The input = 0V, hence IB = 0, in turn IC = 0

 Base-Emitter voltage VBE < 0.7V
 BE and BC junctions are reverse biased
 IC = 0, thus VCE = VCC
 Transistor is “fully-OFF” ( Cut-off region ) and
operates as a “open switch”
 The input is +Vin = VBB, Base current IB flows

 Base-Emitter voltage VBE > 0.7V
 BE and BC junctions are forward biased
 Maximum Collector current flows (IC = Vcc/RL)
and VCE = 0, ( No voltage drop )
 Transistor is “fully-ON” ( saturation region ) and
operates as a “closed switch”
Fig4.4. Transistor as a switch (a) open switch (b) Closed switch
4.4 Transistor Switch Circuit Using Relay

Electromechanical relays are switches used to control high power electrical devices or load (electric
lamp, motor, etc). It is possible to control the relay operation using a transistor as a switch. When a
transistor is able to energize a coil of the relay, so that the external load connected to it is controlled. The
fig.4.5, illustrates transistor switch circuit to switch ON/OFF an LED and a LAMP in a power circuit
using a relay.
Consider the fig.4.5 (a) illustrates a transistor switch circuit used to switch ON/OFF an LED using the
relay coil. The input (+ V) applied at the Base causes to drive the transistor into saturation region, which
further results the circuit becomes short circuit. So the relay coil gets energized and relay contacts get
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operated and LED turned ON. Similarly, fig.4.5 (b) illustrates a transistor switch circuit used to switch
ON/OFF a lamp using the relay coil.
Fig.4.5 (a) illustrates a transistor switch circuit used to switch ON/OFF an LED using the relay
Fig. 4.5(b) illustrates a transistor switch circuit used to switch ON/OFF an LAMP using the relay
In inductive loads, particularly switching of motors and inductors, sudden removal of power can induce
a high potential across the coil. This high voltage can cause considerable damage to the rest circuit.
Therefore, the diode is connected in parallel with inductive load to protect the circuit from induced
voltages.
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4.5 Feedback Amplifiers

Feedback Systems are very useful and widely used in amplifier circuits, oscillators, process control
systems as well as other types of electronic systems. A feedback system is one in which a fraction of the
output signal is sampled and then fed back to the input to form an error signal that drives the system.
4.5.1 Principle of Feedback Amplifier
A feedback amplifier generally consists of two parts. They are the amplifier and the feedback circuit.
The Feedback circuit is essentially a potential divider consisting of resistances R1 and R2. The purpose
of feedback circuit is to return a fraction of the output voltage to the input of the amplifier circuit. The
concept of feedback amplifier can be understood from the following fig.4.6.
Fig. 4.6 Principle of Feedback Amplifier
From the fig.4.6 the gain of the amplifier is represented as A and defined as the ratio of output voltage
Vo to the input voltage Vi. The gain of the feedback circuit is represented as β and extracts a voltage
Vf = β Vo from the output Vo of the amplifier. The quantity β = Vf/Vo is called as feedback ratio
(fraction).
This voltage is added for positive feedback and subtracted for negative feedback, from the signal
voltage Vs. Now,
Vi = Vs + Vf = Vs + βVo (positive feedback)
Vi = Vs – Vf = Vs – βVo (negative feedback)
4. 5. 2 Types of Feedbacks
Depending upon whether the feedback signal aids or opposes the input signal, there are two types of
feedbacks used.
1) Positive Feedback
Positive feedback is when output is added to the input (via feedback) and amplified again. In this case,
the feedback signal (voltage or current) is in phase with the input signal. Both the input signal and
feedback signal introduces a phase shift of 180o thus making a 360o resultant phase shift around the
loop, to be finally in phase with the input signal.
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Though the positive feedback increases the gain of the amplifier, it has the disadvantages such as
Increasing distortion and instability
Though the positive feedback increases the

gain of the amplifier, it has the disadvantages
such as
 Increasing distortion and
 instability
It is because of these disadvantages the positive feedback is not recommended for the amplifiers. If the
positive feedback is sufficiently large, it leads to oscillations, by which oscillator circuits are formed.
Let Af be the overall gain (gain with the feedback) of the amplifier. This is defined as the ratio of
output voltage Vo to the applied signal voltage Vs, i.e.,
The equation of gain of the feedback amplifier, with positive feedback is given by
(Vs + βVo) A = Vo (Vs + βVo) A = Vo
Or
AVs +A βVo = Vo AVs + A βVo = Vo
Or
AVs =Vo (1-Aβ) AVs = Vo (1-Aβ)
2) Negative Feedback
Negative feedback is when the output is subtracted from the input. In this case, the feedback signal
(voltage or current) is out of phase with the input signal. In negative feedback, the amplifier introduces
a phase shift of 180o into the circuit while the feedback network is so designed that it produces no
phase shift or zero phase shift. Thus the resultant feedback voltage V f is 180o out of phase with the
input signal Vin. The output Vo must be equal to the input voltage (Vs - βVo) multiplied by the gain A of
the amplifier. Hence,
(Vs − βVo) A = Vo (Vs − βVo) A = Vo
Or
AVs –A βVo = Vo AVs – A βVo = Vo
Or
AVs =Vo (1+Aβ) AVs = Vo (1+Aβ)
Therefore, the equation of gain of the feedback
amplifier, with negative feedback is given by
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Though the gain of negative feedback amplifier is reduced, there are many advantages.
Advantages of negative feedback
 Stability of gain is improved
 Reduction in distortion
 Reduction in noise
 Bandwidth increases
 Non linear distortion decreases – improves higher fidelity
 Increase in input impedance
 Decrease in output impedance
It is because of these advantages negative feedback is frequently employed in amplifiers.
Disadvantages of negative feedback
 Overall amplifier gain is reduced.
 Unstable and oscillate at high frequencies.
4.6 Properties of Feedback amplifiers

1. Reduced gain
2. Increased bandwidth
3. Increased stability
4. Decreased Noise
5. Modified Input impedance and Output Impedance
4.7 Classification of Feedback Systems (types of feedback topologies)

There are four different types of feedback topologies based on type of output signal and feedback signal
(voltage or current signal). Voltage feedback is taken in series with the load and current feedback is
taken in shunt with the load.
1. Voltage-series or series-shunt feedback
Voltage in and Voltage out or Voltage
Controlled Voltage Source (VCVS).
Works as a voltage amplifier as the input
signal is a voltage and the output signal is a
voltage, so the transfer gain is given as:
Av = Vo / Vi.
2. Current-series or series-series feedback

Voltage in and Current out or Voltage
Controlled Current Source (VCCS).
Works as trans-conductance type amplifier
system as the input signal is a voltage and
the output signal is a current. then for a
series-series feedback circuit the transfer
gain is given as:
Gm = Io / Vi.
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3. Current-shunt or shunt-series feedback
Current in and Current out or Current
Controlled Current Source (CCCS).
Works as a true current amplifier as the input
signal is a current and the output signal is a
current, so the transfer gain is given as:
Ai = Io / Ii.
4. Voltage-shunt or shunt-shunt feedback

Current in and Voltage out or Current
Controlled Voltage Source (CCVS).
Works as trans-resistance type voltage
amplifier as the input signal is a current and
the output signal is a voltage, so the transfer
gain is given as:
Rm = Vo / Ii.
4.8 Voltage-Series Feedback
The input voltage Vi of the basic amplifier is the algebraic sum of input signal Vs and the feedback
signal Vo , where Vo is the output voltage. In this case, feedback connection with a part of the output
voltage V0 fed back in series with the input signal Vs.
If there is no feedback (Vf = 0), the voltage gain of the

amplifier is V V
A o  o
Vs Vi
If a feedback signal Vf is connected with the input in

series, the overall voltage gain is
Input Impedance with the feedback is:

VS = Ii Z i + Vf = I i Z i + βVo
Using voltage divider rule, we get:
Now, Vo = AV Ii ZL =AV Vi
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4.9 Gain Stability with feedback

The gain, A of the basic amplifier depends generally on certain factors (temperature, parameters of
active devices, OP, etc.).
Differentiating,
Where, dAf /Af = fractional change in gain with the feedback;

dA/A = fractional change in gain without the feedback.
( ) = de-sensitivity (reciprocal of sensitivity) indicates the fraction by which the voltage gain has
been reduced due to feedback.
4.10 Oscillators – Barkhausen's criteria for oscillation
An oscillator is a circuit that produces a periodic waveform on its output using only the DC supply
voltage (VCC) as an input.
A transistor amplifier with proper positive feedback can act as an oscillator. That means, it can generate
oscillations without any external signal source. The necessary conditions for oscillations is shown in the
fig. 4.7.
Fig. 4.7Conditions for Oscillation
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Barkhausen Criterion or Conditions for Oscillation
Two conditions are required for a sustained state of oscillation:
1. The phase shift around the feedback loop must be 0o or 360o.
2. The voltage gain, Acl, around the closed feedback loop must be unity (i.e, loop gain, Av β = 1).
The voltage gain around the closed feedback loop, is the product of the amplifier gain, and the feedback
factor, β, of the feedback circuit. Acl = Av β
As illustrated in the fig.4.7, when oscillation starts at t0, the condition Acl > 1 causes the sinusoidal
output voltage amplitude to build up to a desired level. Then Acl decreases to 1 and maintains the desired
amplitude.
4.11 R-C phase shift oscillator

Good frequency stability and waveform can be obtained from oscillators employing resistive and
capacitive elements. Such amplifiers are called R-C or phase shift oscillators and have the additional
advantage that they can be used for very low frequencies. In a phase shift oscillator, a phase shift of 180º
is obtained with a phase shift circuit instead of inductive or capacitive coupling. A further phase shift of
180º is introduced due to the transistor properties.
Fig.4.8 (a) shows a single section of RC network. From the elementary theory of electrical engineering,
it can be shown that alternating voltage V1′across R leads the applied voltage V1 by øº. The value of
ødepends upon the values of R and C. If resistance R is varied, the value of øalso changes. If R were
reduced to zero, V1′will lead input voltage by 90º i.e. ø= 90º. However, adjusting R to zero would be
impracticable because it would lead to no voltage across R. Therefore, in practice, R is varied to such a
value that makes V′1 to lead input voltage by 60º. Similarly as shown in fig.4.8 (b) for three RC stages
output lead the input voltage by 180º.
V1’
(a) (b)
Fig. 4.8 RC phase shift network. (a) RC single section producing 60º phase shift (b) RC three sections producing 180 o
phase shift.
As shown in the fig. 4.9, RC Phase shift oscillator consists of an opamp and a RC phase shift network.
The phase shift network consists of three RC sections. At some particular frequency f0, the phase shift in
each RC section is 60º so that the total phase-shift produced by the RC network is 180º.
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Vo
Fig.4.9 R-C phase shift oscillator
The frequency of oscillations is given by:
N = number of RC stages,
R1 = R2 = R3 =R
C1 = C2 = C3 =C ………………(i)
Circuit operation:
When the circuit is switched on, it produces oscillations of frequency determined by eqn. (i). The output
V0 of the OPAMP is fed back to RC feedback network. A phase shift of 180º is produced by OPAMP. A
further phase shift of 180º is produced by the RC network. As a result, the phase shift around the entire
loop is 360º. This satisfies one of the Barkhausen’s criteria. Another criterion is loop gain, .
RC Oscillators are constant and provide a well shaped sine wave output with the frequency being
proportional to 1/RC and therefore, when we are using a variable capacitor a wide frequency range is
possible.
Advantages
(i) It does not require transformers or inductors.

(ii) It can be used to produce very low frequencies (starting at a few Hertz and up to about 100 kHz).
(iii) The circuit provides good frequency stability.
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Disadvantages
(i) It is difficult for the circuit to start oscillations as the feedback is generally small.
(ii) The circuit gives small output.
4.12 Wien Bridge oscillator
A Wien bridge oscillator is an oscillator that generates sine waves with a wide range of frequencies. The
bridge comprises four resistors and two capacitors. Wien bridge oscillator using RC bridge and OPAMP
is shown in the fig.4.10.
Fig.4.10 Wien bridge oscillator using RC bridge and OPAMP
Circuit operation
When the circuit is switched on, there exists a particular frequency at which the values of the resistance
and the capacitive reactance will become equal to each other, producing maximum output voltage. This
frequency is referred to as resonant frequency which is given as
…………………… (ii)
The output V0 of the OPAMP is fed back to Wien bridge feedback circuit with respect to points a and c.
Points b and d provide – ve and + ve inputs to the OPAMP. A phase shift of 180º is produced by
inverting OPAMP. A further phase shift of 180º is produced by the RC feedback bridge circuit. As a
result, the phase shift around the entire loop is 360º. This satisfies one of the Barkhausen’s criteria.
For oscillations, Barkhausen’s other criterion: loop gain, is Aβ = -1.
Let, | Aβ | = 1
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Solving, R3 = 2R4
Thus ratio of resistances will provide sufficient loop gain for the circuit to oscillate at the frequency of
Eqn. (ii).
Applications of Wien Bridge Oscillators

 To measure the audio frequency
 As a band-pass filter to amplify the 19KHz pilot carrier from FM audio
 To produce sine wave
 For finding the exact value of the capacitor
 For generating 0o phase
Advantages
 By varying capacitances the frequency of oscillation can be easily varied
 Excitation for AC Bridge
 To fabricate pure tune
 Useful audio frequency range (20 Hz to 100 kHz)
Disadvantages
 Maximum frequency output is limited because of amplitude and phase shift characteristics of the
amplifier
 The design is bulky
4.13 IC 555 Timer

IC 555 timer mainly consists three sections: (see fig. 4.11(b)).
1. Comparator:
The two OPAMP Comparators are compare the two input voltages i.e. between the inverting (-) and the
non-inverting (+) input and if the non-inverting input is more than the inverting input then the output of
the comparator is high.
2. A resistive network:
It is formed by three equal resistors (5 KΩ - the IC bears its name as 555 timer). These are arranged in
voltage divider configuration and as a result provide the voltage values of 2⁄3 VCC and 1⁄3 VCC.
3. Flip/Flop (FF):
FF is a memory element that operates as
R = 1, S = 0, output = 0 and R = 0, S = 1, output = 1.
The output of comparators is directly given to the inputs of SR Flip Flop. Thus the output of the SR Flip
Flop will be set according to the outputs of the comparator which in turn depends on the Trigger and
Threshold inputs.
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Fig.4.11 (a) IC 555 timer (b) internal circuitary
Table: Function of different Pins
Pin No. Name Function

1 Ground Used to provide a zero voltage.
A low voltage (less than 1/3 the supply voltage) applied momentarily to the
2 Trigger Trigger input causes the output (pin 3) to go high. The output will remain
high until a high voltage is applied to the Threshold input (pin 6).
3 Output This is the output pin of the timer. It can source or sink 200 mA of current.
A low voltage (< 0.7V) applied to this pin will cause the output (pin 3) to
4 Reset
go LOW. This input should remain connected to +Vcc when not used.
This pin can be used to change the reference voltages of the comparators through
5 Control Voltage
this we can vary the timing.
When the voltage at this input rises above the threshold value (Vth) the
6 Threshold
output will go from high to low.
When the voltage across the timing capacitor exceeds the threshold value.
7 Discharge
The timing capacitor is discharged through this input.
8 Supply Voltage Positive supply voltage terminal is usually between +5V and +15V.
Applications
As an Oscillator (Mono-stable, Astable or in Bistable mode to produce a flip/flop type action)
In Pulse Amplitude Modulation (PAM),
Pulse Width Modulation (PWM) etc.
4.14 Astable Oscillator using IC 555

The astable multi-vibrator is a free running oscillator that generates a continuous rectangular ON/OFF
pulses that switch between two voltage levels. The frequency of the pulses and their duty cycle are
dependent upon the RC values of the circuit.
Working:
From the fig.4.12, assume the Flip Flop is initially cleared, when the power is switched ON, then the output
of inverter will be HIGH.
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Case -1: When output is HIGH
The capacitor C charges towards Vcc through the series resistors R1 and R2 (see fig. 4.13). The charging
time constant TC = 0.693 (R1 + R2) C. Where, R1 and R2 are in Ω and C in Farads. As voltage across the
capacitor is just greater than 2/3 Vcc, upper comparator sets Flip Flop and output goes LOW.
Fig.4.12 Astable Oscillator using IC 555
Fig.4.13 Astable Oscillator waveforms using IC 555

Case -2: When output is LOW
The capacitor C discharges through resistors R2. The discharging time constant TC = 0.693 (R1 + R2) C.
As voltage across the capacitor is slightly lesser than 1/3 Vcc, lower comparator resets Flip Flop and
output goes HIGH.
Since, TC > TD, output wave form is a rectangular pulse train. Total time period of the waveform shown
in the fig.4.13 (b) is
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T = TC + TD = 0.693 (R1 + R2) C + 0.693 (R1 + R2) C = 0.693 (R1 + 2R2) C
The duty cycle can be expressed as a percentage ( % ). If both timing resistors, R1 and R2 are equal in
value, then the output duty cycle will be 2:1 that is, 66% ON time and 33% OFF time with respect to the
period.
Design: Astable Multi-vibrator using 555
Case – 1: The time during which the capacitor C charges from 1/3 VCC to 2/3 VCC is equal to the time
the output is HIGH and is given as TC or THIGH = 0.693 (R1 + R2) C, which is proved below.
Voltage across the capacitor at any instant during charging period is given as,
Vc = VCC (1 – et / RC)
i) Time taken by the capacitor to charge from 0 to +1/3 VCC
Vc = VCC (1 – et / RC) where Vc =1/3 VCC
1/3 VCC = VCC (1 - et/RC)
e-t/RC = (1-1/3)
e-t/RC = 2/3
t1 = loge (3/2)RC where t = t1 (Note: ln = loge)
t1=0.405RC
ii) Time taken by the capacitor to charge from 0 to +2/3 VCC
2/3 VCC = VCC (1 - et/RC)

e-t/RC = (1-2/3)
e-t/RC = 1/3 where t = t2
t2= RC loge 3 = 1.0986 RC
iii) Time taken by the capacitor to charge from +1/3 VCC to +2/3 VCC
TC = (t2 – t1) = (1.0986 – 0.405) RC = 0.693 RC

Substituting R = (R1 + R2) in above equation we have
TC = 0.693 (RA + RB) C
Case -2: The time during which the capacitor discharges from +2/3 VCC to +1/3 VCC is equal to the time
the output is low and is given as
Vc = 2/3 VCC e– Td/ R2C
Substituting Vc = 1/3 VCC and t = td in above equation we have
Easwara M 87
1/3 VCC = 2/3 VCC e – (Td/ R2C)
2*e – (Td/ R2C) = 1, apply loge on both sides,
loge 2 - Td/ R2C = 0
TD = 0.693 R2C
Applications
1. Square Generator
2. FSK Generator
3. Pulse Position Modulator
Appendix A – Analysis of RC Phase shift Oscillator

 Let us find transfer function of the RC feedback network :
 Applying KVL to various loops we get,
 Replacing jω by s and writing the equations in the matrix form,
Using the Crammer’s rule to obtain I3
Easwara M 88
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This is the frequency with which circuit oscillates,
At this frequency,
Negative sign indicates phase shift of 180°
Easwara M 90
Exercise
1. Explain how BJT works as an amplifier and as a switch.
2. Explain how does a transistor used to switch ON/OFF an LED using the relay.
3. Differentiate between oscillator and amplifier.
Oscillators
1. They are self-generating circuits. They generate waveforms like sine, square and triangular
waveforms of their own. Without having input signal.
2. They are not self-generating circuits. They need a signal at the input and they just increase the
level of the input waveform.
3. It has infinite gain
Amplifiers
1. It has finite gain
2. Oscillator uses positive feedback.
3. Amplifier uses negative feedback.
4. What will happen to the oscillation if the magnitude of the loop gain is greater than unity?
In practice loop gain is kept slightily greater than unity to ensure that oscillator work even if there is a
slight change in the circuit parameters.
5. Define feedback. What are the types of it?

6. State the conditions for oscillations.
7. Explain the advantages and disadvantages of negative feedback. State the basic proprerties.
8. A phase shift oscillator has R=220Kohms, C=500pF. Calculate the frequency of oscillation.
9. Draw the block diagram and circuit diagram for Voltage series feedback amplifier.
10. Draw & explain RC phase shift oscillator.
11. Draw block diagram of voltage series -ve feedback amplifier and explain effect on i/p
impedance, o/p impedance and gain.
12. Explain the working of Wein bridge oscillator. Derive the expression for sustained oscillations.

1. An oscillator converts ……………..
1. dc. power into d.c. power
2. dc. power into a.c. power
3. mechanical power into a.c. power
4. none of the above
2. An oscillator employs ……………… feedback
1. Positive
2. Negative
3. Neither positive nor negative
4. Data insufficient
3. The output waveform of a stable oscillator have
1. Constant frequency at low amplitude only
2. Constant frequency at high amplitude only
3. Variable frequency
4. Constant frequency
Answer: d
Easwara M 91
4. The output of oscillator will not depend upon
1. Feedback
2. Amplifier
3. Both feedback and amplifier
4. Input voltage
Answer: d
5. In a phase shift oscillator, the frequency determining elements are …………
1. L and C
2. R, L and C
3. R and C
4. None of the above
6. A Wien bridge oscillator uses ……………. feedback
1. Only positive
2. Only negative
3. Both positive and negative
4. None of the above
Answer : 3
7. In a Wien-bridge oscillator, if the resistances in the positive feedback circuit are decreased, the
frequency……….
1. Remains the same
2. Decreases
3. Increases
4. Insufficient data
Answer : 3
8. An oscillator differs from an amplifier because it ………
1. Has more gain
2. Requires no input signal
3. Requires no d.c. supply
4. Always has the same input
9. One condition for oscillation is ………….
1. A phase shift around the feedback loop of 180o
2. A gain around the feedback loop of one-third
3. A phase shift around the feedback loop of 0o
4. A gain around the feedback loop of less than 1
Answer : 3
10. A second condition for oscillations is ……………….
1. A gain of 1 around the feedback loop
2. No gain around the feedback loop
3. The attention of the feedback circuit must be one-third
4. The feedback circuit must be capacitive
Answer : 1
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Module – 5 Digital Electronics Fundamentals

5.1 Introduction
5.2 Difference between analog and digital
signals
5.3 Number System - Binary, Hexadecimal,
Conversion - Decimal to binary,
Hexadecimal to decimal and vice-versa
5.4 Boolean algebra
5.5 Basic and Universal Gates
5.6 Half and Full adder
5.7 Multiplexer
5.8 Decoder
5.9 SR and JK flip-flops
5.10 Shift register
5.11 Three bit Ripple Counter
5.12 Basic Communication system
5.13 Principle of operations of Mobile phone
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5.1 Introduction
 Digital Electronics is a branch of Electronics which deals with digital circuits and digital systems
that exists in only two possible states. These states described with only two discrete values (0, 1)
which are used to represent numbers, symbols, alphabetic and other type of information in Digital
Electronics.
 Digital circuits are the circuits which are basically transistors to create logic gates operate at high
speed. It is less susceptible to noise than analog circuits. It is also easier to perform error detection
and correction with digital signals.
 Digital systems contain digital circuits used to process digital information using a binary system,
where data can assume with only two possible values: (0, 1). Ex: calculators, computers, etc.
Representation of Binary values: (0, 1)

 Ideally: “no voltage (= 0 V)” represents a logic 0 and “full voltage (= 5V)” represents a logic 1.
 Realistically: “low voltage” (e.g., <1v) represents a 0 and “high voltage” (e.g., > 4v) represents a 1.
 These discrete values can be achieved by using transistor switches.
Type of logic: (i) positive logic and (ii) negative logic is shown in Fig. 5.1
Fig. 5.1 Type of logic: (a) positive logic (b) negative logic
 HIGH voltage = 5V → represents logic 1.  HIGH voltage = 5V → represents logic 0.

(HIGH = logic 1 = Closed switch = ON state)
 LOW voltage = 0V → represents logic 0.  LOW voltage = 0V → represents logic 1.

(LOW = logic 0 = Open switch = OFF state)
Digital Waveforms: Digital waveforms as typical voltage ranges for positive logic 1 and logic 0 are
shown in fig.5.2.
Fig. 5.2 Digital Waveforms as typical acceptable voltage ranges
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 In digital electronics the signals are formed with only two voltage values: logic 1 (HIGH) and
logic 0 (LOW) and it is called binary digital signal. Therefore, the information contained in the
digital signal is represented by the numbers 1and 0. In digital systems the state 1 corresponds to a
voltage range from 3V to 5V while the state 0 corresponds to a voltage range from a 0 to 1 volt as
shown in fig. 5.2. A logic gate within the ‘undefined logic level’ will produce an unpredictable
output level.
 If noise in the circuit is high enough it can push logic 0 up or drop logic 1 down into the undefined
logic level. The magnitude of the voltage required to reach this level is the noise margin. A
quantitative measure of noise immunity is called noise margin.
 Noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise voltages on its inputs.
 High Level Noise Margin, VNH = VOH (min) - VIH (min)
 Low Level Noise Margin, VNL = VIL (max) - VOL (max)
5.2 Analog verses Digital signals

Digital systems cover most areas of our life: still pictures, digital video, digital audio, telephone,
traffic lights, animation, etc. Analog verses Digital is discussed below.
Parameter Analog Digital

Analog signal is a continuous signal which Digital signals are discrete time signals
Signal
has infinite number of values in a range. have limited values (0,1) in a range.
Denoted by sine waves Denoted by square waves
Waves
Representa Uses continuous range of values to Uses discrete or discontinuous values to

tion represent information. represent information
Human voice in air, analog electronic Computers, CDs, DVDs, and other digital
Example
devices. electronic devices.
Analog technology records waveforms as Samples analog waveforms into a limited

Technology
they are. set of numbers and records them.
Data Subjected to deterioration by noise during Can be noise-immune without

transmission transmission. deterioration during transmission.
Response to More likely to get affected reducing Less affected since noise response are
Noise accuracy analog in nature
Flexibility Analog hardware is not flexible. Digital hardware is flexible in

implementation.
Can be used in analog devices only. Best Best suited for Computing and digital
Uses
suited for audio and video transmission. electronics.
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Benefits of Digital over Analog
• Reproducibility
• Not effected by noise means quality
• Ease of design
• Data protection
• Programmable
• Speed
• Economy
5.3 Number System

Set of values used to represent different quantities is known as Number System.
Where b = number system base or radix

dn = nth digit
n = number (can start from negative number if the number has a fraction part).
N+1 = the number of digits
The Natural Numbers: The natural numbers are 1, 2, 3, 4, 5, etc. There are infinitely many natural
numbers. The whole numbers are the natural numbers together with 0.
The Integers: The integers are the set of real numbers consisting of the natural numbers, their additive,
inverses and zero. {..., -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5...}
Some important number systems are as follows.
1. Decimal number system - has a base of 10 with each position weighted by a factor of 10.
2. Octal number system - has a base of 8 with each position weighted by a factor of 8.
3. Binary number system - has a base of 2 with each position weight by a factor of 2.
4. Hexadecimal number system - has a base of 16 with each position weighted by a factor of 16.
The decimal number system is used in general communication. It can be used to represent both the
integer as well as floating point values. The floating point values are generally represented in this system
by using a period called decimal point. The decimal point is used to separate the integer part and the
fraction part of the given real number. However, the computers use binary number system; they can
store and process each type of data in terms of 0s and 1s only. Octal and hexadecimal number systems
are used to represent computer data. The details of these number systems are given in the table 1.
Table 1 Number systems

Number Radix
Digits / symbols Example: with power notation
System / base
1. Decimal 10 0,1,2,3,4,5,6,7,8,9 (338.6)10 3x102+3x101+8x100. 6x10-1
2. Octal 8 0,1,2,3,4,5,6,7 (336.2)8 3x82+3x81+6x80. 2x8-1
3. Binary 2 0,1 (110.10)2 1x22+1x21+0x20. 1x2-1+0x2-2
4. Hexadecimal 16 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F (4AB.2)16 4x162+10x161+11x160. 2x16-1
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5.3.1 Number conversions: Decimal to other number system (NS)

When all the different number conversions from one to another come at one sequence, certainly learners
will get confused. To avoid this and to keep remember easily, we classify all conversions into mainly
three groups. With simple rules and examples these are illustrated below.
Binary ( )2 Octal ( )8 Hexadecimal ( )16

Rules
Integer part Fraction part
Successive Division: Successive Multiplication:

1. Divde Decimal integer number by the radix of 1. Multiply Decimal fraction number by the
NS to be converted. Radix of the NS to be converted.
2. Save remainder ( read remainders from bottom 2. Save the whole number (integer) of the result
to top). (read remainders from top to bottom).
3.Repeat steps 1 and 2 until quotient becomes zero 3. Repeat steps 1 and 2 for the fractional part of
step 2 until to the desired position.
Example: 1 Decimal to Binary (25.625)10 ( ? )2 ( 11001.101)2
25 ÷ 2 12 (R→ 1) 0.625 x 2 1.25 1
12 ÷ 2 6 (R→ 0) (25)10 (11001)2 0.25 x 2 0.5 0 (0.625)10 = (0.101)2
6÷2 3 (R→ 0) 0.5 x2 1.0 1
3÷2 1 (R→ 1) (save remainder (R) backward) (save whole number forward)
1÷2 0 (quotient becomes zero)
Example: 2 Decimal to Hexadecimal (675.15)10 ( ? )16 (257.266)16

675÷ 16 42 (R→ 3) 0.15 x 16 2.40 2
42÷ 16 02 (R→ 10) (675)10 (2A3)16 0.40 x 16 6.40 6 (0.15)10 = (0.266)16
Note: (10)10 = (A)16 (save remainder (R) backward) 0.40 x 16 6.40 6
5.3.2 Number conversion: Other number systems (NS) to Decimal
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Rules:
1. Obtain the power sequence (positional weights) of the NS to be determined.

2. Place the number in position : integers – left of the radix point ( + ve powers)
fraction – right of the radix point ( - ve powers)
3. Multiply the number with positional weights and add, to get decimal number.
Example: Binary to Decimal Example: Hexadecimal to Decimal

Steps (1011.01)2 (?)10 (11. 25)10 (A2B.1D)16 (?)10 (2603.11252)10
power 23 22 21 20 . 2-1 2-2 163 162 161 160 . 16-1 16-2
weight 8 4 2 1 0.5 0.25 4096 256 16 1 0.0625 0.0039
number 1 0 1 1 . 0 1 0 10 2 11 . 1 13
(8 + 0 + 2 + 1) . (0 + 0. 25) (0 + 2560 + 32 + 11) . (0.0625 + 0.052)
value
= (11. 25)10 = (2603.11252)10
5.3.3 Number conversion: Grouping Binary bits

In this case, Decimal NS will not come into picture. However, either Octal or Hexadecimal NS is
converted into Binary NS. Then “grouping” of bits is conducted.
( )8 ( )2 ( ) 16
According to the conversion type, the grouped bits are replaced by Binary Coded Octal (BCO) or Binary
Coded Hexadecimal (BCH) as tabulated in the table 2 (see page 7).
Octal Binary ( )8 ( )2 Hexadecimal Binary ( )16 ( )2
 Replace each octal digit by its 3-bit BCO  Replace each hexadecimal digit by its 4-bit
equivalent (see table 2) both for integer and BCO equivalent (see table 2) both for integer
fractional part. and fractional part.
Example:
(1073.32)8 (?)2 ( 001000111011.011010 )2 (A2B.1D)16 (?)2 ( 001000111011.011010 )2

1 0 7 3 . 3 2 [given octal number]
A 2 B . 1 D [given hexadecimal]
001 000 111 011 . 011 010 [from BCO]
1010 0010 1011 . 0001 1101 [from BCH]
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Table 2. Binary Coded Decimal (BCD), Binary Coded Octal (BCO) and Binary Coded Hexadecimal (BCH)
Decimal Binary Coded Octal Binary Coded Hexadecimal Binary Coded Hexa-
numbers Decimal (BCD) numbers Octal (BCO) Numbers decimal (BCH)
0 00 0 0 0 0 0 0 0 00 0 0
1 00 0 1 1 0 0 1 1 00 0 1
2 00 1 0 2 0 1 0 2 00 1 0
3 00 1 1 3 0 1 1 3 00 1 1
4 01 0 0 4 1 0 0 4 01 0 0
5 01 0 1 5 1 0 1 5 01 0 1
6 01 1 0 6 1 1 0 6 01 1 0
7 01 1 1 7 1 1 1 7 01 1 1
8 10 0 0 10 0 0 1 0 0 0 8 10 0 0
9 10 0 1 11 0 0 1 0 0 1 9 10 0 1
10 0 0 0 1 00 0 0 12 0 0 1 0 1 0 A 10 1 0
11 0 0 0 1 00 0 1 13 0 0 1 0 1 1 B 10 1 1
12 0 0 0 1 00 1 0 14 0 0 1 1 0 0 C 11 0 0
13 0 0 0 1 00 1 1 15 0 0 1 1 0 1 D 11 0 1
14 0 0 0 1 01 0 0 16 0 0 1 1 1 0 E 11 1 0
15 0 0 0 1 01 0 1 17 0 0 1 1 1 1 F 11 1 1
16 0 0 0 1 01 1 0 20 0 1 0 0 0 0 10 0 0 0 1 00 0 0
Binary Octal ( )2 ( )8 Binary Hexadecimal ( )2 ( )16

 Group into set of 3-bits from radix point  Group into set of 4-bits from radix point
- towards left for integer part - towards left for integer part
- towards right for fractional part - towards right for fractional part
 Convert each group to its equivalent octal  Convert each group to its equivalent
using BCO. See table 1 hexadecimal using BCH. See table 1
 Add zeros to complete last groups as needed.  Add zeros to complete last groups as needed.
Example:
(1000111011.01101)2 (?)2 (1073.32)8 (1000111011.01101)2 (?)2 (23B.68)16
1000111011.01101 [given binary number] 1000111011.01101 [given binary number]
001, 000, 111, 011 . 011, 010 [grouping 3-bits] 0010, 0011, 1011 . 0110, 1000 [grouping 4-bits]
1 0 7 3 . 3 2 [equivalent octal] 2 3 B . 6 8 [equivalent hexadecimal]
Octal Hexadecimal ( )8 ( )16 Hexadecimal Octal ( )16 ( )8
 Replace each octal digit by its 3-bit BCO  Replace each hexadecimal digit by its 4-bit
equivalent (as in the table 1) both for integer BCH equivalent (as in the table 1) both for
and fractional part. integer and fractional part.
 Group into set of 4-bits from radix point  Group into set of 3-bits from radix point
- towards left for integer part - towards left for integer part
- towards right for fractional part - towards right for fractional part
 Convert each group to its equivalent  Convert each group to its equivalent octal
hexadecimal using BCH. See table 2 using BCO. See table 2
Easwara M 99
Example:
(2 3 5.6 4)8 (BCO) (?)16 (9D.D)16 (2 E 5.6 B)16 (BCH) (?)8 ( 1345.326)8
2 3 5 . 6 4 [given octal number] 2 E 5 . 6 B [given hexadecimal]
010 011 101 . 110 100 [3-bit BCO] 0010 1110 0101 . 0110 1011 [3-bit BCO]
0, 1001, 1101 . 1101, 0000 [grouping4-bits] 001, 011, 100, 101 . 011, 010, 110 [grouping4-bits]
9 D . D 0 [equivalent hexadecimal] 1 3 4 5 . 3 2 6 [equivalent octal]
5.4 Boolean algebra

Boolean algebra was invented by George Boole in 1854. After 70 years (in 1924) Claude Shannon, who
recognized and worked out the relevance of Boole’s symbolic logic for the field of engineering. Boolean
algebra is a mathematical system for the manipulation of variables that can be used to analyze and
simplify the digital (logic) circuits whose outcome would be either 0 or1, since it uses only the binary
numbers 0 and 1. With regard to the digital logic, a set of rules are used to describe circuits whose state
can either 1 (ON) or 0 be (OFF).
 Boolean Constants - these are 0 (false) and 1 (true).

 Boolean Variables - variables used to represent input-output of digital circuits that can only take the
vales 0 or 1. Example: A, B, X, Y etc.
 Boolean Functions - each of the logic functions (such as AND, OR and NOT) are represented by
symbols.
Consequently, the “Laws” of Boolean algebra often differ from the “Laws” of real-number algebra. A
number of rules can be derived from AND, OR and NOT relations called as basic Boolean postulates.
Boolean postulates and laws are defined in the table 2 and table 3, respectively.
Table 2: Boolean Postulates
Postulate Relation
1 0·0=0
NOTE:
2 1+1=1 Every law has two forms: AND form and OR form as
shown in the following table 2. This is known as duality.
3 0+0=0
These are obtained by changing every AND (·) to OR
4 1·1=1 (+), every OR (+) to AND (·) and all 1's to 0's and vice-
versa. It is conventional to write A·B is as AB by
5 1·0=0 or 0 · 1 = 0 dropping AND (·) symbol.
6 1 + 0 = 1 or 0 + 1 = 1
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Table 3: Boolean Laws
Boolean Laws AND form OR form
Commutative AB=BA A+B=B+A

Associative A (B C) = (A B) C A + (B + C) = (A + B) + C
Identity A⋅1=A A+0=A
Distributive A (B + C) = A B + A C A + B C = (A + B) (A + C))
one/zero A⋅0=0 A+1=1
Idempotency AA=A A+A=A
Inverse A· =0 A+ =1
De Morgan's law = + = ·
Double negation
5.9 De-Morgan’s theorem

De-Morgan's theorem is one of the Boolean law which is useful in the implementation of the basic gate
operations with alternative gates NAND and NOR, which are readily available in IC form.
The two De-Morgan's laws can be implemented in Boolean algebra as in the following steps:
(1) If (+) is there then replace it with (·) and if (·) is there then replace it with (+).
(2) Compliment of each of the term is to be found.
De-Morgan’s theorem – 1:
Statement: The compliment of the product of variables is equal to the sum of the compliment of
each variable.
AND+NOT = NAND is equivalent to Bubbled OR
Proof:
A B A·B A B
0 0 0·0 1 0 0 1 1 1
0 1 0·1 1 0 1 1 0 1
↔
1 0 1·0 1 1 0 0 1 1
1 1 1·1 0 1 1 0 0 0
From the above truth tables LHS is equal to RHS, hence it is proved.
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De-Morgan’s theorem – 2:
Statement: The compliment of the sum of variables is equal to the product of the compliment of
each variable.
OR+NOT = NOR is equivalent to Bubbled AND
Proof:
A B A+B A B
0 0 0+0 1 0 0 1 1 1
0 1 0+1 1 ↔ 0 1 1 0 1
1 0 1 +0 1 1 0 0 1 1
1 1 1+1 0 1 1 0 0 0
From the above truth tables LHS is equal to RHS, hence it is proved.
5.5 Basic Logic Gates

Logic gate is an electronic circuit having one or more than one input and only one output. Logic gates
require a power supply. The inputs of any gate are driven by voltage levels 0 V and 5 V representing
logic 0 and logic 1, respectively. Boolean functions may be practically implemented by using electronic
gates. The output of a gate provides two nominal values of voltages either 0 V or 5 V representing logic
0 or logic 1, respectively. Truth tables are used to show the function of logic gate with input output
relationship. The gates are AND, OR, NOT (basic gates), NAND, NOR, EXOR and EXNOR (derived
gates). Digital systems (FFs, ALU etc) are said to be constructed by using these logic gates.
Table 4 Traditional & IEEE symbol, Boolean Expression and Truth Table of Logic Gates
Traditional IEEE Boolean Truth Table

Logic Gate
symbol symbol Expression Input / Output
A Y=A
1. NOT 0 1
Y=A
1 0
-Only ONE input and one output - Output is inversion of input
A B Y
2. OR Y= A + B 0 0 0
0 1 1
 Two or more inputs (Logic addition) and one output 1 0 1
 Output is logic LOW if both inputs are LOW, Otherwise output is logic HIGH 1 1 1
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A B Y
3. AND Y= A · B
0 0 0
0 1 0
 Two or more inputs (Logic multiplication) and one output 1 0 0
 Output is logic HIGH if both inputs are HIGH, Otherwise output is logic LOW 1 1 1
A B Y
4. NOR
Y= A + B 0 0 1
0 1 0
 Two or more inputs (Logic multiplication + inversion) and one output 1 0 0
 Output is logic HIGH if both inputs are LOW, Otherwise output is logic HIGH 1 1 0
A B Y
5. NAND
Y= A · B 0 0 1
0 1 1
 Two or more inputs (Logic multiplication + inversion) and one output 1 0 1
Output is logic HIGH if both inputs are LOW, Otherwise output is logic HIGH 1 1 0
A B Y
6. EX-OR
Y= 0 0 0
Exclusive OR
0 1 1
 Output is logic HIGH if both inputs are different 1 0 1
 Otherwise, output is logic LOW if both inputs are same 1 1 0
A B Y
7. EX-NOR
Exclusive NOR Y= 0 0 1
0 1 0
 Output is logic HIGH if both inputs are same 1 0 0
 Otherwise, output is logic LOW if both inputs are different 1 1 1
5.5.1 Universal Logic Gates
The NAND and NOR gates are universal gates. Operations of all logic gates can be performed using
only these gates; hence they called as universal gates. In practice, NAND and NOR gates are economical
and easier to fabricate and they are the basic gates used in all IC digital logic families.
Implementation of logic gates: using only NOR Gates
It can be proved that any Boolean function can be implemented and realized (the operations of all logic
gates can be verified) using only NOR gates. It is illustrated in the table 4.
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Table 5: Implementation of logic gates using only NOR Gates
Boolean
Desired gate Implementation using only NOR gates
expression
1. NOT
Y=A
NOT gate can be implemented by tying the two inputs of the NOR gate together.
2. OR Y= A + B
OR gate can be implemented by simply one NOR gate followed by a second whose inputs are joined.
3. AND Y= A · B
AND gate is implemented by inverting the inputs to a 3rd NOR gate.
4. NAND
Y= A · B
NAND gate is implemented by using an AND gate (previous discussion) in series with a NOR gate.
5. XOR Y=
XOR gate is implemented by connecting the output of 3 NOR gates (connected as an AND gate) and the
output of a NOR gate to the respective inputs of a NOR gate. That is Y= (A AND B) NOR (A NOR B).
6. XNOR
Y=
XNOR gate can be constructed from four NOR gates implementing the expression
Y = (A NOR (A NOR B)) NOR (B NOR (A NOR B)).
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Implementation of logic gates: Using only NAND Gates
It can be proved that any Boolean function can be implemented and realized (the operations of all logic
gates can be verified) using only NAND gates. It is illustrated in the table 6.
Table 6: Implementation of logic gates using only NAND Gates
Boolean
Desired gate Implementation using only NAND gates
expression
1. NOT Y=A
NOT gate can be implemented by tying the two inputs of the NAND gate together.
2. OR Y= A + B
OR gate is implemented by inverting the inputs to a 3rd NAND gate.
3. AND Y= A · B
AND gate can be implemented by simply one NAND gate followed by a second whose inputs are joined
together.
4.NOR
Y= A + B
NOR gate is implemented by using an OR gate (previous discussion) in series with a NAND gate.
5. XOR Y=
XOR gate is implemented similarly to OR gate, except with an additional NAND gate inserted such that
if both inputs are high, the inputs to the final NAND gate will also be high, and the output will be low.
6. XNOR
Y=
An XNOR gate is simply an XOR gate with an inverted output.
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5.5.2 Simplification of Boolean Expressions
Boolean Expressions represent Complex combinational logic circuits. The simpler the Boolean
expression, the smaller the circuit that will result. Reduction of a logic circuit means the same logic
function with fewer gates and/or inputs. Simpler circuits are cheaper to build, consume less power, and
run faster than complex circuits. With this in mind, it is desired always to reduce Boolean functions to
their simplest form.
Steps to reduce a logic circuit
 Write the Boolean Equation/expression for the logic function. Apply as appropriate rules and laws as
possible in order to decrease the number of terms and variables in the expression.
1. Solve Bracketed quantities - Inside any parentheses look for more parentheses
2. NOTs, ANDs, ORs
3. If an expression has a bar over it, perform the operations inside the expression first and then invert
the result
 Draw the logic diagram for the reduced Boolean Expression using basic logic gates.
Example 1: A B C + A C+AB + BC
Y=ABC+A C+AB + BC
= A C [B + ] + A B + BC B+ =1
= A C [1] + A B + BC
= C [A + B] + A B A + B = A +B
= C [A + B] + A B
=AC+BC + AB
= A [C + B] + B C C+ B=C+B
= A [C + B] + B C
Y=AC+AB+BC
Example 2: ( )( )
Y= ( )( ) =
= [ + + ]
= + C+
= [1+ ]+ 1+ =1
= +
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= [1 + ]
Y=
Example 3: A + ( )[ + B + ] (A + )
Y=A+ [A +AB+A + +B + ] A = 0 and B =0
=A+ [AB+A + + ]
=A+AB + +A C + C B = 0 and C = 0
=A+ A + B = A +B
Y=A+
5.6 Arithmetic Circuits: Half and Full adder

An arithmetic circuit is a digital logic circuit that performs addition of numbers. In computers and other
types of processors, adders are used to calculate addresses, addition and multiplication operations and
table indices in the ALU.
Adders are classified into two types:

(1) Half Adder and
(2) Full Adder
5.6.1. Half Adder

The half adder circuit is a digital adder circuit capable of adding only two binary bits A and B. It has two
inputs: A and B and adds these two input bits at a time and produce a carry(C) and sum(S) This process
follows the binary addition rules. It can be constructed using one AND and one XOR gate.
 Its block diagram, logic circuit and truth table is shown in the fig. 5.3.
Inputs Outputs
A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
Fig. 5.3 Block diagram, logic circuit and truth table of an Half Adder 1 1 0 1
Truth table gives input-output relationship, from which we observe that,

(i) The output Sum (S) follows XOR operation between A and B inputs
S= = C = A· B
(ii) The output Carry (C) follows AND operation between A and B inputs
=
Hence, half adder circuit is a combination of XOR and AND operations. Implementation of Half Adder
circuit using basic gates is shown in the fig.5.4.
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Limitation: Half Adder circuit cannot receive
an input carry bit.
Fig.5.4 Implementation of half adder circuit using basic gates
5.6.2. Full Adder

The full-adder circuit is a digital adder circuit capable of adding three bit binary numbers (2 bits: A and
B and one bit carry in Cin). This circuit consists of three inputs (A, B and Cin) and two outputs (S and
Cout). It has three inputs (A, B and Cin ) and adds these input bits at a time and produce a carry(C) and
sum(S) This process follows the binary addition rules. It can be constructed using two half adders
where it consists 2 ANDs, 2 XORs, and 1 OR. Block diagram, logic circuit and truth table is shown in
the fig. 5.5.
Fig. 5.5 (a) Block diagram (b) Circuit diagram of Full Adder
From the truth table it is observes that,

Inputs Outputs
A B Cin Sum (S) Carry (Cout) (i) Sum (S) output is equal to 1, when only one input is
equal to1 or when all three inputs are equal to1. For
0 0 0 0 0
this Boolean expression can be written as
0 0 1 1 0
0 1 0 1 0 S  Cin AB  Cin AB  CinAB  CinAB
0 1 1 0 1  Cin( AB  AB) Cin (AB  AB)
1 0 0 1 0  Cin( A  B)  Cin (A  B)
S  Cin  A  B
1 0 1 0 1
1 1 0 0 1 (ii) Output has a carry1, if two or three inputs are equal
to1. For this Boolean expression can be written as
1 1 1 1 1
Cout  AB  Cin( AB  AB)  AB  Cin(A  B)
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5.7 Multiplexer
Multiplexer is a device that has multiple inputs and a single line output. The data select lines determine
which input is connected to the output. It is also called a data selector shown in the fig.5.6 and fig. 5.7.
Fig. 5.6 Block diagram of Multiplexer
Fig. 5.7 Logic diagram of 4:1 Multiplexer
Multiplexers are capable of handling both analog and digital applications. In analog applications,
multiplexers are made up of relays and transistor switches, whereas in digital applications, the
multiplexers are built from standard logic gates.
Multiplexer Types
Multiplexers are classified into four types:
 2-1 multiplexer ( 1select line)
 4-1 multiplexer (2 select lines)
 8-1 multiplexer(3 select lines)
 16-1 multiplexer (4 select lines)
Applications of Multiplexers
1. Communication System - increases the transmission of data (audio, video) from different
channels through single lines or cables.
2. Computer Memory - to maintain a huge amount of memory in the computers, and also to reduce
the number of copper lines required to connect the memory to other parts of the computer.
3. Telephone Network - multiple audio signals are integrated on a single line of transmission with the
help of a multiplexer.
4. Transmission from the Computer System of a Satellite- to transmit the data signals from the
computer system of a spacecraft or a satellite to the ground system by using a GSM satellite.
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5.8 Decoder
A decoder is a combinational logic circuit that takes multiple inputs and gives multiple outputs. A
decoder circuit takes binary data of ‘n’ inputs into ‘2n’ unique output. In addition to input pins, it has an
enable pin. This enable pin makes the circuit active / inactive. It is shown in the fig.5.8.
Example: 2-to-4 line binary decoder:

It consists of an array of four AND gates. Thumb rule with decoders is that, if the number of inputs is
considered as n (here n = 2) then the number of output will always be equal to 2n (22 = 4). The Decoder
has 2 input lines and 4 output lines; hence this type of Decoder is called as 2:4 Decoders.
2:4 decoder has two inputs A1 and A0 and four outputs Y3, Y2, Y1 & Y0. Its block diagram and truth
table is shown in the fig. One of these four outputs will be logic ‘1’ for each combination of inputs
when enable, E is logic ‘1’.
Fig.5.8 Decoder block diagram and truth table
From truth table, we can write the Boolean functions for each output as
Each output is having one product term. We can implement these four product terms by using four
AND gates having three inputs (A1, A0 and E) each and two NOTs. The circuit diagram of 2 to 4
decoder is shown in the fig.5.9.
Fig.5.9 circuit diagram of 2 : 4 decoder
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Applications of Decoder
 In analog to digital conversion in analog decoders.

 Data multiplexing,
 Memory address decoding,
 7 segment display.
5.9 SR Flip-Flop and JK Flip Flop
5.9.1 SR flip-flop (with clock)

SR flip-flop is a one-bit memory bi-stable device that has two inputs, one is labelled S, will SET the
device (meaning the output Q = 1), and other is labelled R, will RESET the device (meaning the output
Q = 0). Then the SR description stands for “Set-Reset”. FFs are made from latches and FFs respond only
on specific times. Logic diagram, truth table and timing diagram is shown in the fig.5.10.
Fig.5.10 (c) Timing diagram
Working: The function of SR flip flop is described in the truth table and analyzed as in the timing
diagram. The table shows four useful modes of operation.
Whenever the clock C is LOW, the inputs S and R are never affect the output. The clock has to be HIGH
for the inputs to get active.
1. Hold state: When S = R = 0 and clock = 1; output of SR FF, Q = 0; so output Q remains as
previous output , therefore, FF is in the hold mode. In the hold mode, the data inputs have no effect
on the outputs. The outputs “hold” the last data present.
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2. Reset state: When S = 0, R =1 and clock = 1; output of SR FF, Q = 0; which RESETs the flip flop.
3. Set State: When S =1, R = 0 and clock = 1; output of SR FF, Q = 1; which SETs the flip flop.
4. Invalid state: When S =1, R = 1 and clock = 1; output of SR FF, Q = = 1, so it is invalid.
5.9.2. JK flip-flop
To overcome the invalid state of SR flip flop an extra feedback from the output to input is given, then
such FF is called JK flip flop. The logic symbol, circuit, truth table and timing diagram of the JK flip-
flop is illustrated in Fig. 5.11.
(a) Logic Symbol (b) circuit using NAND gates
(c) Truth Table
Fig.5.11 : JK flip-flop. (d)Timing diagram

The inputs J and K are the data inputs. JK Flip Flop is same as RS flip-flop with the
same SET and RESET input. The difference is that the JK Flip Flop does not have the invalid states of
the RS FF (when S = R = 1).
This table shows four useful modes of operation.
1. Hold state: When J = K = 0 and clk = 1; output remains in previous state, so the flip-flop is in
the hold mode. In the hold mode, the data inputs have no effect on the outputs. The outputs
“hold” the last data present.
2. Reset state: When J = 0 K =1 and clk = 1; output of JK FF, Q = 0; which RESETs the flip flop.
3. Set state: When J = 1 K = 0 and clk = 1; output of JK FF, Q = 1; which SETs the flip flop.
4. Toggle state: When J = 1 K = 1 and clk = 1; the output Q, turns off-on. This off-on action is
called toggling. Each clock pulse toggles the outputs to switch to their opposite states.
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Race around condition in JK flip-flop
Toggle: switching of state either from 0 to 1 or 1 to 0, which makes the output of the flip-flop unstable
or uncertain.
Within a single clock period if J = K = 1 and clock = 1, output changes its state (toggle) more than one
time. This is called race around condition. This problem can be avoided by introduced the concept of
Master Slave JK flip flop.
5.10 Shift register

Register: A set of N flip-flops is called register. Each flip-flop stores one bit (1 or 0).
Two basic functions: data storage and data movement.
Shift Register: is a register can be used for the storage or the transfer of binary data. This sequential
circuit receives the data from its inputs and then “shifts” it to its output for every clock cycle, hence the
name shift register. Shift Register is made of the number of individual Flip Flops. For example, an 4-bit
wide shift register is constructed from four individual FFs, as shown in the fig.5.12. They used inside
calculators or computers to store data. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:
1. Serial-in to Parallel-out (SIPO) - the
register is loaded with serial data, one bit at
a time, with the stored data being available
at the output in parallel form.
2. Serial-in to Serial-out (SISO) - the data
is shifted serially “IN” and “OUT” of the
register, one bit at a time in either a left or
right direction under clock control.
3. Parallel-in to Serial-out (PISO) - the
parallel data is loaded into the register
simultaneously and is shifted out of the
register serially one bit at a time under
clock control.
4. Parallel-in to Parallel-out (PIPO) - the
parallel data is loaded simultaneously into
the register, and transferred together to their
respective outputs by the same clock pulse. Fig.5.12 Four-bit wide shift register
5.10.1 4-bit Serial-in to Serial-out (SISO)

A basic four-bit SISO shift register can be constructed using four D flip-flops, as shown in fig.5.13. The
operation of circuit is as follows. Assuming for the 4-bit shift register, we need to shift the data 1101.
Fig.5.13 Four-bit Serial-in to Serial-out shift register
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Operational Steps:
1. The register is first cleared, forcing all four outputs to zero.
2. The input data (1101) is then applied sequentially to the D input of the first flip-flop on the left
(FFA).
Clock cycle FF0 FF1 FF2 FF3
First 1 0 0 0
Second 0 1 0 0
Third 1 0 1 0
Fourth 1 1 0 1
3. During each clock pulse, one bit is transmitted from left to right.
4. During the first clock cycle as we apply the data (1101) serially, similarly for four clock cycles the
outputs of the each flip flop is displayed in the above functional table.
5.11 Three bit Ripple Counter
A ripple counter is an asynchronous counter where only the first FF is clocked by an external clock. All
the subsequent FFs are clocked by the output of the preceding FF. Asynchronous counters are also
called ripple-counters, because of the way the clock pulse ripples it way through the flip-flops. Each
stage acts as a divide-by-2 counter on the previous stage's signal. The Q out of each stage acts as both an
output bit and as the clock signal for the next stage. It can chain as many ripple counters together as
need.
A three bit ripple counter shown in the fig.5.14, will count 23 = 8 numbers [count (0-7) → minimum 0
(000) and maximum 7 (111)] and an n-bit ripple counter will count 2n numbers.
Fig.5.14 Three bit Ripple Counter using T- FF
Count Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 1 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Fig.5.15 Function table and timing diagram for 3- bit Ripple Counter
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The clock inputs of the three FFs are connected in cascade. The T input of each FF is connected to logic
1, which means that the state of the FF will toggle at each edge of its clock. FFA is connected to
the clock line and other two FFB and FFC have driven by the Q output of the preceding FF. Therefore,
they toggle their state whenever the preceding FF changes its state from Q = 1 to Q = 0. So as to take the
output from Q0, Q1 and Q2. Then we get the count sequence with different counter states as mention in
the fig.5.15.
5.12 Basic Communication system

Communication is the process of establishing connection or link between two points for information
exchange. The block diagram of basic communication system is shown in the fig.5.16.
Information source: The various massages are in the form of words, picture, code, symbol, sound
signal, video etc. However, out of these one message is selected & conveyed or communicated. It is
used to produce required message which has to be transmitted.
Transducer: is a device which converts one form of signal to another form. The message produced by
source is not electrical; hence an input transducer is used to convert to an electrical signal. Ex: μ-phone.
Transmitter: The main function of transmitter is to process the electric signal from different aspects.
Modulation, amplification and filtering of massage are done to transmit signal over long distance.
Channel: This medium is either wired (twisted pair, co-axial, Optical Fiber Cable (OFC), etc) or
wireless (free space, radio communication, etc), through which the message travel from the transmitter
to receiver.
Noise: It is an unwanted signal which disturbs the message. They can interface with signal at any point
in a communication system.
Receiver: The main function of receiver is to reproduce the massage signal in electrical form. It
performs the functions like de-modulation, filtering, amplification, etc. Ex: loud- speaker
Fig.5.16 Basic Communication system
5.12 Principle of operations of Mobile phone
Radio Waves Cell phones use radio waves to communicate. Radio waves transport
digitized voice or data in the form of oscillating electric and magnetic
fields, called the electromagnetic field (EMF). The rate of oscillation is
called frequency. Radio waves carry the information and travel in air at
the speed of light.
Easwara M 115
Cell phones transmit radio waves in all directions. The waves can be
absorbed and reflected by surrounding objects before they reach the
nearest cell tower. For example, when the phone is placed next to your
head during a call, a significant portion (over half in many cases) of the
emitted energy is absorbed into your head and body. In this event, much
of the cell phone’s EMF energy is wasted and no longer available for
communication.
Cell phones contain at least one radio antenna in order to transmit or

receive radio signals. An antenna converts an electric signal to the radio
Antenna wave (transmitter) and vice versa (receiver). Some cell phones use one
antenna as the transmitter and receiver while others, such as the iPhone 5,
have multiple transmitting or receiving antennas.
An antenna is a metallic element (such as copper) engineered to be a
specific size and shape for transmitting and receiving specific frequencies
of radio waves. While older generation cell phones have external or
extractable antennas, modern cell phones contain more compact antennas
inside the device thanks to advanced antenna technologies. It’s important
to understand that any metallic components in the device (such as the
circuit board and the metal frame for the iPhone) can interact with the
transmission antenna(s) and contribute to the pattern of the transmitted
signal.
Many modern smart phones also contain more than one type of antenna. In
addition to the cellular antenna, they may also have Wi-Fi, Bluetooth
and/or GPS antennas.
As mentioned earlier, a cell phone is a two-way wireless communication
device and needs both the inbound signal (reception) and the outbound
Connectivity signal (transmission) to work. The magnitude of the received signal from
the cell tower is called the “signal strength”, which is commonly indicated
by the “bars” on your phone. The connectivity between a cell phone and
its cellular network depends on both signals and is affected by many
factors, such as the distance between the phone and the nearest cell tower,
the number of impediments between them and the wireless technology
(e.g. GSM vs. CDMA). A poor reception (fewer bars) normally indicates a
long distance and/or much signal interruption between the cell phone and
the cell tower.
In order to conserve battery life, a cell phone will vary the strength of its
transmitted signal and use only the minimum necessary to communicate
with the nearest cell tower. When your cell phone has poor connectivity, it
transmits a stronger signal in order to connect to the tower, and as a result
your battery drains faster. That’s why good connectivity not only reduces
dropped calls, but also saves battery life.
Easwara M 116
Exercise
1. What is a logic circuit? What is the need of Boolean Algebra in digital electronics?
2. Differentiate between analog and digital signals.
3. State and prove Demorgan’s theorem for three variables.
4. Realize two input EXOR and EXNOR gates using
(i) only NOR gates (ii) only NAND gates.

5. Design full adder circuit and implement it using two half adders.
6. Design a logic circuit using basic logic gates with three inputs ABC and output Y that goes low
only when A = 1, and B and C are different.
7. Realize basic logic gates from NOR and NAND gates
8. Design a logic circuit, symbol and truth table of EXOR and EXNOR gates
9. Simplify the following Boolean Expressions:
(i) Y=XYZ+X Z+XY

(ii) Y=
(iii) Y=(A + C)(BC+B )ABC
(iv) Y=(A+ + )(A+ +C)
(v) Y = A B C +A C
(vi) Y=AB+ +A C( +C)
10. With relevant diagrams explain the working principle of Multiplexer and Decoder.
11. Draw a diagram of a clocked (synchronous) R-S latch constructed using four NAND gates.
Consider the following inputs to this latch and draw a graph of how the output Q varies as R, S
and CLK vary. Assume that the latch is initially in the RESET state (Q = 0) and there is no delay
in switching the latch.
12. Analyze the toggling method in J K FF.
Easwara M 117
1. Convert hexadecimal value 16 to decimal.

A. 2210 C. 1010
B. 1610 D. 2010
2. Convert the following decimal number to 8-bit binary. (187)10

A. 101110112 B. 110111012
C. 101111012 D. 101111002
3. Convert binary 111111110010 to hexadecimal.
A. EE216 B. FF216
C. 2FE16 D. FD216
4. Convert the following binary number to decimal. 010112

A. 11 B. 35
C. 15 D. 10
5. Convert the binary number 1001.00102 to decimal.

A. 90.125 B. 9.125
C. 125 D. 12.5
6. Adding in binary, a decimal 26 + 27 will produce a sum of:

A. 111010 B. 110110
C. 110101 D. 101011
7. Add the following hexadecimal numbers.
3C 14 3B
+25 +28 +DC
A. 60 3C 116
B. 62 3C 118
C. 61 3C 117
D. 61 3D 117
8. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.
A. A = 1, B = 1, C = 0 B. A = 0, B = 0, C = 0
C. A = 1, B = 1, C = 1 D. A = 1, B = 0, C = 1
9. Which of the following logical operations is represented by the + sign in Boolean algebra?
A. inversion B. AND
C. OR D. complementation
10. Output will be a LOW for any case when one or more inputs are zero for a(n):
A. OR gate B. NOT gate
C. AND gate D. NOR gate
Easwara M 118
11. A small circle on the output of a logic gate is used to represent the:
A. Comparator operation. B. OR operation.
C. NOT operation. D. AND operation.
12. A NOR gate with one HIGH input and one LOW input:
A. will output a HIGH B. functions as an AND
C. will not function D. will output a LOW
13. The output of a NOR gate is HIGH if ________.

A. all inputs are HIGH B. any input is HIGH
C. any input is LOW D. all inputs are LOW
14. Which of the examples below expresses the associative law of addition:
A. A + (B + C) = (A + B) + C B. A + (B + C) = A + (BC)
C. A(BC) = (AB) + C D. ABC = A + B + C
15. Convert the following SOP expression to an equivalent POS expression.
A. B.
C. D.
16. Determine the values of A, B, C, and D that make the sum term equal to zero.
A. A = 1, B = 0, C = 0, D = 0 B. A = 1, B = 0, C = 1, D = 0
C. A = 0, B = 1, C = 0, D = 0 D. A = 1, B = 0, C = 1, D = 1
17 Which of the following expressions is in the sum-of-products (SOP) form?

A. (A + B)(C + D) B. (A)B(CD)
C. AB(CD) D. AB + CD
18. How many gates would be required to implement the following Boolean expression before
simplification? XY + X(X + Z) + Y(X + Z)
A. 1 B. 2
C. 4 D. 5
19. The output of an exclusive-NOR gate is 1. Which input combination is correct?
A. A = 1, B = 0 B. A = 0, B = 1
C. A = 0, B = 0 D. none of the above
20. If A and B are the inputs of a half adder, the sum is given by
A. A AND B B. A OR B
C. A XOR B D. A EXOR B
21. If A and B are the inputs of a half adder, the carry is given by
A. A AND B B. A OR B
C. A XOR B D. A EXOR B
Easwara M 119
22. Half-adders have a major limitation in that they cannot
A. Accept a carry bit from a present stage B. Accept a carry bit from a next stage
C. Accept a carry bit from a previous stage D. None of the Mentioned
23. In parts of the processor, adders are used to calculate

A. Addresses B. Table indices
C. Increment and decrement operators D. All of the Mentioned
24. How many inputs must a full-adder have?
A. 2 B. 3
C. 4 D. 5
25. What is the hold condition of a flip-flop?
A. both S and R inputs activated B. no active S or R input
C. only S is active D. only R is active
26. How can parallel data be taken out of a shift register simultaneously?
A. Use the Q output of the first FF. B. Use the Q output of the last FF.
C. Tie all of the Q outputs together. D. Use the Q output of each FF.
27. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
A. clock pulse is LOW B. clock pulse is HIGH
C. clock pulse transitions from LOW to HIGH D. clock pulse transitions from HIGH to LOW
28. One example of the use of an S-R flip-flop is as a(n):

A. racer B. astable oscillator
C. binary storage register D. transition pulse generator
29. How is a J-K flip-flop made to toggle?
A. J = 0, K = 0 B. J = 1, K = 0
C. J = 0, K = 1 D. J = 1, K = 1
30. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is
A. constantly LOW B. constantly HIGH
C. a 20 kHz square wave D. a 10 kHz square wave
31. How many different states does a 3-bit asynchronous counter have?
A. 2 B. 4
C. 8 D. 16
32. One of the major drawbacks to the use of asynchronous counters is:
A. low-frequency applications are limited because of internal propagation delays
B. high-frequency applications are limited because of internal propagation delays
C. asynchronous counters do not have major drawbacks and are suitable for use in high- and
low-frequency counting applications
D. asynchronous counters do not have propagation delays and this limits their use in high-
frequency applications Answer: B
Easwara M 120

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CONTENTS

1. Semiconductor Diodes and Applications

2. FET and SCR

3. Operational Amplifiers and Applications

4. BJT Applications, Feedback Amplifiers and Oscillators

5. Digital Electronics Fundamentals

Course objectives: This course will enable students to:

Module-1: Semiconductor Diodes and Applications

Module-2: FET and SCR

Introduction JFET: Construction and operation,

Module-3: Operational Amplifiers and Applications

Introduction to Op-Amp, Op-Amp Input Modes, Op-Amp Parameters-CMRR, Input Offset

Module-4: BJT Applications, Feedback Amplifiers and Oscillators

Difference between analog and digital signals,

· Describe the operation of diodes, BJT, FET and Operational Amplifiers.

Proposed Activities to be carried out for 10 marks of CIE:

Question paper pattern:

Module – 1 Semiconductor Diodes and Applications

1.1 PN junction diode

1.1 PN Junction Diode

Fig.1.1 structure and circuit symbol of the PN junction Diode

[NOTE: The amount of energy required by electrons to cross the junction is

(vii) Dynamic resistance of the diode, rD = Ω

Solution: Given ΔIF = 37.6 mA,

i.e., slope of fig Ex 2 =

Diode parameters or Specifications

1.2 Diode Equivalent Circuit

1. For Unbiased Diode:

2. Forward biased Diode:

3. Revesse biased Diode:

Diode current equation is given by,

Let, VT = KT/q = (1.38 x 10-23 x 298)/1.602 x 10-19

Solution: Given Si =0.7V, Vi =10V, R1 = R2 = 1KΩ.

1.3 Zener Diode

Zener breakdown Avalanche breakdown

V I characteristics of Zener diode

Typical V I characteristics of Zener diode is shown in fig. 1.7 (a).

1.4 Zener diode as voltage regulator

Case 1) : Under No load condition

 Maximum current is IZ(max)=PZ / VZ.

Applications for Zener Diodes:

Solution: Given data

(ii) To find R(min) and R(max):

Solution: Given data

Total current I is determined by applying KVL to the input loop, Vi = IR +Vz

1.5.1 Half-wave rectifier

During negative half cycle of the secondary voltage Vm:

Advantage: Half wave rectifier is cheap, simple and easy to construct.

Solution: Given VF = 0.7V,

(i) Output voltage, Vdc = = =10.8 V

(ii) Load current, IL =

i.e., VL = Vm – VF, since, VF = 0.7V,

1.5.2 Center tapped full-wave rectifier

Fig.1. 10 Center tapped full wave rectifier circuit

1.5.3 Bridge full-wave rectifier

Fig.1. 12. (a) Bridge full wave rectifier circuit

1.5.4 Performance measures of rectifiers

1. Average current (Idc)/ DC Output Voltage (Vdc)

2. RMS Value of Load Current (Irms) / Voltage (Vrms)

3. Ripple Factor (γ)

γ= = = = (where, Irms = and Idc = )

γ= 1= = 1.21 Ripple factor of Half wave

Maximum rectifier efficiency,