1D-7

A 1 GHz CMOS Comparator with Dynamic Offset Control Technique

Xiaolei Zhu1, Sanroku Tsukamoto2, and Tadahiro Kuroda1
1
Department of Electronics and Electrical Engineering, Keio University
Phone/Fax: +81-45-566-1779, E-mail: zhuxl@ kuro.elec.keio.ac.jp
2
Fujitsu Laboratories Limited, Kawasaki, Japan

Abstract− A dynamic offset control technique that employs from the source of M3 is not absorbed by M5 but deposited by CH2 on
charge compensation by timing control is proposed for node d. Thus the charge absorption by M4 in this period contributes
comparator design in scaled CMOS technology. The analysis has to generating a compensation voltage at the initial state of the latch
been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz regeneration. Adjusting the phase between T1 and T2 controls the
comparator that occupies 25 x 65 μm2 and consumes 380 μW. amount of the compensation voltage. The value of T4 - T3 is chosen to
Circuits for offset control occupies 21% of the areas and 12% of be large enough to ensure the charge absorption by M5 affects little
the power consumption of the whole comparator chip. on the latch output since the positive feed back loop is already
generated. The phase offset is then fixed to one of these two values.
I. INTRODUCTION Analysis above shows the threshold level can be controlled by timing
For higher speed and resolutions A/D converter design in deep adjustment of OC1 and OC2. In the case of negative offset, the
sub-micron CMOS technology, it is often necessary to cancel or training operation is the same, but OC1 lags OC2.
calibrate for comparators’ offset by means of circuit or algorithmic Fig. 3 shows an analog-to-timing controller (ACT). Two delay
techniques [1]-[5]. Among recent comparator offset cancellation elements (I2, I3), two tunable delay elements (I7, I8) and four buffers
techniques, an approach using capacitors with dynamic correction to (I1, I4, I5, I6 ) are implemented to control the timing of OC1, OC2 and
adjust the output loads of comparators [4] degrades the response. RES. Fig.4 shows simulated wave forms with the comparator in Fig.
Another approach using capacitors to control current for offset 1 and the timing controller in Fig. 3, giving 50 mV of input offset to
cancellation [5] requires refreshing for the capacitors. This work the preamplifier. Gain of the preamplifier is 3dB. ACTL2 is set 550
presents an 1GHz CMOS comparator by dynamic offset control mV to ensure M5 turns on after M3 completely turns off. ACTL1 is
technique based on charge compensation through timing adjustment. swept from 0.7 V to 1.2 V in 10 mV steps. The transition appears at
the latch output when ACTL1 changes from 850 mV to 840 mV. Fig.
II. CHIP DESIGN AND MEASUREMENT RESULTS 5 shows the relationship between ACTL1 and the input offset, by
Fig. 1 shows a comparator consists of preamplifier and changing the input offset to the preamplifier. According to this
cross-coupled inverters, I1 and I2, which work as a regenerative latch. simulated result, 500 mV of ACTL1 variation causes OC1 delay to
Two source-drain shorted transistors M4 and M5 are implemented on change by approximately 50 ps and 75 mV input offset is controlled.
each regenerative node respectively. M4 and M5 have the same The control ratio (ΔVoff /ΔACTL1) is 0.167.
channel length with that of M3 while have the half channel width of Fig. 6 is a chip photograph of the comparator, including blocks of
M3. During the reset period, the differential inputs pair of the Fig. 1, Fig. 3 and an output flip-flop, fabricated in a 65 nm CMOS
preamplifier is biased to ground through switches S1 and S2. process. It occupies 25 x 65 μm 2
and consumes 380 μW. Fig. 7
Assuming that the offset of the preamplifier is positive and the latch presents the measurement performance of the chip. (a) shows the
stage is ideally symmetric, the regenerative nodes are shorted threshold level of the comparator response at 1 GS/s with 1.2 V
together through M3, resulting in Vc § Vd. The total charge Qch in the power supply. ACTL1 is controlled with a 100 mV gap. Analog
inversion layer of M3 is signals are acquired at the rising edge of the clock. An offset of 10
Qch = LWCox (VRES − Vc − VTH ) = LWCoxVod (1) mV is controlled by 100 mV of ACTL1 variation. Fig. 7 (b) shows a
response with a 500 MHz analog input frequency, synchronized to
where L denotes the effective channel length, Cox multiplied by W the 1 GHz clock. The analog signal is acquired at the top and bottom
presents the total capacitance per unit length, and VTH denotes the voltage and their outputs are compared. 100 mV of ACTL1 variation
threshold voltage of M3. Equation (1) indicates that Qch depends on controls the threshold level of the comparator to be higher than the
the overdrive voltage Vod. Because the charges absorbed by M4 and top of analog signal, so after the transition of ACTL1 to be lower
M5 also have a dependency on the overdrive voltage, the same as M3 level the comparator output is fixed to low. This means the analog
as explained in (1), the voltage at node c and d will be influenced by signal is lower than reference revel. Fig. 8 shows actual performance
the overdrive voltage of M4 and M5 at the moment M3 turns off. of the relationship between ACTL1 and the input offset. The control
To perform the offset compensation, the channel charge is ratio is 0.104 which means 1mV offset can be controlled by 10 mV
absorbed by M4 and M5 with appropriate timings. Fig. 2 shows the of ACTL1. It is well balanced between the controllable range and
mechanism of the proposed timing-based offset control. Let T1, T3 resolution to control several tens of mV offset with mV order
and T4 be the moments at which the overdrive voltages reach the accuracy.
thresh levels of M4, M3 and M5, T2 is the moment at which M3 starts
switching from on to off. During the period T1~T2, M4 absorbs III. SUMMARY
charges Q’, illustrated in Fig. 2 (a), from parasitic capacitors CH1 and A new offset control technique based on charge compensation by
CH2, on the nodes c and d. Thus the charge absorption has timing control is confirmed by a 1 GHz comparator fabricated in 65
approximately the same contribution to the potentials on nodes c and nm CMOS with 1.2 V power supply. The comparator occupies 25 x
d. During the period T2~T3, the latching operation starts as reset 65 μm2 and consumes 380 μW.
transistor M3  is being turned off by RES. Meanwhile, charge
injection and clock feedthrough [6] appear at the latch stage, however
ACKNOWLEDGEMENTS
the charge injection dominates the effects on the potentials of the The authors would like to thank the members of SOC Network division of
regenerative nodes c and d. Since M4 is turned on while M5 remains Fujitsu Laboratories Ltd. for their encouragement and generous support.
off in this period, as illustrated in Fig. 2 (b), some of the charge Q’ch,1
injected from the drain of M3 is absorbed by M4, and the remaining REFERENCES
charge Qch,1 is deposited by CH1 on node c. The charge Qch,2 injected [1] J. Atherton et al., “An Offset Reduction Technique for Use with CMOS

978-1-4244-2749-9/09/$25.00 ©2009 IEEE 103

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Integrated Comparators and Amplifiers,” IEEE Journal of Solid-State
Circuits, vol. 27, No. 8, pp. 1168-1175, Aug. 1992.
[2] D. Weinlader et al., “An eight channel 36G Sample/s CMOS timing Vin, 1 Vin, 2
analyzer,” in IEEE ISSCC Dig. Tech. Papers, pp.170-171, Feb. 2000,. S1 S2
[3] K. L. J. Wong et al., “Offset Compensation in Comparators with Minimum  
Preamp
Input-Referred Supply Noise,” IEEE Journal of Solid-State Circuits, vol.  
39, No. 5, pp. 837-840, May 2004.
[4] G. V. der Plas et al., “A 0.16 pJ/Conversion-Step 2.5 mW 1.25 GS/s 4b
ADC in a 90 nm digital CMOS process,” in ISSCC Dig. Tech. Papers, M1 M2
pp.2308–2309, Feb. 2006
[5] P. M. Figueiredo et al., “A 90nm CMOS 1.2V 6b 1GS/s Two-Step D E
Subranging ADC,” in ISSCC Dig. Tech. Papers, pp. 568-569, Feb. 2006.
[6] A. M. Abo, P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline I3 I1 I2 I4
F G
analog-to-digitalconverter," IEEE Journal of Solid-State Circuits, vol. 34, M4 M3 M5
No. 5, pp. 599-567, May 1999.
OC1 RES OC 2
Q'
F Q ch G Vout,1 Vout, 2 Latch
CH1 CH2
M4 M3 M5 Fig. 1. Comparator with dynamic offset control technique.
RES OC1 ,QSXW2IIVHW P9
OC 1 RES OC 2

(a) T1 < t < T2 CLK in OC2

9ROWDJHV9
OC1
Q ch,1 Q'ch,1 Q ch Q ch,2 I7 I4
F G
CH1 CH2 ACTL1
Q' M1
M4 M3 M5
CLKin I1 I2 I3 RES
OC1 RES OC 2
ACTL 1 = 850mV;
(b) T2 < t < T3 I5
(Td RES, OC = 465ps)

9ROWDJHV9
V Vout, 1 1

RES OC1 OC2

OC 2 I8 I6
ACTL1 = 840mV;
ACTL2 (TdRES, OC = 475ps)
1

M2

T1T2 T3 T4 t
(c) Timing of RES, OC1 and OC2. 7LPH6
Fig. 3. Analog-to-Timing Convertor.
Fig. 2. Mechanism of offset control by Fig. 4. Simulation results.

90
Vin1: 62.5MHz;
80
50mV (P-P) 10mV 50mV
))

70
Input Offset (mV)

60 RESin : 1GHz

50
ACTL1 : 1065mV~ 100mV
3UHDPSOLILHU

40 1165mV
30

20
XP

10
Vout
/DWFK

0
700 800 900 1000 1100 1200

ACTL1 (mV)
&ORFNJHQHUDWRU

Fig. 5. Relationship between analog control (a)

signal and input offset.
$7&

70 Vin1: 500MHz;
50mV (P-P) 50mV
60
XP
RESin : 1GHz
Input Offset (mV)

50

ACTL1 : 875mV~
40 100mV
975mV
30

Fig. 6. Photograph of the

20
comparator test die. Vout
10

0
700 800 900 1000 1100 1200

ACTL1 (mV)
(b)
Fig. 8. Relationship between control signal and Fig. 7. Oscilloscope photographs of waveforms
input offset based on actual dc measurement results. for offset control test.

104