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Intro to Microarchitecture: • Review from last lecture
Single-Cycle • ISA tradeoffs
CS 3330
• Single-cycle Microarchitecture
Samira Khan
University of Virginia
Feb 9, 2017
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• Remember
• Microarchitecture: Implementation of the ISA under specific design constraints
and goals
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• Design point determined by the “Problem” space (application space), • Design point determined by the “Problem” space (application space),
the intended users/market the intended users/market
Look Forward & Up
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Application Space
Tradeoffs: Soul of Computer Architecture
• ISA-level tradeoffs
• Dream, and they will appear…
• Microarchitecture-level tradeoffs
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MIPS ARM
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nop 1 0
mrmovq D (rB), rA 5 0 rA rB D
• What would be the first question you ask in this OPq rA, rB 6 fn rA rB
pushq rA A 0 rA F
popq rA B 0 rA F
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Process instruction
• Microarchitecture implements how AS is transformed to AS’
• There are many choices in implementation
• We can have programmer-invisible state to optimize the speed of instruction
AS’ = Architectural (programmer visible) state after an instruction is processed execution: multiple state transitions per instruction
• Choice 1: AS à AS’ (transform AS to AS’ in a single clock cycle)
• Choice 2: AS à AS+M S1 à AS+M S2 à AS+M S3 à AS’ (take m ultiple clock cycles to
• Processing an instruction: Transforming AS to AS’ according to the ISA transform AS to AS’)
specification of the instruction
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A Very Basic Instruction Processing Engine A Very Basic Instruction Processing Engine
• Each instruction takes a single clock cycle to execute • Single-cycle machine
• Only combinational logic is used to implement instruction execution
• No intermediate, programmer-invisible state updates
AS’ = Architectural (programmer visible) state • What is the clock cycle time determined by?
at the end of a clock cycle • What is the critical path of the combinational logic
determined by?
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Programmer-Visible State
• PC: Program counter
• Multi-cycle machines
• Address of next instruction • Instruction processing broken into multiple cycles/stages
• Memory
• Called “RIP” (x86-64)
• Byte addressable array
• State updates can be made during an instruction’s execution
• Register file • Architectural state updates made only at the end of an instruction’s execution
• Code and user data
• Heavily used program data
• Stack to support procedures
• Advantage over single-cycle: The slowest “stage” determines cycle time
• Condition codes
• Store status inform ation about m ost
recent arithm etic or logical operation n Both single-cycle and multi-cycle machines literally follow the
• Used for conditional branching von Neumann model at the microarchitecture level
Instructions (and programs) specify how to transform
the values of programmer visible state
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Instruction Processing “Stage” Instruction Processing “Cycle” vs. Machine Clock Cycle
• Instructions are processed under the direction of a “control • Single-cycle machine:
unit” step by step.
• All phases of the instruction processing cycle take a single
• Instruction stage: Sequence of steps to process an instruction machine clock cycle to complete
• Fundamentally, there are five phases:
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Instruction Processing Viewed Another Way Single-cycle vs. Multi-cycle: Control & Data
• Single-cycle machine:
• Instructions transform Data (AS) to Data’ (AS’) • Control signals are generated in the same clock cycle as the
• This transformation is done by functional units one during which data signals are operated on
• Units that “operate” on data
• Everything related to an instruction happens in one clock cycle
• These units need to be told what to do to the data (serialized processing)
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Remember…
A Single-Cycle • Single-cycle machine
Microarchitecture
A Closer Look Combinational
AS’
(State) AS
Logic
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Let’s Start with the State Elements For Now, We Will Assume
Reg
• Data and control inputs
valA
Write
• “Magic” memory and register file
srcA A valW 0
PC
Register M UX
valB file
W dstW
1
• Synchronous write
srcB B M UX
• the selected register is updated on the positive edge clock
Select transition when write enable is asserted
M em • Cannot affect read output in between clock edges
Write
Operation
Instr Address
Addr Read A
Instruction A
Data
Instruction Write Data L
U
Mem
Data Mem B
M em 47 48
Read
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in the class
rB L Data
C Addr Instruction ValB U
IF ID EX MEM WB PC
if MEM[PC] == OPq rA, rB
R[rB] ¬ R[rB] op R[rA]
Combinational
PC ¬ PC + 2
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
state update logic
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A From ALU A M
M From ALU
D D U
10 U From M em 10 From M em
D D X
X
M UX M UX
Select Select
if MEM[PC]== irmovq V, rB IF ID EX MEM WB PC if MEM[PC]== irmovq V, rB IF ID EX MEM WB PC
R[rB] ¬ V + 0 R[rB] ¬ V
PC ¬ PC + 10
Combinational Combinational
PC ¬ PC + 10
state update logic 79
state update logic 80
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A M
From ALU
D U
10 From M em
D X
M UX
Select
if MEM[PC]== irmovq V, rB IF ID EX MEM WB PC
R[rB] ¬ V
PC ¬ PC + 10
Combinational
state update logic 81 82
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rB valB
OP
A
Single-Cycle
P Instr
rA L Address
Read
Data
CS 3330
C Addr Instruction ValA M U
rB M U
Instruction DestE Write Data
rA U Register X Data
Mem Mem
?
X ValE file
D Samira Khan
University of Virginia
A M
From ALU Feb 9, 2017
D U
10 From M em
D X
M UX
Select
if MEM[PC]== rrmovq rA, rB IF ID EX MEM WB PC
R[rB] ¬ R[rA]
PC ¬ PC + 2
Combinational
state update logic 89
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