Finite State Machines

• Finite State Machines (FSMs) are a useful abstraction for

sequential circuits with centralized “states” of operation
• At each clock edge, combinational logic computes outputs and
next state as a function of inputs and present state

Finite State Machines

inputs Combinational outputs
+ Logic +
present next
• Design methodology for sequential logic state state
-- identify distinct states
-- create state transition diagram n n
-- choose state encoding
-- write combinational Verilog for next-state logic
-- write combinational Verilog for output signals Q
Registers
D

• Lots of examples CLK

Reminder: Lab #2 due tonight!
6.111 Fall 2012 Lecture 5 1 6.111 Fall 2012 Lecture 5 2

Two Types of FSMs Design Example: Level-to-Pulse

Moore and Mealy FSMs : different output generation • A level-to-pulse converter produces a single-
• Moore FSM: cycle pulse each time its input goes high.
next • It’s a synchronous rising-edge detector.
state
inputs
S+ • Sample uses:
Comb. D Q Comb. outputs
x0...xn Logic
n Registers
Logic yk = fk(S) – Buttons and switches pressed by humans for
CLK arbitrary periods of time
n
– Single-cycle enable signals for counters
present state S

• Mealy FSM:
direct combinational path! Level to
outputs
yk = fk(S, x0...xn) L Pulse P
inputs S+ Comb. Converter
x0...xn Comb. D Q
Logic ...output P produces a
n Registers Whenever input L goes
Logic single pulse, one clock
from low to high...
CLK
n CLK period wide.

6.111 Fall 2012 Lecture 5 3 6.111 Fall 2012 Lecture 5 4

 Step 1: State Transition Diagram Valid State Transition Diagrams
• Block diagram of desired system:
L=1 L=1
Synchronizer Edge Detector

00 11
unsynchronized Level to
L=0 01
D Q D Q L P Low input, High input,
user input Pulse
Waiting for rise
Edge Detected!
Waiting for fall
L=1
FSM
P=0 P=1 P=0
CLK L=0
L=0
• State transition diagram is a useful FSM representation and
design aid:
• Arcs leaving a state are mutually exclusive, i.e., for any
“if L=1 at the clock edge,
then jump to state 01.”
L=1 L=1 Binary values of states combination input values there’s at most one applicable arc
• Arcs leaving a state are collectively exhaustive, i.e., for any
00 11
11
L=0 01 combination of input values there’s at least one applicable arc
Low input, High input,
Waiting for rise
Edge Detected!
Waiting for fall
L=1
P=0 P=1 P=0 • So for each state: for any combination of input values there’s
L=0
L=0 exactly one applicable arc
“if L=0 at the clock This is the output that results
edge, then stay in state from this state. (Moore or
Mealy?)
• Often a starting state is specified
00.”
• Each state specifies values for all outputs (Moore)
6.111 Fall 2012 Lecture 5 5 6.111 Fall 2012 Lecture 5 6

Choosing State Representation Step 2: Logic Derivation

Current Next
Transition diagram is readily converted to a State
In
State
Out
state transition table (just a truth table)
Choice #1: binary encoding S1 S0 L S1 + S0 + P
L=1 L=1
0 0 0 0 0 0
For N states, use ceil(log2N) bits to encode the state with each L=0
00 11
L=1 0 0 1 0 1 0
01
state represented by a unique combination of the bits. Low input,
Waiting for rise
Edge Detected!
High input,
Waiting for fall
0 1 0 0 0 1
P=1
Tradeoffs: most efficient use of state registers, but requires P=0 P=0 0 1 1 1 1 1
L=0
more complicated combinational logic to detect when in a L=0 1 1 0 0 0 0
particular state. 1 1 1 1 1 0

• Combinational logic may be derived using Karnaugh maps

Choice #2: “one-hot” encoding
S1S0 for S1 :
+

L 00 01 11 10
For N states, use N bits to encode the state where the bit 0 0 0 0 X
L S+
corresponding to the current state is 1, all the others 0. 1 0 1 1 X Comb. D Q Comb.
P
for P:
n Registers S1
Tradeoffs: more state registers, but often much less S1S0 for S0+: Logic
CLK
Logic
S0 0 1
combinational logic since state decoding is trivial. L 00 01 11 10 n
0 0 X
0 0 0 0 X S
S1+ = LS0 P = S1S0 1 1 0
1 1 1 1 X S0+ = L

6.111 Fall 2012 Lecture 5 7 6.111 Fall 2012 Lecture 5 8

 Moore Level-to-Pulse Converter Design of a Mealy Level-to-Pulse
next direct combinational path!
state
S+ S+
inputs D Q outputs D Q
Comb.
Comb. Comb. Comb. Logic
x0...xn Logic
n Registers
Logic yk = fk(S) Logic
n Registers
CLK
CLK n
n S
present state S • Since outputs are determined by state and inputs, Mealy FSMs may
S1+ = LS0
S0+ = L
P = S1S0 need fewer states than Moore FSM implementations
1. When L=1 and S=0, this output is
Moore FSM circuit implementation of level-to-pulse converter: asserted immediately and until the
state transition occurs (or L L 1
changes). 2
P
S0+ S0 L=1 | P=1
L D Q
P Clock
L=0 | P=0 0 1 Stat
CLK Q
Input is low Input is high e
D Q
Output transitions immediately.
L=0 | P=0
S1+ S1 State transitions at the clock
Q L=1 | P=0 edge.
2. While in state S=1 and as long as L
remains at 1, this output is asserted.

6.111 Fall 2012 Lecture 5 9 6.111 Fall 2012 Lecture 5 10

Mealy Level-to-Pulse Converter Moore/Mealy Trade-Offs

Next
Pres.
L=1 | P=1 State
In Stat Out • How are they different?
e
0 1 – Moore: outputs = f( state ) only
Input is low Input is high S L S+ P
0 0 0 0
– Mealy outputs = f( state and input )
L=0 | P=0
0 1 1 1 – Mealy outputs generally occur one cycle earlier than a Moore:
L=0 | P=0 L=1 | P=0
1 0 0 0
1 1 1 0
Moore: delayed assertion of P Mealy: immediate assertion of P
Mealy FSM circuit implementation of level-to-pulse converter:
L L
P P P
S+ S
L D Q Clock Clock
CLK Q State[ State
S 0]

• FSM’s state simply remembers the previous value of L • Compared to a Moore FSM, a Mealy FSM might...
• Circuit benefits from the Mealy FSM’s implicit single-cycle – Be more difficult to conceptualize and design
assertion of outputs during state transitions – Have fewer states

6.111 Fall 2012 Lecture 5 11 6.111 Fall 2012 Lecture 5 12

 Example: Intersection Traffic Lights FSM Example
• Design a controller for the traffic lights at the intersection of GOAL:
two streets – two sets of traffic lights, one for each of the Build an electronic combination lock with a reset
streets. button, two number buttons (0 and 1), and an unlock
• Step 1: Draw starting state transition diagram. Just handle the output. The combination should be 01011.
usual green-yellow-red cycle for both streets. How many states?
Well, how many different combinations of the two sets of lights RESET
are needed? “0” UNLOCK
• Step 2: add support for a walk button and walk lights to your “1”
state transition diagram.
• Step 3: add support for a traffic sensor for each of the streets
– when the sensor detects traffic the green cycle for that street STEPS:
is extended. 1. Design lock FSM (block diagram, state transitions)
2. Write Verilog module(s) for FSM
Example to be worked collaboratively on the board…

6.111 Fall 2012 Lecture 5 13 6.111 Fall 2012 Lecture 5 14

Step 1A: Block Diagram Step 1B: State transition diagram

lock RESET
1
1 0
Clock
fsm_clock fsm
generator
RESET 0 “0” 1 “01”
Unlock = 0 Unlock = 0 Unlock = 0
unlock Unlock
reset button LED
Button
reset
Enter 0
1 0
Button b0_in button 0
b0 LED
0 1 1
DISPLAY “01011” “0101” “010”
state Unlock = 1 Unlock = 0 Unlock = 0
Button b1_in
button b1
1 0

6 states  3 bits
6.111 Fall 2012 Lecture 5 15 6.111 Fall 2012 Lecture 5 16
 Step 2: Write Verilog Step 2A: Synchronize buttons
module lock(input clk,reset_in,b0_in,b1_in, // button
output out); // push button synchronizer and level-to-pulse converter
// OUT goes high for one cycle of CLK whenever IN makes a
// synchronize push buttons, convert to pulses // low-to-high transition.
out
// implement state transition diagram module button(
r1 r2 r3
reg [2:0] state,next_state; input clk,in, in D Q D Q D Q
always @(*) begin output out
// combinational logic! );
clk
next_state = ???; reg r1,r2,r3;
end always @(posedge clk) synchronizer state
always @(posedge clk) state <= next_state; begin
r1 <= in; // first reg in synchronizer
// generate output r2 <= r1; // second reg in synchronizer, output is in sync!
assign out = ???; r3 <= r2; // remembers previous state of button
end
// debugging?
endmodule // rising edge = old value is 0, new value is 1
assign out = ~r3 & r2;
endmodule
6.111 Fall 2012 Lecture 5 17 6.111 Fall 2012 Lecture 5 18

Step 2B: state transition diagram Step 2C: generate output

parameter S_RESET = 0; // state assignments
parameter S_0 = 1; RESET
1
parameter S_01 = 2; 1 0
// it’s a Moore machine! Output only depends on current state
0 1
parameter S_010 = 3; RESET
Unlock = 0
“0”
Unlock = 0
“01”
Unlock = 0

parameter S_0101 = 4; assign out = (state == S_01011);

0
parameter S_01011 = 5; 1 0
0
“01011 ” 1 “0101 ” 1 “010”
reg [2:0] state, next_state; Unlock = 1 Unlock = 0 Unlock = 0

always @(*) begin 0

// implement state transition diagram

if (reset) next_state = S_RESET;
Step 2D: debugging?
else case (state)
S_RESET: next_state = b0 ? S_0 : b1 ? S_RESET : state;
S_0: next_state = b0 ? S_0 : b1 ? S_01 : state; // hmmm. What would be useful to know? Current state?
S_01: next_state = b0 ? S_010 : b1 ? S_RESET : state;
S_010: next_state = b0 ? S_0 : b1 ? S_0101 : state; assign hex_display = {1'b0,state[2:0]};
S_0101: next_state = b0 ? S_010 : b1 ? S_01011 : state;
S_01011: next_state = b0 ? S_0 : b1 ? S_RESET : state;
default: next_state = S_RESET; // handle unused states
endcase
end

always @(posedge clk) state <= next_state;

6.111 Fall 2012 Lecture 5 19 6.111 Fall 2012 Lecture 5 20
 Step 2: final Verilog implementation Where should CLK come from?
module lock(input clk,reset_in,b0_in,b1_in,
output out, output [3:0] hex_display);

wire reset, b0, b1; // synchronize push buttons, convert to pulses

• Option 1: external crystal
button b_reset(clk,reset_in,reset); – Stable, known frequency, typically 50% duty cycle
button b_0(clk,b0_in,b0);
button b_1(clk,b1_in,b1); • Option 2: internal signals
parameter S_RESET = 0; parameter S_0 = 1; // state assignments – Option 2A: output of combinational logic
parameter S_01 = 2; parameter S_010 = 3;
parameter S_0101 = 4; parameter S_01011 = 5;

reg [2:0] state,next_state;

always @(*) begin // implement state transition diagram
if (reset) next_state = S_RESET;

• No! If inputs to logic change, output may make several

else case (state)
S_RESET: next_state = b0 ? S_0 : b1 ? S_RESET : state;
S_0: next_state = b0 ? S_0 : b1 ? S_01 : state; transitions before settling to final value  several rising edges,
not just one! Hard to design away output glitches…
S_01: next_state = b0 ? S_010 : b1 ? S_RESET : state;
S_010: next_state = b0 ? S_0 : b1 ? S_0101 : state;
S_0101: next_state = b0 ? S_010 : b1 ? S_01011 : state;
S_01011: next_state = b0 ? S_0 : b1 ? S_RESET : state; – Option 2B: output of a register
default: next_state = S_RESET;
endcase
// handle unused states • Okay, but timing of CLK2 won’t line up with CLK1
end
always @ (posedge clk) state <= next_state;

assign out = (state == S_01011); // assign output: Moore machine

assign hex_display = {1'b0,state}; // debugging D Q CLK2
endmodule

CLK1 CLK1
6.111 Fall 2012 Lecture 5 21 6.111 Fall 2012 Lecture 5 22