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Memory & Programmable Logic Devices: Digital Logic Families: DTL, DCTL,
TTL, ECL & CMOS etc., Fan Out, Fan in, Noise Margin; RAM, ROM, PLA,
PAL; Circuits of Logic Families, Interfacing of Digital Logic Families, Circuit
Implementation using ROM, PLA and PAL; CPLD and FPGA.

Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Q-1 What is Fan-Out?

Ans: Fan out specifies the number of standard loads that the output of the gate can drive without
impairment of its normal operation

Q2- What is Noise Margin in digital circuits?

Ans:It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an
undesirable change in the circuit output. It is expressed in volts

Q-3: Explain Logic Family classification.

Ans: Logic families are sets of chips that may implement different logical functions but use the
same type of transistors and voltage levels for logical levels and for the power supplies. These
families vary by speed, power consumption, cost, voltage & current levels. The most widely used
families are:

 DL (Diode- logic)
 DTL （Diode-transistor logic）
 RTL （Resistor-transistor logic）
 TTL （Transistor -transistor logic）
 ECL （Emitter-coupled logic）
 MOS （Metal-oxide semiconductor）
 CMOS (Complementary Metal-oxide semiconductor）

Q-4 Write TTL Parameters

Ans: based on bipolar transistors one of the most widely used families of small- and medium-
scale devices – rarely used for VLSI

 typically operated from a 5V supply

 typical noise immunity about 1 – 1.6 V
 many forms, some optimised for speed, power, etc.
 High-speed versions comparable to CMOS (~ 1.5 ns)
 low-power versions down to about 1 mW/gate

Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Q-5 What is PROM?

Ans: Read Only Memory (ROM) is a memory device, which stores the binary information permanently.
That means, we can’t change that stored information by any means later. If the ROM has programmable
feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the
binary information electrically once by using PROM programmer.

Q-6 What is PAL ( Programmable Array Logic )

Ans:PAL is a programmable logic device that has Programmable AND array & fixed OR array. The
advantage of PAL is that we can generate only the required product terms of Boolean function instead
of generating all the min terms by using programmable AND gates. The block diagram of PAL is shown in
the following figure.

Q-7 What is PLA (Programmable Logic Array)

Ans: PLA is a programmable logic device that has both Programmable AND array & Programmable OR
array. Hence, it is the most flexible PLD. The block diagram of PLA is shown in the following figure.

Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)

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Digital Logic Design(REC-301) By: Navneet Pal (Assistant Professor)