eGaN® FET DATASHEET EPC2036

EPC2036 – Enhancement Mode Power Transistor

VDSS , 100 V D

RDS(on) , 73 mΩ G EFFICIENT POWER CONVERSION

ID , 1.7 A S
HAL

Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral
device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end
result is a device that can handle tasks where very high switching frequency, and low on-time are
beneficial as well as those where on-state losses dominate. EPC2036 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 0.9 mm x 0.9 mm
Maximum Ratings
Applications
Drain-to-Source Voltage (Continuous) 100
VDS V • High Speed DC-DC conversion
Drain-to-Source Voltage (up to 10,000 5ms pulses at 150˚C) 120 • Wireless Power Transfer
• High Frequency Hard-Switching and
Continuous (TA = 25˚C, R θJA= 340˚C/W) 1.7 Soft-Switching Circuits
ID A
Pulsed (25˚C, TPULSE = 300 µs) 18 • LiDAR/Pulsed Power Applications
• Class-D Audio
Gate-to-Source Voltage 6
VGS V Benefits
Gate-to-Source Voltage -4 • Ultra High Efficiency
TJ Operating Temperature -40 to 150
• Ultra Low RDS(on)
˚C • Ultra low QG
TSTG Storage Temperature -40 to 150 • Ultra small footprint
www.epc-co.com/epc/Products/eGaNFETs/EPC2036.aspx

Static Characteristics (TJ= 25˚C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 µA 100 V
IDSS Drain Source Leakage VDS = 80 V, VGS = 0 V 20 250 µA
Gate-to-Source Forward Leakage VGS = 5 V 0.1 0.9 mA
IGSS
Gate-to-Source Reverse Leakage VGS = -4 V 20 250 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.6 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 1 A 62 73 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
All measurements were done with substrate shorted to source.

Thermal Characteristics
TYP UNIT
RθJC Thermal Resistance, Junction to Case 6.5 ˚C/W
RθJB Thermal Resistance, Junction to Board 65 ˚C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1) 100 ˚C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

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eGaN® FET DATASHEET EPC2036

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance 75 90
COSS Output Capacitance VDS = 50 V, VGS = 0 V 50 75 pF
CRSS Reverse Transfer Capacitance 0.7 1.1
RG Gate Resistance 0.6 Ω
QG Total Gate Charge VDS = 50 V, VGS = 5 V, ID = 1 A 700 910
QGS Gate-to-Source Charge 170
QGD Gate-to-Drain Charge VDS = 50 V, ID = 1 A 140 240
pC
QG(TH) Gate Charge at Threshold 120
QOSS Output Charge VDS = 50 V, VGS = 0 V 3900 5900
QRR Source-Drain Recovery Charge 0
All measurements were done with substrate shorted to source.

Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics

18 18

15 ID – Drain Current (A) 15

ID – Drain Current (A)

12 12
25˚C
9 9 125˚C
VGS = 5 V VDS = 3 V
VGS = 4 V
6 6
VGS = 3 V
VGS = 2 V
3 3

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDS – Drain-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V)

Figure 3: RDS(on) vs. VGS for Various Drain Currents Figure 4: RDS(on) vs. VGS for Various Temperatures
250 250

ID = 0.5 A
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)

ID = 1.0 A 25˚C
200 200
ID = 1.5 A 125˚C
ID = 2.0 A
ID = 1 A
150 150

100 100

50 50

0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V)

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eGaN® FET DATASHEET EPC2036

Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale)
140
100
120 COSS = CGD + CSD
CISS = CGD + CGS
100 CRSS = CGD

Capacitance (pF)
Capacitance (pF)

10
80
COSS = CGD + CSD
CISS = CGD + CGS
60 CRSS = CGD

40 1

20

0 0.1
0 20 40 60 80 100 0 20 40 60 80 100
VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V)

Figure 6: Gate Charge Figure 7: Reverse Drain-Source Characteristics

5 18

ID = 1 A 15
4 25˚C
VDS = 50 V
VGS – Gate-to-Source Voltage (V)

ISD – Source-to-Drain Current (A)

125˚C
12
3
9

2
6

1
3

0 0
0 0.2 0.4 0.6 0.8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
QG – Gate Charge (nC) VSD – Source-to-Drain Voltage (V)

Figure 8: Normalized On Resistance vs. Temperature Figure 9: Normalized Threshold Voltage vs. Temperature
2.0 1.40

ID = 1 A 1.30 ID = 0.6 mA
Normalized On-State Resistance RDS(on)

1.8 VGS = 5 V
Normalized Threshold Voltage

1.20
1.6
1.10

1.4 1.00

0.90
1.2
0.80
1.0
0.70

0.8 0.60
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TJ – Junction Temperature (°C) TJ – Junction Temperature (°C)

All measurements were done with substrate shortened to source.

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eGaN® FET DATASHEET EPC2036

Figure 10: Gate Leakage Current

3.0

2.5
25˚C
125˚C

IG – Gate Current (mA)

2.0

1.5

1.0

0.5

0
0 1 2 3 4 5 6
VGS – Gate-to-Source Voltage (V)

Figure 11: Transient Thermal Response Curves

Junction-to-Board
1 Duty Cycle:
ZθJB, Normalized Thermal Impedance

0.5

0.1
0.1
0.05
0.02
PDM
0.01
0.01
t1
t2
0.001
Notes:
Single Pulse Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
0.0001
10-5 10-4 10-3 10-2 10-1 1 10+1
tp, Rectangular Pulse Duration, seconds

Junction-to-Case
1 Duty Cycle:
ZθJB, Normalized Thermal Impedance

0.5
0.2
0.1
0.1
0.05
0.02
PDM
0.01
0.01
t1
t2
0.001
Single Pulse Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
0.0001
10-6 10-5 10-4 10-3 10-2 10-1 1
tp, Rectangular Pulse Duration, seconds

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eGaN® FET DATASHEET EPC2036

Figure 12: Safe Operating Area

10

I D – Drain Current (A)

Limited by RDS(on)
Pulse Width
1
100 ms100 ms
10 ms10 ms
1 ms
100 µs1 ms
100 µs
0.1
0.1 1 10 100
VDS - Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse

TAPE AND REEL CONFIGURATION

4mm pitch, 8mm wide tape on 7”reel Loaded Tape Feed Direction
d e f g

7” reel Die
b orientation
YYY dot

c AB Gate
a solder bar is
under this
corner

Die is placed into pocket

solder bar side down
EPC2036 (note 1) (face side down)
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
f (see note) 2.00 1.95 2.05
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
g 1.5 1.5 1.6 not the pocket hole.

DIE MARKINGS

AB Laser Markings
Die orientation dot Part
YYY Number Part # Lot_Date Code
Gate Pad bump is Marking Line 1 Marking line 2
under this corner EPC2036 AB YYY

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eGaN® FET DATASHEET EPC2036
A
DIE OUTLINE DIM MIN Nominal MAX
Solder Bump View g
A 870 900 930
B 870 900 930
2 4 c 450 450 450
d 450 450 450
e 210 225 240

d
Pads 1 is Gate; f 210 225 240
Pad 3 is Drain; g 187 208 229
Pads 2, 4 are Source
1 3

e c

f
Side View

(625)

815 Max
165+/- 17
SEATING PLANE

RECOMMENDED 900 The land pattern is solder mask defined

LAND PATTERN Solder mask is 10 μm smaller per side than bump
(measurements in µm)
Pads 1 is Gate;
1 3
Pad 3 is Drain;
X4 Pads 2, 4 are Source
900

200 +20 / - 10 (*)

450

242
2 4
225

225 450

* minimum 190

RECOMMENDED 900 Recommended stencil should be 4mil (100 µm) thick, must
STENCIL DRAWING 250 be laser cut, openings per drawing.
(measurements in µm)
0

Intended for use with SAC305 Type 4 solder, reference 88.5%

R6

metals content.
900

450

Additional assembly resources available at

http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
225

225 450

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit Information subject to change
described herein; neither does it convey any license under its patent rights, nor the rights of others. without notice.
eGaN® is a registered trademark of Efficient Power Conversion Corporation. Revised May, 2018
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

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