IEEE - 40222

IMPLEMENTATION OF 4-BIT UNIVERSAL

SHIFT REGISTER USING DIODE FREE
ADIABATIC LOGIC

Shazia Pervez Manisha Sahoo

School of Electronics School of Electronics
CDAC, Noida CDAC, Noida
India India
spervez29@gmail.com manishasahoo98@gmail.com

Dr. Arti Noor

School of Electronics
CDAC, Noida
India

Abstract— In digital circuits, shift registers are used as the
basic memory units. This paper presents a low power adiabatic
Universal Shift Register, which can perform both serial and
parallel shift operations. Since power dissipation is a critical
factor many low power dissipation techniques have been
proposed but most of these techniques have some trade-offs.
Adiabatic logic technique as compared to that of a conventional
CMOS technique shows promising results. A type of adiabatic
technique, DFAL (Diode Free Adiabatic Logic), has been studied
in this paper and NOR gate, NAND gate, XOR gate, D Flip-Flop
and Universal Shift Register have been designed using this
configuration. DFAL circuits are analyzed based on transistor
count, power dissipation and delay. All the circuits are simulated
in Pyxis (Mentor Graphics) 180nm technology at 1.8V.
Keywords— adiabatic; low power; DFAL; shift register
I. INTRODUCTION
The ever increasing number of portable systems, the
reduction in size of devices and the widespread usage of
battery operated systems are emphasizing on the development
of power and area efficient circuits. Low power techniques are
becoming popular in circuits and systems nowadays [1]-[3].
Adiabatic Logic Circuits recycle the energy back to the source
by using a variable power clock supply instead of the fixed
voltage, to reduce the power consumption.
Adiabatic circuits are generally of two types: Fully
Adiabatic and Partially Adiabatic logic circuits [4]. In case of
fully adiabatic circuits, ideally there are no losses. The energy
dissipation during charging can be given in terms of time
period (T), Stored Charge (CL.VDD), and Load capacitance
(CL). Yibin Ye and Kaushik Roy have presented a detailed
analysis and modelling of adiabatic-switching technique [4]
and have observed a significant reduction in power dissipation
using this technique. They have also introduced Quasi-static
energy recovery logic family (QSERL) using the principle of
adiabatic switching [5] which uses two complementary
sinusoidal supply clocks. P.Sasipriya, V.S. Kanchana
Bhaaskaran have presented a comprehensive analysis and
evaluation of ASL (Adiabatic Static logic), QSERL (Quasi
Static Energy Recovery Logic), CEPAL (Complementary
Energy Path Adiabatic Logic) and QSECRL (Quasi Static
Efficient Charge Recovery Logic)logic [6]. Due to diode
connected MOSFET in QSERL there is degradation of output
amplitude. This problem was overcome by Sanjay Singh, K.
Srinivasarao [7]. They have introduced Diode Free Adiabatic
Logic (DFAL) which also reduces the delay and circuit
complexity. Different circuits have been designed using
DFAL [8], [9]. This paper presents a 4 bit DFAL Universal
Shift Register, which is a type of register that can perform
shift left operation, shift right operation, serial to
serial/parallel, parallel to serial/parallel operations. It is
commonly used in applications where conversion between
serial and parallel interfaces is required.
In this paper a new approach has been used for designing a
4-bit universal shift register. Instead of using the conventional
DC power supply, a sinusoidal adiabatic power clock has been
used. The remaining part of this paper is described as follows.
Section II is a detailed study on adiabatic logic and section III
describes the Universal shift register. In section IV the various
schematics and their analysis are presented and finally the
conclusion is stated in section V.
II. ADIABATIC LOGIC
A. Adiabatic Technique
Adiabatic technique is a low power technique which
promises no power dissipation in ideal situations
(asymptotically zero power dissipation).The main feature of

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 IEEE - 40222
this technique is that the used supply voltage is not a constant
voltage. The supply is also called the power clock. The
variable power supply is implemented by a resonant LC
circuit that reclaims the energy which is stored in the capacitor
and reuses it in the succeeding cycle. The power clock can be
sinusoidal (shown in Fig. 1), trapezoidal or triangular.
According to the type of the power clock the circuit operates
in different modes.
Fig. 1. Sinusoidal Power Supply
To charge a given node which is associated with a
capacitance CL from 0 to V Volts in conventional CMOS
circuit, VQ (=CLV2) of energy is extracted from the supply (as
shown in Fig. 2). 50% of the energy, 0.5CLV2, is stored in the
capacitance, and the remaining is dissipated through resistance
in the path. Energy dissipates with a rate of iΔV
(instantaneous dissipative power) whenever there is a voltage
drop ΔV (i is the current) [10]. This type of energy dissipation
can be decreased to a great extent by considering adiabatic
technique.
Fig. 2. Adiabatic Switching
Hence, the power dissipation in the static CMOS and adiabatic
circuits are described as follows:
Static CMOS: CLV2 (1)
Adiabatic Logic: (2RCL/T) CLV2 (2)
From the above equations it is obvious that the power
dissipation in case of adiabatic circuits depends on the ratio
RCL/T (R stands for resistance, T denotes clock phase period).
So if R, CL and T are adjusted such that RCL<<T then the total
power dissipation will be
(RCL/T) CLV2 << 0.5 CLV2 (3)
It is suggested that the logic gates designed using adiabatic
technique show that approximately 90% of the energy can be
reused at an operating frequency of around 1 MHz
[4].Adiabatic circuits show better results in the low frequency
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range. In this paper we have focused on DFAL (Diode Free
Adiabatic Logic).
B. DFAL (Diode Free Adiabatic Logic)
DFAL circuits do not have any diode connected MOSFETs
in the charging or discharging path. Adiabatic circuits such as
the Complementary Energy Path Adiabatic Logic, Two phase
clocked static CMOS logic [11], and quasi-static energy
recovery logic have the following problems:
1) Delay
2) Complex circuit
3) Degradation of output amplitude.
DFAL can be used to overcome the above shortcomings
[7].In DFAL, split level sinusoidal complementary power clock
supply VPC and VPCbar are used. The voltage level of VPC is
taken such that it is VPC/2 greater than that of VPCbar; this
tends to decrease power dissipation. The DFAL inverter shown
in Fig.3 is similar to the conventional CMOS logic; however its
operation differs as it operates in an adiabatic way.
The M3 transistor of the pull down path is used to replace
the diode of the discharging path. VPC controls the turning
ON and OFF of M3. M3 recycles the charges at the output
node therefore the adiabatic losses are further recovered. In
evaluation phase, when the p MOS tree is ON and output node
is at logic 0, load capacitance charges through transistor M1
so output goes to logic 1. When n MOS tree turns ON and
output node is at logic 1, M2 and M3 discharge and recycle
the charges towards the power clock (VPC), resulting in the
output to be at logic 0. During hold phase, no transitions occur
which reduces dynamic switching and hence energy
dissipation [12].
Fig. 3. DFAL Inverter
III. UNIVERSAL SHIFT REGISTER
The universal shift register is a type of shift register that
can perform three different operations: Parallel loading, Left
shift and Right shift. This implies that, the universal shift
register can store and transmit the data in both ways i.e. in
parallel and in serial.
As shown in Fig. 14, D1, D2, D3 and D4 are the parallel
inputs and Q1, Q2, Q3 and Q4 are the parallel outputs. To shift
 IEEE - 40222

the data both left and right, a serial input port is provided to
input the corresponding data.

TABLE I. OPERATING MODES OF UNIVERSAL SHIFT REGISTER

S1 S0 Operating Mode
0 0 Parallel Load
0 1 Shift Left
1 0 Shift Right
1 1 Locked
Fig. 5. DFAL Inverter Waveform (X axis:Time in seconds, Y axis:Voltage in
Volts)
Mode S1 = 0 and S0 = 0, correspond to the parallel loading
of the universal shift register. When S1 = 0 and S0 = 1, then it
TABLE II. COMPARISON OF INVERTERS
is in the shift left mode. When S1 = 1 and S0 = 0 then it is in
the shift right mode. When S1 = 1 and S0= 1, then the register Type of Logic
Parameters
results in locked mode, which means implies no operation. CMOS DFAL

Time delays in various digital circuits are provided by the Power(pW) 15.58 0.73
serial in serial out shift registers. Whereas serial in parallel out
Delay(pS) 24.10 176.81
registers are used for serial to parallel transformation of the
data. Similarly parallel in serial out registers are used for PDP(J) 0.375e-21 0.129e-21
parallel to serial transformation of the data. Shift registers are
used in computers as memory elements. A large amount of data No of
2 3
Transistors
has to be stored in all types of digital circuits and systems that
too in an efficient manner so; there is the need to use storage
components like RAM and different registers. The DFAL 2-input NOR is designed as depicted in Fig. 6
and its waveform is presented in Fig. 7. The comparative study
IV. OBSERVATIONS AND RESULTS is recorded in TABLE III. The power consumed by the DFAL
2 input NOR is approximately 95.30% less than the
The DFAL inverter is designed as illustrated in Fig.4 and conventional CMOS NOR gate.
its waveform is shown in Fig.5 [13]. It can be clearly analyzed
from the waveform that the output follows Vpc in the
evaluation period and Vpcbar in the hold phase. The
comparative study with respect to power consumed, delay,
transistor count and the power delay product (PDP) is depicted
in TABLE II. The power consumed by the DFAL inverter is
approximately 95.3% less than the conventional CMOS
inverter.

Fig. 6. DFAL NOR Schematic

Fig. 4. DFAL Inverter Schematic

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 IEEE - 40222

Fig. 9. DFAL 3-Input NAND Waveform (X axis:Time in seconds, Y

Fig. 7. DFAL NOR Wavewform (X axis:Time in seconds, Y axis:Voltage in axis:Voltage in Volts)
Volts)

TABLE IV. COMPARISON OF 3-INPUT NAND

TABLE III. COMPARISON OF NOR Type of Logic
Parameters
Type of Logic CMOS DFAL
Parameters
CMOS DFAL Power(pW) 4.14 0.39
Power(pW) 31.16 1.46 Delay(pS) 76.86 192.50
Delay(pS) 87.11 63.92 PDP(J) 0.318 e-21 0.074 e-21
PDP(J) 2.714 e-21 0.093 e-21 No of
6 7
Transistors
No of
4 5
Transistors
The DFAL 2 input XOR is designed as presented in Fig.
The DFAL 3 input NAND gate is designed as shown in 10 and its waveform is depicted in Fig. 11. The comparative
Fig.8 and its waveform is depicted in Fig.9. The comparative analysis is recorded in TABLE V. The power consumed by
analysis is depicted in TABLE IV. The power consumed by the DFAL 2 input XOR is approximately 34.32% less than the
the DFAL 3 input NAND gate is approximately 90.64% less conventional CMOS XOR gate.
than the conventional CMOS 3 input NAND gate.

Fig. 8. DFAL 3-Input NAND Schematic Fig. 10. DFAL XOR Schematic

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 IEEE - 40222

Fig. 11. DFAL XOR Waveform (X axis:Time in seconds, Y axis:Voltage in Fig. 13. DFAL D flip flop Waveform (X axis:Time in seconds, Y axis:Voltage
Volts) in Volts)

TABLE V. COMPARISON OF XOR TABLE VI. COMPARISON OF D FLIP FLOP

Type of Logic Type of Logic

Parameters Parameters
CMOS DFAL CMOS DFAL

Power(pW) 49.67 32.62 Power(pW) 86.83 15.11

Delay(pS) 93.23 80.18 Delay(pS) 395.88 1239.80

PDP(J) 4.630 e-21 2.615 e-21 PDP(J) 34.375 e-21 18.733 e-21
No of No of
12 13 36 42
Transistors Transistors

The DFAL 4 bit universal shift register is designed as shown

The DFAL D Flip Flop is designed as shown in Fig. 12
in Fig. 14 and its waveform is shown in Fig. 15. The
and its waveform is shown in Fig. 13. The comparison is
comparison is recorded in TABLE VII. The power consumed
recorded in TABLE VI. The power consumed by the DFAL D
by the 4 bit universal shift register is approximately 31.59%
Flip Flop is approximately 82.59% less than the conventional
less than the conventional CMOS 4 bit universal shift register.
CMOS D Flip Flop.

Fig. 12. DFAL D flip flop Schematic

Fig. 14. DFAL 4 Bit Universal Shift Register Schematic

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 IEEE - 40222

be embedded into MEMS and thereby explore the technology

of AdiaMEMS and Nanotechnology in the near future.

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