Vlsi Laboratory: List of Experiments

Roll Number: Type here
VLSI LABORATORY
The students are required to design the schematic diagrams using CMOS logic
and to draw the layout diagrams to perform the following experiments using CMOS
130nm Technology with necessary EDA tools (Mentor Graphics/Tanner).
List of Experiments:
1. Design and implementation of an inverter
2. Design and implementation of universal gates
3. Design and implementation of full adder
4. Design and implementation of full subtractor
5. Design and implementation of RS-latch
6. Design and implementation of D-latch
7. Design and implementation asynchronous counter
8. Design and Implementation of static RAM cell
9. Design and Implementation of differential amplifier
10. Design and Implementation of ring oscillator
Equipment Required:
1. Mentor Graphics/Tanner software-latest version
2. Personal computer with necessary peripherals.
DEPARTMENT OF E.C.E Page 1

INTRODUCTION
LAYOUT DESIGN RULES
The physical mask layout of any circuit to be manufactured using a particular
process must confirm to a set of geometric constraints or rules which are generally
called layout design rules. The main objective of design rules is to manufacture any
circuit with a particular process a high overall yield and reliability while using the
smallest possible silicon area.
The design rules are usually described in two ways:
1. Micron rules in which the layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of absolute dimensions in
micro meters.
2. Lambda based rules are based on a single parameter λ which leads to a simple set of
rules for the designer, allows for scaling of the designs to a limited extent. This feature
may help to give designs a longer lifetime.
Design rules for wires (nMOS and CMOS):

Transistor design rules (nMOS, pMOS and CMOS):
Contacts (nMOS and CMOS):

Contacts polysilicon to diffusion (nMOS only in the main text)

Particular rules for p-well CMOS process

EXPERIMENTAL PROCEDURE
SCHEMATIC PROCEDURE:
1. Open S-edit; then create a new design file
File→ New→ New design and save the file with design name.
2. Then add the library files
Add→ Documents→ Tanner EDA→ Tanner tools v13.0→ Libraries→
All→All.tanner
3. To open the schematic view, select schematic in view 0 and then click ok.
Cell→ New view→ Ok
4. Draw the design and then check for errors and then save the design.
5. Then generate the net list program of schematic.
Tools→ T-spice.
6. Then add the necessary modeling and input commands to the net-list and then save
and run simulation.
7. Output waveforms will be generated in W-Edit
LAYOUT PROCEDURE:
1. Open the layout edit create a new cell and save the cell.
2. Create the design layout and save it.
3. Check for the design rule errors by clicking on DRC.
4. Extract the layout design by going to
Tools→ extract setup→ tanner EDA →tanner tools v 13.0→L-edit and LVS→tech→
Generic_250nm→ Generic_250nm.ext.
5. Run the extract.
6. Generate the net list on T-spice by forcing the input command and run the net list then
observe waveform in W-edit.

1. CMOS INVERTER
AIM:
To draw the schematic and layout of the Inverter and to verify the simulation
results using Tanner Tools v13.0
APPARATUS:
1. Tanner Tools v 13.0
2. PC
THEORY:
The inverter is universally accepted as the most basic logic gate doing a
Boolean operation on a single input variable. Fig.1 depicts the symbol, truth table and
a general structure of a CMOS inverter. As shown, the simple structure consists of a
combination of an pMOS transistor at the top and a nMOS transistor at the bottom.
Fig.1: Symbol, circuit structure and truth table of a CMOS inverter
SCHEMATIC DIAGRAM:

SYMBOL:
LAYOUT:
NETLIST:
.model nmos nmos(level=1 vto=1)
.model pmos pmos(level=1 vto=-1)
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 Z A Gnd 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Z A Vdd Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
********* Simulation Settings - Analysis section *********
vdd vdd gnd dc 5v

********* Simulation Settings - Additional SPICE commands *********

VA A gnd BIT ({10101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
.tran 1n 20n
.print v(A) v(Z)
.end
OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the Inverter is drawn and simulation

results are verified using Tanner Tools v13.0

2. UNIVERSAL GATES
AIM:
To draw the schematic and layout of the NAND & NOR gates and to verify
the simulation results using Tanner Tools v13.0
APPARATUS:
 Tanner Tools v 13.0
 PC
THEORY:
Notice how transistors Q1 and Q3 resemble the series-connected complementary

pair from the inverter circuit. Both are controlled by the same input signal (input A),
the upper transistor turning off and the lower transistor turning on when the input is
“high” (1), and vice versa. Notice also how transistors Q2 and Q4 are similarly
controlled by the same input signal (input B), and how they will also exhibit the same
on/off behavior for the same input logic levels. The upper transistors of both pairs (Q1
and Q2) have their source and drain terminals paralleled, while the lower transistors
(Q3 and Q4) are series-connected. What this means is that the output will go “high” (1)
if either top transistor saturates, and will go “low” Only if both lower transistors
saturate. The following sequence of illustrations shows the Behavior of this NAND
gate for all four possibilities of input logic levels (00, 01, 10, and 11):
A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate,
except that its transistors are differently arranged. Instead of two paralleled sourcing

(upper) transistors connected to Vdd and two series-connected sinking (lower)

transistors connected to ground, the NOR gate uses two series-connected sourcing
transistors and two parallel-connected sinking transistors.
SCHEMATIC DIAGRAM:
NAND:
NOR:
SYMBOL:

LAYOUT:
NAND
NOR

NETLIST:
NAND:

MNMOS_1 Z B N_1 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_1 A Gnd 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Vdd B Z Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
vdd vdd gnd dc 5v
delay=0.1n) AC 5
VB B gnd BIT ({0101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
.tran 1n 20n
.print v(A) v(B) v(Z)
.end
NOR:
PD=6.8u

MNMOS_2 Gnd B Z 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p

PD=6.8u
MPMOS_1 Z A N_1 Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_1 B Vdd Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
vdd vdd gnd dc 5v
delay=0.1n) AC 5
delay=0.1n) AC 5
.tran 1n 20n
.print v(A) v(B) v(Z)
.end
OUTPUT WAVEFORMS:
NAND

NOR
RESULT:
The schematic and layout of the NAND and NOR are drawn and simulation

3. FULL ADDER
AIM:
To draw the schematic and layout of the Full Adder and to verify the
simulation results using Tanner Tools v13.0
APPARATUS:
 PC
THEORY:
A full adder is a logical circuit that performs an addition operation on three
one-bit binary numbers. The full adders produce a sum of the two inputs and carry
value. Fig.1 depicts the symbol, truth table and a general structure of a full adder. As
shown, the simple structure consists of a combination of logic gates (AND, OR and
XOR).
The full adder is usually a component in a cascade of adders, which add 8, 16,
32, etc. bit binary numbers. The circuit produces a two-bit output, output carry and
sum typically represented by the signals Cout and S. A full adder can be implemented
in many different

Ways such as with a custom transistor circuit or composed of other gates. One
example implementation is given below using logic gates.
In this implementation, the final OR gate before the carry-out output may be
replaced by an XOR gate without altering the resulting logic. Using only two types of
gates is convenient if the circuit is being implemented using simple IC chips which
contain only one gate type per chip.
SCHEMATIC DIAGRAM:
SYMBOL:

LAYOUT:
NETLIST:
*************** Subcircuits *****************
.subckt Cell0 A Z Gnd Vdd
PD=6.8u
PD=6.8u
.ends
.subckt Cell1 A B Z Gnd Vdd

PD=6.8u
PD=6.8u
PD=6.8u


PD=6.8u
.ends

PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
.ends

XCell0_1 N_1 Z Gnd Vdd Cell0
XCell1_1 A B N_1 Gnd Vdd Cell1
.ends

.ends

XCell2_1 A N_1 N_2 Gnd Vdd Cell2
XCell2_2 B N_3 N_4 Gnd Vdd Cell2
XCell4_1 N_2 N_4 Z Gnd Vdd Cell4
XCell0_1 B N_1 Gnd Vdd Cell0
XCell0_2 A N_3 Gnd Vdd Cell0
.ends

.subckt Cell6 A B Carry Sum Gnd Vdd

XCell2_1 A B Carry Gnd Vdd Cell2
XCell5_1 A B Sum Gnd Vdd Cell5
.ends
XCell4_2 N_3 N_2 Carry Gnd Vdd Cell4

XCell6_1 A B N_2 N_1 Gnd Vdd Cell6
XCell6_2 N_1 C N_3 Sum Gnd Vdd Cell6

vdd vdd gnd dc 5v
delay=0.1n) AC 5
delay=0.1n) AC 5
VC C gnd BIT ({01010101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
.tran 1n 20n
.print v(A) v(B) v(C) v(Sum) v(Carry)
.end

OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the Full Adder is drawn and simulation results are
verified using Tanner Tools v13.0

4. FULL SUBTRACTOR
AIM:
To draw the schematic and layout of the Full Subtractor and to verify the
APPARATUS:
3. Tanner Tools v 13.0
4. PC
THEORY:
A full subtractor is a combinational circuit that performs subtraction involving
three bits, namely minuend, subtrahend, and borrow-in. Fig.1 depicts the symbol,
truth table and a general structure of a full Subtractor. As shown, the simple structure
consists of a combination of logic gates (AND, OR,NOT and XOR).
As in the case of the addition using logic gates, a full Subtractor is made by
combining two half-subtractors and an additional OR-gate. A full Subtractor has the
borrow in capability and so allows cascading which results in the possibility of multi-
bit subtraction.
Fig.1: Symbol, circuit structure and truth table of a full subtractor

SCHEMATIC DIAGRAM:
SYMBOL:
LAYOUT:

NETLIST:
*************** Subcircuits *****************
PD=6.8u
PD=6.8u
.ends

PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
.ends

PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u

.ends

.ends

.ends

XCell2_1 A N_1 N_2 Gnd Vdd Cell2
XCell2_2 B N_3 N_4 Gnd Vdd Cell2
XCell4_1 N_2 N_4 Z Gnd Vdd Cell4
XCell0_2 A N_3 Gnd Vdd Cell0
.ends
.subckt Cell6 A B Carry Sum Gnd Vdd

XCell2_1 A B Carry Gnd Vdd Cell2
XCell5_1 A B Sum Gnd Vdd Cell5
.ends
.subckt Cell7 A B C Carry Sum Gnd Vdd

XCell4_2 N_3 N_2 Carry Gnd Vdd Cell4
XCell6_1 A B N_2 N_1 Gnd Vdd Cell6
XCell6_2 N_1 C N_3 Sum Gnd Vdd Cell6
.ends
XCell0_3 N_3 Borrow Gnd Vdd Cell0
XCell7_1 A N_2 N_1 N_3 Difference Gnd Vdd Cell7

XCell0_2 C N_1 Gnd Vdd Cell0

vdd vdd gnd dc 5v
delay=0.1n) AC 5
delay=0.1n) AC 5
VC C gnd BIT ({01010101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
.tran 1n 20n
.print v(A) v(B) v(C) v(Difference) v(Borrow)
.end
OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the Full Subtractor is drawn and simulation

5. SR LATCH
AIM:
To draw the schematic and layout of the SR Latch and to verify the simulation
APPARATUS:
 PC
THEORY:
Latches and flip-flops are the basic elements for storing Information. Latch is
an electronic device that can be used to store one bit of information. RS latch have
two inputs, A bistable Multivibrator has two stable states, as indicated by the prefix bi
in its name. Typically, one state is referred to as set and the other as reset. The
simplest bistable device, therefore, is known as a set-reset, or S-R, latch. S is called
set and R is called reset..Fig.1 depicts the symbol, truth table and a general structure
of a D latch. As shown, the simple structure consists of a combination of logic gates
(NOR gates).
Fig.1: Symbol, circuit structure and truth table of a RS latch

The S input is used to produce HIGH on Q (i.e. store binary 1 in flip-flop). The R
input is used to produce LOW on Q (i.e. store binary 0 in flip-flop). Q' is Q
complementary output, so it always holds the opposite value of Q.
The output of the S-R latch depends on current as well as previous inputs or
state, and its state (value stored) can change as soon as its inputs changeThe Q and Q
bar outputs are supposed to be in opposite states. Making both the S and R inputs
equal to 1 results in both Q and Q bar being 0. For this reason, having both S
and R equal to 1 is called an invalid or illegal state.
SCHEMATIC DIAGRAM:
SYMBOL:

LAYOUT:
NETLIST:
*************** Subcircuits *****************
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
.ends
XCell1_2 Q N_2 Qb Gnd Vdd Cell1
XCell1_3 E R N_2 Gnd Vdd Cell1
XCell1_4 S E N_1 Gnd Vdd Cell1

XCell1_1 N_1 Qb Q Gnd Vdd Cell1

vdd vdd gnd dc 5v
VS S gnd BIT ({0011} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VR R gnd BIT ({0101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VE E gnd BIT ({1111} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
.tran 1n 20n
.print v(S) v(R) v(E) v(Q) v(Qb)
.end
OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the SR Latch is drawn and simulation results are

6. D LATCH
AIM:
To draw the schematic and layout of the D Latch and to verify the simulation
APPARATUS:
 PC
THEORY:
Latches and flip-flops are the basic elements for storing information. Latch is
an electronic device that can be used to store one bit of information. The D latch is
used to capture, or 'latch' the logic level which is present on the Data line when the
clock input is high. Fig.1 depicts the symbol, truth table and a general structure of a D
latch. As shown, the simple structure consists of a combination of logic gates (NAND
and NOT gates).

SCHEMATIC DIAGRAM:
SYMBOL:
LAYOUT:

NETLIST:
*************** Subcircuits *****************
PD=6.8u
PD=6.8u
.ends

PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
.ends
.subckt Cell9 E Q Qb R S Gnd Vdd

.ends
XCell0_1 D N_1 Gnd Vdd Cell0
XCell9_1 E Q Qb N_1 D Gnd Vdd Cell9


vdd vdd gnd dc 5v
VD D gnd BIT ({0011} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VE E gnd BIT ({1111} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
.tran 1n 20n
.print v(D) v(E) v(Q) v(Qb)
.end
OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the D Latch is drawn and simulation results are

7. ASYNCHRONOUS COUNTER
AIM:
To draw the schematic and layout of the Asynchronous Counter and to verify
APPARATUS:
 PC
THEORY:
we know that binary count sequences follow a pattern of octave (factor of
2) frequency division, and that Master slave J-K flip-flop multivibrators set up for the
“toggle” mode are capable of performing this type of frequency division, we can
envision a circuit made up of several Master slave J-K flip-flops, cascaded to produce
four bits of output. The main problem facing us is to determine how to connect these
flip-flops together so that they toggle at the right times to produce the proper binary
sequence. Examine the following binary count sequence, paying attention to patterns
preceding the “toggling” of a bit between 0 and 1:
If we used flip-flops with negative-edge triggering (bubble symbols on the
clock inputs), we could simply connect the clock input of each flip-flop to the Q
output of the flip- flop before it, so that when the bit before it changes from a 1 to a 0,
the “falling edge” of that signal would “clock” the next flip-flop to toggle the next bit:
Fig.1: circuit structure and truth table of a asynchronous counter

As you can see, the more bits that toggle with a given clock pulse, the more
severe the accumulated delay time from LSB to MSB. When a clock pulse occurs at
such a transition point (say, on the transition from 0111 to 1000), the output bits will
“ripple” in sequence from LSB to MSB, as each succeeding bit toggles and
commands the next bit to toggle as well, with a small amount of propagation delay
between each bit toggle. If we take a close-up look at this effect during the transition
from 0111 to 1000. Instead of cleanly transitioning from a “0111” output to a “1000”
output, the counter circuit will very quickly ripple from 0111 to 0110 to 0100 to 0000
to 1000, or from 7 to 6 to 4 to 0 and then to 8. This behavior earns the counter circuit
the name of ripple counter, or asynchronous counter.
SCHEMATIC DIAGRAM:
LAYOUT:
NETLIST:
*************** Subcircuits *****************
PD=6.8u
PD=6.8u

.ends
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
.ends
.subckt Cell9 E Q Qb R S Gnd Vdd
.ends
.subckt Cell10 D E Q Qb Gnd Vdd

XCell9_1 E Q Qb N_1 D Gnd Vdd Cell9
XCell0_1 D N_1 Gnd Vdd Cell0
.ends
.subckt Cell12 CLK D Q Qb Gnd Vdd

XCell10_1 D CLK N_1 N_2 Gnd Vdd Cell10
XCell9_1 N_3 Q Qb N_2 N_1 Gnd Vdd Cell9
XCell0_2 CLK N_3 Gnd Vdd Cell0
.ends
XCell12_1 CLK N_1 Q0 N_1 Gnd Vdd Cell12
XCell12_2 Q0 N_2 Q1 N_2 Gnd Vdd Cell12


vdd vdd gnd dc 5v
VCLK CLK gnd PULSE (0 5 0 0.1n 0.1n 1.25n 2.5n)
.tran 1n 40n
.print v(CLK) v(Q0) v(Q1) v(Q2) v(Q3)
.end
OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the Asynchronous Counter is drawn and
simulation results are verified using Tanner Tools v13.0

8. SRAM
AIM:
To draw the schematic and layout of the SRAM and to verify the simulation
APPARATUS:
 PC
THEORY:
SRAM (static RAM) is random access memory (RAM) that retains data bits in
its memory as long as power is being supplied. Unlike dynamic RAM (DRAM),
which stores bits in cells consisting of a capacitor and a transistor, SRAM does not
have to be periodically refreshed. Static RAM provides faster access to data and is
more expensive than DRAM.
A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored
on four transistors (M1, M2, M3, and M4) that form two cross-coupled inverters. This
storage cell has two stable states which are used to denote 0 and 1. Two additional
access transistors serve to control the access to a storage cell during read and write
operations. In addition to such six-transistor (6T) SRAM, other kinds of SRAM chips
use 4, 8, 10 (4T, 8T, 10T SRAM), or more transistors per bit. Four-transistor SRAM
is quite common in stand-alone SRAM devices, implemented in special processes
with an extra layer of poly silicon, allowing for very high-resistance pull-up resistors.
The principal drawback of using 4T SRAM is increased static power due to the
constant current flow through one of the pull-down transistors.

SCHEMATIC DIAGRAM:
LAYOUT:
NETLIST:
VVpwr Vpwr gnd SIN (0 5 1G 0) AC 5

*************** Subcircuits *****************

PD=6.8u
PD=6.8u
.ends
*-------- Devices: SPICE.ORDER == 0 --------
XBusStimulus_1 N_1 N_1 N_1 N_1 N_1 N_1 N_1 N_1 Gnd BusStimulus
BusValue=255 HighVoltage=Vpwr
XCell0_1 N_3 Ob Gnd Vdd Cell0
XCell0_2 Ob O Gnd Vdd Cell0
MNMOS_1 N_1 WR N_3 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_3 RST O 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 O RD N_1 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VRD RD gnd BIT ({00000101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VWR WR gnd BIT ({01010000} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VRST RST gnd BIT ({00000101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5

.tran 1n 20n
.print v(RD) v(WR) v(RST) v(O) v(Ob)
.end
OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the SRAM is drawn and simulation results are

9. DIFFERENTIAL AMPLIFIER
AIM:
To draw the schematic and layout of the Differential Amplifier and to verify
APPARATUS:
 PC
THEORY:
The amplifier, which amplifies the difference between two voltages is called
Differential Amplifier. It is used to provide high voltage gain and high common mode
rejection ratio. It has another characteristic such as very low input bias current, very
low offset voltage and very high input impedance. Differential amplifier can operate
in two modes which are differential mode and common mode. Common mode type
gives result of zero output while differential mode gives a result of high output, hence
this amplifier has high common mode rejection ratio. If two input voltages are equal,
then the differential amplifier gives an output voltage of almost zero volt and if the
two input voltages are not equal the differential amplifier gives high output voltage.
Fig.1.Circuit diagram of Differential amplifier

The NMOS transistor is biased with positive gate to source voltage (Vgs=1.8V) and
drain to source voltage (Vds=1.5V) whereas the body is connected to a source. The
PMOS transistor is biased with negative gate to source voltage (Vgs=-1.8V) and drain
to source voltage (Vds=-1.5V) whereas body is connected to source.

SCHEMATIC DIAGRAM:
LAYOUT:
NETLIST:


MNMOS_1 N_1 V1 N_2 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_2 V2 Vout 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_2 Vb Gnd 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Vout N_1 Vdd Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MPMOS_2 Vdd N_1 N_1 Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

vdd vdd gnd dc 5v
VV1 V1 gnd BIT ({0011} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VV2 V2 gnd BIT ({0101} pw=5n lt=2.5n ht=2.5n on=5 off=0 rt=0.1n ft=0.1n
delay=0.1n) AC 5
VVb Vb gnd dc 2v
.tran 1n 20n
.print v(V1) v(V2) v(Vout)
.end
OUTPUT WAVEFORMS:

RESULT:
The schematic and layout of the Differential Amplifier is drawn and simulation

10. RING OSCILLATOR

AIM:
To draw the schematic and layout of the Ring Oscillator and to verify the
APPARATUS:
 PC
THEORY:
A five stage CMOS ring oscillator, is shown in Figure below. A ring oscillator
comprises of an odd number of CMOS inverters. The output of each inverter is used
as input for the next one. The last output is fed back to the first inverter. Because of
the delay time of each stage the whole circuit spontaneously starts oscillating at a
certain frequency. The frequency depends on the number of stages and the delay
time of the inverters as follows
SCHEMATIC DIAGRAM:

LAYOUT:
NETLIST:
*************** Subcircuits *****************
PD=6.8u
PD=6.8u
.ends
XCell0_3 N_2 Q Gnd Vdd Cell0
XCell0_1 Q N_1 Gnd Vdd Cell0
XCell0_2 N_1 N_2 Gnd Vdd Cell0
vdd vdd gnd dc 5v
.tran 0.01n 20n
.print v(Q)
.end

OUTPUT WAVEFORMS:
RESULT:
The schematic and layout of the Ring Oscillator is drawn and simulation

Vlsi Laboratory: List of Experiments

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DEPARTMENT OF E.C.E Page 1

DEPARTMENT OF E.C.E Page 2

Transistor design rules (nMOS, pMOS and CMOS):

Contacts (nMOS and CMOS):

DEPARTMENT OF E.C.E Page 3

Contacts polysilicon to diffusion (nMOS only in the main text)

DEPARTMENT OF E.C.E Page 4

Particular rules for p-well CMOS process

DEPARTMENT OF E.C.E Page 5

DEPARTMENT OF E.C.E Page 6

Fig.1: Symbol, circuit structure and truth table of a CMOS inverter

DEPARTMENT OF E.C.E Page 7

DEPARTMENT OF E.C.E Page 8

********* Simulation Settings - Additional SPICE commands *********

The schematic and layout of the Inverter is drawn and simulation

DEPARTMENT OF E.C.E Page 9

Notice how transistors Q1 and Q3 resemble the series-connected complementary

DEPARTMENT OF E.C.E Page 10

(upper) transistors connected to Vdd and two series-connected sinking (lower)

DEPARTMENT OF E.C.E Page 11

DEPARTMENT OF E.C.E Page 12

*-------- Devices: SPICE.ORDER > 0 --------

DEPARTMENT OF E.C.E Page 13

MNMOS_2 Gnd B Z 0 NMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p

DEPARTMENT OF E.C.E Page 14

DEPARTMENT OF E.C.E Page 15

DEPARTMENT OF E.C.E Page 16

DEPARTMENT OF E.C.E Page 17

.subckt Cell1 A B Z Gnd Vdd

DEPARTMENT OF E.C.E Page 18

MPMOS_2 Z A Vdd Vdd PMOS W=520n L=130n AS=2.25p PS=6.8u AD=2.25p

.subckt Cell3 A B Z Gnd Vdd

.subckt Cell2 A B Z Gnd Vdd

.subckt Cell4 A B Z Gnd Vdd

.subckt Cell5 A B Z Gnd Vdd

DEPARTMENT OF E.C.E Page 19

.subckt Cell6 A B Carry Sum Gnd Vdd

********* Simulation Settings - Parameters and SPICE Options *********

XCell4_2 N_3 N_2 Carry Gnd Vdd Cell4

********* Simulation Settings - Analysis section *********

********* Simulation Settings - Additional SPICE commands *********

DEPARTMENT OF E.C.E Page 20

DEPARTMENT OF E.C.E Page 21

Fig.1: Symbol, circuit structure and truth table of a full subtractor

DEPARTMENT OF E.C.E Page 22

DEPARTMENT OF E.C.E Page 23

.subckt Cell1 A B Z Gnd Vdd

.subckt Cell3 A B Z Gnd Vdd

DEPARTMENT OF E.C.E Page 24

.subckt Cell2 A B Z Gnd Vdd

.subckt Cell4 A B Z Gnd Vdd

.subckt Cell5 A B Z Gnd Vdd

.subckt Cell6 A B Carry Sum Gnd Vdd

.subckt Cell7 A B C Carry Sum Gnd Vdd

DEPARTMENT OF E.C.E Page 25

XCell0_2 C N_1 Gnd Vdd Cell0

DEPARTMENT OF E.C.E Page 26

Fig.1: Symbol, circuit structure and truth table of a RS latch

DEPARTMENT OF E.C.E Page 27

DEPARTMENT OF E.C.E Page 28

DEPARTMENT OF E.C.E Page 29

* Simulation Settings - Additional SPICE commands *

* Simulation Settings - Parameters and SPICE Options *

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *

* Simulation Settings - Analysis section *

* Simulation Settings - Analysis section *

* Subcircuits ***

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *

* Simulation Settings - Parameters and SPICE Options *

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *