1 The mnemonic that is placed before the arithmetic operation is

performed is
A. AAA
B. AAS
C. AAM
D. AAD
ANSWER: D

2 The Carry flag is undefined after performing the operation

A. AAA
B. ADC
C. AAD
D. AAM
ANSWER: C

3 The instruction that performs logical AND operation and the result of
the operation is not available is
A. AAA
B. TEST
C. AND
D. XOR
ANSWER: B

4 In the RCL instruction, the contents of the destination operand

undergoes function as
A. carry flag is pushed into MSB & LSB is pushed into carry flag
B. auxiliary flag is pushed into LSB & MSB is pushed into carry flag
C. parity flag is pushed into MSB & LSB is pushed into carry flag
D. carry flag is pushed into LSB & MSB is pushed into carry flag
ANSWER: D

5 The instruction that is used as prefix to an instruction to execute it

repeatedly until the CX register becomes zero is
A. SCAS
B. REP
C. CMPS
D. STOS
ANSWER: B

6 The instructions that are used to call a subroutine from a main program
and return to the main program after execution of called function are
A. CALL,JMP
B. JMP,IRET
C. CALL,RET
D. JMP,RET
ANSWER: C

7 The instruction that unconditionally transfers the control of execution

to the specified address is
A. CALL
B. JMP
C. RET
D. IRET
ANSWER: B
8 Which instruction cannot force the 8086 processor out of ‘halt’ state?
A. Interrupt request
B. Reset
C. both interrupt request and reset
D. Hold

ANSWER: D

9 NOP instruction introduces

A. Address
B. Delay
C. Memory location
D. None
ANSWER: B

10 Which of the following is not a machine controlled instruction?

A. HLT
B. CLC
C. LOCK
D. ESC
ANSWER: B

11 What is the output of the following code when SI=93ADh, CF=0

SHR SI, 1
A. SI= 94D6h CF=1
B. SI= 49D4h CF=0
C. SI= 49D6h CF=1
D. SI= 94D3h CF=0
ANSWER: C

12 The assembler directive used to reserve byte or bytes of memory

locations in the available memory
A. DB
B. DA
C. DC
D. DD
ANSWER: A

13 The _____ directive updates the location counter to the next even
address
A. ENDP
B. EQU
C. END
D. EVEN
ANSWER: D

14 The instruction, “INC” increases the contents of the specified

register or memory location by
A. 2
B. 0
C. 1
D. 3
ANSWER: C
15 The instruction that subtracts 1 from the contents of the specified
register/memory location is
A. INC
B. SUBB
C. SUB
D. DEC
ANSWER: D

16 The instruction that enables subtraction with borrow is

A. DEC
B. SUB
C. SBB
D. None of the mentioned
ANSWER: C

17 The semiconductor memories are organised as ….. dimension(s) of array

of memory locations.
A. one dimensional
B. two dimensional
C. three dimensional
D. none
ANSWER: B

18 If a location is selected, then all the bits in it are accessible

using a group of conductors called
A. control bus
B. address bus
C. data bus
D. None
ANSWER: C

19 To address a memory location out of N memory locations, the number of

address lines required is
A. log N (to the base 2)
B. log N (to the base 10)
C. log N (to the base e)
D. log (2N) (to the base e)
ANSWER: A

20 If the microprocessor has 10 address lines, then the number of memory

locations it is able to address is
A. 512
B. 1024
C. 2048
D. none
ANSWER: B

21 In static memory, the upper 8-bit bank of available 16-bit memory chip
is called
A. upper address memory bank
B. even address memory bank
C. static upper memory
D. odd address memory bank
ANSWER: D

22 In static memory, the lower 8-bit bank of available 16-bit memory

chip is called
A. lower address memory bank
B. even address memory bank
C. static lower memory bank
D. odd address memory bank
ANSWER: B

23 In most of the cases, the method used for decoding that may be used
to minimise the required hardware is
A. absolute decoding
B. non-linear decoding
C. linear decoding
D. none
ANSWER: C

24 To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are
arranged in
A. parallel
B. serial
C. both serial and parallel
D. neither serial nor parallel
ANSWER: A

25 The flag that acts as Borrow flag in the instruction, SBB is

A. direction flag
B. carry flag
C. parity flag
D. trap flag
ANSWER: B
26 In general, the source operand of an instruction can be
A. memory location
B. register
C. immediate data
D. all the above

ANSWER: D

27 If (address line) Ao=0 then, the status of address and memory are
A. address is even and memory is in ROM
B. address is odd and memory is in ROM
C. address is even and memory is in RAM
D. address is odd and memory is in RAM
ANSWER: C

28 If at a time Ao and BHE(active low) both are zero then, the chip(s)
selected will be
A. RAM
B. ROM
C. RAM and ROM
D. ONLY RAM
ANSWER: C
29 Dynamic ROM requires _________cycle
A. Refresher
B. BUS
c: Address
D. control
ANSWER: A