Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity ROM24*256 is

Port (ADIN: in STD_LOGIC_VECTOR (3 down to 0);

COND14: out STD_LOGIC;

COND13: out STD_LOGIC;

PL : out STD_LOGIC;

BOP10: out STD_LOGIC;

BOP09: out STD_LOGIC;

BOP08: out STD_LOGIC;

ADOUT: out STD_LOGIC_VECTOR (7 down to 0));

End ROM24*256;

Architecture behavioral of ROM24*256 is signal ROMOUT : STD_LOGIC_VECTOR (21 down to 0);

Begin

ROMOUT<= ” “ when ADIN= x”00” else

” “ when ADIN= x”01” else

” “ when ADIN= x”34” else;

DTOUT(3 down to 0) <=ROMOUT(20 down to 17)

COND14<=ROMOUT(14);

COND13<=ROMOUT(13);

PL<=ROMOUT(12);

BOP10<=ROMOUT(10);

BOP09<=ROMOUT(9);

BOP08<=ROMOUT(8);

ADOUT (7 down to 0)<=ROMOUT(7 down to 0);

End behavioral;