62 (IJCNS) International Journal of Computer and Network Security,

Vol. 2, No. 9, September 2010

A Novel design of High Speed Adders Using

Quaternary Signed Digit Number System
Reena Rani1, L.K. Singh2 and Neelam Sharma 3
1
B.S.A. College of Engineering & Technology, Mathura
Uttar Pradesh, India
reena_rani1331@yahoo.co.in

2
Dr. R.M.L. Avadh University Faizabad, Uttar Pradesh, India
proflksingh@yahoo.com
3
Institute of Engg. & Technology, Alwar, Rajasthan, India.
neelam_sr@yahoo.com

The paper is structured as follows: Section 2 presents the

Abstract: We proposed fast adders based on Quaternary signed
digit number system. Quaternary Signed Digit number system in
arithmetic circuits has the advantage of constant addition time
irrespective of word length. Arithmetic operations in digital
signal processing applications still suffer from problems
including propagation delay and circuit complexity. QSD
number representation allows a method of fast
addition/subtraction because the carry propagation chains are
eliminated and hence it reduces the propagation time. In QSD,
each digit can be represented by a number from -3 to 3. The
design of QSD adder is carried out using FPGA tools. The
designs are simulated using Modelsim SE 6.4 software and
synthesized using Leonardo Spectrum.
Keywords: Carry free addition, Fast computing, FPGA, VLSI.
1. Introduction
Arithmetic operations play an important role in various
digital systems such as computers, process controllers,
signal processors computer graphics and image processing.
Recent advances in technologies for integrated circuits make
large scale arithmetic circuits suitable for VLSI
implementation. However, arithmetic operations still suffer
from known problems including limited number of bits,
propagation time delay, and circuit complexity [1].
Now, the flexibility of field programmable gate arrays
(FPGAs) allows the rapid development of high performance
custom hardware [12]. By selecting arithmetic algorithms
suited to the FPGA technology and subsequently applying
optimal mapping strategies, high performance FPGA
implementations can be developed [5].
In this paper, we propose a high speed QSD arithmetic
logic unit which is capable of carry free addition, borrow
free subtraction, up-down count and multiply operations.
The QSD addition/subtraction operation employs a fixed
number of minterms for any operand size.
Signed digit number system offers the possibility of carry
free addition. QSD Adder / QSD Multiplier circuits are
logic circuits designed to perform high-speed arithmetic
operations. In QSD number system carry propagation chain
are eliminated which reduce the computation time
substantially, thus enhancing the speed of the machine [7].
Quaternary Signed digit number system. In Section 3, we
Presented the Adder design using QSD number system
which contains two step additions. Section 4 presents
simulation results. Section 5 presents results
implementation. Then we provide our conclusions in
Section 6.
2. Quaternary Signed Digit numbers
QSD numbers are represented using 3-bit 2’s complement
notation. Each number can be represented by:
n -1
D = ∑ Χi 4 i
i=0
Where Xi can be any value from the set { 3, 2, 1, 0, 1, 2, 3 } for
producing an appropriate decimal representation. A QSD
negative number is the QSD complement of QSD positive
number [2] i.e 3 ' = 3, 3' = 3 , 2 ' = 2, 2’ = 2 , 1' = 1, 1' = 1.
For digital implementation, large number of digits such as
64, 128, or more can be implemented with constant delay. A
higher radix based signed- digit number system, such as
quaternary signed digit (QSD) number system, allows
higher information storage density, less complexity, fewer
system components and fewer cascaded gates and
operations. A high speed and area effective adders and
multipliers can be implemented using this technique.
For example
Conversion of (43)10 to QSD number
For n = 3, the number can be converted as
(43)10 = 2 × 42 + 2 × 41 + 3 × 40 = (223)QSD
The same number can be represented in another way as
(43)10 = 3 × 42 + 1 × 41 + 1 × 40 = (3 11)QSD
The number can be represented in one more way as
(43)10 = 2 × 42 + 3 × 41 + 1 × 40 = (23 1)QSD
Similarly one more representation is
(43)10 = 3 × 42 + 2 × 41 + 3 × 40 = (3 2 3)QSD
As a QSD negative number is the QSD complement of
the QSD positive number. So
(-43)10 = ( 2 2 3 )QSD = ( 3 11)QSD = ( 2 3 1)QSD = ( 3 2 3 )QSD
 (IJCNS) International Journal of Computer and Network Security, 63
Vol. 2, No. 9, September 2010

3. Adder Design two rules are chosen. The chosen intermediate carry and
intermediate sum are listed in the last column of Table 2 as
3.9 Design Algorithm the QSD coded number.
Table 2: The Intermediate Carry and Sum Between -6 to 6
Arithmetic has played an important role in human
civilization especially in the field of science, engineering
and technology. The everlasting need for higher computing
power and processing speed in a wide range of information
processing applications are placing stringent demands for
fast computation on digital computer design.
Recent advances in technologies for integrated circuits
make large scale arithmetic circuits suitable for VLSI
implementation [9]. However, arithmetic operations still
suffer from known problems including limited number of
bits, propagation time delay, and circuit complexity [6].
With recent advances of integrated circuits technology
higher radix circuits are becoming a reality.
Addition is the most important arithmetic operation in
digital computation. A carry-free addition is highly
desirable as the number of digits becomes large. We can
achieve carry-free addition by exploiting the redundancy of
QSD numbers and the QSD addition. The redundancy
allows multiple representations of any integer quantity i.e. This addition process can be well understood by following
example.
(-5)10 = ( 2 3)QSD = ( 11)QSD
There are two steps involved in the carry-free addition Example: To perform QSD addition of two numbers A =
[3]. The first step generates an intermediate carry and sum 107 and B = -233.
from the addend and augend. The second step combines the First convert the decimal number to their equivalent QSD
intermediate sum of the current digit with the carry of the representation:
lower significant digit[10]. (107)10 = 2 × 43 + 2 × 42 + 3 × 41 + 1 × 40 = (2 2 3 1 )QSD
To prevent carry from further rippling, we define two
rules. The first rule states that the magnitude of the (233)10 = 3 × 43 + 3 × 42 + 2 × 41 + 1 × 40 = (33 2 1)QSD
intermediate sum must be less than or equal to 2. The Hence, (-233)10 = ( 3 3 2 1 )QSD
second rule states that the magnitude of the carry must be Now the addition of two QSD numbers can be done as
less than or equal to 1.Consequently, the magnitude of the follows:
second step output cannot be greater than 3 which can be
represented by a single-digit QSD number; hence no further A = 107 2 2 3 1
carry is required. In step 1, all possible input pairs of the B = -233 2
3 3 1
addend and augend are considered. The output ranges from
Decimal
-6 to 6 as shown in Table 1. -1 -5 5 -2
Sum
Table 1: The ouputs of All Possible Combinations of a Pair IC 0 1 1 0
of Addend (A) and Augend(B) IS 1 1 1 2
S 2 0 1 2
Cout 0

The sum output is ( 2 01 2 )QSD which is equivalent to (-

126)10 and carry output is 0.
The QSD adder design process will carry two stages for
addition. The first stage generates intermediate carry and
sum according to the defined rules. In the second stage the
intermediate carry from the lower significant digit is added
to the intermediate sum of current digit which results in
carry free output. In this step the current digit can always
absorb the carry-in from the lower digit.

In the step 1 QSD adder, the range of output is from -6 to 3.10 Step 1 Adder Design
+6 which can be represented in the intermediate carry and
The step 1 QSD adder accepts QSD number as the input and
sum in QSD format as shown in Table 2 [4]. We can see in
gives intermediate carry and sum as the output. Figure 1
the first column of Table 2 that some numbers have multiple
shows the step 1 adder block as the intermediate carry and
representations, but only those that meet the above defined
sum circuit.
 64 (IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 9, September 2010

Table 3: The Mapping Between Inputs and Outputs of the

Second Step QSD Adder

Figure 1. The intermediate Carry and Sum Generator

The range of input numbers can vary from -3 to +3, so the

addition result will vary from -6 to +6 which needs two
QSD digits. The lower significant digit serves as sum and
most significant digit serves as carry. The generation of the
carry can be avoided by mapping the two digits into a pair of
intermediate sum and intermediate carry such that the nth
intermediate sum and the (n-1)th intermediate carry never
form any carry generating pair (3,3), (3,2), (3,1), ( 3 , 3 ),
( 3 , 2 ), ( 3 , 1 )[13] .
Both inputs and outputs can be encoded in 3-bit 2’s
complement binary number [8]. The mapping between the
inputs, addend and augend, and the outputs, the
intermediate carry and sum considered in binary format.
3.11 Step 2 Adder Design
In step 2, the intermediate carry from the lower significant
digit is added to the sum of the current digit to produce the
final result. The addition in this step produces no carry
because the current digit can always absorb the carry-in
from the lower digit [11]. The step 2 adder accepts 3.4 Single Digit QSD Adder design
intermediate carry and intermediate sum as input and gives The single digit QSD adder accepts two QSD numbers as
single digit carry free QSD output. Figure 2 shows the inputs and gives carry and sum as the output. Figure 3
block diagram for step 2 adder. shows the single digit QSD adder . At the input side, the
addend Ai is represented by 3 variable input as a2, a1, a0 and
the augend Bi is represented by 3 variable input as b2, b1, b0.
At the output side, the carry C is represented by C2, C1, C0
and the sum S is represented by S2, S1, S0. The addend and
augend can be selected in the range of -3 to +3.
The addition result according to the specified rules can
be represented in the range of -3 to +3. The addition result
is a single digit QSD number; hence no further carry is
Figure 2. The Second Step QSD Adder required. Both inputs and outputs are encoded in 3-bit 2’s
complement binary number.As the range of carry is from -1
The range of the intermediate carry is -1 to +1 and the to +1, it can be represented in 2 bit binary number but we
range of the intermediate sum is -2 to +2. The addition take the 3 bit representation for the bit compatibility with
result of intermediate carry and intermediate sum lies in the the sum, So C2 = C1.
range of -3 to +3, which can be represented by single digit
QSD number. Table 3 shows all possible combinations of
the summation between the intermediate carry and the sum.
Table 3: Outputs of All Possible Combinations of A pair of
Intermediate carry (IC) and Sum(IS)

Figure 3. Single Digit QSD Adder

The internal logic diagram for single digit QSD adder is

shown in figure 4.
 (IJCNS) International Journal of Computer and Network Security, 65
Vol. 2, No. 9, September 2010

4. Simulation Results
The four digit QSD adder written in VHDL, compiled
and simulated using Modelsim SE 6.4. The simulated result
for 4-digit QSD adders is shown in figure 6.

Figure 5. Simulated Result of Four Digit QSD Adder

5. Result Implementation

Design Synthesized on Xilinx VIRTEX-IV FPGA devices

using Leonardo Spectrum from Mentor Graphics. Figure 7
shows the RTL schematic for four digit QSD adder.

Figure 6. RTL Schematic of Four Digit QSD Adder

The delay for QSD adder is 2ns which is the minimum delay
in comparision to Ripple Carry Adder (RCA) and Carry
Look Ahead (CLA) Adder The QSD adders have constant
delay of 2ns for higher number of bits. Figure 8 shows the
Figure 4. Single Digit QSD Adder Structure timing comparision chart for RCA, CLA Adder and QSD
Adders.
66 (IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 9, September 2010

Symposium on circuits and Systems, august 1996, pp.

180 187-189.
170
160 [8] A. A. S. Awwal and J. U. Ahmed, “Fast Carry Free
150
140 Adder Design Using QSD Number System”, Proc.
130 IEEE National Aerospace and Electronic Conference,
120
110 RCA Vol. 2, 1993, pp 1085-1090.
Delay (ns)

100
90 CLA [9] Hwang K., ComputerArithmatic Principles
80
70 QSD Architecture and Design. New York : Wiley, 1979.
60
50 [10] Reena Rani, Neelam Sharma, L.K.Singh, “Fast
40 Computing using Signed Digit Number System” proc.
30
20 IEEE International Conference On Control,
10
0 Automation, Communication And Energy
Conservation -2009, 4th-6th June 2009, pp.1-4.
16

32

64
4
8

128
Number of Bits
Figure 7. Timing Comparision of RCA, CLA and QSD
Adder
6. Conclusion
We have presented an algorithm for radix-4 carry free
addition which is suitable for realizing high-speed compact
arithmetic VLSI circuits. The QSD addition scheme is
independent of the processed bit strings length and thus it is
very fast. QSD based addition technique is also memory
efficient since more information can be encoded in fewer
digits than its BSD addition counterpart.
References
[1] A. Avizienis, "Signed-digit number representations for
fast parallel arithmetic," IRE Trans. on Electronic
Computers, vol.- EC-10, pp. 389-400, 1961.
[2] Abdallah K. Cherri, “Canonical Quaternary
Arithmetic Based on Optical Content- Addressable
Memory (CAM)”, Proc. IEEE National Aerospace and
Electronic Conference, vol.- 2, 1996, pp. 655-661.
[3] Reena Rani, Upasana Agrawal, Neelam Sharma, L.K.
Singh, “High Speed Arithmetic Logical Unit using
Quaternary Signed Digit Number System”
International Journal Of Electronic Engineering
Research, ISSN 0975 – 6450, Volume 2 Number 3,
2010 pp. 383–391.
[4] Songpol Ongwattanakul, Phaisit Chewputtanagul,
David J. Jackson, Kenneth G. Ricks, “Quaternary
Arithmetic Logic Unit on a Programmable Logic
Device”, proc. IEEE conference, 2001.
[5] Reena Rani, Neelam Sharma, L.K.Singh, “FPGA
Implementation of Fast Adders using Quaternary
Signed Digit Number System” proc. IEEE
International Conference on Emerging Trends in
Electronic and Photonic Devices & Systems
(ELECTRO-2009), 2009, pp 132-135.
[6] Behrooz Parhami, “Carry-Free Addition of Recoded
Binary Signed-Digit Numbers”, IEEE Transactions on
Computers, Vol. 37, No. 11, pp. 1470-1476, November
1988.
[7] A. T. M. Shafiqul Khalid, A. A. S. Awwal and O. N.
Garcia, “Digital Design of Higher Radix Quaternary
Carry Free Parallel Adder”, Proc. 39th Midwest
[11] N. Takagi, H. Yasuura, and S. Yajima, “High Speed
VLSI Multiplication Algorithm with a Redundant
Binary Addition Tree, ” IEEE Trans. Comp., C-34, pp.
789-795, 1985
[12] A.A.S Awwal, Syed M. Munir, A.T.M. Shafiqul
Khalid, Howard E. Michel and O. N. Garcia,
“Multivalued Optical Parallel Computation Using An
Optical Programmable Logic Array”, Informatica,
vol. 24, No. 4,2000, pp. 467-473.
[13] P. K. Dakhole, D.G. Wakde, “ Multi Digit
Quaternary adder on Programmable Device : Design
and verification” International Conference on
Electronic Design, 2008, 1-3 Dec, pp. 1-4.
Authors Profile
Reena Rani obtained M.Tech (VLSI design)
from Banasthali Vidyapith, Rajasthan,
INDIA. Currently pursuing Ph.D. in
Electronics from Dr. Ram Manohar Lohiya,
Avadh University. Wnner of Prize 3rd from
AMIETE council of INDIA. Her research
area is VLSI design.She is Senior Lecturer
in department of Electronics &
Communication Engineering at B.S.A. College of Engineering &
Technology, Mathura (U.P.), and Associate Member Institution of
Electronics and Telecommunication Engineering.
Lakshami Kant Singh obtained Ph.D.
(Optoelectronics) in 1976. He is currently
Director and Professor in Dr. Ram Manohar
Lohiya, Avadh University, Faizabad.U.P.
India. Posts hold was dean faculty of
science, Pro-Vice Chancellor. He has over
35 years of teaching experience and has
published around 30 research papers and
articles. He is a member of the Institution of
Engineers, Institution of Electronics and Telecommunication
Engineering, Delhi, and Computer Society of India.
Neelam Sharma received the PhD and
M.Tech from U.P.T.U., Lucknow UP
and B.E. from Thapar Institute of
Engineering and Technology, Punjab
India. Presently she is Professor in the
Department of Electronics and
Instrumentation Engineering, Institute of
Engineering and Technology, Alwar,
Raj. India. Her current research interests
are Computer Architecture, Neural Networks, VLSI, FPGA, etc.
She has twenty-five research publications and convened number of
sponsored research projects. She is member of IEEE, IETE and IE.