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AGENDA

▪ Introduction to Timing Analysis

▪ What, Why, Where, STA?
▪ Concepts of STA
▪ Delays
▪ Timing Paths
▪ Clocks and their network effects
▪ Timing Arcs, Timing Paths and Path Groups
▪ Setup, Hold, Recovery and Removal Timing Checks
▪ Timing Exceptions

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 TIMING ANALYSIS
▪ Timing Analysis is a method of checking the timing correctness of any design
▪ Checking timing correctness requires the ability to measure delay through the circuit during various steps in the
design flow.
▪ Synthesis, Place & Route, Optimizations
▪ Timing correctness has to be checked across a range of PVT variations
▪ Verify device core and periphery works at specified frequency
▪ Identify poorly driven / overhead nets
▪ Identify nodes with large rise / fall time
▪ Types of Timing Analysis
▪ Static Timing Analysis
▪ Dynamic Timing Analysis

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 STATIC TIMING ANALYSIS (STA)
▪ STA is a method of analyzing, debugging and validating the timing performance of a design without having to
simulate it
▪ Much faster than timing-driven, gate-level simulation
▪ due to usage of simplified timing models
▪ Vector generation NOT required
▪ Proper circuit functionality is not checked

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 DTA V/S STA

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 CONCEPTS OF STATIC TIMING ANALYSIS

▪ Delays
▪ Clocks
▪ Timing Arcs
▪ Timing Paths
▪ Setup, Hold, Recovery and Removal Timing Checks
▪ Timing Exceptions

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 DELAYS
▪ Delay is the time taken by a signal to propagate through a gate or net (wire).
▪ The delay for a signal to propagate through a cell / gate is called Gate of Cell Delay and for a wire / net is
called Net Delay.
▪ Delays related to Cells:
▪ Intrinsic Delay
▪ Cell Delay / Propagation Delay / Gate Delay
▪ Transition Time or Slew
▪ Contamination Delay
▪ Delays related to Net:
▪ Net Delay / Interconnect Delay / Wire Delay / Extrinsic Delay / Flight Time

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 CELL DELAY / GATE DELAY / PROPAGATION DELAY
▪ Propagation delay of a gate or cell is the time it takes for a change of a
signal level at the input pin to result in a change at the output pin.

▪ Gate Delay = Function of (Input Slew Time, Output Load)

▪ Where, Output Load = Cnet + Cpin, Cnet = Net Cpacitance
▪ Cpin = pin capacitance of the driven cell
▪ Cell delay is also same as Gate delay

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 TEST YOUR UNDERSTANDING…
▪ Is the delay for Rise and Fall same? Why?
▪ No. There is a different delay corresponding to rise and fall
transitions. Rise and Fall delays depend on sizes of N & P transistors in
the design.
▪ What happens to the delay if the Load is increased?
▪ As the load increases the delay increases.
▪ What happens to Cell Delay if input transition time is reduced?
▪ Cell Delay decreases if the input transition time is reduced.

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 EFFECTS OF NET GEOMETRY ON R & C
Capacitance Resistance

Length

Width

Thickness

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TEST YOUR UNDERSTANDING…

▪ Which is more significant? Cell Delays or Wire Delays?

▪ In similar geometries wire delays are more significant than Cell Delays and Vice Versa.

▪ If Input transition is increased, what will be the effect on Net Delay?

▪ Transition Times have no effect on Net Delays.

▪ Do Nets have different Rise and Fall Delays?

▪ No. Unlike Cells, there are no active devices to make the Rise and Fall delays different in Nets .

▪ What was more significant in 0.35µm Technology compared to 90nm Technology?

▪ Cell Delay were more significant in 0.35µm Technology because the delay offered by cells was more
than the Net delay. In 90nm Technology, Wire delays dominate.

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 CONCEPTS OF STATIC TIMING ANALYSIS
▪ Delays
▪ Clocks
▪ Timing Arcs
▪ Timing Paths
▪ Setup, Hold, Recovery and Removal Timing Checks
▪ Timing Exceptions

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 CLOCKS

▪ Why do we need clocks?

▪ We need outputs to depend on inputs as well as previous outputs (state bits of FSM)
▪ Clocks provide a reference to determine previous, present, and next state bits
▪ Flip-Flops and Latches use clock to hold state bits
▪ Flip-Flops and Latches move the data in lockstep, advancing the data a stage ahead at each
clock tick
▪ Can you implement FSM without clocks?
▪ Yes, provided delay through each path in the logic as exactly same
▪ In this case, state is in gates and wires

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 CLOCK LATENCY
▪ Clock Latency is the time taken by a clock signal to reach the leaf pins (e.g. clock pin of Flip-Flops)
from the source of clock.

▪ Clock Latency is also referred as ‘ Insertion Delay’

FF2
D Q

Clock Latency
CLK
CLK FF2
D Q

CLK

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 TYPES OF CLOCK LATENCY
▪ Clock Latency can be seen in two ways- Source Latency and Network Latency
▪ Source Latency is the delay of clock from oscillator to clock port
▪ Network Latency is the delay from clock port to clock end port

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16
 CAUSES OF CLOCK SKEW

▪ Different length wires (wires have delay)

▪ Different gates (buffers) on the paths

▪ Temperature variations

▪ Flip-Flops that clock on different edges (need to invert clock for some Flop-Flops)

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 POSITIVE CLOCK SKEW
▪ Positive Clock Skew occurs when the clock reaches the receiving
register later than it reaches the register sending data to the
receiving register.

Input Output
D Q D Q

DFF DFF
D1 D2
1ns
CLK
Clock at D1

In this example, D1 gets clock at 0ns, Clock at D2

D2 gets clock at 1 ns,
Skew
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Skew = 1ns – 0ns = +1ns
 NEGATIVE CLOCK SKEW

▪ Negative Clock Skew occurs when the clock reaches the receiving register earlier
than it reaches the register sending data to the receiving register.
Input Output
D Q D Q

DFF DFF
D1 D2

1ns
CLK

In this example, D1 gets clock at 1ns,

Clock at D1
D2 gets clock at 0 ns,
Skew = 0ns – 1ns = – 1ns Clock at D2

19 Skew
TEST YOUR UNDERSTANDING…

▪ What is the difference between Slew and Skew?

▪ Slew refers to rise or fall time of a signal.

▪ Skew is the time difference of arrival of clock at two or more endpoints.

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 TEST YOUR UNDERSTANDING…
C x z
Combo
Delay

FF1 FF2
y

▪ Is there a Clock Skew in this design?

▪ There is no skew in this design if net lengths used for
clock routing is matching.
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 CLOCK JITTER
▪ Clock Jitter is the uncertainty about when the clock edges occur.
▪ Clock Jitter is caused by many factors
▪ Imperfections in the clock oscillator performance
▪ Supply Voltage / temperature variation causing delay to vary in clock buffers
▪ Xtalk

Launch Edge Capture Edge

T-j

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 MULTIPLE CLOCKS

▪ Synchronous Clocks
▪ Two clocks are synchronous with respect to each other if they share a common source and have a fixed
phase relationship.

▪ Asynchronous Clocks
▪ Two clocks are asynchronous with respect to each other if they don’t have a fixed phase relationship.

▪ Exclusive Clocks
▪ Two clocks are exclusive if only one of them is active at a given time.

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 SYNCHRONOUS CLOCKS
▪ Unless specified, tools (primetime/dc) assumes clocks to be synchronous
▪ You might see timing paths launched by one clock and captured by another
▪ Clock waveforms are synchronized at time 0

CK1
D Q CK2
U1

CLK QN
CK2
CK1

create_clock -period 2 -name CK1 [get_ports CKP]

24 create_generated_clock -name CK2 -source [get_ports CKP]\
-divide_by 2 [get_pins U1/Q]
 ASYNCHRONOUS CLOCKS
▪ Explicitly specify timing between paths of asynchronous clocks as
false paths with set_false_path or with clock groups.
▪ If there is no timing relationship between clocks, you cannot calculate slack

CK1 CP1

CK2 CP2

create_clock -period 2 -name CK1 [get_ports CP1]

create_clock -period 2 -name CK1 [get_ports CP2]
25 create_clock_groups -asynchronous -group {CK1} \ -group {CK2}
 EXPLICIT CLOCKS

▪ Out of CLK and TCLK, only one can be acting on the circuit at any given time

FF1 FF2

CLK

TCLK

create_clock -period 2 -name CK1 [get_ports CP1]

create_clock -period 2 -name CK1 [get_ports CP2]
set_clock_groups –logically_exclusive -group {CLK} \ -group {TCLK}
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 CONCEPTS OF STATIC TIMING ANALYSIS

▪ Delays
▪ Clocks
▪ Timing Arcs
▪ Timing Paths
▪ Setup, Hold, Recovery and Removal Timing Checks
▪ Timing Exceptions

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 TIMING ARC

▪ Timing Arc is a point path in an electronic network that specifies timing

information
▪ The timing information can be:
▪ Delay of the Cell
▪ Setup Time
▪ Hold Time
▪ Recovery Time
▪ Removal Time
▪ Minimum Pulse Width Time

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 TYPES OF TIMING ARC

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 UNATE TIMING ARC
Timing Arc
of buffer

Input Output
Rise A Y Rise
Fall Fall
Bufx1

Timing Arc
Positive Unate of Inverter

Input Output
A Y
Rise Fall
Fall Rise
Invx1

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Negative Unate
 More on Timing Arcs..

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 TEST YOUR UNDERSTANDING…
In1
A
Output
Y
In2
B

Invx1

Sel

What is the sense of the signal at the output?

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 DIFFERENT TIMING ARC
▪ Delay Arcs
▪ Normally Input Transition V/s Output Load Arcs
▪ A ? Y of inverter (invx1) specifies the propagation delay of the cell
▪ CK ? Q of Flip-Flop (dffrx1)

▪ Set Arcs and Hold Arcs

▪ Input Transition V/s Clock Pin Transition
▪ CK -> D of Flip-Flop (dffrx1) specifies the setup time

▪ Minimum Pulse Width Arcs

▪ CK -> CK of any Flip-Flop specifies a minimum pulse width for clocks

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 CONCEPTS OF STATIC TIMING ANALYSIS
▪ Delays
▪ Clocks
▪ Timing Arcs
▪ Timing Paths
▪ Setup, Hold, Recovery and Removal Timing Checks
▪ Timing Exceptions

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 TIMING PATH
▪ Timing Path is a point to point path in a design that can propagate data
▪ From one Flip-Flop to another (reg to reg path)
▪ Input port to Output port
▪ Input port to Flip-Flop
▪ A Flip-Flop to a Output port

▪ Each path has certain valid start and end points

▪ Start Points: Input ports, CLK pins of sequential cell
▪ End Points: Output ports, D pins of sequential cell

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 TYPES OF TIMING PATH
The four paths are:
▪ Path 1: Primary Input to D Input of sequential cell
▪ Path 2: Primary Input to Primary Output
▪ Path 3: Clock to D Input of next sequential cell
▪ Path 4: Clock to Primary Output

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 ??

??
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 CONCEPTS OF STATIC TIMING ANALYSIS

▪ Delays

▪ Clocks

▪ Timing Arcs

▪ Timing Paths

▪ Setup, Hold, Recovery and Removal Timing Checks

▪ Timing Exceptions

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 SETUP & HOLD TIME
▪ Setup Time
▪ For an edge triggered sequential element, the Setup Time is the time interval before the active
clock edge during which the data should remain unchanged.
▪ Setup Timing violation occurs when the data changes too late, missing the time at which it should
advance

▪ Hold Time
▪ Time interval after the active clock edge during which the data should remain unchanged.
▪ A hold timing violation occurs when data changes too quickly after clock’s active transition

IN Data must Constrained Pin

Remain Stable

D Q

Clock CLK
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 SETUP CHECK

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 Hold Check

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 Complete list of checks that STA does ::

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 RECALLING PATH GROUPS ..

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 WHAT ABOUT LATCHES??

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 WHAT ARE MULTI CYCLE PATHS ( MCPS)

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 COMBINATIONAL FEEDBACK LOOPS

Using a dynamic
simulation tool
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