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DATA BOOK

Lattice°
Semiconductor
Corporation
GAL PRODUCT INDEX

Commercial Grade Devices


DEVICE PINS tpo
tpD (ns) Icc (rnA)
Icc (mA) DESCRIPTION
DESCRIPTION PAGE
PAGE
GAL16V8NB 20 7.5,10,15,25
7.5, 10, 15,25 55,90,115
55, 90, 115 FCMOS
E2CMOS Generic PLD 2-1
2-1
GAL20V8NB 24 7.5,10,15,25
7.5, 10, 15,25 55,90,115
55, 90, 115 E2CMOS
E2CMOS Generic PLD 2-25
2-25
GAL18V10
CALI 8V10 20 15,20
15,20 115
115 E2CMOS
E2CMOS Universal PLO
PLD 2-47
2-47
GAL22V10/B 24 10,15,25
10, 1 5 , 2 5 130
130 E2CMOS
E2CMOS Universal PLD
PLO 2-61
2-61
GAL26CV12 28 15,
15, 20 130
130 E2CMOS
E2CMOS Universal PLD
PLO 2-81
2-81
GAL20RA10
GAL2ORA10 24 12,15,20,30
12, 15, 20, 30 100
100 E2CMOS
E2CMOS Asynchronous PLD
PLO 2-95
2-95
GAL6001 24 30,35
30, 35 150
150 E2CMOS
E2CMOS FPLA 2-109
2-109
ispGAL 16Z8
i5pGAL16Z8 24 20, 25 90
90 E2CMOS
E2CMOS In-System-Programmable PLD
PLO 2-121
2-121

Industrial Grade Devices


DEVICE PINS tpD (ns)
tpD (ns) Icc (rnA)
Icc (mA) DESCRIPTION
DESCRIPTION PAGE
PAGE
GAL16V8NB 20 10,15,20,25
10, 15, 20, 25 65, 130 E2CMOS
E2CMOS Generic PLD
PLO 2-1
2-1
GAL20V8A 24 15,20,25
15, 20, 25 65,
65, 130 FCMOS
E2CMOS Generic PLD
PLO 2-25
2-25
GAL18V10 20 20 125
125 E2CMOS
E2CMOS Universal PLD 2-47
2-47
GAL22V10/B 24 15,20,25
15, 20, 25 150
150 E2CMOS
E2CMOS Universal PLD
PLO 2-61
2-61
GAL26CV12 28 20 150
150 E2CMOS
E2CMOS Universal PLO
PLD 2-81
2-81
GAL20RA10
GAL2ORA10 24 20 120
120 E2CMOS
E2CMOS Asynchronous PLD
PLO 2-95
2-95

MIL-STD-883C Grade Devices


DEVICE PINS (ns)
tpD (ns)
tpD Icc
Icc (rnA)
(mA) DESCRIPTION
DESCRIPTION PAGE
PAGE
GAL16V8NB 20 10,15,20,25,30
10, 15, 20, 25, 30 65,130
65, 130 E2CMOS
E2CMOS Generic PLD
PLO 3-5
3-5
GAL20V8A 24 15,20,25,30
15, 20, 25, 30 65,130
65, 130 E2CMOS
E2CMOS Generic PLD
PLO 3-13
3-13
GAL22V10/B 24 15,20,25,30
15, 20, 25, 30 150
150 E2CMOS
E2CMOS Universal PLO
PLD 3-19
3-19
GAL20RA10
GAL2ORA10 24 20, 25 120
120 E2CMOS
E2CMOS Asynchronous PLD 3-27
3-27
line.
Thank you for your interest in our high performance GAL product line.

As the inventor and world leader of the GALS device, we at Lattice are
GAL· device,
dedicated to providing you with the fastest, highest quality and most
flexible solution to your logic needs.

In our new 1991 Data


Data Book, you will see that we have substantially
expanded our product line and continue to offer the world's highest
performance CMOS programmable logic devices.

We look forward to satisfying all of your programmable logic requirements.

Sinc rely,

.Steven Laub
Vice President and General Manager
iiii
GAL Data Book
1991

f/J
.l..I
Lattice®
Semiconductor
IldISnaficto!dincr®
Corporation
Corporation
ic
iiiiii
itLLattke®
/;Lattire°
.l.J SemiconducUJr
Semiconductor
Corporation
Corporation
Copyright ©
1 91991 Lattice Semiconductor Corporation
9 1 Lattice Corporation

Generic Array Logic, Latch-Lock, and RFT are


are trademarks
trademarks of
of Lattice Semiconductor
Semiconductor Corporation.
Corporation.
ispGAL, GAL, PCMOS and UltraMOS are
GAL, E2CMOS are registered
registered trademarks
trademarks of Lattice
Lattice Semiconductor
Semiconductor Corporation.
Corporation.

PAL is a registered trademark of Advanced Micro Devices, Inc.

Products discussed in this literature are


are covered
covered by U.S. Patents No.4,
U.S. Patents 761,768, 4,766,569,
No. 4,761,768, 4,766,569, 4,833,646,
4,833,646, 4,852,044,
4,852,044,
4,855,954, 4,879,688, 4,887,239 and 4,896,296 issued to to Lattice
Lattice Semiconductor
Semiconductor Corporation,
Corporation, and
and by
by U.S.
U.S. and
and
foreign patents pending.
foreign patents pending.

LATTICE
LATTICE SEMICONDUCTOR CORP.
5555
5555 Northeast Moore Court
Hillsboro, Oregon 97124
Hillsboro, Oregon 97124 U.S.A.
U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
TELEX 277338 LSC
TELEX 277338 LSC UR
UR

iv
iv
Section 1:
1: Introduction
Introduction to Generic Array Logic
Introduction to Generic Array Logic 1-1
1-1
II
Section 2: GAL Datasheets 22
Datasheet Levels 2-ii
2-ii
GAL16V8NB
GAL16V8A1B 2-1
2-1
GAL20V8A/B
GAL20V8A1B 2-25
2-25
GAL18V10 2-47
2-47
GAL22V10/B 2-61
2-61
GAL26CV12 2-81
2-81
GAL2ORA10
GAL20RA10 2-95
2-95
GAL6001 2-109
2-109
ispGAL16Z8 2-121
2-121

Section 3: GAL Military Products


Military Program Overview 3-1
3-1
33
MIL-STD-883C Flow 3-2
3-2
Military Ordering Information 3-3
3-3
GAL16V8A/B
GAL 16V8A1B Military Datasheet 3-5
3-5
GAL20V8A Military
Military Datasheet 3-13
3-13
GAL22V10/B Military Datasheet 3-19
3-19
GAL2ORA10
GAL20RA 10 Military Datasheet 3-27
3-27

Section 4: Quality and Reliability


Quality Assurance Program 4-1
4-1 44
Qualification Program 4-3
4-3
E2CMOS Testability Improves Quality 4-5
4-5

Section 5: Technical Notes


GAL Metastability Report 5-1
5-1 55
Latch-up Protection
Protection 5-17
5-17

Section 6: Article
Article Reprints
Avoid the Pitfalls of High-Speed Logic Design 6-1
6-1 66
Extending the 22V1
22V10 0 EPLD 6-7
6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6-9
6-9
Multiple Factors Define True Cost of PLDs 6-13
6-13
Section 7: General Information
Development Tools 7-1
7-1 77
Copying PAL, EPLD & PEEL Patterns into GAL Devices 7-3
7-3
GAL Product Line Cross Reference 7-5
7-5
Package Thermal Resistance 7-8
7-8
Package Diagrams 7-9
7-9
Tape-and-Reel Specifications 7-16
7-16
Sales Offices 7-17
7-17

1-i
1-i
1-ii
Introduction to wit .J
Logic a t
Generic Array Logic I

INTRODUCTION THE GAL


THE GAL CONCEPT
CONCEPT I

Lattice Semiconductor,
Lattice Semiconductor, located
located in
in Hillsboro,
Hillsboro, Oregon,
Oregon, was
was E2CMOS -— THE
EZCMOS THE IDEAL
IDEAL TECHNOLOGY
TECHNOLOGY
founded in I
founded in 1983
1983 toto design,
design, develop
develop and
and manufacture
manufacture Of the three
Of three major
major technologies
technologies available
available for
for producing
producing
high-performance semiconductor components. It is a firm
high-performancesemiconductorcomponents.ltisafirm PLDs, the
PLDs, the technology
technology of choice
choice is clearly
clearly E2CMOS.
E2CMOS.
belief at
belief at Lattice
Lattice that
that technological
technological evolution
evolution can
can be
be E2CMOSoffers
E2CMOS offerstestability,
testability, quality,
quality, high
high speed,
speed, low
lowpower,
power,
accelerated through
accelerated through the
the continued
continued development
developmentof ofhigher-
higher- and instant erasure.
and erasure.
speed and architecturally superior products.
TESTABILITY
TESTABILITY
GAL devices are ideal for four important reasons:
reasons: The biggest
The biggest advantage
advantage of of E2CMOS
PCMOS over over competing
competing
technologies is its inherent testability.
technologies testability. Capitalizing on
Capitalizing on
1. GAL
GAL devices
devices have
have inherently
inherently superior
superior quality
quality and very fast(1
and veryfast (100ms) erasetimes,
OOms) erase times, Lattice
Lattice repeatedly
repeatedlypatterns
patterns
reliability. and erases
and erases allall devices
devices during
during manufacture.
manufacture. Lattice tests
Lattice tests
eachGAL
each GALdevice
devicefor
forAC,
AC,DC,
DC,and
andfunctional
functionalcharacteristics.
characteristics.
2. GAL devices can directly
directly replace PAL devices in nearly
nearly The
The result
result i is
s guaranteed
guaranteed 100%100% programming
programming and and
every application. functional yields.
functional yields.

3. GAL
GAL devices
devices have
have the
the low
low power
power consumption
consumption of LOW POWER
LOW POWER
CMOS, one-fourth to one-haH
one-half that of
of bipolar devices. Another advantage of E2CMOS
Another E2CMOS technology
technology is the the low
low
powerconsumption
power consumption of of CMOS.
CMOS. CMOS provides users
CMOS provides usersthethe
4. GAL devices utilize Output Logic Macrocells (OLMCs), immediate benefit
immediate benefit ooff decreased
decreased systemsystem powerpower
which allow the user to configure outputs as needed. requirements allowing
requirements allowing for higher reliability
reliability and cooler
running systems. LLow
running o w power CMOS
CMOS technology
technology alsoalso
permits circuit
permits circuit designs
designs of
of much
much higher
higherfunctional
functional density,
density,
because of
because of lower
lower junction
junction temperatures
temperatures and and power
power
requirements on
requirements on Chip.
chip. The user
user benefits
benefits because
because higher
higher
functional density means
functional means further
further reduction
reduction of of chip
chip count
count
and smaller boards
and boards in
in the
the system.
system.

HIGH
HIGH SPEED
Also advantageous
Also advantageous is is the
the very
veryhigh
high speed
speed attainable
attainablewith
with
Lattice's state-of-the-art E2CMOS
Lattice's process. Lattice
PCMOS process. Lattice GAL
GAL
devices are as
devices as fast
fast or
or faster
faster than
than bipolar
bipolar and LJVCMOS
and UVCMOS
PLDs.
PLDs.

PROTOTYPING
PROTOTYPING AND AND ERRORERROR RECOVERY
RECOVERY
Finally, E2CMOS
Finally, E2CMOSgivesgivesthethe user
userinstant
instanterasabilitywith
erasability with no
no
additional handling
additional handling or or special
special packages
packages necessary.
necessary. This
provides ideal
provides ideal products
products for for prototyping
prototyping because
because designs
designs
can be
can be revised
revisedinstantly,
instantly, with
with nonowaste
wasteand
and no
nowaiting.
waiting. On
On
the manufacturing
the manufacturing floorfloor instant
instant erasability
erasability can
can also
also be
be aa
big advantage
big dealing with
advantage for dealing with pattern
pattern changes
changes or or error
error
recovery. If aa GAL
recovery. GAL device
device is is accidentally
accidentally programmed
programmed to to
the wrong
the wrong pattern,
pattern, simply
simply reprogram
reprogramthethe device.
device. No
No other
other
technology offers
technology offers this
this advantage.
advantage.

1-1
1-1
Introduction to
Generic Array Logic
A LOOK AT OTHER TECHNOLOGIES THE
THE GAL ADVANTAGE
ADVANTAGE
Here, the
the technologies
technologies that competecompete with E2CMOS E2CMOS -— GAL GAL devices
devices are are ideal
ideal programmable
programmable logic logic devices
devices
bipolar and UVCMOS -are — are compared with with the E2CMOS because,
the E2CMOS because, as the name implies, implies, they are architecturally
architecturally
approach. generic. Lattice
generic. Lattice has has employed
employed the the macrocell
macrocell approach,
approach,
which allows
allows users users to definedefine the the architecture
architecture and and
BIPOLAR functionality of
functionality of each
eachoutput.
output. The key keybenefit
benefitto tothetheuser
userisis
Bipolar fuse-link technology was the first available available for the the freedom
freedom from from beingbeing restricted
restricted tto o any
any specific
specific
programmable logic logic devices.
devices. Although
Although itit offers
offers high architecture. T This
high architecture. h i s iis s advantageous
advantageous aatt both both the the
speed, itit is
is saddled
saddled with high high power dissipation. High manufacturing level
High manufacturing level and
and thethe design
design level.
level.
power dissipation increases your system power supply
cooling requirements, and limits
and cooling limitsthethefunctional
functionaldensity DESIGN ADVANTAGES
density DESIGN ADVANTAGES
of bipolar devices. Early programmable
Early programmable logic logic devices gave the user user thethe
ability to
ability to specify
specify a function,
function, but but limited
limited them
them to to specific,
specific,
Another weakness of this technology technology is the one-time- predetermined predetermined output output architectures.
architectures. Comparing
Comparing the theGAL
GAL
programmable fuses. Complete testing testing of ofbipolar
bipolar PLDs
PLDsis devicewith
is device withfixed-architecture
fixed-architectureprogrammable
programmablelogic logicdevices
devices
impossible because
because the the fuse
fuse array
array cannot
cannot be tested is
be tested is much
much like
like comparing
comparing these these same
same fixed
fixed PLDs
PLDs with with SSI/
SSI/
before programming. Bipolar Bipolar PLD manufacturers must MSI MSI devices. The The GAL GAL family
family isis the
the next
next generation
generation in in
rely on complex schemes using test rows rows and
and columns
columns to simplified system
to simplified system design. TThe h e user does not have have to
simulate and correlate their device's performance. The search for the architecture
The search architecture that best best suits a particular
particular
result is programming failures at the customer location. design. design. Instead, the theGALGALfamily's
family'sgeneric
genericarchitecture
architecturelets lets
Any misprogrammed
misprogrammed devices devices due due to mistakes during him
mistakes during him configure
configure as as he goes.goes.
prototyping or or errors
errors onon the
the production
production floor must be
because bipolar
discarded because bipolarPLDscannot
P LDs cannotbe bereprogrammed. MANUFACTURING ADVANTAGES
reprogrammed. MANUFACTURING ADVANTAGES
The one-device-does-all
The one-device-does-all approach approach greatlygreatly simplifies
simplifies
UVCMOS manufacturingflow
manufacturing flow.. Inventorying one onegeneric-architecture
generic-architecture
UVCMOS addresses many
UVCMOSaddresses many weaknesses of the bipolar bipolar GALGAL device type type versus
versus having
having to to monitor
monitor and and maintain
maintain
approach but introduces many shortcomings of of its own. many manydifferent
different device
devicetypes,
types, saves
saves money
moneyand andminimizes
minimizes
This technology
technology requiresrequires l eless s s ppower
o w e r aand s paperwork:
n d i is paperwork. Manufacturing
Manufacturingflow flowisismuch
muchsmoother
smootherbecausebecause
reprogrammable, but but reprogrammability
reprogrammability comes comes at the the handling process
the handling process is greatly simplified.simplified. AA generic generiC
expense of slower speeds. architecture
architecture GAL GAL device
device alsoalso reduces
reduces the the risk
risk of of running
running
out of
out of inventory
inventory and and halting
haltingproduction,
production, whichwhichcan canbe bevery
very
Testability is increased over bipolarbipolar since
since the array expensive.
the "fuse" array expensive. ReducedReduced chance chance of of obsolete
obsolete inventory
inventory and and
can be programmed and tested tested by the manufacturer. The easier
by the easier QA tracking ate
QA tracking are additional
additional benefits
benefits of of the
the generic
generic
problem here ill is the
the long (20 minutes) erase times coupled architecture.
timescoupled architecture.
with the requirement of exposing the the devices
devices to to ultraviolet
ultraviolet
THE IDEAL
THE IDEAL PACKAGE
PACKAGE
light for erasing. This becomes a very
erasing. This very expensive step in in
themanLJfacturing
the manufacturing process.
process. Because ofthe of thetime
time involved,
involved, Programmable
Programmable logic
logicdevices
devicesare areideal
idealfordesigningtoday's
for designing today's
patterning and and erasing
erasing is is performed
performed only only once
once — - a systems. Lattice Semiconductor
systems. Lattice Semiconductor believes believes thatthat thethe ideal
ideal
compromised rather than complete functional functional test. design approach should
design approach should be supported
supported with the the ideal
ideal
products.
products. It It was
was on on this
this premise
premise that that GAL
GAL devices
devices were were
Additionally, the devices must be housed in expensive invented. invented. The The ideal
idealdevice-with
device—withaageneric genericarchitecture-
architecture—
windowed packages to allow users to to erase them. Again, fabricated
them. Again, fabricated withwith thethe ideal
ideal process
process technology,
technology, E2CMOS.
E2CMOS.
programming these these devices
devices is is time-consuming
time-consuming and and
cumbersome due to the 20-minute UV exposure exposure required
required
to erase them. As As a a cost-cutting
cost-cutting measure, UVCMOS UVCMOS PLD PLD
manufacturers offertheirdevices
offe r their devices ininwindowless
windowlesspackages.
packages.
Although windowless packages are less expensive, expensive, they they
cannot be completely tested or reprogrammed. These These
factors significantly
significantly detract from the desirability
desirability of this
technology.

1-2
1-2
Section 1: Introduction to Generic Array Logic 1
Introduction to Generic Array Logic 1 - 1 1-1

Section 2: GAL Datasheets


Datasheet Levels
GAL16V8NB
GAL16VSNB
GAL20V8NB
GAL20VSNB 2
2
2
-
-
-
2
i
1
i

5
2-ii
2-1
2-25
at
GAL18V10
GAL1SV10 2 - 4 7 2-47
GAL22V10/B 2 - 6 1 2-61
GAL26CV12 2 - 8 1 2-S1
GAL2ORA10
GAL20RA10 2 - 9 5 2-95
GAL6001 2 - 1 0 9 2-109
ispGAL16Z8
ispGAL16ZS 2 - 1 2 1 2-121

Section 3: GAL Military Products


3
Military Program Overview 3 - 1 3-1
MIL-STD-883C Flow
MIL-STD-S83C 3 - 2 3-2
Military Ordering Information 3 - 3 3-3
GAL16V8NB
GAL 16VSNB Military Datasheet 3 - 5 3-5
GAL20V8A Military Datasheet
GAL20VSA 3 - 1 3 3-13
GAL22V10/B Military Datasheet 3 - 1 9 3-19
GAL2ORA10
GAL20RA 10 Military Datasheet 3 - 2 7 3-27

Section 4: Quality and Reliability


Quality Assurance Program 4 - 1 4-1
4
Qualification Program 4 - 3 4-3
E2CMOS Testability Improves Quality
FCMOS 4 - 5 4-5

Section 5: Technical Notes


GAL Metastability Report 5 - 1 5-1 5
Latch-up Protection 5 - 1 7 5-17

Section 6: Article Reprints


Avoid the Pitfalls of High-Speed Logic Design 6 - 1 6-1 8
Extending the 22V1
22V10 0 EPLD 6 - 7 6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6 - 96-9
Multiple Factors Define True Cost of PLDs 6 - 1 3 6-13

Section 7: General Information


Development Tools 7 - 1 7-1 7
Copying PAL, EPLD & PEEL Patterns into GAL Devices 7 - 37-3
GAL Product Line Cross Reference 7 - 5 7-5.
Package Thermal Resistance 7 - 8 7-S
Package Diagrams 7 - 9 7-9
Tape-and-Reel Specifications 7 - 1 6 7-16
Sales Offices 7 - 1 7 7-17

2-i
2-1
Definition of Datasheet Levels

DEFINITION OF DATASHEET
DATASHEET LEVELS
LEVELS

Datasheet Identification Product Status


Product Status DeflnHlon
Definition

'PA""ii'F't
Preliminary Sampling
Sampling or
Pre-Production
Pre-Production
This
This datasheet contains
data
data will
will be
contains preliminary
be published
published at
preliminary data
at aa later
later date.
data and
and supplementary
date. Lattice
supplementary
Lattice reserves
reserves the
the
right
right to make
make changes
changes at
at any
any time
time without
without notice.
notice.

No Identification Full Production This


This datasheet contains
contains final
final specifications. Lattice reserves
specifications. Lattice reserves the
the
right
right to
to make
make changes
changes at
at any
anytime
time without
without notice.
notice.

2-ii
2-11
[JJtatUce®
Ind /Lattice®
SemioonducWr
Corporation
Corporation
GAL1 6118B
GAL16V8B
GAL1 61113A
GAL16V8A
High Performance E2CMOS
High E2CMOS PLD
PLD
FEATURES FUNCTIONAL BLOCK
FUNCTIONAL BLOCK DIAGRAM
DIAGRAM
• HIGH PERFORMANCE E2CMOS®
ElCMOS· TECHNOLOGY
-— 7.5 ns Maximum Propagation Delay Voc
Vee.
-— Fmax ==100 MHz 20 J
20
-— 5 ns Maximum from Clock Input to
to Data Output
-— TTL Compatible 24 mA Outputs 8 OLIAC 19
19
-— UltraMOS®
UHraMOS· Advanced
Advanced CMOS Technology 19
22 - - D =
• 50%
500/0 to 75')/o
750/0 REDUCTION IN POWER FROM BIPOLAR
-— 75mA Typ I = on Low Power Device
TYP Icc 4 OLMC
18
18
18
-— 45mA Typ TYP lex
Icc on Quarter Power Device 33 — 0 =
• ACTIVE PULL-UPS ON ALL
ALL PINS (GAL16V8B)
OLPAC 17
17
• E2E2 CELL TECHNOLOGY 17
-— Reconfigurable
Reconflgurable Logic
logic 44 - - 0 =
1
-— Reprogrammable Cells OLMC
-1000/0 16
16
— 100% Tested/Guaranteed 100%
1000/0 Yields 16
-— High Speed Electrical Erasure «100ms)
(<100ms) 5 — 0 =
-— 20 Year Data Retention
MAC 15
15
• EIGHT
EIGHT OUTPUT LOGIC MACROCELLS 15
-— Maximum Flexibility
FlexlbllHy for Complex Logic Designs 6
1
-— Programmable Output Polarity OIJAC
-— Also Emulates 2o-pln PAL· Devices with Full Func-
20-pin PAL® 14
14
14
tion/Fuse Map/Parametric CompatlbllHy
tlon/Fuse Compatibility 7
1
• PRELOAD
PRELOAD AND POWER-ON RESET OF ALL
ALL REGISTERS
REGISTERS OLMC 1 3 13
8
-1000/0
— 100% Functional Testability 13
8 =0—
• APPLICATIONS
APPLICATIONS INCLUDE:
-— DMA Control MAC 12
12
-— State Machine Control 12
-— High Speed Graphics Processing 99 — 1 : =
11
-— Standard Logic Speed Upgrade 10

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION PIN
PIN CONFIGURATION
CONFIGURATION
The GAL 16V8B, at 7.5 ns maximum propagation
GAL16V8B, propagation delay
delay time,
time,
combines a high performance CMOS process with Electrically DIP
DIP
(E') floating gate technology to provide the highest speed
Erasable (E2)
performance available in the PlD PLD market. High
High speed erase
erase times
times PLCC
PLCC
«100ms)
(<100ms) allow the devices to be reprogrammed quickly and IICLK
I/CLK Vee
Vcc

efficiently. IIOJQ
trOr0
l'CUC
I VO Veos I /roIO
L K Ve 0/0
The generic architecture provides maximum design flexibility
flexibility by E71:1=111
20 11010
1 1/0/0
allowing the Output logic (OLMC) to be configured by
Logic Macrocell (OlMC) 1vOla
110/0
the user. An An important
important subset of the many architecture con· con- VOID
figurations
figurations possible with the GAL 16V8A1B are the PAL archi-
GAL16V8A/B vOla
V0/0
11010
tectures listed in the table of the
the macrocell description section. GAL16V8A/B
GAL16VSAlB
1vOla
1/010
GAL 16V8AIB devices are capable of
GAL16V8A/B of emulating
emulating any of these
these PAL
PAL Top View
Top View 11010
architectures with full function/fuse maplparametric
map/parametric compatibility.
compatibility. 1VOla
IIOJQ
1
Unique test circuitry and reprogrammable cells allow
allow complete
complete 1VO/Q 1 11010
AC, DC, and functional testing during manufacture. As As a result,
result,
LATTICE is able to guarantee 100%1000/0 field programmability and II CIHO rIIOi
ONO VOla tioto
t a tio/o vOla 1 11010
functionality of all GAL·
GAL® products. LATTICE
LATTICE also guarantees 100 aND
GND
erase/rewrite cycles and data retention in in excess of
of 20 years.
Copyright C1991 Lattice Semiconductor Corp. G
01991 Lattice GAL. PCMOS and UlltaMOS
A L E'CMOS regls..rod trademarks
UltraMOS are registered trademarks 01
of lattice Semiconductor Corp.
Lattice Semiconductor GonorIc "ray
Corp. Generic Logic Is
Array Logic is aatrademarl<
trademark of Lattice SeRiconduc·
of Lattlca Semiconduc-
tor
tor Corp. PAL is
Corp. PAL a registered
Is a registered tradomar1< of Advanced
trademark of Micro Dovlcoo.
Advanced Micro Devices, Inc. The specifications
Inc. The and Information
specifications and information heroin
herein are subject to
are subject to change
change without
without noflca.
notice.

Hillsboro, Oregon 97124, U.S.A.


LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, U.S.A. April
April 1991.Rev.A
1991.1:tev.A
Tel. (503) 681-0118: 1-800-FASTGAL;
1-800-FASTGAL: FAX (503)681-3037
(503) 681-3037 2 - 1 2-1
LLattice®
flJ.Semiconductor
Semiconductor
GAL1
Specifications GAL 6118B
16V8B
Corporation
Corporation GAL16118A
GAL 16V8A·
GALII6V8A/B
GAL 16V8A'B ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)
Tpd(n8) Tsu (n8)
T8U (ns) Teo (ns) icc (mA)
Icc(mA) Ordering #
Ordering Package
Package
7.5 7 55 115
115 GAL16V8B-7LP
GAL16V8B-7LP 20-Pin Plastic
20-Pin Plastic 01
DIPP
115
115 GAL16V8B-7LJ
GAL16V8B-7LJ 20-Lead PLCC
20-Lead PLCC
10 10 77 115
115 GAL16V8B-10LP
GAL16V8B-l0LP 20-Pin Plastic
20-Pin Plastic DIP
DIP
115
115 GAL16V8B-101—I
GAL16V8B-l0LJ 20-Lead PLCC
20-Lead PLCC
115
115 GAL 16V8A-l OLP
GAL16V8A-10LP 20-Pin Plastic
20-Pin Plastic DIP
DIP
115
115 GAL16V8A-l0LJ
GAL16V8A-10LJ 20-Lead PLCC
20-Lead PLCC
15 12 10
10 55
55 GALI6V8A-I50P
GAL16V8A-15QP 20-Pin Plastic
20-Pin Plastic DIP
DIP
55
55 GAL16V8A-I50J
GAL16V8A-150,1 20-Lead
20-Lead PLCC
PLCC
115
115 GAL 16V8A-15LP
GAL16V8A-15LP 20-Pin
20-Pin Plastic
Plastic DIP
DIP
115
115 GAL16V8A-15LJ
GAL16V8A-15LJ 20-Lead PLCC
20-Lead PLCC
25 15
15 12 55
55 GAL 16V8A-250P
GAL16V8A-25QP 20-Pin
20-Pin Plastic
Plastic DIP
DIP
55
55 GAL 16V8A-25QJ
GAL16V8A-25al 20-Lead
20-Lead PLCC
PLCC
90
90 GAL 16V8A-25LP
GAL16V8A-25LP 20-Pin
20-Pin Plastic
Plastic DIP
DIP
90
90 GAL 16V8A-25LJ
GAL16V8A-25LI 20-Lead
20-Lead PLCC
PLCC

Industrial Grade Specifications


Tpd (n8)
(ns) Tsu(ns)
Tsu (ns) Teo
Tco (ns) Icc
icc (mA) Ordering ##
Ordering Package
Package
10
10 10
10 7 130
130 GALI6V8B-l0LPI
GAL16V8B-10LPI 2O-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GAL 16V8B-l0LJI
GAL16V813-10LJI 20-Lead
20-Lead PLCC
PLCC
15 12
12 10 130
130 GAL 16V8B-15LPI
GAL16V8B-15LPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GAL 16V8B-15LJI
GAL16V8B-15LJI 20-Lead
20-Lead PLCC
PLOD
130
130 GAL 16V8A-15LPI
GAL16V8A-15LPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GALI6V8A-15LJI
GAL16V8A-151-11 20-Lead
20-Lead PLCC
PLCC
20 13 11
11 65
65 GAL 16V8A-200PI
GAL16V8A-200PI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
65
65 GAL 16V8A-2OQJI
GAL16V8A-200,11 20-Lead
20-Lead PLCC
PLOD
25 15 12
12 65
65 GAL 16V8A-250PI
GAL16V8A-25QPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
65
65 GAL 16V8A-25QJ1
GAL16V8A-250J1 20-Lead
20-Lead PLCC
PLCC
130
130 GAL 16V8A-25LPI
GAL16V8A-25LPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GAL 16V8A-25LJI
GAL16V8A-25LJI 20-Lead
20-Lead PLCC
PLOD

PART NUMBER DESCRIPTION


DESCRIPTION

XXXXXXXX X X X X X

GAL16V8A D e v i c e Name
GAL16V8B
Speed (ns) _ _ _ _ _ _....J
Speed (ns) lank =
Grade BBlank = Commercial
Commercial
II = Industrial
Industrial
L _ Low Power Power _ _ _ _ _ _ _ _....J ' - - - - - - Package
L = Low Power Power Package PP =Plastic
Plastic DIP
DIP
QQ=-1/4
1/4 Power J.= PLCC
PLCC
2-2
2-2 4/91.Rev.A
4/91.IRev.A
GALI16VBB
Specifications GAL 6169B
1 1 s t Semiconductor
Corporation GAL1
GAL 6118A
16VBA
OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic


macrocell. ItIt should be noted that actual implementation is
is ac- PAL Architectures
PAL Architectures GAL161/8A/6
GALl6V8AlB
software/hardware and is completely
complished by development softwareJhardware completely Emulated by
Emulated by GAL
GA Ll6V8A/B
16V8A1B Global ollie
Global W I C Mode
Mode
transparent to the user.
16R8
16R8 Registered
Registered
There are three global OlMC
There OLMC configuration modes possible: 16R6
16R6 Registered
Registered
simple, complex, and and registered. Details
Details of each of of these
these 16R4
16R4 Registered
Raglstered
modes is illustrated
illustrated in
in the
the following pages. Two
Two global bits,
bits, SYN 16RP8
16RP8 Registered
Raglstered
16RP6
16RPB Registered
Raglstered
and ACO, control the mode configuration for all macrocells. The 16RP4
16RP4 Registered
Raglstered
XOR bit of each macrocell controls the polarity of the
the output
output in any
of the three modes, while the AC1 bit of of each of
of the
the macrocells 16L8
16La Complex
Complex
configuration. These two global and
controls the input/output configuration. and 16 16H8
18H8 Complex
Complex
individual architecture bits define all possible configurations in a 16P8
16P8 Complex
Complex
GAL 16V8A1B. The
GAL16V8A/B. The information given on these architecture bits 10L8
lOLa Simple
Simple
is only to give a better understanding of the the device. Compiler
Compiler 12L6
1216 Simple
Simple
software will transparently set these architecture bits
bits from
from the
the pin
pin 1414
14L4 Simple
Simple
definitions, so the user should not need to directly manipulate 1612
16L2 Simple
Simple
these architecture bits. 10H8
10H8 Simple
Simple
12H6
12H6 Simple
Simple
14H4
14H4 Simple
Simple
The following is a list of the PAL
PAL architectures that
that the
the GAL 16V8A
GAL16V8A 16H2
16H2 Simple
Simple
and GAL16V8B
GAL 16V8B can emulate. IItt also also shows the OlMCOLMC mode 10P8
10P8 Simple
Simple
under which the GAL16V8A/B
GAL16V8A1B emulates the the PAL
PAL architecture. 12P6
12P6 Simple
Simple
14P4
14P4 Simple
Simple
16P2
16P2 Simple
Simple

COMPILER SUPPORT FOR OLMC


Software compilers support the three different global OlMC OLMC In
In registered
registered mode
mode pin and pin
pin 1 and pin 11
11 are
are permanently
permanentlyconfigured
configured
modes as different device types. These device types are listed as
as clock
clock and
and output
output enable,
enable, respectively. These pins
respectively. These pins cannot
cannotbe
be
in the table below. Most
Most compilers have the the ability
ability to
to automati-
automati- configured
configured asas dedicated
dedicated inputs
inputs in
in the
the registered
registered mode.
mode.
cally select the device type, generally based on on the
the register usage
usage
and output enable (OE) usage. RegisterRegister usage on the device In
Incomplex
complex modemode pinpin 1 and
and pin
pin 11
11 become
become dedicated
dedicated inputs
inputsand
and
forces the software to choose the registered mode. All All combi-
combi- use
usethethe feedback
feedbackpaths
pathsofofpin
pin 19 andpin
19 and pin 12
12respectively. Because
respectively. Because
natorial outputs with OE controlled by the product term term will
will force
force of
of this
this feedback
feedback path
path usage,
usage, pin
pin 19
19 and
and pin
pin 12
12 do
do not
not have
have the
the
the software to choose
choose the complex mode. The The software will feedback
feedback option
option in
in this
this mode.
mode.
choose the simple mode only when all outputs are dedicated
combinatorial without OE control. TheThe different device types
types listed In
In simple
simple mode
mode allall feedback
feedback paths
paths of
ofthe
the output
output pins
pins are
are routed
routed
in the table can be used to override the
the automatic device
device selection
selection via
via the
the adjacent
adjacent pins. In doing
pins. In doing so,
so, the
thetwo
two inner
inner most
mostpins
pins ((pins
pins
by the software. For
For further details, refer to
to the compiler
compiler software
software 15
15 and
and 16)
16) will
will not
not have
have the
the feedback
feedback option
option as
as these
these pins
pins are
are
manuals. always
always configured
configured as dedicated
dedicated combinatorial
combinatorial output.
output.

When using compiler software to configure the device, the user


must pay special attention to the
the following
following restrictions in each
mode.

Registered Complex Simple


Simple Auto
Auto Mode
Mode Select
Select
ABEL P16V8R
P1 6V8R P16V8C
P16V8C P16V8AS
P1 6V8AS P16V8
P1 6V8
CUPL G16V8MS G16V8MA
G1 6V8MA G16V8AS
G1 6V8AS G16V8
G1 6V8
LOG/IC GAl16V8
GAL16V8_13R GAl16V8
GAL1 6V8S7C7 GAl16V8
GAL16V8S8 C8 GAL16V8
CALI 6V8
OrCAD-PLD
OrCAD- PLO "Registered"'
"Registered"' "Complex"'
"Complex"' "Simple"'
"Simple"' GAL16V8A
GAL16V8A
PLDeslgner
PLDesigner P16V8R2
P1 6V8R2 P16V8C2
P1 6V8C2 P16V8C2
P16V8C2 P16V8A
P1 6V8A
TANGO-PLD G16V8R
G1 6V8R G16V8C
G1 6V8C G16V8AS3
G16V8AS3
AS G16V8
G1 6V8
1) Used with Configuration
1) Used Configuration keyword.
keyword.
2) Prior to Version
2) Prior Version 2.0
2.0 support.
support.
3) Supported
Supported on Version 1.20 or later.

2-3 4/91.Rev.A
4/91.Rev.A
GAL161/13B
Specifications GAL 16VBB
1 1 1 "itt e r ;
Corporation GAL116VBA
GAL 61113A
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated mode. Dedicated input
mode. input or
oroutput
outputfunctions
functions can
can be
be implemented
implemented
registered outputs or as
as I/O functions. as subsets
as subsets of the VO
of the I/Ofunction.
function.

Archkecture
Architecture configurations available in this mode are similar to
to Registered
Registered outputs
outputs have
have eight
eightproduct
product terms
terms per
per output. VO's
output. VO's
the common 16R8 and 16RP4 devices
devices with
with various
various permutations
permutations have
have seven
seven product
product terms
terms per
per output.
output.
VO and register placement.
of polarity, I/O
The
TheJEDEC
JEDECfuse fusenumbers,
numbers, including
includingthe
theUser
UserElectronic
ElectronicSignature
Signature
All registered macrocells share common clockclock and
and output
output enable
enable (UES)
(UES) fuses
fuses andand the
the Product
Product Term
Term Disable
Disable (PTD)
(PTD) fuses,
fuses, are
are
control pins. Any
Any macrocell can be configured as registered or shown
shown onon the
the logic
logic diagram
diagram onon the
the followihg
following page.
page.
VO. Up to eight registers or up to
I/O. Up eight VO's
to eight I/0's are
are possible
possible in
in this
this

ClK
CLK
---____ .-------.. . . . . . . . -------.. . . . . . -- -----! Registered
Registered Configuration
Configuration for
for Registered
Registered Mode
Mode

-SYN=O.
- SYN=0.
-ACO .. 1.
ACO-1.
-- XOR",O
XOR-0 defines
defines Active
Active Low
LowOutput.
Output.
-- XOR
X0R-1..1 defines Active
Active High
High Output.
Output.
-- AC1 ",0 defines
AC1-0 defines this
this output
output configuration.
configuration.
-- Pin
Pin 1 controls
controls common
common CLK CLKfor
forthe
the registered
registered outputs.
outputs.
-- Pin 11 controls
Pin 11 controls common
common OE OE for
forthe
the registered
registered outputs.
outputs.

·· .. -- Pin
Pin 1 &
OE.
OE.
& Pin 11 are permanently
Pin 11 permanently configured
configured asas CLK
CLK &
&
.. --------.---- . -. -----------.
OE
OE

..... -- .. - .. _- ...... -- ........ -- ...... - ..... .


Combinatorial
Combinatorial Configuration
Configuration for
for Registered
Registered Mode
Mode

-SYN",O.
- SYN=0.
-ACO=1.
- AC0=1.
- XOR
XOR=0 ..Odefines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR-1 ..1 defines Active
Active High
High Output.
Output.
-- AC1
AC1-1=1 defines this
this output
output configuration.
configuration.
-- Pin
Pin 11 & Pin 11 are permanently
Pin 11 permanently configured
configured as
as CLK
CLK &&
OE.
OE.

Note: The development software configures all


all of
of the
the architecture
architecture control
control bits and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.

2-4
2-4 4191.Rev.A
4/91.Rev.A
Lattice® GAL161/13B
Specifications GAL 16V8S
1.,.;
LISemiconductor
Semiconductor
Corporation GAL16118A
GAL 16V8A
Corporation

REGISTERED MODE LOGIC DIAGRAM

.....
DIP &
DIP & PLCC
PLCC Package Pinouts
Plnouts II
I

J
2126
!
0 44 8 8 2 12 1 6 2 020 24
2 4 2 62tI P pm
M
" I.
0000
00(81
1111111111111111111111111M111011 §: OLMC 19
OLMC 19 1 "...,.,
—t>0— C 1 119
9

022'
0224
:§: X0A-2048
XOR·2048
IInumm•Immommommommo

I II
AC1-2120
AC1·2120

0256
0256

1r>0
-
OLIAC 18
OLMC 18 18
0480
X0R-2049
XOR·2049
AC1•2121
AC1·2121

0512
0512

:g: OLMC 17
OLMC 1 C 1117
7
073<
0736 :§:
411mommi
H U M ' XOR•2050
XOR·1050
4E C . ; 3 AC1·2122
AC1.2122
lu
1
0768
0765
IIMIIMMIIIIIIIM1111111111111111111111 OLMC 16 n
OLMC 16 16
0992
D
0912
mmumuni munnimummlionitin XOR·1051
XOR-2051
AC1·2123
AC1-2123

1024
1024
111111111111111111111111111MIIIMERIE
! : ! M I W I T U I L I I I : = P W • • • • • • • " ' " ' " ' "§:
=••••
OLMC15
OLMC 15 1 ....... 1515
.-....
1248
1240 UIUIIIIIIIUIIIII :::IMMIMEMEM1111
zuranraurzmiziEziFFETF:==ii
1110111111101111•1111111191 111k1 11 9 1 1 1 1 1 1 1 f i r r i l i i i
- XOR·1052
XOR-2052
AC1·2124
AC1-2124

1280
1200
1111111111111111111 M I 6 1·
IIIlIIIIIItlIIIIIlIIIlIUItlIIIIII .......
s: M K 14
OLMC 14 -1)0 K J 14
14
1504
::c
D
1504
iiiimiiiiiummol
IME111•1111•11111111111111111
miumummol: .If
XOR·1053
XOR-2053
AC1·2125
AC1-2125

HIIIIIIIIIIIIIIIIIII111111MI6
,,3<
1536

EimimprommErpanur.::;==3222
,..,. OLMC 13
M C 13 1 ....... 1313
1760 §:
1760
nunimmommunnim XOR·1054
X0R-2054
AC1·2126
AC1-2120

IIIIHIIIIIIIHIIIIIHIII 111111E16
1792
1792
IIIIIIMIIIIIIMIIM11111111111111111111
ESEESEEMEMBEFERF-7:=Ersz OLMC 12
OLIE 12 1 12
2016
limmoommoomummol I!S.:::;
-
2016 XOR·1055
.-.... XOR-2055
1111•11111•111111EMEIIIIMIBIEIMEI AC1·2127
AC1-2127
A OE,....,
11
2191
fI4.USEII ElECTRONIC SIGNA
04-USER ELECTRONIC lURE FUSES
SIGNATURE FUSES
12068, 2057, ..•. .... 211 21181
.. 2118
2118, SYN·2192
SYN-2192
Byte71Byte8
Byte7-1Byte ....B y t e 11Byte 0 ACO·2193
A00-2193
M
M L
S5 5 S
B
B BB

4/91.Rev.A
4/91.Rev.A
2-5
2-5
[JJ
.Ii
.
l.J
Lattice-
/Lattice
Semiconductor
Semiconducwr
GAL1
Specifications GAL 61MB
16V8B
Corporation
Corporation . GALI16V8A
GAL 6118A
COMPLEX MODE
In the Complex mode, macrocells are configured as output only pability. Designs
pability. requiring eight
Designs requiring eight I/O's
I/0's can
can be
be implemented
implemented in
inthe
the
or I/O
110 functions. . Registered mode.
Registered mode.

Architecture configurations available in


in this
this mode are similar to
to All
All macrocells
macrocells have
have seven
sevenproduct
product terms
terms per
peroutput.
output. One
One product
product
the common 16L8 and 16P8 devices withwith programmable polarity
polarity term is
term is used
usedfor
for programmable
programmable output
output enable
enable control.
control. Pins and
Pins 1 and
in each macrocell. 11
11 are always
always available
available as
as data
data inputs
inputs into
into the
theAND
AND array.
array.

Up to six I/O's
I/0's are possible
possible in
in this
this mode. Dedicated
Dedicated inputs
inputs or
or The
TheJEDEC
JEDECfuse
fuse numbers
numbers including
includingthe
the UES
UESfuses
fusesand
andPTD
PM fuses
fuses
outputs can be implemented as subsets of the I/O function.
function. The are shown
are shown on
on the
the iogic
logic diagram
diagram on on the
thefollowing
following page.
page.
two outer most macrocells (pins 12 & 19) do not have input ca-
ca-

·......................................................
·
,
.. Combinatorial I/O Configuration
Combinatorial 1/0 Configuration for
for Complex
Complex Mode
Mode

-- SYN.1.
SYN=1.
-ACO-1.
• AC0=1.
-• XOR.O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR.1 defines Active
XOR=1 defines Active High
HighOutput.
Output.
-AC1-1.
-AC1=1.
-- Pin
Pin 13
13 through
through Pin
Pin 18 are
are configured
configured to
to this
thisfunction.
function.
,
..................................................... .

....................................................,
: : Combinatorial
Combinatorial Output
Output Configuration
Configuration for
for Complex
Complex Mode
Mode

Pr7R ·
- SYN.1.
SYN-1.
-ACO-1.
- AC0=1.
-- XOR.O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1.. 1 defines Active
Active High
High Output.
Output.
-- AC1-1.
AC1=1.
-- Pin
Pin 12 and Pin 19
and Pin 19 are
are configured
configured to
to this
this function.
function.
...............................................................:

Note: The development software configures all


all of
of the architecture control bitt;
bits and
and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.

2·6
2-6 4/91.Rev.A
4/91.Rev.A
[[J
I Ld
.J.,,; S
/aLatuoo
em
t tc
iiocnd
SemJoonducUJr
Corporation
eu
co
tr e
GAL116VBB
Specifications GAL 6118B
GAL16118A
GAL 16VBA
COMPLEX MODE LOGIC
LQGIC DIAGRAM
DIAGRAM
& PLCC Package Pinouts
DIP & Pinouts

..., ...
v

.... • • 4 a8 12
12 11
16 20 24
24 2B
28
mJ
PTD
2128

0000

.224
0224
:i=t::=
=1::$
:B=
OLIAC 19
OLMC 19
XOR·2048
X0R-2048
n L:119
':::1

AC1-2120
AC1·2120
D-
.251
0256

<= OLMC 18
OLJAC18 n .... 18

D--
D<8O
0480
-. XOR·2049
X0R-2049
AC1·2121
AC1-2121

0512
0612
:a= M C 17
OLMC 17 n 117

.-...
...,
.731
0716 XOR·2050
XOR-2050
AC1-2122
Ad1-2122 U
.788

-
0768
:R:::::=:
OLMC 16
OLJAC16 Il. -0116

.-...
...,
0902 XOR·2051
X011-2051
ACl·2123
AC1-2123 U
P.M I I1024I I M
I I IIMI E
I I' 11111111111111"1
InEmommillommunmunumm-a:l'•
1024

<= OLMC15
IIIEFEEMEISESIEMEIREIREBE-.- OLMC 15 Il.....L>oJ E l 15
1241 HIEIHEE:BilialhEnarmain==E=
1248 -0--;.... XOR·2052
X0R-2052
D - k IHIMM111111111111111111111111M AC1·2124
Ad1-2124

IIIII IIIIIIIIIIII 111111111ln


limiumumpmemmEsimmoneom
Il
l!SO
1280

.-...
'--'
150.
1604
INEINES:SittwastunignmEEEE OLMC
INEWMISEMETME:::E:::::=E=--
=1111111111•111110•11111•1111M
11 M i 1n i m. u m 0 1'
I
1 11 1 1
.1
M
-0--;....
1
14
OLJAC14
XOR·2053
X0R-2053
AC1:2.125
AC1-2125
v
J-G 14
14

1531
1536
1
is1im
11muumummommegunnomommE
1111111111111011111111111
ISESEEMENEEMILINIMITME= n ,....,.

D-
176.
1760

eitemommusemi1 muelb:
§= OLMC 13
MAC 13
-: XOR·2054
X011-2054
AC1·2126
AC1-2126
J- 13
13

IIIIIIIIIIIIIIIIIIIIIIIIIi11111
17112
1792
111111111111111111111111111111111111111111111211•11
SIEREMEESERIBEHEISEIESEE=
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84-USER ELECTRONIC
II4-USER ELECTRONICSIGNATURE
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2-7 4191.Rev.A
4/91.1Rev.A
[JJ
'L tattiOO-
.
Lattices
Semiconductor
SemkxJnductor
Corporation
Corporation
GAL1
Specifications GAL 61/8B
16V8B
GAL161/8A
GAL 16V8A
SIMPLE MODE
In the Simple mode, macrocells
macrooells are configured as dedicated inputs Pins 1 and
Pins and 1111 are always available
are always available as
as data
data inputs
inputs into
intothe
theAND
AND
or as dedicated, always active, combinatorial outputs. array. The center
array. centertwo
two macrocells
macrocells (pins
(pins 15
15 &
& 16)
16) cannot
cannotbe beused
used
as input or
as or I/O
I/O pins,
pins, and
and are
areonly
only available
available as
as dedicated
dedicated outputs.
outputs.
in this
Architecture configurations available in this mode are similar to
to
the common 10L8
10la and 12P6 deviCes
devices with many permutations of of TheJEDEC
The JEDECfuse
fusenumbers
numbers including
includingthe
the UES
UESfuses
fusesand
and PTD
PTDfuses
fuses
generic output polarity or input choices. are shown
are shown on
on the
the logic
logic diagram.
diagram.

All outputs in the simple mode have a maximum


maximum of eight
eight product
product
terms that can control the logic. In addition, each
logic. In each output has
has
programmable polarity.

Combinatorial
Combinatorial Output
Output with
with Feedback
Feedback Configuration
Configuration
Vcc for Simple
for Simple Mode
Mode

---+--\ -SYN=1.
- SYN=1.
-ACO.O.
- AC0=0.
-- XOR.O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
• - XOR
XOR=1.. 1 defines
defines Active
Active High
High Output.
Output.
XO R --AC1
AC1.0 =0 defines
defines this
this configuration.
configuration.
--All
All OlMC
OLMC except
except pins
pins 15 & 16
15 & 16 can
can be
be configured
configured to
to
this
this function.
function.
t. __ ... __ ....... _............................... j
;._- ..........................................
Combinatorial
Combinatorial Output
Output Configuration
Configuration for
for Simple
Simple Mode
Mode
Voo
-- SYN=1.
SYN=1.
-ACO.O.
- AC0=0.
-• XOR=O
XOR.0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1.. 1 defines
defines Active
Active High
High Output.
Output.
-- AC1-0
AC1=0 defines
defines this
this configuration.
configuration.
-- Pins
Pins 15
15 && 16 are
are permanently
permanently configured
configured to
tothis
this
... __ ................... _-
'............ _.............. _ function.
function.

Dedicated
Dedicated Input
Input Configuration
Configuration for
for Simple
Simple Mode
Mode

-SYN.1.
- SYN=1.
-ACO.O.
- AC0=0.
-- XOR=O
XOR.0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1 .. 1 defines
defines Active
Active High
High Output.
Output.
--AC1
AC1=1 .. 1 defines this
this configuration.
configuration.
--All
All OlMC
OLMC except
except pins
pins 15 & 16
15 & 16 can
can be
be configured
configured to
to
this
this function.
function.

Note:
Note: The
The development
development software
software configures
configures all
all of
of the
the architecture
architecture control
control bits
bits and
and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.

2-8
2-8 4/91.Rev.A
4/91.Flev.A
Lattice® I 6118B
Specifications GAL 16V8B
1..1 Corporation
Semiconductor
Semronductor
Corporation GAL1
GAL 6118A
16V8A
i
I

SIMPLE MODE LOGIC DIAGRAM

L..I v

...
, •
DIP &
DIP

I
& PLCC Package Pinouts

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1
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84-USER
64-USEREl£CTRONIC
ELECTRONICSIONATURE
SKINAIUREFUIES
FUSES
12056, 2057, •.•• •....2118,2110
•.• 2118, 211P
11
I SYN·2192
SYN-2192
ACO·2193
BYte718y1e
EIy!e 71%11 8e .•. B y t••• eEIy!e 11EIy!e
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2-9
2-9 4 / 9 1 4/91.Rev.A
•Rev.A
[JJ
.l..J
'LatUoo@
LLattice® Semiconductor
Semiconductor
Corporation
Corporation
GALI16V8B
Specifications GAL 61/13E3
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS0)
RATINGS(1) RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
Supply voltage Vcc — 0 . 5-0.5 to
Vee ....................................... to +7V
+7V Commercial
Commercial Devices:
Input voltage applied ...........................
— 2 . -2.5 5 to to Vcc
Vee +1.0V Ambient Temperature
Ambient Temperature (TAl
(TA)................................
0 to 75°C
0 to 75°C
Off-state
Off -state output voltage applied ..........— 2-2.5 . 5 toto Vee
Vcc +1
+1.0V
.OV Supply voltage
Supply voltage (Veel
(Vcc)
Storage Temperature .................................
— 6 5 -65 to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.2SV
+5.25V
Ambient Temperature with
— 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses
1°Stresses above those listed under the the "Absolute
"Absolute Maximum
Ratings·
Ratings" may cause permanent damage to to the device. These
These
are stress only ratings and functional operation of the
the device
device
at these or at any other conditions above those indicated in
in the
the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
programming.

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating
Operating Conditions (Unless Otherwise
Otherwise Specified)
Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP.'
TYR' MAX.
MAX. UNITS
UNITS

VII_
VIL Input Low
Low Voltage
Voltage Vss-0.5
Vss –0.5 -— 0.8
0.8 VV
VIH
V1H Input High Voltage 2.0
2.0 -— VCC+1
Vcol-1 VV
ILI
IlL' Input or 1/0
I/O Low
Low Leakage
Leakage Current OV
OV5S_VIN
VIN 5S_VII_
VIL (MAX.)
(MAX.) -- -- -1 oo
-100 RA
Illi
IIH Input or 1/0
I/O High Leakage Current 3.SV
3.5V S VIN S
s. VIN Vcc
5 VCC -
— -— 10
10 IlA
RA
VOL Output Low Voltage IOL
lot_..= MAX. Vin
MAX. Vi n ..= VIL
VII_or
or VIH
Vii-i -— -— 0.5
0.5 VV
VOH Output High Voltage IOH
ION..
= MAX. Yin = VII_
MAX. Vin VIL or VIH
or VIH 2.4
2.4 -— -— VV
10L
IOL Low Level Output Current -— -— 24
24 mA
mA
10H High Level Output Current -— -— -3.2
–3.2 mA
mA
los·
10S2 Output Short Circuit Current Vcc=5V YOUTz= O.SV
Vcc = 5V VOLIT TA= 25°C
0.5V TA= 25*C -30
–30 -— -150
–150 mA
mA
ICC
Icc Operating Power Supply Current VIL=
\in_ = 0.5V ViH =
0.5V VIH = 3.0V ftoggle ..= 2SMHz
3.0V ftoggle 25MHz -— 75
75 115
115 mA
mA
Outputs
Outputs Open
Open (no
(no load)
load)
1) The leakage current is due to the internal pull-up resistor
resistor on
on all
all pins. See Input Buffer
pins. See Buffer section
secfon for
for more
more information.
information.
2) One output at a time for a maximum duration of one second. Vout ..0O.SV
second. Vout . 5 V was
was selected
selected to
to avoid
avoid test
test problems
problems caused bytester
caused by tester
ground degradation. Guaranteed
Guaranteed but not 100%
100*k tested.
3) Typical values are at Vee
Vcc ..
= 5V
5V and TA== 25°C
and TA 25 'C

(TA = 2.5°C,
CAPACITANCE (TA 25°C, f = 1.0 MHz) =
SYMBOL PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C, Input
Input Capacitance 88 pF
pF Vcc -= 5.0V.
Vcc 5.0V, V,
V,..= 2.0V
2,0V
Ciic
C'iO 1/0
I/O Capacitance 88 pF
pF Vcc =5.0V.
Vcc = 5.0V, VIIO -2.0V
Vito = 2.0V
'Guaranteed
*Guaranteed but not 100% tested.

2-10
2-10 4191.Rev.A
4/91.RevA
[JJ
J.J,
Sem iconductor
LatUCC
'Lattice® SemiconduCUJr
Corporation
CorporaUon
Gl
Specifications GAL
GAL161/8B
16V8S
Commercial
AC SWITCHING CHARACTERISTICS
Recommended Operating
Over Recommended Operating Conditions
Conditions

TEST -7
-7 -10
-10
PARAMETER DESCRIPTION UNITS
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O to Combinational Output
Output I 88 outputs
outputs switching
switching 33 7.5
7.5 33 10
10 ns
ns
J 11output switching
switching -
— 77 -
— - — ns
ns

tco 11 Clock to Output Delay 22 55 22 77 ns


ns

tcf2
tcf' -— Clock to Feedback Delay -
— 33 -
— 66 ns
ns

tsu -— Setup Time, Input or Feedback before


before Clock"
Clocki 77 -— 10
10 -— ns
ns

th -— Hold Time, Input or Feedback after Clock"


Clocki 00 -— 00 -— ns
ns
11 Maximum Clock Frequency with 83.3
83.3 -— 58.8
58.8 -— MHz
MHz
External Feedback, 1/(tsu + teo)
tco)

fmax33
fmax 11 Maximum Clock Frequency with 100
100 -— 62.5
62.5 -— MHz
MHz
Internal Feedback, 1/(tsu + tcf)
tcf)
11 Maximum Clock Frequency with 100
100 -— 62.5
62.5 -— MHz
MHz
No Feedback

twh4
twh -— Clock Pulse Duration, High
High 55 -— 88 -— ns
ns

tw14
twt' -— Clock Pulse Duration, Low 55 -— 88 -— ns
ns
ten 2 Input or I/O to Output 33 99 33 10
10 ns
ns
22 OE.!.
0E,I, to Output 22 66 22 10
10 ns
ns

tdis
td is 33 Input or I/O to
to Output 22 99 22 10
10 ns
ns
3 °ET to Output
OE" 1.5
1.5 66 1.5
1.5 10
10 ns
ns
i) SWitching Test Conditions section.
1) Refer to Switching section.
!) Calculated from imax
fmax with internal feedback.
feedback. Refer to fmax Descriptions section.
section.
I) Refer to fmax Descriptions section.
I)
t) Clock pulses of widths less than the specification may be detected as
as valid clock
clock signals.
signals.

SWITCHING TEST CONDITIONS


CONDITIONS
Input Pulse Levels GNDto
GND to 3.0V +5V
+5V
Input Rise and Fall Times
Times 3ns
3ns 10%-90%
10'/0 – 90%
Input Timing Reference Levels 1.SV
1.5V
Output Timing Reference Levels 1.SV
1.5V
Output Load See
See Figure
I-state
-state levels are measured 0.5V
O.SV from steady-state active FROM OUTPUT (0/0)
FROMOUTPUT (0/0) - -.....- -....-TESTPOINT
TESTPOINT
°vol.I.
eve UNDER TEST
UNDERTEST
)utput Load Conditions (see figure)
R2
Test
Test Condition Rl
131 Rz
R2 CL
CL
11 200n
2000 390n
3900 SOoF
50pF
2 Active High
Active High .0 3900
3900 SOpF
50pF
Active Low 200n
200c1 390n
390c2 SOpF
50pF
3
3 Active High
Active High ,,. 3900
39012 SpF
5pF C
CLLIN
INCLUDES
CLUDESJIG AND
JIGANDPPROBE
ROBETTOTAL
OTALCCAPACITANCE
APACITANCE
Active Low 200n
2000 390n
390c2 SpF
5pF

2-11
2-11 4191.Rev.A
4/91.Rev.A
LILattice
'L Semiconductor
C()IJXX'aUOIl
Corporation
Specifications GAL
GAL1 61/8A
16V8A
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS(l)
RATINGS') RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
Supply voltage Vcc
Vee .......................................
— 0 . 5-o.5to to +7V Com Commercial
m e r c i a l Devices:
Devices:
Input voltage applied ...........................
— 2 . -2.5to
5 to Vee
Vcc +1.0V
+1.0V A m Ambient
b i e n t Temperature
Temperature (T(TA) 0
A ) •••••••••••••••••••••••••••••••• 0 to
to 75°C
75°C
Off-state output voltage applied .......... — 2-2.5 . 5 to Vee
Vcc +1.0V
+1.0V S u Supply
p p l y voltage (Vee)
(Vcc)
Storage Temperature .................................
— 6 5 -65 to 150°C w i twith
h Respect to to Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Ambient Temperature with
— 5 5 -55 to 125°C
Power Applied ...•....................................
1.Stresses above those listed under the the "Absolute
"Absolute Maximum
Ratings'. may cause permanent damage to
Ratings" to the
the device.
device. These
These
are stress only
only ratings and functional operation
operation of the device
device
or at any other conditions
at these or conditions above those
those indicated
indicated in
in the
the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
programming.

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise
Over Otherwise Specified)
Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP}
TYP.2 MAX.
MAX. UNITS
UNITS

VIL
VIL Input Low Voltage
Input Vss – 0,5
Vss-O.5 -- 0.8
0.8 VV

VIH Input High Voltage 2.0


2.0 -— Vcc+l
VcC+1 VV

IlL
IlL Input or 1/0
Input Low Leakage Current
I/O Low Current OV VIN S5 VIL
OVSVIN VII, (MAX.)
(MAX.) -- -- -10
-10 p.A
I1A
IIH Input or
or 110
I/O High Leakage Current VIHS5 VIN
VIH VIN S5 VCC
Vee -— -— 10
10 ixA
I1A
VOL Output Low Voltage
Voltage 10L=MAX. Yin
l a = MAX. Vi n == VIL
Vit. or
or VIH
VIH -— -— 0.5
0.5 VV

VOH Output High Voltage loH = MAX.


IOH MAX. Vi n == VILor
Yin VII. or VIH
VIH 2.4
2.4 -— -— VV

10l
10L Low level
Level Output Current -— -— 24
24 mA
mA
10H High Level Output Current -— -— -3.2
–3.2 mA
mA
los'
lost Output Short Circuit Current Vcc=5V VOUT
Vcc = 5V Va i l ' == 0.5V TA=
0.5V TA =25·C
25°C -30
–30 -— -150
–150 mA
mA
Operating Power
Power VIL=
ViL = 0.5V VIH=3.0V
0.5V VIH = 3.0V ftoggle
floggie =
= 15M
1 5 M Hz
Hz LL -25
-25 -— 75
75 90
90 mA
mA

Icc
iCC Supply Current Outputs
Outputs Open (no load) floggle
(no load) fungi° == 25MHz
25MHz L-10/-15
L -10/-15 -— 75
75 115
115 mA
mA
ftoggle = 15MHz
ftoggle = 15MHz
I Q
Q -15/-25
-15/-25 -— 45
45 55
55 mA
mA
1}
1) One output at a time for a maximum duration of one second. Vout
Vout == 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
ground degradation. Guaranteed
Guaranteed but not 100'/0
100% tested.
tested.
2) Typical values are at Vcc = 5V
5V and TA
TA = 25
25 ·C
'C

CAPACITANCE (TA
(TA = 25°C, =
25°C, ft = 1_0
1.0 MHz)
MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM'
MAXIMUM* UNITS
UNITS TEST
TESTCONDITIONS
CONDITIONS
C, Input
Input Capacitance 88 pF
pF Vcc =
Vee = 5.0V.
5.0V, V,
Vi == 2.0V
2.0V
Cm
Coo ilO
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V. VIJO
5.0V, V1 10== 2.0V
2.0V
'Guaranteed
*Guaranteed but not 100"/0
but not 100% tested.
tested.

2-12
2-12 4!91.Rev)
4/91.Rev.i
I
1 6118A
Specifications GAL 16VBA I:
I m d Semiconductor
t ®
Corporation Commercial
Commercial
1 AC SWITCHING CHARACTERISTICS
Over Recommended
OVer Recommended Operating Conditions
Conditions
..•

-10
-10 -15
-15 -25
-25
TEST DESCRIPTION
PARAMETER UNITS
UNITS
CONDt.
COND'. MlfIC
MI )ftAx.
AX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 to Combinational Output
Input or I/O to Output 33 •' 10
10 33 15
15 33 25
25 ns
ns

tco
teo 11 Clock to Output Delay 22 ,; 77 22 10
10 22 12
12 ns
ns
,
1 t c ftcf2
2 -— to Feedback Delay
Clock to -
—i 7 - 88 -— 10
10 ns
ns

tsu -— Setup Time, Input or Feedback before


Input or before Clocki
Clockt 10
10 -— 12
12 -— 15
15 -— ns
ns

- Hold Time,
Time, Input or
or Feedback
Feedback after
after Clocki
ClockT 0
= -- - ns
58.8 =-
th - Hold - 00 00 - ns
o
11 Maximum Clock Frequency with
External Feedback,1/(tsu
with
tco)
Feedback, 1f(tsu + teo) all . - 45.5
45.5 -- 37
37 -- MHz
MHz

tmax33
fmax 11 Maximum Clock Frequency with
Internal Feedback, 1/(tsu
with
1f(tsu ++ tcf)
tcf)
58.8
58.84
*

i
S- 50
50 -— 40
40 -— MHz
MHz

11 Maximum Clock Frequency with 62.5 ..:: 62.5


62.5 -— 41.6
41.6 -— MHz
MHz
No Feedback )
twh4 -— Clock Pulse Duration, High 88 t ;- 88 -— 12
12 -— ns
ns

tw14
tw" -— Clock Pulse Duration, Low 88 •'I — 88 -— 12
12 -— ns
ns

ten 2 Input or I/O


Input I/O to
to Output Enabled —.t.: 10
-SCI '10 -— 15
15 -— 25
25 ns
ns
22 0E1 to Output Enabled
OE.!. . )10
I.' 10 -— 15
15 -— 20
20 ns
ns

' t d tdis
i s 33 to Output
Input or I/O to Output Disabled 10 -— 15
15 -— 25
25 ns
ns
33 OEi
0E1 to Output Disabled -:
—1 )10
10 -— 15
15 -— 20
20 ns
ns

1) Refer
Aefer to Switching Test Conditions section.
section.
2) Calculated from fmax
'max with internal feedback. Aefer to
feedback. Refer to 'max
fmax Descriptions
Descriptions section.
section.
3) Refer
Aefer to 'max
fmax Descriptions section.
4) Clock pulses of widths less than the
the specification may bebe detected
detected as valid
valid clock signals.
signals.

1SWITCHING TEST CONDITIONS


Input
i1Input GNDt03.0V +5V
+5V
Pulse Levels GND to 3.0V
: Input Rise
Aise and Fall Times 3ns
3ns 10"04
10% -– 90%
, Input Timing Reference
Aeference Levels 1.5V
1.5V
Output Timing Reference
Aeference Levels 1.5V
1.5V
Output Load See
See Figure
3-state levels are
are measured 0.5V
0.5V from
from steady-state active FROM OUTPUT (0/0)
FROMOUTPUT (0/0) - - + - - ' - - T E STEST
T POINT
POINT
level. UNDER TEST
UNDERTEST
OUtput
Output Load Conditions (see
(see figure)
figure) CL
R2
Test Condition R1
RI R2
R2 CL
CL
11 2000
2000 3900
390Q 50pF
50pF
2
2 Active High
Active High co
0. 3900
390n 50pF
50pF
Active Low 2000
2000 3900
3900 50pF
50pF
3
3 Active High co
.0 3900
3902 5pF
5pF C
CL INCLUDES JIG
LINCLUDES AND PROBE
JIGAND TOTAL CAPACITANCE
PROBETOTAL CAPACITANCE
Active
Active Low
Low 2000
2000 3900
3900 5pF
5pF

2-13 4/91.Aev.A
4/91.Rev.A
[JJ
.l...I
'LattiOO*
LLattice® Semiconductor
SemJconductor·
Corporation
Corporation
GAL16118B
Specifications GAL 16VBB
Industrial
Industrial
ABSOLUTE MAXIMUM RATINGS(1)
RATINGS(1) RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
Supply voltage
Supply voltage Vcc — 0 . 5-0.5 to
Vee ....................................... to +7V
+7V Industrial Devices:
Industrial
Input voltage applied ...........................
— 2 . -2.5 5 to to Vcc +1 .0V
Vee +1.0V Ambient Temperature
Ambient Temperature (TAl
(TA)............................
— 4 0-40 to
to 85°C
85°C
Off-state output
Off-state output voltage
voltage applied
applied ..........
— 2-2.5 . 5 toto Vcc
Vee + +11.0V
.0V Supply voltage
Supply voltage (V
(Vcc)
eel
Storage Temperature .........•.......................
— 6 5 -65 to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
Ambient Temperature with
— 5 5 -55to
Power Applied .......................................• to 125°C
1.Stresses above those listed under the "Absolute "Absolute MaximumMaximum
Ratings" may cause permanent damage to the device. These
device. These
are stress only ratings and functional operation of of the
the device
above those
at these or at any other conditions above those indicated
indicated in in the
the
operational sections of this specification is not implied (while
programming, follow
follow the
the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer
Over Recommended
Recommended Operating
Operating Conditions (Unless Otherwise
Otherwise Specified)
Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP.3
TYP.3 MAX.
MAX. UNITS
UNITS

VII_
VIL Input Low Voltage Vss –0.5
Vss-O.5 -— 0.8
0.8 VV
VIH Input High Voltage 2.0
2.0 -— VCC+1
Vcc+l VV
IlL'
ilLI Input or 110
I/0 Low Leakage Current OV
OVS5 VIN VIL (MAX.)
VIN SVII_ (MAX.) -— -— -100
–100 pA
IIH Input or 1/0
I/0 High Leakage Current 3.5V VIN _S•VCC
3.5V SVIN Vee -— -
— 10
10 I.LA
VOL Output Low Voltage 10L
loL ..= MAX. Vin
MAX. Vi n ..= VIL
Vii_or
orVIH
VIH -— -— 0.5
0.5 VV
VOH Output High Voltage 10H
loH = MAX. Vin
Vin ..
= VIL
VILor VIH
or VIH 2.4
2.4 -— -— VV
10L
IOL Low Level Output Current -— -— 24
24 mA
mA
10H
i0H High Level Output Current -— -— -3.2
–3.2 mA
mA
los'
i0S2 Output Short Circuit Current Vce=5V VOUT== 0.5V TA
Vcc = 5V VOUT TA==25°C
25°C -30
–30 -— -150
–150 mA
mA
Icc
iCC Operating Power Supply Current VIL=
Vit. = 0.5V VIH = 3.0V
0.5V VIH 3.0V ftoggle
f.toggle == 25MHz
25MHz -— 75
75 130
130 mA
mA
Outputs
Outputs Open
Open (no load)
load)
1) The leakage current is due to the internal pull-up on
on all
all pins. See
See Input Buffer
Buffer section
section for
for more
more information.
information.
2) One output at
at a time for
for a maximum duration of one
one second. Vout =00.5V
second. Vout . 5 V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
bytester
tester
ground degradation. Guaranteed
Guaranteed but
but not 100% tested.
tested.
3) Typical values are at Vcc ..55V TA = 25 °C
V and TA

(TA = 25'C,
CAPACITANCE (TA 25°C, ff = 1.0 MHz)

SYMBOL PARAMETER
PARAMETER MAXIMUM·
MAXIMUM* UNITS
UNITS TEST
TESTCONDITIONS
CONDITIONS
C,
CI Input
Input Capacitance 88 pF
pF Vee
Vcc=. 5.0V,
5.0V, V,
VI == 2.0V
2.0V
C10
C'iO I/O Capacitance
1/0 88 pF
pF Vcc =5.0V,
Vcc . 5.0V, VIJO=2.0V
Vvo. 2.0V
·Guaranteed
*Guaranteed but not 100°/0
100% tested.

2-14 4191.Rev.A
4/91.RevA
/1.l..J
L LlLattice"
attice
Semiconductor
Semiconductor
Corporation
Corporation
GAL161/8B
Specifications GAL 16V8B
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended
Recommended Operating
Operating Conditions
Conditions
-10
-10 -15
-15
TEST DESCRIPTION
PARAMETER
PARAMETER UNITS
UNITS
COND1.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O to
to Combinational Output 33 10
10 33 15
15 ns
ns

too
tco 11 Clock to Output Delay 22 77 22 10
10 ns
ns

tcf2 -— Clock to Feedback Delay -— 66 -— 88 ns


ns

tsu -— Setup Time, Input before Clocki


Input or Feedback belore 10
10 -— 12
12 -— ns
ns
I
I th -— Hold Time, Input or Feedback alter
after Clocki 00 -— 00 -— ns
ns
11 Maximum Clock Frequency with 58.8
58.8 -— 45.5
45.5 -— MHz
MHz
External Feedback, 1/(tsu + tco)
,
I
f max
fmax' 11 Maximum Clock Frequency with 62.5
62.5 -— 50
50 -— MHz
MHz
1/(tsu + tcl)
Internal Feedback, 1/(tsu tot)
11 Maximum Clock Frequency with 62.5
62.5 -— 62.5
62.5 -— MHz
MHz
No Feedback

twh4 -— Clock Pulse Duration, High 88 -— 88 -— ns


ns
twt'
tw14 -— Clock Pulse Duration, Low 88 -— 88 -— ns
ns
ten 2 Input or I/O to
to Output 33 10
10 -— 15
15 ns
ns
2 OEL
OE/ to Output 22 10
10 -— 15
15 ns
ns
tdis 3 Input or I/O to
to Output 22 10
10 -— 15
15 ns
ns
3 OEi
OET to Output 1.5
1.5 10
10 -— 15
15 ns
ns

1) Refer
Reier to Switching Test Conditions section.
Refer to
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
section.
3}
3) Refer to fmax Descriptions section.
01 widths less than the specification may be
4) Clock pulses of be detected as valid
valid clock
clock signals.
signals.

SWITCHING TEST CONDITIONS


Input Pulse Levels GND
GND t03.0V
to 3.0V +5V
+5V
Input Rise and Fall Times 3ns 10%-90%
3n s 10'k – 90%
input
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
1.5V R1
Output Load See
See Figure
3-state levels are measured 0.5V from
from steady-state active FROM OUTPUT (010)
FROMOUTPUT (0/0) - -.....- -.....-TESTPOINT
TESTPOINT
level. UNDER TEST

1J
UNDERTEST
Output Load
Load Conditions (see figure)

Test Condition Rl
RI R2
R2 CL
CL R2
1 2000 3900 50pF
50pF
2 Active High .0
co 3900 50pF
50pF
Active Low 2000 3900 50pF
50pF -
3 Active High
Active High ..
00 3900 5pF
5pF C
CL INCLUDESJIG
llNClUDES JIGA NDP
AND ROBET
PROBE OTALC
TOTAL APACITANCE
CAPACITANCE
Active
Active Low 2000
2000 3900
3900 5pF
5pF

2-15
2-15 4 / 9 1 . R e v .4191.Rev.A
A
U Lattice'
1..1 j;Lattioo'
Semiconductor
Semicondllctor
C o r p Corporation
oration
GAL16118A
Specifications GAL 16V8A
Industrial
Industrial
MAXIMUM RATINGS(l)
ABSOLUTE MAXIMUM RATINGS') RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
Supply voltage Vcc - 0 . 5 -0.5 to +
Vce ....................................... +7V
7V Industrial
Industrial Devices:
Input voltage applied ...........................
- 2 . 5-2.5 to Vcc
Vee +1.0V Ambient Temperature
Ambient Temperature (T(TA) - 4
A) ............................ to 85°C
0 -40 to 85°C
Oft-state output voltage applied ..........
Off-state - 2 -2.5
. 5 to VccVee ++1.0V
1.0V Supply voltage (Vee)
Supply (Vcc)
Storage Temperature .................................
- 6 5 -65 to 150°C with Respect to
with + 4 . 5+4.50
to Ground ...................... to +5.50V
0 to +5.50V
Ambient Temperature with
- 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses above those listed under the the "Absolute Maximum
Ratings" may cause permanent damage to to the
the device.
device. These
These
are stress only ratings and functional operation of the device device
at these or at any other conditions above those those indicated inin the
the
operational sections of this specification is not not implied (while
programming, follow thethe programming specifications).

CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
(Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP.2
TYR' MAX.
MAX. UNITS
UNITS

VIL Input Low Voltage Vss -0.5


Vss-O.5 -— 0.8
0.8 VV

VIH Input High Voltage 2.0


2.0 -— Vcc+1
Vcc+1 VV

IIL
IlL Input or I/O Low
Low Leakage Current OV 5 VIN
OV:s VIN:SVit. (MAX.)
Vil (MAX.) -— -— -10
·10 p,A
IIH Input or I/O High Leakage Current VIH:S VIN .•:SVCC
VIH 5 VIN Vec -- -- 10
10 I.LA
VOL Output Low Voltage l a = MAX.
10l= MAX. Vi
Vinn = VIL
Vii_ or
or VIH
VIH -- -- 0.5
0.5 VV

VOH
VOH Output High Voltage loH = MAX.
IOH MAX. Vi n = VIL
Yin or VIH
VIL or ViH 2.4
2.4 -— -— VV

10l
IOL Low
Low Level Output Current -— -— 24
24 mA
mA
10H High Level Output Current -— -— -3.2
-3.2 mA
mA
los'
IOS Output Short Circuit Current Vcc = 5V
Vee VOUT = O.SV
5V VOUT TA== 25°C
0.5V TA 25°C -30
-30 -— -150
-150 mA
mA

ICC
Icc Operating Power
Power VIL VIH = 3.0V
VII_ = 0.5V V11-I 3.0V toggle = 25M
floggl. Hz
25MHz lL ·15/-25
-15/-25 -— 75
75 130
130 mA
mA
Supply Current Outputs Open (no load) f10991o
floggie =- 15MHz
15M Hz a0 -20/·25
-20/-25 -— 45
45 65
65 mA
mA

1) One output at a time for a maximum duration


duration of
of one
one second. Vout == 0.5V
second. Vout 0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but not 100% tested.
ground degradation. Guaranteed tested.
2) Typical
Typical values are at Vcc
Vce = 5V and TA
TA = 25
25°C
*C

=
(TA = 25°C, f = 1.0 MHz)
CAPACITANCE (TA =
SYMBOL PARAMETER
PARAMETER MAXIMUM'
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
Input Capacitance 88 pF
pF Vcc =- 5.0V,
Vee V, = 2.0V
5.0V, V, 2.0V
CliO I/O Capacitance 10
10 pF
pF Vcc== 5.0V:
Vee 5.0V, V,,c,
VIIO =. 2.0V
2•0V
"Guaranteed
'Guaranteed but not 100% tested.
tested.

2-16 4/91.Rev.A
4/91.Rev.A
/fILatUre"
/L
1.J
Lattice®
Semiconductor
Semiconductnr
Corporation
Specifications GAL-16118A
GAL 16V8A
Industrial
1AC SWITCHING CHARACTERISTICS
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-15
-15 -20
-20 -25
-25
)ARAMETER
TEST DESCRIPTION UNITS
UNITS
'ARAMETER
COND'. MIW7.MAX.
Mlt{;.,. )v1AX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
,„
11 Input or I/O to
to Combinational Output &t 15
33 te,,,,t 33 20
20 33 25
25 ns
ns
t pd
tpd >I' ""15
==::.

tco 11 Clock to Output Delay ?


k4k,,
22 0,-.,"'10 10

22 11
11 22 12
12 ns
ns

tolz
tct> -— Clock to Feedback Delay -— i"V<,..„.JI 88 -— 99 -— 10
10 ns
ns

tsu -— Setup Time, Input or


or Feedback belore
before Clock!
Clocki 12 L-,'• -
12 C 13
13 -— 15
15 -— ns
ns

th -— Hold Time, Input or Feedback alter


after Clocki o 00 -— 00 -— ns
ns
1!!Ij
11 Maximum Clock Frequency with 45.54, — 41.6
41.6 -— 37
37 -— MHz
MHz
.1l
External Feedback, 1/(tsu + tco)
"', '"
f max3 Maximum Clock Frequency with 5 0 P<: 45.4
45.4 -— 40 -— MHz
fmax 11 50 ''
l- - 40 MHz
Internal Feedback, 1/(tsu ++ tet)
tcf) tL?',...
.-

1 Maximum Clock Frequency with 62.5 r:p!,i\!•—


- 50
50 -— 41.6
41.6 -— MHz
MHz
No Feedback
No C
P 5
twh4
twh' -— Clock Pulse Duration, High 88t
¢' ."
C)- 10
10 -— 12
12 -— ns
ns
w.,
twl4
tw14 -— Clock Pulse Duration, Low
Low 88 10
10 -— 12
12 -— ns
ns

ten 2 110 to
Input or I/O to Output :i 151
.*
-— 20
20 -— 25
25 ns
ns
22 OEJ.
0E1 to Output _— to!
' ' •f15
15 -— 18
18 -— 20
20 ns
ns
s,
tdis 3 Input or I/O to
to Output -— ;>'1;15 -— 20
20 -— 25
25 ns
ns
3
3 OEi
OET to Output — ""
- 4 ,$15
15 -— 18
18 -— 20
20 ns
ns
) Refer to Switching Test Conditions section.
')) Calculated from
lrom fmax with internal feedback. Refer to
to Imax
fmax Descriptions section.
section.
;)) Refer to fmax Descriptions section.
) Clock pulses of widths less than the
the specification may be detected as valid
valid clock
clock signals.
signals.

SWITCHING TEST CONDITIONS


Input Pulse Levels GNDt03.0V
GND to 3.0V +5V
+5V
Input Rise and
and Fall Times 3ns
3ns 10% -– 90e/0
90%
Input Timing Reference Levels 1.5V
1.5V
Output Timing Reference
Reference Levels 1.5V
1.5V
Output Load
Load See
See Figure
,-state
-state levels are measured 0.5V from steady-state active FROM OUTPUT (O/Q)
FROMOUTPUT (0/0)
weI.
?vel. TESTPOINT
POINT
UNDER TEST
UNDERTEST
)utput Load Conditions (see figure)
CL
Test Condition R1 R2 CL R2
ill R2 CI-
1 2000 3900 50pF
2 Active High 0. 3900 50pF
50pF
Active Low i 2000
2000 3900 50pF
50pF
3
3 Active High
Active Hlgn .. 3900
3900 5pF
5pF C
C L INCLUDES
INCLUDES JIG AND PROBE
JIGAND PROBE TOT
TOTAL
ALCAPACITANCE
CAPACITANCE
Active
Active Low 2000
2000 3900
3900 5pF
5pF

2-17 4/91.Rev.A
4/91.Rev.A
IllLattioo
Lattice®
'
.l..I Corporation
Semiconductor
Semiconductor
GAL1
Specifications GAL 6118B
16VBB
GAL16143A
GAL 16VBA
SWITCHING WAVEFORMS
SWITCHING

INPUTor
INPUT or
vaVOFEEDBACK
FEEDBACK
VALIDINPUT
to u th

INPUTor CLK
elK
INPUT or
va
VOFEEDBACK
FEEDBACK VALIDINPUT
4— to
tpd REGISTERED
REGISTERED
OUTPUT
OUTPUT 1
COMBINATORIAL
COMBINATORIAL if imax
OUTPUT
OUTPUT (external idbk)

Combinatorial Output Registered


Registered Output
Output

INPUT
INPUTor
OE
OE
va FEEDBACK
VOFEEDBACK

tdIs 4—ten—0•• 4 — t d s —111.• 4— t en

OUTPUT
OUTPUT OUTPUT
OUTPUT

Input or UO
I/O to Output Enable/Disable O E OE to
to Output
Output Enable/Disable
Enable/Disable

elK
CLK
tw h Iwl
tw
1/ titian (internal UN() *
elK
CLK

REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
mss2,/, 4—tct 0 4 t s u

Clock Width

fmax with
fmax with Feedback
Feedback

2-18
2-18 4191.Rev.l
4/91.Revi
aJLattire'
.l..J ILattice®
Semiconductor
Semiconductor
C o r p CorporaUon
oration
Specifications GAL
GAL16118B
16V8B
GAL16118A
GAL 16V8A
firm
fmax DESCRIPTIONS
DESCRIPTIONS

CLK
elK
.......................................... _--_ ..
elK
CLK
_. _. _ •• - _ • • • • • _. - - - - _. - - - _. - eo • • _ •• _ 00 _ . _ • • • •,

LOGIC
lOGIC REGISTER
REGISTER
AR R AY
RRAV LOGIC
ARRAY
REGISTER
REGISTER

14
/o.II1
. I s o t i ..o
....f - -o-

fmax with External Feedback 1/(tsu+tco) • • • • OM • • • • • _ •• __________ • ____ •• _______ • ____ • ___ !

r.-14------tcl
tcl O k i
Note: fmax
'max with
with external feedback is
is calculated
calculated from
from measured 1<I!041-----tpd
tpd0 1

tsu and too.


tco.
frnax with
fmax with Internal Feedback 1/(tsu+tcf)
Internal Feedback 1/(tsu+tcf)

Note: tet
Note: tcf is aa calculated
calculated value,
value, derived
derived by by subtracting
subtracting tsu tsu from
from
the period
the period ofof fmax
Imax w/internal
w/internal feedback
feedback (tet(tot 1/Imax
1lfmax -- tsu).
tsu). The
The
value of tet
value tot is
is used
used primarily
primarily when
when calculating
calculating the the delay
delay from
from
elK
CLK clocking
clocking a register
register to
to aa combinatorial
combinatorial output
output (through
(through registered
registered
. . . . . 0-- 0 . - - - • • • • • • • • • • • • • • • • - _ . __ • • _-_ • • • • • • • • • feedback), as
feedback), as shown
shown above. For example,
above. For example, the the timing
timing from
from clock
clock
to
to a combinatorial output is
combinatorial output is equal
equal to tcl ++ tpd.
to tcf tod.
V
LOGIC
lOGIC
REGISTER
REGISTER
ARRAY I--+--'

.
• __ . 0 • • • • • • - ••••••• - . · · ••• - . · · . - . · _ - •••• -- •• ·_--
.
fmax With No Feedback

with no feedback may be less than 1ltwh


Note: fmax with litwh + twl. This
This
is to allow for a clock duty cycle ol'other
of other than 50%•
50%.

2-19 4/91.Rev.A
4/91.Flev.A
U
l..tI lLattiooo
L_Lattice® Semiconductor
Semiconductor
Corporation
CorporaUon
GAL16118B
Specifications GAL 16VBB
GAL16118A
GAL 16VBA
ELECTRONIC SIGNATURE OUTPUT REGISTER
OUTPUT REGISTER PRELOAD
PRELOAD
every GAL
An electronic signature (ES) is provided in every GAL16V8A
16V8A and
and When testing
When testing state
state machine
machine designs.
designs, all
allpossible
possiblestates
statesand
andstate
state
GAL16V8B
GAL 16V88 device. ItIt contains 64 bits
bits of
of reprogram
reprogrammable memory
mabie memory transitions must
transitions must bebe verified
verified inin the
the design.
design, not
not just
just those
those required
required
that can contain user defined data. Some Some uses include user ID 10 in the
in the normal
normal machine
machine operations.
operations. This is because.
This is because, in in system
system
codes, revision numbers,
codes. inventory control.
numbers. or inventory control. The signature data operation, certain
operation. certain events
events occur
occurthat
that may
may throw
throwthethe logic
logicinto
into an
an
is always available to the user independent of the the state
state of the
the illegal state
illegal state (power-up.
(power-up, line
line voltage
voltage glitches.
glitches, brown-outs,
brown-outs, etc.).
etc.). To
security cell. test a design
test design for
forproper
propertreatment
treatment ofofthese conditions, aaway
theseconditions, waymust
must
be
be provided
provided to to break
break the
the feedback
feedback paths,
paths, and force any
and force anydesired
desired
NOTE: The
The ES is is included
included in checksum calculations. Changing
calculations. Changing (i.e., illegal) state
(i.e., state into
into the
the registers.
registers. Then the machine
Then the machine can can bebe
the ES will alter checksum.
checksurn. sequenced
sequenced and andthe
theoutputs
outputstested
tested for
forcorrect
correct next
nextstate
stateconditions.
conditions.

The GAL
The GAL16V8A and GAL
16V8A and GAL16V8B devices include
16V88 devices include circuitry
circuitry that
that
allows each
allows each registered
registered output
outputto
tobe
besynchronously
synchronously setseteither
eitherhigh
high
SECURITY CELL or
or low.
low. Thus, any present
Thus, any present state
state condition
condition can
can be
be forced
forced for
fortest
test
sequencing.
sequencing. If necessary,
necessary, approved
approved GAL
GALprogrammers
programmers capable
capable
A security
security cell is provided in the GAL16V8A
GAL 16V8A and GAL16V8B
GAL 16V88 of
of executing
executing text
text vectors
vectors perform
perform output
output register
register preload
preload auto-
auto-
devices to prevent unauthorized copying of the the array patterns. matically.
matically.
Once programmed,
programmed. this cell prevents further readread access to the
the
functional bits in the device. This
This cell can
can only be erased
erased by re-
re-
programming the device.
device, so
so the
the original configuration
configuration can
can never
be examined
examined once this cell is programmed.
programmed. TThe h e Electronic INPUT BUFFERS
INPUT BUFFERS
Signature is always available to to the user. regardless
the user, regardless of the
the state
of this control cell. GAL 16V8A and
GAL16V8A and GAL 16V88 devices
GAL16V8B devices are
are designed
designed with
withTIL TTLlevel
level
compatible
compatible input
input buffers.
buffers. These buffers
buffers have
have aacharacteristically
characteristically
high
high impedance,
impedance, andand present
present aa much
much lighter
lighter load
load to
to the
the driving
driving
logic
logic than
than bipolar
bipolar TIL
- r n devices.
devices.
PROTECTION
LATCH-UP PROTECTION
The
The GAL 16V88 input
GAL16V8B input and
and 110
I/O pins
pins have
have built-in
built-in active
active pull-ups.
pull-ups.
GAL 16V8A and GAL
GAL16V8A 16V88 devices
GAL16V8B devices are designed with an on- on- As
As a result,
result, unused
unused inputs and I/O's I/0's will
will float
float to
to aa TIL
TTL "high"
"high"
board charge pump to negatively bias the the substrate.
substrate. The
The negative
negative (logical
(logical "1").
"1"). In contrast,
contrast, the
the GAL 16VSA does
GAL16V8A does notnot have
haveactive
activepull-
pull-
bias is of sufficient magnitude to prevent input undershoots from from ups
ups within
within their input
input structures. Lattice recommends
structures. Lattice recommends that that all
all
causing the
the circuitry
circuitry to latch. Additionally,
Additionally. outputs
outputs are
are designed
designed unused
unused inputs and and tri-stated
tri-stated I/O
I/O pins
pins for
for both
both devices
devices bebe con-
con-
with n-channel pull-ups instead of the the traditional p-channel
p-channel pull- nected
nected toto another
another active
active input,
input, VCJ::' or
Vcc, orGround. Doing this
Ground. Doing thiswill
willtend
tend
ups to
to eliminate any possibility of SCASCR induced latching. to
to improve
improve noise
noise immunity
immunity andand reduce
reduce Icc lc, forthe
for thedevice.
device.

DEVICE PROGRAMMING Typical


Typical Input
Input Pull-up
Pull-up Characteristic
Characteristic

GAL devices are programmed using using a Lattice-approved Logic


Logic
Programmer.
;;; 0
Programmer, available from
from a number ofof manufacturers (see
(see the
the /
GAL Development Tools section). Complete programming of of the
the
device takes only aa few seconds.
takes only seconds. Erasing
Erasing of the device
device isis ;" ·20
/'
transparent to the
the user.
user, and
and is done automatically as part of
of the
the " ./
V
(,)

programming cycle. :; ·40


•40
Q.

.!:
·60
-60
o0 1.0
1.0 2.0
2.0 3 . 3.0
0 4.0
4.0 5.0
5.0
Input
Input Voltag'
Voltage (Volts)
(Volts)

2-20 4/91.Rev.A
4/91.Rev.A
1 1.Ilattice®
.l.Jd Semiconductor
SemJronducwr
Specifications GAL
GALI16V8B
61f8B
Corporation
COl'poration GAL1
GAL 61f8A
16V8A
POWER-UP RESET

Vee
V cc
OV
0V
t pr
V
V IH rT"...-tt...--.-rrrr"\lr---------
CL K
CLK
Vil
V IL lk 1 VALIDCLOCK
VALID CLOCKSIGNAL
SIGNAL

INTERNAL
INTERNAL INTERNAL
INTERNAL REGISTER
REGISTER
REGISTER
REGISTER RESET
RESETTO
TO LOGIC
LOGIC00
0-OUTPUT
a·OUTPUT

FE
F E EDBACK/E
EDBACK/EXXTE
TERRNAL
NAL EXTERNAL REGISTER
EXTERNAL REGISTER
OUTPUT REGISTER
OUTPUT R EGISTER OUTPUT
OUTPUT =L OLOGIC
GIC 1

circuitry within the GALA


GAL 16V8A
6V8A and GAL 16V8B provides a reset
GAL16V8B reset The
The timing
timing diagram for for power-up
power-up is is shown
shown above. Because of
above. Because of
,ignalto
signal to all registers during power-up. All
All internal registers
registers will the
the asynchronous
asynchronous nature
nature of of system
system power-up,
power-up, some
some conditions
conditions
lave their Q0 outputs set
set low after a specified time (t R
RESET' 45115
ESET' 45P,S must
must be be met
met to guarantee
guarantee a valid valid power-up
power-up reset
reset of the the
\/lAX).
MAX). As a result, the state on the registered output pins (if they GAL 16V8A and
GAL16V8A and GAL 16V8B. First,
GAL16V8B. First, the
the Vee
Vcc rise
rise must
must bebe mono-
mono-
ue
ore enabled through OE) will always be high on power-up, re- re- tonic. Second, the
tonic. Second, the clock
clock input
input must
must become
become aa proper
proper TTL
TTLlevel
level
Jardless
jardless of the programmed polarity of the the output pins: This
pins. This within
within the
the specified
specified time
time (tPR' 100ns MAX).
(tpn, lOOns MAX). The registers
registers will
will reset
reset
'eature
eature can greatly simplify state machine design by providing a within
within a maximum
maximum of tREsETtime. time. AsAs inin normal
normal system
system operation,
operation,
mown
(nown state on on power-up. avoid
avoid clocking
clocking the
the device
device until
until all
all input
input and
and feedback
feedback path
path setup
setup
times
times have been
been met.
met.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN PIN

Feedback
Active Pull-up
Vcc
Vee
CircuM
Circuit ActivePull-tJp
Active Pull-up
(GALI6V8B
(GALA6V8D only)
only) Cil'aJit
Circuit
(GAL16V88
(GAL16V8Bonly)
-------------- --- _., ....y.... ...y.....
only)

Vco
Wet Trl-State
Tri-State W e it Vret i
Control
Control
: ESD
ESD
: Protection
i ClrcuR
Circuit

:----------------- _eo!
Data
Data
!lIN
PIN PIN
PIN
Output
Output
,.---------------- __ e.
: ESD
ESD :
: Protection
Protection :
l
··
CircuM
Circuit l
.
··.----.-------.-.- ----... Feedback
Feedback
(To
(ToInput
inputBuffer)
Buffer)
Typ. Vref =
= 3.2V Typ.
Typ. Vref == 3.2V
3.2V

Typical Input Typical


Typical Output
Output

2-21
2-21 4191.Rev.A
4/91.Rev.A
GALI16V8B
Specifications GAL 6118B
I I s I Sleiscondue ctor6
Corporation Typical Characteristics
Normalized Tpd vs Vee
Normalized Vcc Normalized Teo
Normallzad Tco vs
vs Vee
Vcc Normalized Tsu
Normallzad I s u vs
vs Vee
Vcc

t1.2
.•
J.....
1.2

,I--FALL
u t.'

i---t---t-i
PTH..L
..... RISE
PT 1.1-8.1.,

!-
t.t
......... 1--
- PT L-9H
J!122
0 Lt.t
I
- FALL
,!!
0 1t.t
.1
- PT 1.-›/.1

1 +1--====1=' ]t --- -" ....... ]t


II--PTL ..H

J
]

0.9 t---t--+.,--t---;
-'-
•48.4.4,8,8

........
J 0.'
. ...... ............
J 0.'
0.' 0.9 0.9

.... .... .... ....


•.• + - - - - 1 - - 4 - - - - 1 - - - - 1
.... •...... .... .... ....
4.50 ".75
4 . 7 5 5 . 0 0 5 . 2 5 5.50
00.8
.•
4.50 4 . 74.711
5 .... ....
5 . 0 0 5 2 5 5 . 5 0 ...0 4 . 0
0.8

0 4 2 4.711
5 5 . 0 0 5 2 5 5.50

Supply (V)
Supply Voltage (V) Supply
Supply Voltage
Voltage (V) Supply Vohage
Supply Voltage (V)
(V)

Normalized Tpd vs Temp


Normalized Normalized Teo
Normalized Tco vs
vs Temp
Temp Normalized Tsu
Normellzad Tsu vs
vs Temp
Temp

t.3
1.3 t.3
1.5
t.'
1.4

LI
1.2 ••••. PTH
PT H..
91_
t.'
1.2 RISE t.3
1.3 ••••. PTH..L I L
.., ./ /'

-- .. ..
o
,.2-1.1 --PTL->HI
PT I.-9H 1.1 - - FALL
,
.' iii t1••2
--PTL.. HI
/
1 /'
0- '
] •• "i
:os 1 ,.,..
1
t.t
.. ' .'
/.-
J . 0.•
'
e 0.9
0.'
t

Z 0.9
0.'
t
....... . /
0.8
0.8 0.'
0.8
0.' /"
0.8
......
0.1
0.7
...
55 0 2 5 ..
Temperature (deg. C)
9 0 to t125
..
0.1
0.7
...
55 0 2 5 .. 9 0 to t125
..
0.1
0.7
... 55 0 2 5 .. 9 0 to t 125
..
Temperature
Temperature (deg. C) Temperature
Temperature (deg.
(deg. C)
C)

Delta Tpd vs #It of


Delta of Outputs
Outputs Delta
Delta Teo vs ## of
Tco vs of Outputs
Outputs
Switching
Switching Switching
Switching

:.:-
.. , .. ' ;;.:.. p .. .' .
'
pr""
] : -0.5

..,
.'
.'
/
i-"'"
_-0.55
..s. .. '
.'
/
.-'
.e- ., ./ J! ·t ./

c!'l .t .•
V ••••• RISE}
RISE /" ..... RISJ
c!'l .t.'
--FALL
- FALL FALL
..
-2 .. I I
2 3 4 5 6 7 6 2 3 4 5 6 7

Number of Outputs SwUching


Number Switching Number of Outputs
Number Outputs SwUching
Switching

Delta
Delta Tpd vs Output
Output Loading Delta
Delta Teo vs Output
Too VI Output loading
Loading

to

j .....
R I S RISE
E I
/
to

••••. I
V
g' --FALLI
- FALL
/,. 134
'
--FALLI
..'
1--;':".,
L /.
.' .'
/- L
-. ..
50
50 1 0 tOO
0 1 5150
0 2 0200
0 2 529
0 3 0300
0 0 5 050 1 0100
0 I S150
O 2 0200
0 2 5250
0 300
300

Output
Output Loading (pF) O u t p u Output
t Loading
Loading (pF)
(pF)

2-22 4191.Rev.A
4/91.Rev.A
Ita Lattice® GAL16V8B
Specifications GAL 16V8S
.l.J oSemiconductor
Semiconductor
C o r p Corporation
ration Typical Characteristics
I'

lol
Vol vs 101 Voh VI
Voh vs Ioh
loh V o h vs loh
Voh VI loh

5 ....
4-50

0.75
0.75

....
0.25
,/
,/
,/'
/
/
s

5 0 2
3
........
""-
--- r- r-- ,
425
42'

4.00

'.75
3.75
"'- r-.
---r---
0 V 0 .... .... ....
3.50
0.00 2 020.00
00 4 40.00
0 00 6 10.00
0 00 8 '0.00
0 00 100.00
0000 0.00
0_00 1 10.00
0 00 2 20.00
0 00 330.00
0 00 4 CO.OO
0 00 550.00
0 00 610.00
0 00 0.00
0_00 1 . 0 0 2 . 0 0 3 . 03.00
0 4.00
4.00

lol (mA)
101 loh(mA)
Ioh(mA) loh(mA)
10h(mA)

Normalized Ice
Icc vs Vee
Vec Normalized lee vs
Normalized Icc vs Temp
Temp Normalized !cc vs
Normalized Icc vs Fraq.
Freq.

12.
120 12.
120 u.
1.30

I'-.. ....
120
1.10
1.10

V
1.10
1.10

I'--- .l;l L V
"il
3 too "il I'-.. "2
13 1.10
.......
----- 1,·00 V L
1.00 _1_1 1.00
1.00

1
= 00.80
.90
1.... 0.00
1""- I'..
... .0.90

f'-, .A.
0.80
0.80
....
4_50 4 . 74.75
5 0 , 05.00
0

Supply Voltage (V)


5 . 25.25
5 ....
5.00
0.80
020

-55 . 2 5 0

Temperature
2 5Z5

Temperature (deg. C)
1'5
7 5 t o tOO
o 125
125 .0.80

25 5

Frequency
.
0

Frequency (MHz)
(MHz)
7 5 ...
100

Delta Icc vs Vin (1


Delta Ice (1 input)
input) Input
Input Clamp
Clamp (Vik)
(Vik)

.....
•• /
4
••
20
3D
30
/
40
<-,40 1/

2 2
/1\ .§. ..
50
60 /

..
60

J \ 70
70
/
/
1
.....
II
80
1/
I'- 90
•100
00
0.00
0.00 0.50
0.50 1 1.00
. 0 0 1 1.50
. 5 0 22.00
. 0 0 2 2.50
_ 5 0 33.00
. 0 0 33.50
. 5 0 C4.00
OO ·2.00
-2 00 - 1 ·1.$0
50 . 1 . -1.00
0 0 -0.50
. 0 9 0 0.00
0.00

Vin(V)
Vito (V) Vik(V)
VA (V)

2·23
2-23 4191.Rev.A
4/91.Rev.A
[J;J
.l..i
'Lattice@
LLattice® SemiconductDr
Semiconductor
Corporation
CorporaUon
GAL161/8A
Specifications GAL 16V8A
Typical Characteristics
Normalized Tpd vs.
VS. Vcc
Vee Normalized Tsu
Normalized Ts u vs. Vee
Vcc Normalized TTco
Normalized vs. Vee
co vs. Vcc
"- 1.3
1.3

--- -
02
1.'

Oil 08

- r--
1 1.1
1-

-
'0
al to
1'"
1 1.0
OJ
E
o 0 05
0.'
Z
0.6
0.'

0.7
t1'74-!:
..
430 475 5 ...
00 5 2 5 5...
50 O. 0.7
450
.5O 4 75
4.76 5 0 5.00
0 5 2 5.25
5 5.50
450
'.SO 75
4.75 6 0 6.00
0 5 . 25.25
5 50
5,SO
Supply Voltage (V)
(V) S u p p l y
Supply Voltage (V)
Voltage Supply Vonage
Supply Voltage (V)
(V)

Normalized Tpd vs
vs. Temperature
Temperature N o r m a l Normalized
i z e d Tsu vs.
vs Temperature
Temperalure Normalized Too vs.
Normalized Teo vs. Temperature
1.3 1.3 I.,
1.3

-
2
1.2 12
12

1:111.1
'0 1.1
. . .v '"
II
1.1
. . .v I.'1.2
0.. III
g 1.1
1—
1-
V 1-
V 0
0

.. . /V
I-
a1
-? 1.0
1.0 a1-E t1.0
o
.to!
To
EE 00.'
4
V stt
IV

§ 09
E 0.'
V al4,4
g
13
.!:! 1.0
V
0'6
z V Z V 0.9
5 0.'
z
./
V
0.•
8 0.8
0.8

0.7 / 0.7
0.7
/ 0.'
0.8

.•
00.6
·so
.50 2 ·25
5 0 2 525 5 050 7 575 t o100
o 125
'25
00.•
6
·.0
.so ·25 0 25
2S 50 75
7S 100
100 125
125
0.7
07
.,
..50 • 2 ·25
5 0 2 5 5 0 5 1 0 0 1 2'25
5 "0
Ambient Temperalure (OC)
Temperature (CC) Ambient Temperature (0C)
Ambient ('C) Ambient Temperature('C)
Ambient (T)

Normalized Tpd
Tod vs.
.s.• Swhching
# of Outputs Switching Delta pd vs.
Delta TTpd vs. Output
Output Loading
Loading Normalized tcc vs.
Normalized Icc vs. Vcc
Vcc
1Co "1,3
/
1.00

V 12
12

R
090
0.98 L /
V
............
/
'.1
t—
/
1-
'0
/B
090
1-0T, 0.95
'iii
./ <D
1.0
.!:i 1.0
E
/ 77:
'iii
E 0.9 " ...............
....
ost
, /
Z
a'5 0.'

OS
0.'
...........
,/ ., /'
.92
0117
o 11110
2 0 0200 3 0 0300
100
07
0.7
•.4.50
SO 4 7 4.75
5 0 0 5.00
0 5 2 5.25
5 ....
5.50
• of Outputs Output
Output Loading
Loading Capacitance
Capacitance (pQ
(pf) Supply Voltage(V)
SupplyVoltage M

IOL vs. VOL


loL ye. VOL lom VS.
IOH VOH
vs. VOH Normalized icc vs.
Normalized Icc vs. Temperature
Temperature

-
250
2SO 150
·150
'.3

200
200
,.- '2

<" 150
.s
-'
12
056

,13 too
100

/
V :?
.s
::t
.Q
100
·'00

.50
·50
'" " ""'" ........
a1N
1ij
'TO
E
1.1

...
1.0

0.8
--r-- I'--..
......
i'--
r-....
""
a
Z
so
so

V
OS
0.'

•. 7
07 50
2 4 2 3 -50 25
-25 0 2 525 50 7 5
50 75 100
100 125
125

VOL
V O L (V)
(V) VOH(V)
VOH (V) Ambienl
Ambient Temperature
Temperature (0C)
(°C)

2-24 4/91.Rev.A
4 / 9 1 . R ev.A
i Lattke®
J; lLatUoo"
Semiconductor
Semiconductor
C o r pCorporation
oration
GAL20118B
GAL20V8B
GAL20118A
GAL20V8A
High Performance E2CMOS
High E2CMOS PLD
PLD r o
FEATURES FUNCTIONAL BLOCK
FUNCTIONAL BLOCK DIAGRAM
DIAGRAM
• HIGH
HIGH PERFORMANCE E2CMOS® TECHNOLOGY Voc
— 7.5 ns Maximum Propagation Delay
-7.5
-— Fmax == 100 MHz 24 —I
23
-— 5 ns Maximum from Clock Input to Data Output 11AUX
-— TTL Compatible 24 mA Outputs
-— UltraMOS® Advanced
Advanced CMOS Technology / OLL1C 22
22
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
I
-— 75mA Typ
lYP !cc
Icc on Low Power Device
01-PAC 21
-— 45mA Typ
lYP !cc
Icc on Quarter Power
Power Device 21

• ACTIVE
ACTIVE PULL-UPS ON ALL PINS (GAL20V8B) ,t
20
• E2
E2 CELL TECHNOLOGY
-— Reconfigurable
Reconflgurable Logic
Logic
-— Reprogrammabie
Reprogrammable Cells 41
— 100% Tested/Guaranteed 100% Yields
-100% ouxig
-— High Speed Electrical Erasure «100ms)
(<100ms) =r3--
-— 20 Year Data Retention
°LAC 18
18
• EIGHT
EIGHT OUTPUT LOGIC MACROCELLS
-— Maximum Flexibility for
for Complex Logic Designs
-— Programmable Output Polarity OLMC 17
17
-— Also Emulates 24-pln
24-pin PAL® Devices with Full
Full Func-
tion/Fuse Map/Parametric Compatibility
8 OLPAC 16
• PRELOAD
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
REGISTERS 16
.3--
-— 100% Functional Testability
• APPLICATIONS
APPLICATIONS INCLUDE: OLOAC 15
15
-— DMA
DMA Control
-— State Machine Control 11 —C. 14
11111®
-— High Speed Graphics Processing 12 13
-— Standard Logic Speed Upgrade
• ELECTRONIC
ELECTRONIC SIGNATURE FOR IDENTIFICATION PIN
PIN CONFIGURATION
CONFIGURATION
DESCRIPTION
The GAL20V8B,
GAL20\18B, at 7.Sns
7.5ns maximum propagation delay time,
time, com-
com- DIP
DIP
bines a high performance CMOS process with Electrically Eras- PLCC
PLCC
able (E2)
(E2) floating gate technology to provide the
the highest speed IICLK
VCLK 1 2 4 1 Vee
Vcc
performance available in the PLD market. High
High speed
speed erase
erase times
times
«1 OOms) allow the devices to be reprogrammed quickly and I!
(<looms) and ef-
_ g !11 >8 -
ficiently. 1/0/0
1/0/0
2.28
The generic architecture provides maximum design flexibility
flexibility by 1/0/0
VOIQ 1/0/0
i/O/Q
allowing the Output Logic Macrocell (OLMC) to bebe configured
configured by 110/0
3 1/0/0
110/0
I/0/0
the user.
user. An
An important subset of the many architecture con- GAL20VSAlB
GAL20V8A/B 1/0/0
IIO/Q

figurations possible with the


the GAL20V8A1B
GAL20V8A/13 are the PAL architec- NC
NC • NC
NC GAL I 1/0/o
1/0/0
tures listed in
in the table of the macrocell description
description section. 1 Top
Top View
View 110/0
8083
20V8A I 110/0
tioio
GAL20V8A1B
GAL20V8A/B devices are capable of emulating any of of these
these PAL
PAL 1 UOIO
90/0
architectures with full functionlfuse
function/fuse map/parametric compatibility.
compatibility. 1I0/Q
1NOM I 110/0
I/0/G
- - - - - - 1/0/0
1/0/0
Unique test circuitry and reprogrammable
reprogram mabie cells allow complete
complete 0
-
AC, DC,
DC, and functional testing during manufacture. AsAs a result,
result,
z2 2
" '" " 1/0/0
1/0/0
LATTICE is able to guarantee 100% fieldfield programmability and I
functionality of all GAL®
GAL products. LATTICE
LATTICE also guarantees 100
erase/rewrite cycles and data retention in in excess of 20 GND
GND 12 1 3 I IIOE
20 years.
years.

Copyright 01991
e1991 Lattice
Lattice Semiconductor
Semicondudor Corp. GAL. PCMOS
Corp. GAL, PCMOS andand UltraMOS
UltraMOS are
are registered
registered trademarks of Lattice
trademarksof Lattice Semiconductor
SemiconductorCorp. Generic Array
Corp. Generic ArrayLogic
Logicisic aatrademark ofLattice
trademarkof LatticeSemiconduc·
Semiconduc-
tor Corp.
Corp. PAL is a registered trademark of Advanced
PAl is Advanced Micro
Micro Devices, Inc. The
Devices, Inc. The specifications
specifications and
and information herein are
are subject
subject to
to change
change without
without notice.
notice.

LATTICE SEMICONDUCTOR CORP.,


LATTICE SEMICONDUCTOR CORP., 5555
5555 N.E.
N.E. Moore
Moore Ct., Hillsboro, Oregon
Ct., Hillsboro, Oregon 97124,
97124, U.S.A.
U.S.A. M a y May 1991.Rev.A
1991.13evA
Tel. (503) 681-0118;
Tel. (503) 681-0118; 1-800-FASTGAL;
1-800-FASTGAL; FAX (503) 681-3037
FAX (503) 681-3037
2-25
!lJtattiOOGl
LLattice®
.l.J Corporation
Semiconductor
Semironducwr
GAL201/8B
Specifications GAL20V8B
GAL20118A
GAL20V8A
GAL20V8A/B ORDERING INFORMATION

Commercial Grade Specifications


Tpd (ns)
Tpd Ts(' (n8)
Tsu (ns) Tco (ns)
Tco icc (mA)
Icc (mA) Ordering ##
Ordering Package
Package

7.5 7 55 115
115 GAL20V8B-71-1
GAL20V8B-7W 28-Lead PLCC
28-Lead PLCC
10 10 7 115
115 GAL20V8B-l0W
GAL20V8B-10LJ 28-Lead PLCC
28-Lead PLCC

115
115 GAL20VSA-l0LP
GAL20V8A-1 OLP 24-Pin
24-Pin Plastic DIP
DIP
115
115 GAL20V8A-l0LJ
GAL20V8A-101-1 28-Lead
28-Lead PLCC
PLCC
15 12 10
10 55
55 GAL20VSA-15QP
GAL20V8A-150P 24-Pin
24-Pin Plastic DIP
DIP
55
55 GAL20V8A-I5QJ
GAL20V8A-150J 2B-Lead
28-Lead PLCC
PLCC
115
115 GAL20V8A-15LP
GAL20V8A-15LP 24-Pin
24-Pin Plastic
Plastic DIP
DIP

115
115 GAL20V8A-15LJ
GAL20V8A-15LI 28-Lead
28-Lead PLCC
PLCC
25 15
15 12 55
55 GAL20V8A-25QP
GAL20V8A-250P 24-Pin
24-Pin PlastK:
Plastic DIP
DIP

55
55 GAL20V8A-25QJ
GAL20V8A-25CLI 28-Lead
28-Lead PLCC
PLCC
90
90 GAL20V8A-25LP
GAL20V8A-25LP 24-Pin
24-Pin Plastic
Plastic DIP
DIP
90
90 GAL20V8A-25LJ
GAL20V8A-251-1 28-Lead
28-Lead PLCC
PLCC

Industrial Grade Specifications


Tpd (ns)
(n5) Tsu (n5)
T5U (ns) Tco (n5)
Tco (ns) icc (mA)
Icc Ordering ##
Ordering Package
Package

15 12
12 10 130
130 GAL20V8A-15LPI
GAL20V8A-15LPI 24-Pin
24-Pin Plastic DIP
DIP

130
130 GAL20V8A-151-11
GAL20V8A-15WI 28-Lead
28-Lead PLCC
PLCC
20 13
13 11
11 65
65 GAL20V8A-200PI
GAL20V8A-200PI 24-Pin
24-Pin Plastic
Plastic DIP
DIP
65
65 GAL20V8A-200JI
GAL20V8A-200JI 28-Lead PLCC
28-Lead PLCC
25 15 12
12 65
65 GAL20V8A-25QPI
GAL20V8A-25QPI 24-Pin
24-Pin Plastic
Plastic DIP
DIP
65
65 GAL20V8A-25OJ1
GAL20V8A-250,11 28-Lead
28-Lead PLCC
PLCC
130
130 GAL20V8A-25LPI
GAL20V8A-25LPI 24-Pin
24-Pin Plastic
Plastic DIP
DIP
130
130 GAL20V8A-25WI
GAL20V8A-25LJI 28-Lead
28-Lead PLCC
PLCC

PART NUMBER DESCRIPTION

xxxxxxxx
XXXXXXXX -Xxx
X XX XX X
X

GAL20V8A DDevice
e v i c e N,me
Name
GAL20V8B

Speed (ns)
(n5) ' - - - - - Grade
Grade BBlank
l a n k == Commercial
Commercial
II = Industrial

L ==Low Power Power


Power L -_ _ _ _
Package PP =
Package = Plastic
Plastic DIP
DIP
Q = Quarter Power J== PLCC

2-26
2-26 4191.Rev.A
4/91.Rev.A
Serniconducwr
Specifications GAL20V8B
Corporation GAL20V8A
OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic


macrocell. It should be noted that actual implementation is ac- PAL Architectures GAL20V8A1B
complished by development soflwarelhardware and is completely Emulated by GAL20V8A1B Global OlMC Mode
transparent to the user.
20R8 Registered
There are three global DLMC configuration modes possible: 20R6 Registered
simple, complex, and registered. Details of each of these 20R4 Registered
modes is illustrated in the following pages. Two global bits, SYN 20RP8 Registered
20RP6 Registered
and ACO, control the mode configuration for all macrocells. The 20RP4 Registered
XDR bit of each macrocell controls the polarity of the output in any
of the three modes, while the ACI bit of each of the macrocells 2018 Complex
controls the input/output configuration. These two global and 16 20H8 Complex
individual architecture bits define all possible configurations in a 20P8 Complex
GAL20V8A1B. The information given on these architecture bits l4l8 Simple
is only to give a better understanding of the device. Compiler soft- l6l6 Simple
ware will transparently set these architecture bits from the pin l8l4 Simple
definitions, so the user should not need to directly manipulate 2012 Simple
these architecture bits. l4H8 Simple
l6H6 Simple
l8H4 Simple
The following is a list of the PAL architectures that the GAL20V8A 20H2 Simple
and GAL20V8B can emulate. It also shows the DLMC mode un- l4P8 Simple
der which the devices emUlate the PAL architecture. l6P6 Simple
l8P4 Simple
20P2 Simple

COMPILER SUPPORT FOR OLMC


Software compilers support the three different global DLMC In registered mode pin 1 and pin 13 are permanently configured
modes as different device types. These device types are listed as clock and output enable, respectively. These pins cannot be
in the table below. Most compilers have the ability to automati- configured as dedicated inputs in the registered mode.
cally select the device type, generally based on the register usage
and output enable (DE) usage. Register usage on the device In complex mode pin 1 and pin 13 become dedicated inputs and
forces the software to choose the registered mode. All combi- use the feedback paths of pin 22 and pin 15 respectively. Because
natorial outputs with DE controlled by the product term will force of this feedback path usage, pin 22 and pin 15 do not have the
the software to choose the complex mode. The software will feedback option in this mode.
choose the simple mode only when all outputs are dedicated
combinatorial without DE control. The different device types listed In simple mode all feedback paths of the output pins are routed
in the table can be used to override the automatic device selection via the adjacent pins. In doing so, the two inner most pins ( pins
by the software. For further details, refer to the compiler software 18 and 19) will not have the feedback option as these pins are
manuals. always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user


must pay special attention to the following restrictions in each
mode.

Registered Complex Simple Auto Mode Select


ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/IC GAL20V8 R GAL20V8 C7 GAL20V8 C8 GAL20V8
OrCAD-PLD "Registered"' "Complex"' "Simple"' GAL20V8A
PLDeslgner P20V8R2 P20V8C2 P20V8C2 P20V8A
TANGO-PLD G20V8R G20V8C G20V8AS3 G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
2-27 4/91.Rev.A
[JJ
1.J
LattiOO@
LLattice® Semiconductor
Semironductor
Corporation
Corporation
Specifications GAL20V8B
GAL20118B
GAL20118A
GAL20V8A
REGISTERED MODE
In the Registered mode, macrocells are
In are configured
configured as dedicated mode. Dedicated
mode. input or
Dedicated input oroutput
output functions
functions can
can be
be implemented
implemented
registered outputs or as I/O
110 functions. as subsets
as subsets of
of the
the VO
I/O function.
function.

Architecture configurations available in this


this mode
mode are similar to
to Registered outputs
Registered outputs have
have eight
eight product
product terms
terms per
per output.
output. I/0's
I/O's
the common 20R8 and 20RP4 devices with with various permutations
permutations have seven
have seven product
product terms
terms per
per output.
output.
of polarity, I/O and register placement.
TheJEDEC
The JEDECfuse
fuse numbers,
numbers, including
includingthe
theUser
UserElectronic
ElectronicSignature
Signature
All registered macrocells share common
common clock
clock and
and output
output enable
enable (UES) fuses
(UES) fuses and
and the
the Product
Product Term
Term Disable (PTD) fuses,
Disable (PTD) fuses, are
are
control pins. Any
Any macrocell can be configured as registered or shown on
shown on the
the logic
logicdiagram
diagram on
on the
the following
following page.
page.
I/O. Up
Up to eight registers or up to
to eight
eight I/O's
I/0's are
are possible
possible in
in this
this

CLK
elK

Registered Configuration
Registered Configuration for
for Registered
Registered Mode
Mode

- SYN-0.
-SYN=O.
- AC0=1.
-ACO=1.
X0R-0 defines
- XOR=O defines Active
Active Low
Low Output.
Output.
-• XOR=1
XOR.1 defines Active High
defines Active High Output.
Output.
AC1=0
- AC1 defines this
=0 defines this output
output configuration.
configuration.
-- Pin
Pin 1 controls common CLK
controls common CLK for
for the
the registered
registered outputs.
outputs.
-- Pin
Pin 13
13 controls
controls common
common OEOE for
for the
the registered
registered outputs.
outputs.
-- Pin
Pin 1 & Pin 13 are
Pin 13 are permanently
permanently configured
configured asas CLK
CLK &&
OE.
OE.
'.. ... - .. ,_._----------------------------------,
OE
OE

Combinatorial
Combinatorial Configuration
Configuration for
for Registered
Registered Mode
Mode

- SYN=O.
SYN=0.
-ACO:1.
- AC0=1.
-- XOR=O
XOR=0 defines
defines Active
Active low
Low Output.
Output.
-- XOR=1 defines Active
XOR=1 defines Active High
High Output.
Output.
-- AC1
AC1=1=1 defines
defines this
this output
output configuration.
configuration.
-- Pin
Pin 11 & Pin
Pin 13
13 are
are permanently
permanently configured
configured as
as CLK
CLK &
&
OE.
OE.
'..----------------------.---------------------,

Note: The development software configures all


all of
of the architecture control
control bits and
and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.

2-28
2-28 4/91.Rev.A
4/91.Rev.A
I id c t o r ®
GAL201f8B
Specifications GAL20V8B
Corporation GAL20118A
GAL20V8A
REGISTERED MODE LOGIC DIAGRAM
DIP (PLCC)
DIP (PLCC) Package Pinouts

....
".
1(2)
1(2) D ....
0 • B ,. 11 20 .. 211
" " Pro
2(3)
2(3) D 23(27)
-CJ23( 27)

rr'
0000 I n • URIC 22
M•m•!".•"•!!!•1"•M•MEMEHIE:111•! OLMC 22
22(26)
2(26)
0210 XOIT2560
XDR·2560
3(4)
3(4) D Otamsommomm molomoolosonumumoomelsosoomounwl ACI2632
AC1·2632

tr"
03,. 1111111111111111111111111111111111110
LIKIMEMEMEMEMEREMEMENEMEIN OLMC21
OLMC 21
(25)
21(25)
111111111 P I N E 1111111111111111 M a r i l l
06DO X011-2561
XOR·2561
4(5)
4(5) D AC12633
AC1·2633

kl..111111111111111111111111111111111111111111

0='
0840"'0 M E M B E I R F L I T H E I R E E R E I M I S I L I
OLMC20
OLMC 20
20(24)
0(24)
0920
== 3=f XOR·2562
X011-2562
5(6)
5(0 AC1-2634
AC1·2634

k 709S0„ 0 11111111111111111111111111111111111111111111

0='
-0- OLMC19
OLMC 19
MIMMIRMIMMONIMMIREMI 9(23)
9(23)
1240 X011-2563
XDR·2563
6(7)
6(7) molusloomosnosieneoloum AC1·2635
AC1-2635

1280 I H I I I I I I I I I I I I I I 1111111111111111111111111
M C 18
OLMC 18 rJ 8(21)
18(21)

[J
1
"'"1'"1'"1'111111111111111111111111!
1560 XOR·2564
XOR-2564
7(9))8
7(9 AC1·2636
AC1-2636

1600
•LELEMEMBLIEREMEMEMEHEREILI
.r, OLMC17
OLMC 17 rJ 7(20)
(7(20)

8(10))8
8(10
"10
kannto•oommoolomsnagoonummin lionmentimosariii
3=f
1880i i i i i i i i i i i i i i i i I i i i i i i i i • i i i i i i i i i i i i i i i ; j j XDR·2565
XOR-2565
AC1·2637
ACI-2637 [J
/820 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M e i n
1920
IPEIPLIMELIELTEMBRIMEMERMI OLMC 16
OLMC 16 11 6(19)
116(19)

9(11
9(11)
22DO XOR·2566
XOR-2566
AC1·2638
ACI-2638
[J
2240
2240IHEMEREMEMEHEIPMEH•EEKILI -0 OLMC 15
U K 15 rJ 15(18)

10(12)) 0
10{12
2520
2520
moulz:::::::Emzsuzuoamii=111SEEE1
Iltsioninommeamloomanootommemoneoloom luitonin
XDR·2567
X0R-2567
AC1·2639
ACI-2639 [J
11(13)) 0
11111111111 I I I M i l l
11(13 Oltassoommoonalommoulanutin m u m n o m • E i n :4 -CJ 14(17)
14(17)
DE
"03 13(16)
3(16)
64-USERELECTRONIC SIGNATUIEFUSES
•-••2630, 2eal SYN·2704
SYN-2704
Byte 71Byte 8 B y t e 1 !Byte 0 ACO·2705
AC0-2705
L
S
B B

2-29
2-29 4 / 9 1 . 1 R e v 4/91.Rev.A
. A
ALLattice
.l..J Semiconductor
Semioonductor
GAL20118B
Specifications GAL20VBB
Corporation
Corporation GAL20118A
GAL20VBA
COMPLEX MODE
In the Complex mode, macrocells are configured as
as output
output only pability. Designs
pability. requiring eight
Designs requiring eight IIO's
I/0's can
can be
be implemented
implemented in
inthe
the
or I/O
1/0 functions. Registered mode.
Registered mode.

Architecture configurations available in


in this
this mode are similar to
to All macrocells
All macrocells have
have seven
seven product
productterms
termsperperoutput.
output. One
One product
product
the common 20L8 and 20P8 devices withwith programmable
programmable polarity
polarity term is
term is used
used for
for programmable
programmable output
output enable
enable control.
control. Pins and
Pins 1 and
in each macrocell. 13 are
13 are always
always available
available as
as data
data inputs
inputs into
intothe
theAND
AND array.
array.

Up to six IIO's
I/0's are possible
possible in this mode. Dedicated
Dedicated inputs
inputs or
or The
TheJEDEC
JEDECfuse
fuse numbers
numbers including
including the
the UES
UESfuses
fusesand
and PTD
PTDfuses
fuses
outputs can be implemented as subsets of of the I/O function.
function. The are
are shown
shown on
on the
the logic
logic diagram
diagram on on the
thefollowing
following page.
page.
two outer most macrocells (pins
(pins 15 &
& 22) do
do not have input
input ca-
ca-

................... _------_ ..... _............ Combinatorial I/O Configuration


Combinatorial 1/0 Configuration for
for Complex
Complex Mode
Mode

J -SYN-1.
- SYN=1.
-ACO
- XOR.O
.. 1.
- AC0=1.
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR=1
XOR=1 defines Active
Active High
High Output.
Output.
-AC1=1.
-AC1=1.
-- Pin
Pin 16
16 through
through Pin
Pin 21 are configured
21 are configured to
tothis
this function
function..

...... -............ -- ................................

po . . . - . . . . . . . . . . _ - . . . . - - • • - - . . . . . . . - - . - - - _ . . . - . . .

Combinatorial
Combinatorial Output
Output Configuration
Configuration for
for Complex
Complex Mode
Mode

i; P-r,D XOR
X0 R
Cl--o
o f l
-SYN=1.
- SYN=1.
-ACO .. 1.
- AC0=1.
-- XOR
XOR=0
-- XOR=1
..Odefines
defines Active
Active Low
XOR=1 defines Active
-AC1-1.
Low Output.
Active High
Output.
High Output.
Output.
- AC1=1.
-- Pin
Pin 15
15 and Pin 22
and Pin 22 are
are configured to
to this
this function.
function.
-- .... ---.-.. _-_ ...... __ ._------------_ ...

Note: The development software configures all


all of the
the architecture control bits.and
bits and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.
!
/

2-30
2-30 4191.Rev.A
4/91.Rev.A
!lJ
tBttice
LLattice®
Semiconductor
Semironductor
Corporation
®

GAL20118B
Specifications GAL20V8B
GAL20118A
GAL20V8A
COMPLEX MODE LOGIC DIAGRAM
DIP (PLCC)
DIP (PLCC) Package Pinouts
Package Pinouts

.. .. ....
1(2) D .
1(2)

2(3) E
2(3) >
L.>---
• • • I 1 212 1 6
11 2 010 2 414 2 221 Pill
PlD

.A
j - - C D 23(
23(27)
27)

.,,,
0K7.:122(26)
0000
a=
0280
:a=
'tj=
DUE 22
OLMC 22
X0R-2560
XOR-2560
... -r122(26)

3(4)
3(4) ACl-2632
AC1-2632

"" J
OLMC21
OLMC 21 ,..r,2121(25)
(25)
"., "'--': XOR-2561
XOR-2561
401 .--..
4(5) ACI-2633
ACl-2633

"40
0640
:a= OLMC
OLMC20
20 =:l
--.::J 02
20(24)
0(24)
XOR-2562
MR-2562
5(6)
5(6) D "" ACl-2634
AC1-2634

,."
!!! IC ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! = CILMC19
OLMC 19 n v
J-G1
9(23)
19(23)
-=-
-
1240
1240 XOR-2563
XOR-2563
6(7)
6(7)
.---.. i i i i i i i i i ni i i i i i i i i 11 1 0 1 • M= • i i i i i i i i i i i i
mossiminommilenommon t o s o m onn a o i sl n s m o i l w l ACl-2635
ACI-2635

k I"80
I I I I I I I I I I I I I I I I 11111111111111111111N

M
1280
gigEmmemellimili•ilinitimmi ,_
ilEMEMEMENIEMMIIIIIMPIPc M C 18
OLMC 18 18(21)
1580 XOR-2564
X0R-2564
7(0))0
1580
gnillIMIIIMIMIIIIIIII - ACl-2636
ACI-2636
7(9 k-7—Iiiiiiiiiiini
60, Iiiiiiiiiiiiiiimul I i i i i i i i i i i i i i i r
"" glimmemenemenmeming= .0-
OLMC 17
0ilfi1111111:iiiiiiiiissimislimiligm = MAC 17 — dv) o D -Y"'l1
1 7 ( 27(20)
0)

8(10))D
8(10
1880
1880
iiiiiiiiiiiiiiiiiiiiiiiiiriiiiiiinolL
1.-atimamosomuswoomoolooesmilen1•I m. .
XOR-2565
XOR-2565
ACl-2637
ACI-2637 J
1320111111111111111111111111111111111M1
"" FIERIERELIELI"Ll"!1"EMEME--
:::=:::211=:::=:•:=Eirdireirmancramms OLMC 16
OLMC16 v 16(19)
22" =8= XOR-2566
XOR-2566
9(11))8
9(11 2200l n a n a s o n l i k AnommosounnasseaumnI!.m ACl-2638
AC1-2638

2240111111E1111111111111111111111111111
2240
LIMEHIETI• !I!!!!! MITEMBEE--
OLMC 15
OLMC15 15(18)
K=315(18)

10(12)
10(12)
,--,. .."
2620 i i i i i i i i i i i i i i i i i
II.M o s i o o nm m m u m . u n n
i i i i i i i i i i i i i r l . "
o os no m o n felloonot:41
i
XOR-2567
XOR-2567
ACl-2639
ACI-2639
I -a 14(17)
110. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111111111 I I I I I I ..... C314(17)
11(13),--,.
11(13) mel ono ommemoon emounolegalumelo • moust4
-a 13(16)
C l 1306)
1113
2703
fI4.U8EII ELECTRONIC8IGNAlURE
64-USERB.fCIlIONIC SIGNATUREFU8EB
FUSES

l&:7iC.·....
M
bits 7IByts 6
M LL
B y . . _,:01
t e
2030, 2031
1 'Byte 0
SYN-2704
SYN-2704
ACO-2705
AC0-2705

88 8 8
B8 BB

2-31
2-31 4 / 9 1 . 1 R e v 4/91_Rev.A
. A
L/Semiconductor
Lattice
Corporation
GAL201/8B
Specifications GAL20VBB
GAL201/8A
GAL20VBA
SIMPLE MODE
In the Simple mode, pins are configured as dedicated inputs or Pins 1 and
Pins are always
and 13 are always available
available as
asdata
datainputs
inputs into
intothe
theAND
AND
as dedicated, always active, combinatorial outputs. array. The "center"
array. ''center two
two macrocells
macrocells (pins
(pins 18
18 && 19)
19)cannot
cannotbe beused
used
in the
in the input
input configuration.
configuration.
Architecture configurations available in
in this
this mode are similar to
to
the common 141_8
14L8 and 16P6 devices with
with many permutations
permutations ofof The
TheJEDEC
JEDECfuse
fuse numbers
numbers including
includingthe
the UES
UESfuses
fusesand
andPTD
PTDfuses
fuses
generic output polarity or input choices. are
are shown
shown on
on the
the logic
logic diagram
diagram onon the
thefollowing
following page.
page.

All outputs in the simple mode have a maximum of of eight


eight product
product
terms that can control the logic. In addition, each
logic. In each output
output has
has
programmable polarity.
polarity.

...... _--------------_. __ ._------.----------


Combinatorial
Combinatorial Output
Output with
with Feedback
Feedback Configuration
Configuration
Vee
V cc for
for Simple
Simple Mode
Mode

-- SYN=1.
SYN=1.
-ACO=O.
- AC0=0.
-- XOR=O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1 .. 1 defines
defines Active
Active High
High Output.
Output.
-- AC1
AC1=0 =0 defines
defines this
this configuration.
configuration.
-- All
All OLMC
OLMC except
except pins 18 &
pins 18 & 19 can
can be
be configured
configuredto
to
this
this function.
function.

Combinatorial Output
Combinatorial Output Configuration
Configuration for
for Simple
Simple Mode
Mode

-- SYN=1.
SYN=1.
-ACO=O.
- AC0=0.
-- XOR=O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR=
XOR=11 defines
defines Active
Active High
High Output.
Output.
-- AC1 =0 defines
AC1=0 defines this
this configuration.
configuration.
-- Pins 18 &
Pins 18 & 19 are
are permanently
permanently configured
configured to
to this
this
.'-------._.---------------------------------_.: function.
function.

Dedicated
Dedicated Input Configuration
Configuration for
for Simple
Simple Mode
Mode

-SYN .. 1.
-ACO-O.
-- XOR
XOR=0 ..Odefines
defines Active
Active Low
Low Output.
Output.
-- XOR=1
XOR=1 defines
defines Active
Active High
High Output.
Output.
- AC1
AC1=1 =1 defines
defines this
this configuration.
configuration.
.._---------------------------.--------------,. --All
All OLMC
this
OLMC except
except pins 18 &
pins 18 & 19
19 can
can be
be configured
configured to
to
this function
function..

Note: The development software configures all of the architecture control


control bits
bits and
and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.

2-32
2-32 4f91.Rev.A
4/91.Rev.A
I,
::j

Lattice® GAL201f8B
Specifications GAL20V8B I.;
1.1
1 Ind ISemiconductor
Semironductor
Corporation
Corporation GAL20118A
GAL20V8A Ii

SIMPLE MODE LOGIC DIAGRAM


DIP (PlCC)
DIP (PLCC) Package Pinouts
Package Pinouts

. ....
1(2)
1(2) LJ
0 '

2(3) LJ
2(3)
, • • ,.
" 8 1 2 1 6 .. 1M 211
2
II
40

.A
j 23(27)
rCJ23( 27)

11111•1.11L1
.... !!!!!!!!!!1!!•!!!!!"EMILSIMEIMME OLMC 22
OLMC 22 N I b
.... i i i n i i i i i i i i i i i i i i i i i i i i::a=:::t XOR·2560
i i i a . 0011-2560
AC1-2632
AC1·2632
J ... 22(26)
-cl22( 26)

.A
3(4)
3(4) 0

"..
0280 1 1 1 1 1 1 1 1 1 1
0320
WEN HEREPIEHEMEMELTEnr47 •• • 0I-MC
1111 0 111111 0 111 a l
OLMC 21
21
XOR-2561
XOR·2561
n
J .. -cl2121(25)
(25)
....
0600
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 P E E ::::a=:::::::I
....•01•
A C 1 -AC1·2633
2633

4(5)
4(5) LJ 10.. i m e e m 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1

....
0940

....
MIME 11011111111111111111111111
MELSEMEMEMEMEHEMEHLIMEmeml .0.
111111111MILitinitilliiiiiiii110-
OLMC 20
XOR·2562
AC1·2634 J
n n220(24)
0(24)

5(6))L..J
5(6 .....

....
0960
1111111111111111111111111111111111m1
MENELHEMEHIEHLIPIERIELEWIr4: In OLMC °WC 19
19 h
XOR-2563
XOR·2563 0 119(23)
9(23)
'240
i i r i i i i r i i E • i i i i i ! i " E 2::a=:::t
E'- AC1-2635
AC1-2635
::;,
J
6(7)
6(7) D

"t'4'
'2" "1"11"1"111
IIIIIIIIIIIIIII I 11111111111110111=
1 momonim. ;$
Jb..
1280
OLMC 18
I H I M E I B M M I R I M I N I M h a — OLMC18 X0R-2564
XOR·2564 8(21)
"""'118(21)
iiiiiiiEhEiliEricao•-:„Eram:::=SE=
7(9)
7( 9) L....J
" 1560
..
iiiiiiiiiiiiiiiiiiiiIIMINIIIIiiiiiiii
lomollootoomomi taoloomounmoomoommososomm$1
::::a=:::::::I AC1·2636
AC1-2636

"..
1600
IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIII
-0- OISIC 17
OLMC 17
X0B2565
XOR·2565
n -C"] 117(20)
7(20)
(B80 1 1 41 1" 111 "1 1
"SO
1 11 111 21 49 111 9B 1E 1 : 1" 2! : :: : 1 21: 1
se 1m1t •1pm
1 1• 1 1 1 : 1 3 1 1 r 7 AC1-2637
AdI-2637 J
8(10
8(10)) IIP. M E I M E N E M I I I I I M I N E M I L K I I I

""
1920
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
HINEEMEMEMEMBEEMEME
== 1111111111111111,1111111EllisilElialikri=
OLIC 16
OLMC 16
XOR-2566
XOR·2566
AC1-2638
AC1-2638
n
J ... -nl16(
6(19)
9)
22,.
2200
9(1 1)
9(11) —1..iAnannommEnammonnol mnino
iiiiiiiiiiiiiiiiiiiiiiiiiiilliiiiiiiiii
n
s
lg
m

Jb,. . . .-
2240
2240
1111111111111011111111111111 1111111111
I M E H I M I H I M I H E M E M E M B E :.1.n1 OLMC 15
OLMC 15
25"2
mainsidainsirmialEMELEIREEL:1 9::::::=1 X0R-2567
XOR·2567
AC1-2639
15(18)
15(18)

10(1 2)D
10(12)
0iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiir .A
AC1-2639

11(1 3)
11(13)
ilimmilummilimilffilU
.11mul.11111111111..11.1u...1"."111 R I '
III* s o i n o m m o i o u s m o l l s s o s s o s s o u t i m a s •es m e gill
....
I -CJ 14(17)
13(16)

84-USER
134-USERElECI'RONIC
ELECTRONICSIGNATURE
SIGNATUREFUSSS
FUSES
2'"
2703

1:\=,··....
Byte71Byte
101 L
B y t .. . e
2830, 2e31
1IByte
SYN·2704
SYN-2704
ACO·2705
ACO-2705

8S S S
B
B BB

2-33
2-33 4 / 9 1 . R e v .4191.Rev.A
A
[JJ
.l.I
tattice®
Lattke®
Semiconductor
C o r p Corporation
oration
GAL20118B
Specifications GAL20V8B
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS')
RATINGS(l) RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
Supply voltage Vcc — 0 . 5-0.5 to +7V
Vee ....................................... Commercial Devices:
Commercial Devices:
Input voltage applied ...........................
— 2 . -2.5 5 to Vee
Vcc +1.0V Ambient
Ambient Temperature
Temperature (T(TA) 0
A ) •••••••••••••••••••••••••••••••• 0 to
to 75°C
75°C
Off-state output voltage applied ........ — ,.2-2.5
. 5 to Vee
Vcc ++1.0V
1.0V Supply
Supply voltage
voltage (Vee)
(Vcc)
Storage Temperature .................................
— 6 5 -65 to 150°C with
with Respect to
to Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Ambient Temperature with
Power Applied ........................................
— 5 5 -55 to 125°C
1.Stresses above
above those listed under the "Absolute Maximum
Maximum
Ratings" may cause permanent damage to the device. These These
are stress only ratings and functional operation ofof the
the device
at these or at any other conditions above
above those
those indicated
indicated in
in the
the
operational sections of this specification is not implied (while
programming, follow
follow the
the programming specifications).
specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating
Operating Conditions (Unless Otherwise
Otherwise Specified)
Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP."
TYP.3 MAX.
MAX. UNITS
UNITS

VIL Input Low Voltage Vss-0.5


Vss – 0.5 -- 0.8
0.8 VV
VIH Input High Voltage 2.0
2.0 - VCC+1
Vcc-1-1 VV
ilL' Input or 1/0
I/O Low
Low Leakage Current OV VIN 5 VIL
DV5_ VIN Vit. (MAX.)
(MAX.) -— -— -100
–100 p.A
!LA
IIH
ilH Input or 1/0
I/O High Leakage Current 3.5V VIN 5 Vee
3.5V S VIN Vcc -- -- 10
10 ;.LA
!LA
VOL Output Low Voltage 10L=MAX. Yin
lot_ = MAX. Vi n = VIL
VII_or VIH1-I
or V1 -— -
— 0.5
0.5 VV
VOH Output High Voltage 10H
loH = MAX. Vin
MAX. Vi n = VII_
VIL or VIH
or V11-I 2.4
2.4 -— -— VV
10L
i0L Low Level Output Current -— -— 24
24 mA
mA
10H
i0H High Level Output Current -— -— -3.2
–3.2 mA
mA
los2
i0S2 Output Short Circuit Current Vcc=5V VOUT== 0.5V
Vcc = 5V VOUT TA= 25°C
0.5V TA= 25°C -30
–30 -— -150
–150 mA
mA
Icc
1CC Operating Power
Power Supply
Supply Current VIL=
Vit.. = 0.5V VIH = 3.0V
0.5V Vii-l= ftoggle == 25MHz
3.0V toggle 25MHz -— 75
75 115
115 mA
mA
Outputs
Outputs Open
Open (no
(no load)
load)
1) The leakage current is due to the internal pull-up resistor on
on all pins. See Input
pins. See Input Buffer
Buffer section
secfon for
for moreJnformation.
mo e information.
2) One output at a time for a maximum duration of of one
one second. Vout = 0.5V
second. Vout 0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
bytester
tester
Guaranteed but not
ground degradation. Guaranteed not 100% tested.
3) Typical values are
are at Vcc = 5V
5V and TA == 25°C
and TA 25 °C

CAPACITANCE (TA =
(TA = 25°C, ft = 1.0 MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
CI Input Capacitance 88 pF
pF Vcc=
Vee = 5.0V,
5.0V, V,
VI == 2.0V
2.0V
Clic
CliO 1/0
I10 Capacitance 88 pF
pF Vcc == 5.0V,
Vcc V'iO
5.0V, V1 10== 2.0V
2.0V
"Guaranteed
*Guaranteed but not 100%
100% tested.

2-34 4/91.Rev.A
4/91.Rev.A
flJ
LLattice'
•AC
UJtticeGP
Semironductor
Semiconductor
C0i'p(X'8t/01l
Corporation

AC SWITCHING CHARACTERISTICS
GAL,201/8B
Specifications GAL20V8B
Commercial

Over Recommended Operating


OVer Operating Conditions
Conditions

TEST -7
·7 -10
·10
PARAMETER
PARAMETER DESCRIPTION UNITS
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or 110
Input I/0 to
to Combinational Output I 88outputs switching
switching 33 7.5
7.5 33 10
10 ns
ns
I 11output switching
switching -— 77 -— -— ns
ns

tco 11 Clock to Output Delay 22 S5 22 77 ns


ns
tcf2 -— Clock to Feedback Delay -— 33 -— 66 ns
ns
tsu -— Time, Input
Setup lime, or Feedback
Input or Feedback before Clockt
Clocki 77 -— 10
10 -— ns
ns
th -— Hold Time,
lime, Input or Feedback after
after Clockt
Clock')' 00 -— 00 -— ns
ns
11 Maximum Clock Frequency with 83.3
83.3 -— 58.8
S8.8 -— MHz
MHz
External Feedback, 1/(tsu + teo)
External tco)

f max33
fmax 11 Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
tcf)
100
100 -— 62.5
62.S -— MHz
MHz

11 Maximum Clock Frequency with


with 100
100 -— 62.5
62.S -— MHz
MHz
No Feedback

twh4
twh -— Clock Pulse Duration, High 5
S -— 88 -— ns
ns

twt'
twi's -
— Clock Pulse Duration, Low S5 -— 88 -— ns
ns
ten 22 Input or 110
Input I/O to
to Output 33 99 33 10
10 ns
ns
22 OE.!.
0E1 to Output 22 66 22 10
10 ns
ns
tdis 33 Input or 1/0
Input I/O to
to Output 22 99 22 10
10 ns
ns
33 OEt
0E1 to Output 1.S
1.5 66 1.S
1.5 10
10 ns
ns
1) Refer to Switching Test Conditions sectIOn.
section.
2) Calculated from fmax with internal feedback. Refer
Refer to
to fmax
fmax Descriptions
Descriptions section.
section.
3) Refer to fmax
imax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as
as valid
valid clock signals.

SWITCHING TEST CONDITIONS


CONDITIONS
Input Pulse Levels GNDt03.0V
GND to 3.0V +5V
+5V
Input Rise and Fall limes
Times 3ns 10%-90%
3ns 10*/0 – 90%
Input Timing Reference Levels 1.SV
1.5V
Output Timing Reference Levels
OutpU1liming 1.SV
1.5V 1
Output Load See
See Figure
O.SV from steady-state active
3-state levels are measured 0.5V
level.
FROM OUTPUT (010)
FROMOUTPUT (0/0) --+---..- TEST
TESTPOINT
POINT
UNDER TEST
UNDERTEST
Output Load Conditions (see
(see figure)
figure) CL
R2
Test Condition RI
Hi R2
R2 CL
CL
1 2000
2000 3900 SQpF
50pF
2 Active
Active High .0
00 3900
3900 SOpF
50pF

3
Active
Active
Low
Active Low
Active High
High
Active Low
-
2000
2000
.0
2000
3900
3900
3900
3900
3900
50pF
50pF
SpF
5pF
5pF
5pF
C
CL INCLUDESJIGA
LlNCLUDESJIG NDP
AND ROBET
PROBE OTALC
TOTAL APACITANCE
CAPACITANCE

2-35 4/91.Rev.A
4/91.Rev.A
1£ Lattice® Semiconductor
SemiconduGwr
Corporation
Specifications GAL201113A
GAL20V8A
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS(1)
ABSOLUTE RATINGS(1) RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
vee .......................................
Supply voltage Vcc — 0 . 5-0.5 to ++7V
7V Commercial
Commercial Devices:
Devices:
Input voltage applied ...........................
— 2 -2.55 to to Vcc +1.0V
Vee + 1.0V Ambient Temperature
Ambient Temperature (TA) 0
(TA ) •••••••••••••••••••••••••••••••• to 75°C
0 to 75°C
Off-state output voltage applied ..........— 2-2.5 . 5 toto Vee
Vcc +
+1.0V
1.0V Supply voltage
Supply voltage (Vee)
(Vcc)
Storage Temperature .................................
— 6 5 -65 to to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Ambient Temperature with
— 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses above those listed under the· the "Absolute Maximum
Absolute Maximum
Ratings" may cause permanent damage to to the
the device. These
These
are stress only ratings and functional
functional operation of the
the device
device at
at
these or at any other conditions above those indicated in the the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise
Otherwise Specified)
Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP.2
TYP.2 MAX.
MAX. UNITS
UNITS

VIL Input Low Voltage Vss -0.5


Vss-O.5 -— 0.8
0.8 VV

VIH Input High Voltage 2.0


2.0 -— VcC+1
Vcc+1 VV

IlL
ilL Input or 1/0
input I/O Low Leakage Current OV VIN 5 VII_
OV 5 VIN VIL (MAX.)
(MAX.) -— -— -10
-10 J.,4
J.lA
IIH Input or 110 leakage Current
I/O High Leakage VIH 5 VIN
VIH VIN _c_VCC
Vee -
— -— 10
10 p_A
J.lA
VOL Output Low
Low Voltage loL =
10L = MAX.
MAX. Vi
Yinn=
= VIL
Vit. or
or VIH
VIH -
— -— 0.5
0.5 VV

VOH Output High Voltage IOH


loH == MAX. Vin
MAX. Vi VIL or
n == VII_ VIH
or VIH 2.4
2.4 -— -— VV

10l
i0L Low Level Output Current
low -— -— 24
24 rnA
mA
10H High Level
level Output Current -— -— -3.2
-3.2 rnA
mA
los'
lost Output Short Circuit Current VOUT=
Vcc = 5V Va
Vcc=5V l i ' = 0.5V
0.5V T,TA- =, 25°C
25°C -30
-30 -— -150
-150 rnA
mA
Operating Power VIL
ViL =. 0.5V
0.5V VVIH
H = 3.0V
3.0V toggle =
f,oggl8 - , 15MHz
15MHz L·25
L -25 -— 75
75 90
90 rnA
mA

ICC
Icc Supply Current Outputs
Outputs Open (no
(no load)
load) flO9gl8 = 25MHz
toggle --, 25MHz LL -101-15
-10/-15 -— 75
75 115
115 rnA
mA
f'099I8 15MHz
fioggie = 15MHz 0·15/-25
0 -15/-25 -— 45
45 55
55 rnA
mA
1) One output at a time
time for
for aa maximum duration of
of one second. Vout
Vout == 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
p oblems caused
caused by
by tester
tester
ground degradation. Guaranteed
Guaranteed but not 100% tested.
tested.
2) Typical values are at Vcc = - 5V
5V and TA = 25 ·C
and TA *C

=
(TA = 25°C, f1= 1.0 MHz)
CAPACITANCE (TA MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM-
MAXIMUM UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
Ci Input
Input Capacitance 88 pF
pF VVcc
cc == 5.0V,
5.0V, V,
Vi == 2.0V
2.0V
Cu,
ClIO 1/0
I/O Capacitance
Capacitance 10
10 pF
pF Vee
Vcc== 5.0V, VIIO == 2.0V
5.0V, VL,0 2.0V
'Guaranteed
'Guaranteed but not 100%
but not 100% tested.
tested.

2-36
2-36 4191.Rev.A
4/91.Rev.A
GAL20118A
Specifications GAL20V8A
.lJ
L ISeicot nd.uctor®'c
SemioonducUJr
CorporaUon
Corporation
e
Commercial
Commercial
AC SWITCHING CHARACTERISTICS
AC CHARACTERISTICS
Over Recommended
Over Recommended Operating Conditions
Conditions

TEST -10
-10 -15
-15 -25
-25
PARAMETER
PARAMETER DESCRIPTION
DESCRIPTION UNITS
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tod
tpd 1 Input or va
input or I/0 to
to Combinational Output
Combinational Output 33 10
10 33 15
15 33 25
25 ns
ns

tco
teo 1 Clock to
Clock to Output Delay 22 77 22 10
10 22 12
12 is
ns

'Liz2
tel Clock to
Clock to Feedback Delay
Delay -
— 77 -— 88 -— 10
10 ns
ns

tsu Time, Input or Feedback


Setup Time, before Clocki
Feedback before 10
10 -— 12
12 -— 15
15 -— ns
ns

th Hold Time, Input or


Hold or Feedback after
after Clocki
Clockt 00 -— 00 -— 00 -— ns
ns
11 Maximum Clock
Maximum Frequency with
Clock Frequency with 58.8
58.8 - — 45.5
45.5 -— 37
37 - — MHz
MHz
External Feedback, 1/(tsu + teo)
External too)

fmax33
fmax 11 Maximum Clock
Maximum Clock Frequency with
with 58.8
58.8 -— 50
50 -— 40
40 -— MHz
MHz
Feedback, 1/(tsu + tel)
Internal Feedback, tcf)
11 Maximum Clock Frequency
Maximum Clock Frequency with
with 62.5
62.5 -— 62.5
62.5 -— 41.7
41.7 -— MHz
MHz
No
No Feedback
twh4
twh Clock Duration, High
Clock Pulse Duration, High B
8 -— 88 -— 12
12 -— ns
ns
twl4
tw14 Clock
Clock Pulse Duration, Low
Low B
8 -— 88 -— 12
12 -— ns
ns
ten 22 Input va to
Input or I/O Output Enabled
to Output Enabled -
— 10
10 -— 15
15 -— 25
25 ns
ns
22 OE.!. Output Enabled
0E1 to Output -— 10
10 -— 15
15 -— 20
20 ns
ns
tdis 33 Input va to
input or I/O Output Disabled
to Output -— 10
10 -— 15
15 -— 25
25 ns
ns
3 OEi
OET to
to Output Disabled
Disabled -— 10
10 -— 15
15 -— 20
20 ns
ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to
feedback. Refer to fmax
fmax Descriptions section.
section.
3) Refer to Imax
fmax Descriptions llection.
section.
4) Clock pulses of widths
widths less than
than the specification
specification may be detected as valid clock
clock signals.

SWITCHING TEST CONDITIONS

Input Pulse Levels GNDto


GND to 3.0V +5V
+5V
Input Rise and Fall Times 3ns 10%-90%
3ns 10'/0 – 90%
Input Timing Reference Levels 1.5V
1.5V
Output Timing Reference
Reference Levels 1.5V
1.5V
1
Output Load See
See Figure
3-state levels are measured 0.5V from steady-state active
from steady-state FROM OUTPUT (010)
FROMOUTPUT (0/0) ---+----+--TEST
TESTPOINT
POINT
level.
UNDER TEST
UNDERTEST
Output Load Conditions (see figure)
Cl
Test Condition R,
RI Rz
R2 CL
CL
11 2000 3900
3900 500F
50pF
2 Active
Active High ...
00 3900
3900 50pF
50pF
Active
Active Low 2000 3900 50pF
50pF
3 Active
Active High e.
00 3900
3900 5pF
5pF C
CL INCLUDES
INCLUDES JIG AND PROBE
JIGAND PROBE TOT
TOTAL CAPACITANCE
ALCAP ACITANCE
Active Low
Active Low 2000 3900
3900 5pF

2-37 4191.Rev.A
4/91.Rev.A
Lattice® GAL20118A
Specifications GAL20V8A
.l..J oScmiconductnr
Semiconductor
C o r p Corporation
ration Industrial
Industrial
ABSOLUTE MAXIMUM RATINGS0)
RATINGS(1) RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.

Supply voltage Vcc — 0 . 5-{).5 to +7V


Vee ....................................... +7V Industrial
Industrial Devices:
— 2 . -2.5
Input voltage applied ........................... 5 to to vee
Vcc +
+1.0V
1.0V Ambient Temperature
Ambient Temperature (TA) — 4 0-40 to
(TA) ............................ to 85°C
85°C
Oft-state output voltage applied ..........
Off-state — 2-2.5 . 5 to Vcc +1.0V
Vee + 1.0V Supply voltage
Supply voltage (Vee)
(Vcc)
Storage Temperature .................................
— 6 5 -65 to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
Ambient Temperature with
— 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses above those listed under the the "Absolute Maximum
Maximum
Ratings·
Ratings" may cause permanent damage to to the device. These
These
are stress only ratings and functional
functional operation
operation of the device
device at
these or at any other conditions above those indicated in in the
the
operational sections of this specification is not
not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer
Over Recommended Operating Conditions (Unless
(Unless Otherwise
Otherwise Specified)
Specified)

SYMBOL PARAMETER CONDITION


CONDITION MIN.
MIN. TYP."
TYR, MAX.
MAX. UNITS
UNITS

VIL Input Low Voltage Vss-O.S


Vss –0.5 -— 0.8
0.8 VV
VIH Input High Voltage 2.0
2.0 -— VcC+1
Vcc+l VV
IlL Input or 110
I/O Low
Low Leakage
Leakage Current OV
CVSVIN
VIN S Vil (MAX.)
VII_ (MAX.) -— -— -10
–10 RA
J-lA
IIH Input or VO
I/O High Leakage Current VIH
Vit-i SVIN
VIN S Vee
VOC -— -— 10
10 J-lA
1.1.A

VOL Output Low


Low Voltage
Voltage 101.
lot. -= MAX. Vi
Yinn -= Vil
Va. or
or VIH
VII-, -— -— 0.5
0.5 V
VOH Output High Voltage IOH
lok ..
= MAX. Vin.= VIL
MAX. Vin Vit. or VIH
or VII-1 2.4
2.4 -— -— VV
10L
i0L Low Level Output Current
Curren: -— -— 24
24 mA
mA
10H
i0H High Level Output Current -— -
— -3.2
–3.2 mA
mA
los'
i0S1 . Output Short Circuit Current Vccz
Vcc = 5V YOUTz= 0.5V
5V VOUT TA=- 25·C
0.5V TA 25°C -30
–30 -— -150
–150 mA
mA
Operating Power VIL=
Vit. = 0.5V VIH=3.0V
0.5V VIH = 3.0V floggle
toggle = 25MHz LL ·15/-25
-15/-25 -— 75
75 130
130 mA
mA

Icc
iCC Supply Current Outputs load) floggle
Outputs Open (no load) toggie ..
= 15M Hz
15MHz a0 -20/-25
-20/-25 -— 45
45 65
65 mA
mA
1) One output at a time
time for
for a maximum duration of one
one second. Vout ..= 0.5V
second. Vout 0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
ground degradation. Guaranteed
Guaranteed but not 100% tested.
2) Typical values are at Vcc =- 5V and TA
TA"225
5 ·C
'C

=
(TA = 25°C, ff = 1.0 MHz)
CAPACITANCE (TA

SYMBOL PARAMETER
PARAMETER MAXIMUM-
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C, Input Capacitance 88 pF
pF Vee
Vcc== 5.0V,
5.0V, V,
V, == 2.0V
2.0V
Coo 110
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V,
5.0V, VIIO=
Vuo = 2.0V
2.0V
. Cito
Guaranteed but not 100'/0
"Guaranteed 100% tested
tested..

2-38 4/91.Rev.A
4/91.Rev.A
[JJ
.l..tI
:Lattice
I AILattice®
Semiconductor
C o r p Corporation
oration
GD
GAL20118A
Specifications GAL20V8A
Industrial
Industrial
1AC SWITCHING CHARACTERISTICS
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
Operating Conditions
-15
·15 -20
·20 -25
-25
PA R A M ETER
TEST DESCRIPTION
OESCRIPnON UNITS
UNITS
CONDI.
CONO'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O to
to Combinational Output 33 15
15 33 20
20 33 25
25 ns
ns

tco
teo 11 Clock to Output Delay 22 10
10 22 11
11 22 12
12 ns
ns

tcf2 Clock to Feedback Delay -— 88 -— 99 -— 10


10 ns
ns

tsu Time, Input or Feedback before Clocki


Setup lime, 12
12 - — 13
13 -
— 15
15 - — ns
ns
th Hold Time,
lime, Input or Feedback after Clocki
Input or Clocki 00 -— 00 -— 00 -— ns
ns
11 Maximum Clock Frequency withwith 45.5
45.5 -— 41.6
41.6 -— 37
37 -— MHz