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GAL PRODUCT INDEX

Commercial Grade Devices


DEVICE PINS tpD (ns) Icc (rnA) DESCRIPTION PAGE
GAL16V8NB 20 7.5,10,15,25 55,90,115 FCMOS Generic PLD 2-1
GAL20V8NB 24 7.5,10,15,25 55,90,115 E2CMOS Generic PLD 2-25
GAL18V10 20 15,20 115 E2CMOS Universal PLD 2-47
GAL22V10/B 24 10,15,25 130 E2CMOS Universal PLD 2-61
GAL26CV12 28 15, 20 130 E2CMOS Universal PLD 2-81
GAL20RA10 24 12,15,20,30 100 E2CMOS Asynchronous PLD 2-95
GAL6001 24 30,35 150 E2CMOS FPLA 2-109
ispGAL 16Z8 24 20, 25 90 E2CMOS In-System-Programmable PLD 2-121

Industrial Grade Devices


DEVICE PINS tpD (ns) Icc (rnA) DESCRIPTION PAGE
GAL16V8NB 20 10,15,20,25 65, 130 E2CMOS Generic PLD 2-1
GAL20V8A 24 15,20,25 65, 130 FCMOS Generic PLD 2-25
GAL18V10 20 20 125 E2CMOS Universal PLD 2-47
GAL22V10/B 24 15,20,25 150 E2CMOS Universal PLD 2-61
GAL26CV12 28 20 150 E2CMOS Universal PLD 2-81
GAL20RA10 24 20 120 E2CMOS Asynchronous PLD 2-95

MIL-STD-883C Grade Devices


DEVICE PINS tpD (ns) Icc (rnA) DESCRIPTION PAGE
GAL16V8NB 20 10,15,20,25,30 65,130 E2CMOS Generic PLD 3-5
GAL20V8A 24 15,20,25,30 65,130 E2CMOS Generic PLD 3-13
GAL22V10/B 24 15,20,25,30 150 E2CMOS Universal PLD 3-19
GAL20RA10 24 20, 25 120 E2CMOS Asynchronous PLD 3-27
Thank you for your interest in our high performance GAL product line.

As the inventor and world leader of the GAL· device, we at Lattice are
dedicated to providing you with the fastest, highest quality and most
flexible solution to your logic needs.

In our new 1991 Data Book, you will see that we have substantially
expanded our product line and continue to offer the world's highest
performance CMOS programmable logic devices.

We look forward to satisfying all of your programmable logic requirements.

.Steven Laub
Vice President and General Manager
ii
GAL Data Book
1991

f/J
.l..I
Lattice®
Semiconductor
Corporation
iii
it /;Lattire°
.l.J SemiconducUJr
Corporation
Copyright © 1991 Lattice Semiconductor Corporation

Generic Array Logic, Latch-Lock, and RFT are trademarks of Lattice Semiconductor Corporation.
ispGAL, GAL, PCMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corporation.

PAL is a registered trademark of Advanced Micro Devices, Inc.

Products discussed in this literature are covered by U.S. Patents No.4, 761,768, 4,766,569, 4,833,646, 4,852,044,
4,855,954, 4,879,688, 4,887,239 and 4,896,296 issued to Lattice Semiconductor Corporation, and by U.S. and
foreign patents pending.

LATTICE SEMICONDUCTOR CORP.


5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
TELEX 277338 LSC UR

iv
Section 1: Introduction to Generic Array Logic
Introduction to Generic Array Logic 1-1
II
Section 2: GAL Datasheets 2
Datasheet Levels 2-ii
GAL16V8A1B 2-1
GAL20V8A1B 2-25
GAL18V10 2-47
GAL22V10/B 2-61
GAL26CV12 2-81
GAL20RA10 2-95
GAL6001 2-109
ispGAL16Z8 2-121

Section 3: GAL Military Products


Military Program Overview 3-1
3
MIL-STD-883C Flow 3-2
Military Ordering Information 3-3
GAL 16V8A1B Military Datasheet 3-5
GAL20V8A Military Datasheet 3-13
GAL22V10/B Military Datasheet 3-19
GAL20RA 10 Military Datasheet 3-27

Section 4: Quality and Reliability


Quality Assurance Program 4-1 4
Qualification Program 4-3
E2CMOS Testability Improves Quality 4-5

Section 5: Technical Notes


GAL Metastability Report 5-1 5
Latch-up Protection 5-17

Section 6: Article Reprints


Avoid the Pitfalls of High-Speed Logic Design 6-1 6
Extending the 22V1 0 EPLD 6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6-9
Multiple Factors Define True Cost of PLDs 6-13

Section 7: General Information


Development Tools 7-1 7
Copying PAL, EPLD & PEEL Patterns into GAL Devices 7-3
GAL Product Line Cross Reference 7-5
Package Thermal Resistance 7-8
Package Diagrams 7-9
Tape-and-Reel Specifications 7-16
Sales Offices 7-17

1-i
1-ii
Introduction to .J
Generic Array Logic I

INTRODUCTION THE GAL CONCEPT I

Lattice Semiconductor, located in Hillsboro, Oregon, was EZCMOS - THE IDEAL TECHNOLOGY
I
founded in 1983 to design, develop and manufacture Of the three major technologies available for producing
high-performancesemiconductorcomponents.ltisafirm PLDs, the technology of choice is clearly E2CMOS.
belief at Lattice that technological evolution can be E2CMOS offers testability, quality, high speed, low power,
accelerated through the continued development of higher- and instant erasure.
speed and architecturally superior products.
TESTABILITY
GAL devices are ideal for four important reasons: The biggest advantage of PCMOS over competing
technologies is its inherent testability. Capitalizing on
1. GAL devices have inherently superior quality and veryfast (1 OOms) erase times, Lattice repeatedly patterns
reliability. and erases all devices during manufacture. Lattice tests
each GAL device for AC, DC, and functional characteristics.
2. GAL devices can directly replace PAL devices in nearly The result is guaranteed 100% programming and
every application. functional yields.

3. GAL devices have the low power consumption of LOW POWER


CMOS, one-fourth to one-haH that of bipolar devices. Another advantage of E2CMOS technology is the low
power consumption of CMOS. CMOS provides users the
4. GAL devices utilize Output Logic Macrocells (OLMCs), immediate benefit of decreased system power
which allow the user to configure outputs as needed. requirements allowing for higher reliability and cooler
running systems. Low power CMOS technology also
permits circuit designs of much higher functional density,
because of lower junction temperatures and power
requirements on Chip. The user benefits because higher
functional density means further reduction of chip count
and smaller boards in the system.

HIGH SPEED
Also advantageous is the very high speed attainable with
Lattice's state-of-the-art PCMOS process. Lattice GAL
devices are as fast or faster than bipolar and UVCMOS
PLDs.

PROTOTYPING AND ERROR RECOVERY


Finally, E2CMOS gives the user instant erasabilitywith no
additional handling or special packages necessary. This
provides ideal products for prototyping because designs
can be revised instantly, with no waste and no waiting. On
the manufacturing floor instant erasability can also be a
big advantage for dealing with pattern changes or error
recovery. If a GAL device is accidentally programmed to
the wrong pattern, simply reprogram the device. No other
technology offers this advantage.

1-1
Introduction to
Generic Array Logic
A LOOK AT OTHER TECHNOLOGIES THE GAL ADVANTAGE
Here, the technologies that compete with E2CMOS - GAL devices are ideal programmable logic devices
bipolar and UVCMOS -are compared with the E2CMOS because, as the name implies, they are architecturally
approach. generic. Lattice has employed the macrocell approach,
which allows users to define the architecture and
BIPOLAR functionality of each output. The key benefit to the user is
Bipolar fuse-link technology was the first available for the freedom from being restricted to any specific
programmable logic devices. Although it offers high architecture. This is advantageous at both the
speed, it is saddled with high power dissipation. High manufacturing level and the design level.
power dissipation increases your system power supply
and cooling requirements, and limits the functional density DESIGN ADVANTAGES
of bipolar devices. Early programmable logic devices gave the user the
ability to specify a function, but limited them to specific,
Another weakness of this technology is the one-time- predetermined output architectures. Comparing the GAL
programmable fuses. Complete testing of bipolar PLDs is device with fixed-architecture programmable logic devices
impossible because the fuse array cannot be tested is much like comparing these same fixed PLDs with SSI/
before programming. Bipolar PLD manufacturers must MSI devices. The GAL family is the next generation in
rely on complex schemes using test rows and columns to simplified system design. The user does not have to
simulate and correlate their device's performance. The search for the architecture that best suits a particular
result is programming failures at the customer location. design. Instead, the GAL family's generic architecture lets
Any misprogrammed devices due to mistakes during him configure as he goes.
prototyping or errors on the production floor must be
discarded because bipolar PLDscannot be reprogrammed. MANUFACTURING ADVANTAGES
The one-device-does-all approach greatly simplifies
UVCMOS manufacturing flow . Inventorying one generic-architecture
UVCMOSaddresses many weaknesses of the bipolar GAL device type versus having to monitor and maintain
approach but introduces many shortcomings of its own. many different device types, saves money and minimizes
This technology requires less power and is paperwork: Manufacturing flow is much smoother because
reprogrammable, but reprogrammability comes at the the handling process is greatly simplified. A generiC
expense of slower speeds. architecture GAL device also reduces the risk of running
out of inventory and halting production, which can be very
Testability is increased over bipolar since the "fuse" array expensive. Reduced chance of obsolete inventory and
can be programmed and tested by the manufacturer. The easier QA tracking ate additional benefits of the generic
problem here ill the long (20 minutes) erase times coupled architecture.
with the requirement of exposing the devices to ultraviolet THE IDEAL PACKAGE
light for erasing. This becomes a very expensive step in
themanLJfacturing process. Because ofthe time involved, Programmable logic devices are ideal fordesigningtoday's
patterning and erasing is performed only once - a systems. Lattice Semiconductor believes that the ideal
compromised rather than complete functional test. design approach should be supported with the ideal
products. It was on this premise that GAL devices were
Additionally, the devices must be housed in expensive invented. The ideal device-with a generic architecture-
windowed packages to allow users to erase them. Again, fabricated with the ideal process technology, E2CMOS.
programming these devices is time-consuming and
cumbersome due to the 20-minute UV exposure required
to erase them. As acost-cutting measure, UVCMOS PLD
manufacturers offertheirdevices in windowless packages.
Although windowless packages are less expensive, they
cannot be completely tested or reprogrammed. These
factors significantly detract from the desirability of this
technology.

1-2
Section 1: Introduction to Generic Array Logic 1
Introduction to Generic Array Logic 1-1

Section 2: GAL Datasheets


Datasheet Levels
GAL16VSNB
GAL20VSNB
2-ii
2-1
2-25
at
GAL1SV10 2-47
GAL22V10/B 2-61
GAL26CV12 2-S1
GAL20RA10 2-95
GAL6001 2-109
ispGAL16ZS 2-121

Section 3: GAL Military Products


3
Military Program Overview 3-1
MIL-STD-S83C Flow 3-2
Military Ordering Information 3-3
GAL 16VSNB Military Datasheet 3-5
GAL20VSA Military Datasheet 3-13
GAL22V10/B Military Datasheet 3-19
GAL20RA 10 Military Datasheet 3-27

Section 4: Quality and Reliability


Quality Assurance Program 4-1
4
Qualification Program 4-3
FCMOS Testability Improves Quality 4-5

Section 5: Technical Notes


GAL Metastability Report 5-1 5
Latch-up Protection 5-17

Section 6: Article Reprints


Avoid the Pitfalls of High-Speed Logic Design 6-1 8
Extending the 22V1 0 EPLD 6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6-9
Multiple Factors Define True Cost of PLDs 6-13

Section 7: General Information


Development Tools 7-1 7
Copying PAL, EPLD & PEEL Patterns into GAL Devices 7-3
GAL Product Line Cross Reference 7-5.
Package Thermal Resistance 7-S
Package Diagrams 7-9
Tape-and-Reel Specifications 7-16
Sales Offices 7-17

2-i
Definition of Datasheet Levels

DEFINITION OF DATASHEET LEVELS

Datasheet Identification Product Status DeflnHlon

'PA""ii'F't Sampling or
Pre-Production
This datasheet contains preliminary data and supplementary
data will be published at a later date. Lattice reserves the
right to make changes at any time without notice.

No Identification Full Production This datasheet contains final specifications. Lattice reserves the
right to make changes at any time without notice.

2-ii
[JJtatUce® SemioonducWr
Corporation
GAL16V8B
GAL16V8A
High Performance E2CMOS PLD
FEATURES FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE ElCMOS· TECHNOLOGY


- 7.5 ns Maximum Propagation Delay Vee.
- Fmax =100 MHz J
20
- 5 ns Maximum from Clock Input to Data Output
- TTL Compatible 24 mA Outputs 19
- UHraMOS· Advanced CMOS Technology
2
• 500/0 to 750/0 REDUCTION IN POWER FROM BIPOLAR
- 75mA TYP Icc on Low Power Device 18
- 45mA TYP Icc on Quarter Power Device 3
• ACTIVE PULL-UPS ON ALL PINS (GAL16V8B)
17
• E2 CELL TECHNOLOGY
- Reconflgurable logic 4
- Reprogrammable Cells
-1000/0 Tested/Guaranteed 1000/0 Yields 16
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
15
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum FlexlbllHy for Complex Logic Designs 6
- Programmable Output Polarity
- Also Emulates 2o-pln PAL· Devices with Full Func- 14
tlon/Fuse Map/Parametric CompatlbllHy 7
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
13
-1000/0 Functional Testability
8
• APPLICATIONS INCLUDE:
- DMA Control 12
- State Machine Control
- High Speed Graphics Processing 9
11
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION PIN CONFIGURATION

The GAL16V8B, at 7.5 ns maximum propagation delay time,


combines a high performance CMOS process with Electrically DIP
Erasable (E2) floating gate technology to provide the highest speed
performance available in the PlD market. High speed erase times PLCC
«100ms) allow the devices to be reprogrammed quickly and IICLK Vee
efficiently. IIOJQ
l'CUC Veo roIO
The generic architecture provides maximum design flexibility by 20 11010
allowing the Output logic Macrocell (OlMC) to be configured by vOla
the user. An important subset of the many architecture con·
figurations possible with the GAL 16V8A1B are the PAL archi- vOla
11010
tectures listed in the table of the macrocell description section. GAL16VSAlB vOla
GAL16V8AIB devices are capable of emulating any of these PAL Top View 11010
architectures with full function/fuse maplparametric compatibility. VOla
IIOJQ

Unique test circuitry and reprogrammable cells allow complete VO/Q


11010
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 1000/0 field programmability and I CIHO IIOi VOla vOla 11010
functionality of all GAL· products. LATTICE also guarantees 100 aND
erase/rewrite cycles and data retention in excess of 20 years.
Copyright C1991 Lattice Semiconductor Corp. GAL. E'CMOS and UlltaMOS are regls..rod trademarks 01 lattice Semiconductor Corp. GonorIc "ray Logic Is a trademarl< of Lattlca SeRiconduc·
tor Corp. PAL Is a registered tradomar1< of Advanced Micro Dovlcoo. Inc. The specifications and Information heroin are subject to change without noflca.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A. April 1991.Rev.A
Tel. (503) 681-0118: 1-800-FASTGAL: FAX (503)681-3037 2-1
flJ.Semiconductor Specifications GAL 16V8B
Corporation GAL 16V8A·
GAL 16V8A'B ORDERING INFORMATION
Commercial Grade Specifications
Tpd(n8) T8U (n8) Teo (ns) Icc(mA) Ordering # Package
7.5 7 5 115 GAL16V8B-7LP 20-Pin Plastic 01 P
115 GAL16V8B-7LJ 20-Lead PLCC
10 10 7 115 GAL16V8B-l0LP 20-Pin Plastic DIP
115 GAL16V8B-l0LJ 20-Lead PLCC
115 GAL 16V8A-l OLP 20-Pin Plastic DIP
115 GAL16V8A-l0LJ 20-Lead PLCC
15 12 10 55 GALI6V8A-I50P 20-Pin Plastic DIP
55 GAL16V8A-I50J 20-Lead PLCC
115 GAL 16V8A-15LP 20-Pin Plastic DIP
115 GAL16V8A-15LJ 20-Lead PLCC
25 15 12 55 GAL 16V8A-250P 20-Pin Plastic DIP
55 GAL 16V8A-25QJ 20-Lead PLCC
90 GAL 16V8A-25LP 20-Pin Plastic DIP
90 GAL 16V8A-25LJ 20-Lead PLCC

Industrial Grade Specifications


Tpd (n8) Tsu(ns) Teo (ns) Icc (mA) Ordering # Package
10 10 7 130 GALI6V8B-l0LPI 2O-Pin Plastic DIP
130 GAL 16V8B-l0LJI 20-Lead PLCC
15 12 10 130 GAL 16V8B-15LPI 20-Pin Plastic DIP
130 GAL16V8B-15LJI 20-Lead PLCC
130 GAL 16V8A-15LPI 20-Pin Plastic DIP
130 GALI6V8A-15LJI 20-Lead PLCC
20 13 11 65 GAL 16V8A-200PI 20-Pin Plastic DIP
65 GAL 16V8A-2OQJI 20-Lead PLCC
25 15 12 65 GAL 16V8A-250PI 20-Pin Plastic DIP
65 GAL 16V8A-25QJ1 20-Lead PLCC
130 GAL 16V8A-25LPI 20-Pin Plastic DIP
130 GAL 16V8A-25LJI 20-Lead PLCC

PART NUMBER DESCRIPTION

GAL16V8A
GAL16V8B
Speed (ns) _ _ _ _ _ _....J Blank =Commercial
I Industrial
L _ Low Power Power _ _ _ _ _ _ _ _....J ' - - - - - - Package P = Plastic DIP
Q -1/4 Power J. PLCC
2-2 4/91.Rev.A
Specifications GAL 16VBB
GAL 16VBA
OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic


macrocell. It should be noted that actual implementation is ac- PAL Architectures GALl6V8AlB
complished by development softwareJhardware and is completely Emulated by GAL16V8A1B Global ollie Mode
transparent to the user.
16R8 Registered
There are three global OlMC configuration modes possible: 16R6 Registered
simple, complex, and registered. Details of each of these 16R4 Raglstered
modes is illustrated in the following pages. Two global bits, SYN 16RP8 Raglstered
16RPB Raglstered
and ACO, control the mode configuration for all macrocells. The 16RP4 Raglstered
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells 16La Complex
controls the input/output configuration. These two global and 16 18H8 Complex
individual architecture bits define all possible configurations in a 16P8 Complex
GAL 16V8A1B. The information given on these architecture bits lOLa Simple
is only to give a better understanding of the device. Compiler 12L6 Simple
software will transparently set these architecture bits from the pin 14L4 Simple
definitions, so the user should not need to directly manipulate 16L2 Simple
these architecture bits. 10H8 Simple
12H6 Simple
14H4 Simple
The following is a list of the PAL architectures that the GAL16V8A 16H2 Simple
and GAL 16V8B can emulate. It also shows the OlMC mode 10P8 Simple
under which the GAL16V8A1B emulates the PAL architecture. 12P6 Simple
14P4 Simple
16P2 Simple

COMPILER SUPPORT FOR OLMC


Software compilers support the three different global OlMC In registered mode pin 1 and pin 11 are permanently configured
modes as different device types. These device types are listed as clock and output enable, respectively. These pins cannot be
in the table below. Most compilers have the ability to automati- configured as dedicated inputs in the registered mode.
cally select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device In complex mode pin 1 and pin 11 become dedicated inputs and
forces the software to choose the registered mode. All combi- use the feedback paths of pin 19 and pin 12 respectively. Because
natorial outputs with OE controlled by the product term will force of this feedback path usage, pin 19 and pin 12 do not have the
the software to choose the complex mode. The software will feedback option in this mode.
choose the simple mode only when all outputs are dedicated
combinatorial without OE control. The different device types listed In simple mode all feedback paths of the output pins are routed
in the table can be used to override the automatic device selection via the adjacent pins. In doing so, the two inner most pins ( pins
by the software. For further details, refer to the compiler software 15 and 16) will not have the feedback option as these pins are
manuals. always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user


must pay special attention to the following restrictions in each
mode.

Registered Complex Simple Auto Mode Select


ABEL P16V8R P16V8C P16V8AS P16V8
CUPL G16V8MS G16V8MA G16V8AS G16V8
LOG/IC GAl16V8 R GAl16V8 C7 GAl16V8 C8 GAL16V8
OrCAD-PLD "Registered"' "Complex"' "Simple"' GAL16V8A
PLDeslgner P16V8R2 P16V8C2 P16V8C2 P16V8A
TANGO-PLD G16V8R G16V8C G16V8AS3 G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.

2-3 4/91.Rev.A
Specifications GAL 16VBB
GAL 16VBA
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated mode. Dedicated input or output functions can be implemented
registered outputs or as I/O functions. as subsets of the VO function.

Archkecture configurations available in this mode are similar to Registered outputs have eight product terms per output. VO's
the common 16R8 and 16RP4 devices with various permutations have seven product terms per output.
of polarity, VO and register placement.
The JEDEC fuse numbers, including the User Electronic Signature
All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are
control pins. Any macrocell can be configured as registered or shown on the logic diagram on the followihg page.
VO. Up to eight registers or up to eight VO's are possible in this

ClK
---____ .-------.. . . . . . . . -------.. . . . . . -- -----! Registered Configuration for Registered Mode

-SYN=O.
-ACO.. 1.
- XOR",O defines Active Low Output.
- XOR..1 defines Active High Output.
- AC1 ",0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.

·· .. - Pin 1 & Pin 11 are permanently configured as CLK &


OE.
.. --------.---- . -. -----------.
OE

..... -- .. - .. _- ...... -- ........ -- ...... - ..... .


Combinatorial Configuration for Registered Mode

-SYN",O.
-ACO=1.
- XOR..Odefines Active Low Output.
- XOR..1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

2-4 4191.Rev.A
Specifications GAL 16V8S
1.,.; Semiconductor
GAL 16V8A
Corporation

REGISTERED MODE LOGIC DIAGRAM

.....
DIP & PLCC Package Pinouts II
I

0 4 8 12
"
20 24 2tI pm
J !

0000

§: OLMC 19 1 "...,.,
19
022'
:§: XOR·2048
AC1·2120

0256
1
-
OLMC 18 18

XOR·2049
AC1·2121

0512
:g: OLMC 17 1 17
073< :§: XOR·1050
AC1·2122

1
0768

OLMC 16 n 16
0992
XOR·1051
D AC1·2123

1024

§: OLMC 15 1 ....... 15
.-....
1248
- XOR·1052
AC1·2124

1280

s: OLMC 14
1· ....... 14
1504
::c
.If
XOR·1053
D AC1·2125

,,3<
,..,. OLMC 13 1 ....... 13
1760 §: XOR·1054
AC1·2126

1792

OLMC 12 1 12
2016
I!S.:::;
-
.-.... XOR·1055
AC1·2127
A OE,....,
11
fI4.USEII ElECTRONIC SIGNAlURE FUSES
12068, 2057, ..•. .... 211 .. 21181 SYN·2192
Byte71Byte8 .... ACO·2193
M L
S S
B B

4/91.Rev.A
2-5
[JJ
.
.
l.J
Lattice-
Semiconducwr
Specifications GAL 16V8B
Corporation . GAL 16V8A
COMPLEX MODE
In the Complex mode, macrocells are configured as output only pability. Designs requiring eight I/O's can be implemented in the
or 110 functions. . Registered mode.

Architecture configurations available in this mode are similar to All macrocells have seven product terms per output. One product
the common 16L8 and 16P8 devices with programmable polarity term is used for programmable output enable control. Pins 1 and
in each macrocell. 11 are always available as data inputs into the AND array.

Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses
outputs can be implemented as subsets of the I/O function. The are shown on the iogic diagram on the following page.
two outer most macrocells (pins 12 & 19) do not have input ca-

·......................................................
·
,
.. Combinatorial 1/0 Configuration for Complex Mode

- SYN.1.
-ACO-1.
- XOR.O defines Active Low Output.
- XOR.1 defines Active High Output.
-AC1-1.
- Pin 13 through Pin 18 are configured to this function.
,
..................................................... .

....................................................,
: : Combinatorial Output Configuration for Complex Mode

Pr7R ·
- SYN.1.
-ACO-1.
- XOR.O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1-1.
- Pin 12 and Pin 19 are configured to this function.
...............................................................:

Note: The development software configures all of the architecture control bitt; and checks for proper pin usage automatically.

2·6 4/91.Rev.A
[[J
.J.,,;
Latuoo
SemJoonducUJr
Corporation
e
Specifications GAL 16VBB
GAL 16VBA
COMPLEX MODE LQGIC DIAGRAM
DIP & PLCC Package Pinouts

..., ...
v

.... • • a 12 11 20 24 2B
mJ
.224
:i=t::=
=1::$
:B=
OLMC 19
XOR·2048
n ':::1

D- AC1·2120

.251
<= OLMC 18 n ....
D--
D<8O
-. XOR·2049
AC1·2121

0512
:a= OLMC 17 n 1

.-...
...,
.731 XOR·2050
AC1-2122 U
.788

- Il.
:R:::::=:
OLMC 16 -01

.-...
...,
XOR·2051
ACl·2123 U
Il..... J
1024

<= OLMC15
1241 -0--;.... XOR·2052
D- AC1·2124

Il
l!SO

.-...
'--'
150. -0--;....
OLMC 14
XOR·2053
AC1:2.125
v
J-G 14

1531
n ,....,.

D-
176.
§=
-:
OLMC 13
XOR·2054
AC1·2126
J- 13

17112
B==
OLMC 12 n .... -a 12
- 2011 XOR·2055
' --'

II4-USER ELECTRONIC SIGNATURE RJ8fiS


rr
21"
l
AC1·2127
a 11

12068,2067..... .... 2118.2"'1 SVN·2192


By\! 7 IBy\! • .... .... By\! 11 By\! 0 . ACO-2193
II L
S S
B B

2-7 4191.Rev.A
[JJ
'L tattiOO-
.
SemkxJnductor
Corporation
Specifications GAL 16V8B
GAL 16V8A
SIMPLE MODE
In the Simple mode, macrooells are configured as dedicated inputs Pins 1 and 11 are always available as data inputs into the AND
or as dedicated, always active, combinatorial outputs. array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.
Architecture configurations available in this mode are similar to
the common 10la and 12P6 deviCes with many permutations of The JEDEC fuse numbers including the UES fuses and PTD fuses
generic output polarity or input choices. are shown on the logic diagram.

All outputs in the simple mode have a maximum of eight product


terms that can control the logic. In addition, each output has
programmable polarity.

Combinatorial Output with Feedback Configuration


for Simple Mode

---+--\ -SYN=1.
-ACO.O.
- XOR.O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1 =0 defines this configuration.
- All OlMC except pins 15 & 16 can be configured to
this function.
t. __ ... __ ....... _............................... j
;._- ..........................................
Combinatorial Output Configuration for Simple Mode
Voo
- SYN=1.
-ACO.O.
- XOR=O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1-0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
... __ ................... _-
'............ _.............. _ function.

Dedicated Input Configuration for Simple Mode

-SYN.1.
-ACO.O.
- XOR=O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1 .. 1 defines this configuration.
- All OlMC except pins 15 & 16 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

2-8 4/91.Rev.A
Specifications GAL 16V8B
1..1 Corporation
Semronductor
GAL 16V8A
i
I

SIMPLE MODE LOGIC DIAGRAM

L..I v

...
, •
DIP & PLCC Package Pinouts

I
"
11 II .. " iI:a::::::: OLMC 19
IJ
- I

,.....,
... XOR·2Q.48
AC1·2120
v -01

""
l
-
OLMC18
H= -01
1<= XOR·2Q.49
......---- AC1·2121
-
'512
:!3= OLMC 17
XOR·2050
J
:§=:
'''' AC1·2122

'''' OLMC 16
XOR·2051
IJ
.---. "'" AC1·2123

,.,.
OLMC 15
XOR·2052
11 v - 0 15

D '''' AC1·2124

'2!D

,SOl
1<=
=c:::
OLMC 14
XOR·2053
I.l v - 0 14
AC1·2125
D

's:!6

IJ..
-=-
:§::::::
OLMC 13
XOR·2054
IJ v - 0 13
-: AC1·2126
.r--..

'102

=8=
OLMC 12
XOR·2055
I.l -........
v 12
,." AC1·2127
- I'" 11

84-USER El£CTRONIC SIONATURE FUIES


12056, 2057, •.••
EIy!e 718y1e 8 .•.
••.• 2118, 211P I
••• EIy!e 11 EIy!e 0 .
SYN·2192
ACO·2193
hi L
S S
B B

2-9 4/91.Rev.A
[JJ
.l..J
'LatUoo@
Semiconductor
Corporation
Specifications GAL 16V8B
Commercial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -0.5 to +7V Commercial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TAl ................................ 0 to 75°C
Off-state output voltage applied .......... -2.5 to Vee +1 .OV Supply voltage (Veel
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.2SV
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.' MAX. UNITS

VIL Input Low Voltage Vss-0.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
IlL' Input or 1/0 Low Leakage Current OV S VIN S VIL (MAX.) - - -100
IIH Input or 1/0 High Leakage Current 3.SV S VIN S Vcc - - 10 IlA
VOL Output Low IOL .. MAX. Vin .. VIL or VIH - - 0.5 V
VOH Output High Voltage IOH .. MAX. Yin = VIL or VIH 2.4 - - V
10L Low Level Output Current - - 24 mA
10H High Level Output Current - - -3.2 mA
los· Output Short Circuit Current Vcc=5V YOUTz O.SV TA= 25°C -30 - -150 mA
Icc Operating Power Supply Current VIL= 0.5V ViH =3.0V ftoggle .. 2SMHz - 75 115 mA
Outputs Open (no load)
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout .. O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. 5V and TA= 25°C

CAPACITANCE (TA = 25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS
C, Input Capacitance 8 pF Vcc - 5.0V. V, .. 2.0V

C'iO 1/0 Capacitance 8 pF Vcc =5.0V. VIIO -2.0V


'Guaranteed but not 100% tested.

2-10 4191.Rev.A
[JJ
J.J
LatUCC SemiconduCUJr
CorporaUon
Gl
Specifications GAL 16V8S
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

TEST -7 -10
DESCRIPTION UNITS
COND'. MIN. MAX. MIN. MAX.
tpd 1 Input or I/O to Combinational Output I 8 outputs switching 3 7.5 3 10 ns
J 1 output switching - 7 - - ns

tco 1 Clock to Output Delay 2 5 2 7 ns

tcf' - Clock to Feedback Delay - 3 - 6 ns

tsu - Setup Time, Input or Feedback before Clock" 7 - 10 - ns

th - Hold Time, Input or Feedback after Clock" 0 - 0 - ns


1 Maximum Clock Frequency with 83.3 - 58.8 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with 100 - 62.5 - MHz


Internal Feedback, 1/(tsu + tcf)

1 Maximum Clock Frequency with 100 - 62.5 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 5 - 8 - ns

twt' - Clock Pulse Duration, Low 5 - 8 - ns


ten 2 Input or I/O to Output 3 9 3 10 ns
2 OE.!. to Output 2 6 2 10 ns

tdis 3 Input or I/O to Output 2 9 2 10 ns


3 OE" to Output 1.5 6 1.5 10 ns
i) Refer to SWitching Test Conditions section.
!) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
I) Refer to fmax Descriptions section.
I) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS


Input Pulse Levels GNDto 3.0V +5V
Input Rise and Fall Times 3ns 10%-90%
Input Timing Reference Levels 1.SV
Output Timing Reference Levels 1.SV
Output Load See Figure
I-state levels are measured O.SV from steady-state active FROM OUTPUT (0/0) - -.....- -....-TESTPOINT
eve I. UNDER TEST
)utput Load Conditions (see figure)
R2
Test Condition Rl Rz CL
1 200n 390n SOoF
2 Active High 3900 SOpF
Active Low 200n 390n SOpF
3 Active High 3900 SpF C LINCLUDES JIG AND PROBE TOTAL CAPACITANCE
Active Low 200n 390n SpF

2-11 4191.Rev.A
'L Semiconductor
C()IJXX'aUOIl
Specifications GAL 16V8A
Commercial
ABSOLUTE MAXIMUM RATINGS(l) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -o.5to +7V Commercial Devices:
Input voltage applied ........................... -2.5to Vee +1.0V Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Off-state output voltage applied .......... -2.5 to Vee +1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ...•.................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP} MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - VcC+1 V

IlL Input or 1/0 Low Leakage Current OV S VIN S VIL (MAX.) - - -10 I1A
IIH Input or 110 High Leakage Current VIH S VIN S Vee - - 10 I1A
VOL Output Low Voltage 10L=MAX. Yin = VIL or VIH - - 0.5 V

VOH Output High Voltage IOH = MAX. Yin = VILor VIH 2.4 - - V

10l Low level Output Current - - 24 mA

10H High Level Output Current - - -3.2 mA

los' Output Short Circuit Current Vcc=5V VOUT = 0.5V TA=25·C -30 - -150 mA
Operating Power VIL= 0.5V VIH=3.0V ftoggle = 15M Hz L -25 - 75 90 mA

Icc Supply Current Outputs Open (no load) floggle = 25MHz L-10/-15 - 75 115 mA
ftoggle = 15MHz I Q -15/-25 - 45 55 mA

1} One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25 ·C

CAPACITANCE (TA =25°C, f =1_0 MHz)


SYMBOL PARAMETER MAXIMUM' UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee =5.0V. V, = 2.0V

Coo ilO Capacitance 10 pF Vee = 5.0V. VIJO = 2.0V


'Guaranteed but not 100% tested.

2-12 4!91.Rev)
I

Specifications GAL 16VBA I:


Commercial
AC SWITCHING CHARACTERISTICS
..•
OVer Recommended Operating Conditions
-10 -15 -25
TEST DESCRIPTION
PARAMETER UNITS
COND'. MlfIC )ftAx. MIN. MAX. MIN. MAX.
tpd 1 Input or I/O to Combinational Output 3 • 10 3 15 3 25 ns

teo 1 Clock to Output Delay 2 ,; 7 2 10 2 12 ns

tcf2 - Clock to Feedback Delay -i 7 - 8 - 10 ns

tsu - Setup Time, Input or Feedback before Clocki 10 - 12 - 15 - ns

th - Hold Time, Input or Feedback after Clocki


o ==- 0 - 0 - ns
1 Maximum Clock Frequency with
External Feedback, 1f(tsu + teo) all . 45.5 - 37 - MHz

fmax 3 1 Maximum Clock Frequency with


Internal Feedback, 1f(tsu + tcf)
58.84
i
S- 50 - 40 - MHz

1 Maximum Clock Frequency with 62.5 - 41.6 - MHz


No Feedback )
twh4 - Clock Pulse Duration, High 8 t ;- 8 - 12 - ns

tw" - Clock Pulse Duration, Low 8 'I 8 - 12 - ns

ten 2 Input or I/O to Output Enabled -SCI '10 - 15 - 25 ns


2 OE.!. to Output Enabled )10 - 15 - 20 ns

tdis 3 Input or I/O to Output Disabled - 15 - 25 ns


3 OEi to Output Disabled -: )10 - 15 - 20 ns

1) Aefer to Switching Test Conditions section.


2) Calculated from 'max with internal feedback. Aefer to 'max Descriptions section.
3) Aefer to 'max Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS

i Input Pulse Levels GNDt03.0V +5V


: Input Aise and Fall Times 3ns 10"04 - 90%
, Input Timing Aeference Levels 1.5V
Output Timing Aeference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active FROM OUTPUT (0/0) - - + - - ' - - T E S T POINT
level. UNDER TEST
OUtput Load Conditions (see figure) CL
R2
Test Condition R1 R2 CL
1 2000 3900 50pF
2 Active High co 3900 50pF
Active Low 2000 3900 50pF
3 Active High co 3900 5pF C LINCLUDES JIG AND PROBE TOTAL CAPACITANCE
Active Low 2000 3900 5pF

2-13 4/91.Aev.A
[JJ
.l...I
'LattiOO*
SemJconductor·
Corporation
Specifications GAL 16VBB
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -0.5 to +7V Industrial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TAl ............................ -40 to 85°C
Off-state output voltage applied .......... -2.5 to Vee + 1.0V Supply voltage (Veel
Storage Temperature .........•....................... -65 to 150°C with Respect to Ground ...................... +4.50 to +5.50V
Ambient Temperature with
Power Applied .......................................• -55to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
IlL' Input or 110 Low Leakage Current OV S VIN S VIL (MAX.) - - -100
IIH Input or 1/0 High Leakage Current 3.5V S VIN S Vee - - 10
VOL Output Low Voltage 10L .. MAX. Vin .. VIL or VIH - - 0.5 V
VOH Output High Voltage 10H = MAX. Vin .. VIL or VIH 2.4 - - V
10L Low Level Output Current - - 24 mA
10H High Level Output Current - - -3.2 mA
los' Output Short Circuit Current Vce=5V VOUT= 0.5V TA=25°C -30 - -150 mA
Icc Operating Power Supply Current VIL= 0.5V VIH = 3.0V ftoggle = 25MHz - 75 130 mA
Outputs Open (no load)
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc .. 5V and TA = 25 °C

CAPACITANCE (TA = 25'C, f = 1.0 MHz)


SYMBOL PARAMETER MAXIMUM· UNITS TEST CONDITIONS
C, Input Capacitance 8 pF Vee = 5.0V, V, = 2.0V

C'iO 1/0 Capacitance 8 pF Vcc =5.0V, VIJO=2.0V


·Guaranteed but not 100% tested.

2-14 4191.Rev.A
/1.l..JlLattice"
Semiconductor
Corporation
Specifications GAL 16V8B
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-10 -15
TEST DESCRIPTION
PARAMETER UNITS
COND'. MIN. MAX. MIN. MAX.
tpd 1 Input or I/O to Combinational Output 3 10 3 15 ns

tco 1 Clock to Output Delay 2 7 2 10 ns

tcf2 - Clock to Feedback Delay - 6 - 8 ns

tsu - Setup Time, Input or Feedback belore Clocki 10 - 12 - ns


I
I th - Hold Time, Input or Feedback alter Clocki 0 - 0 - ns
1 Maximum Clock Frequency with 58.8 - 45.5 - MHz
External Feedback, 1/(tsu + tco)
,
I
fmax' 1 Maximum Clock Frequency with 62.5 - 50 - MHz
Internal Feedback, 1/(tsu + tcl)

1 Maximum Clock Frequency with 62.5 - 62.5 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 8 - 8 - ns


twt' - Clock Pulse Duration, Low 8 - 8 - ns

ten 2 Input or I/O to Output 3 10 - 15 ns


2 OEL to Output 2 10 - 15 ns

tdis 3 Input or I/O to Output 2 10 - 15 ns


3 OEi to Output 1.5 10 - 15 ns

1) Reier to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3} Refer to fmax Descriptions section.
4) Clock pulses 01 widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS


Input Pulse Levels GND t03.0V +5V
Input Rise and Fall Times 3ns 10%-90%
input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active FROM OUTPUT (010) - -.....- -.....-TESTPOINT
level. UNDER TEST
Output Load Conditions (see figure)
Test Condition
1
2 Active High
Rl
2000
R2
3900
3900
CL
50pF
R2 1J
co 50pF
Active Low 2000 3900 50pF -
3 Active High 00 3900 5pF C llNClUDES JIG AND PROBE TOTAL CAPACITANCE
Active Low 2000 3900 5pF

2-15 4191.Rev.A
U
1..1 j;Lattioo' Semicondllctor
Corporation
Specifications GAL 16V8A
Industrial
ABSOLUTE MAXIMUM RATINGS(l) RECOMMENDED OPERATING CONDo
Supply voltage Vce ....................................... -0.5 to +7V Industrial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TA) ............................ -40 to 85°C
Off-state output voltage applied .......... -2.5 to Vee + 1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.50 to +5.50V
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.2 MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - Vcc+1 V

IlL Input or I/O Low Leakage Current OV:s VIN:S Vil (MAX.) - - ·10

IIH Input or I/O High Leakage Current VIH:S VIN :S Vec - - 10

VOL Output Low Voltage 10l= MAX. Vin = VIL or VIH - - 0.5 V

VOH Output High Voltage IOH = MAX. Yin = VIL or VIH 2.4 - - V

10l Low Level Output Current - - 24 mA

10H High Level Output Current - - -3.2 mA

los' Output Short Circuit Current Vee = 5V VOUT = O.SV TA= 25°C -30 - -150 mA

Icc Operating Power VIL = 0.5V VIH = 3.0V floggl. = 25M Hz l ·15/-25 - 75 130 mA

Supply Current Outputs Open (no load) f10991o = 15M Hz a -20/·25 - 45 65 mA

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vce = 5V and TA = 25°C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM' UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee = 5.0V, V, = 2.0V


CliO I/O Capacitance 10 pF Vee = 5.0V: VIIO = 2.0V
"Guaranteed but not 100% tested.

2-16 4/91.Rev.A
/fILatUre"
1.J Semiconductnr
Corporation
Specifications GAL 16V8A
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-15 -20 -25
TEST DESCRIPTION UNITS
'ARAMETER
COND'. Mlt{;.,. )v1AX. MIN. MAX. MIN. MAX.
Input or I/O to Combinational Output 3 &t 3 20 3 25 ns
tpd 1 >I' ""15
==::.

tco 1 Clock to Output Delay 2 ? "'10



2 11 2 12 ns

tct> - Clock to Feedback Delay - i" .J 8 - 9 - 10 ns

tsu - Setup Time, Input or Feedback belore Clock! 12 C 13 - 15 - ns

th - Hold Time, Input or Feedback alter Clocki o 0 - 0 - ns


Ij
1 Maximum Clock Frequency with 41.6 - 37 - MHz
.1l
External Feedback, 1/(tsu + tco)
"', '"
fmax 3 1 Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tet)
50 <: l - 45.4 - 40 - MHz
t
.-

1 Maximum Clock Frequency with \- 50 - 41.6 - MHz


No Feedback C 5
twh4 - Clock Pulse Duration, High 8
¢' ."
C)- 10 - 12 - ns
twl4 - Clock Pulse Duration, Low 8 10 - 12 - ns

ten 2 Input or 110 to Output :i 15


.*
- 20 - 25 ns
2 OEJ. to Output _ to! f15 - 18 - 20 ns

tdis 3 Input or I/O to Output - ;>' ;15 - 20 - 25 ns


3 OEi to Output - "" ,$15 - 18 - 20 ns
) Refer to Switching Test Conditions section.
') Calculated lrom fmax with internal feedback. Refer to Imax Descriptions section.
;) Refer to fmax Descriptions section.
) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS


Input Pulse Levels GNDt03.0V +5V
Input Rise and Fall Times 3ns 10% - 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
,-state levels are measured 0.5V from steady-state active
FROM OUTPUT (O/Q) POINT
weI.
UNDER TEST
)utput Load Conditions (see figure)
CL
Test Condition R1 R2 CL R2
1 2000 3900 50pF
2 Active High 3900 50pF
Active Low i 2000 3900 50pF
3 Active Hlgn 3900 5pF
C L INCLUDES JIG AND PROBE TOTAL CAPACITANCE
Active Low 2000 3900 5pF

2-17 4/91.Rev.A
IllLattioo'
.l..I Corporation
Semiconductor
Specifications GAL 16VBB
GAL 16VBA
SWITCHING WAVEFORMS

INPUT or
va FEEDBACK

elK
INPUT or
va FEEDBACK
REGISTERED
OUTPUT
COMBINATORIAL
OUTPUT

Combinatorial Output Registered Output

INPUT or
OE
va FEEDBACK

OUTPUT OUTPUT

Input or UO to Output Enable/Disable OE to Output Enable/Disable

elK
Iwl

elK

REGISTERED
FEEDBACK
Clock Width

fmax with Feedback

2-18 4191.Rev.l
aJLattire'
.l..J CorporaUon
Semiconductor
Specifications GAL 16V8B
GAL 16V8A
fmax DESCRIPTIONS

elK
.......................................... _--_ ..
elK
_. _. _ •• - _ • • • • • _. - - - - _. - - - _. - eo • • _ •• _ 00 _ . _ • • • •,

lOGIC
REGISTER
A RRAV

REGISTER

/o.II1
. i ..f - - -
....

fmax with External Feedback 1/(tsu+tco) • • • • OM • • • • • _ •• __________ • ____ •• _______ • ____ • ___ !

r.-14------tcl
Note: 'max with external feedback is calculated from measured 1<I!041-----tpd
tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)

Note: tet is a calculated value, derived by subtracting tsu from


the period of fmax w/internal feedback (tet 1lfmax - tsu). The
value of tet is used primarily when calculating the delay from
elK clocking a register to a combinatorial output (through registered
. . . . . 0-- 0 . - - - • • • • • • • • • • • • • • • • - _ . __ • • _-_ • • • • • • • • •
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

lOGIC
REGISTER
ARRAY I--+--'

.
• __ . 0 • • • • • • - ••••••• - . · · ••• - . · · . - . · _ - •••• -- •• ·_--
.
fmax With No Feedback

Note: fmax with no feedback may be less than 1ltwh + twl. This
is to allow for a clock duty cycle ol'other than 50%.

2-19 4/91.Rev.A
U
l..tI lLattiooo
Semiconductor
CorporaUon
Specifications GAL 16VBB
GAL 16VBA
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD

An electronic signature (ES) is provided in every GAL 16V8A and When testing state machine designs. all possible states and state
GAL16V88 device. It contains 64 bits of reprogram mabie memory transitions must be verified in the design. not just those required
that can contain user defined data. Some uses include user 10 in the normal machine operations. This is because. in system
codes. revision numbers. or inventory control. The signature data operation. certain events occur that may throw the logic into an
is always available to the user independent of the state of the illegal state (power-up. line voltage glitches. brown-outs, etc.). To
security cell. test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
NOTE: The ES is included in checksum calculations. Changing (i.e., illegal) state into the registers. Then the machine can be
the ES will alter checksum. sequenced and the outputs tested for correct next state conditions.

The GAL 16V8A and GAL 16V88 devices include circuitry that
allows each registered output to be synchronously set either high
SECURITY CELL or low. Thus, any present state condition can be forced for test
sequencing. If necessary, approved GAL programmers capable
A security cell is provided in the GAL 16V8A and GAL 16V88 of executing text vectors perform output register preload auto-
devices to prevent unauthorized copying of the array patterns. matically.
Once programmed. this cell prevents further read access to the
functional bits in the device. This cell can only be erased by re-
programming the device. so the original configuration can never
be examined once this cell is programmed. The Electronic INPUT BUFFERS
Signature is always available to the user. regardless of the state
of this control cell. GAL 16V8A and GAL16V88 devices are designed with TIL level
compatible input buffers. These buffers have a characteristically
high impedance, and present a much lighter load to the driving
logic than bipolar TIL devices.
LATCH-UP PROTECTION
The GAL16V88 input and 110 pins have built-in active pull-ups.
GAL16V8A and GAL 16V88 devices are designed with an on-
As a result, unused inputs and I/O's will float to a TIL "high"
board charge pump to negatively bias the substrate. The negative
(logical "1"). In contrast, the GAL16VSA does not have active pull-
bias is of sufficient magnitude to prevent input undershoots from
ups within their input structures. Lattice recommends that all
causing the circuitry to latch. Additionally. outputs are designed unused inputs and tri-stated I/O pins for both devices be con-
with n-channel pull-ups instead of the traditional p-channel pull-
nected to another active input, VCJ::' or Ground. Doing this will tend
ups to eliminate any possibility of SCA induced latching.
to improve noise immunity and reduce Icc forthe device.

DEVICE PROGRAMMING Typical Input Pull-up Characteristic

GAL devices are programmed using a Lattice-approved Logic


Programmer. available from a number of manufacturers (see the
;;; 0
/
GAL Development Tools section). Complete programming of the
device takes only a few seconds. Erasing of the device is ;" ·20
/'
transparent to the user. and is done automatically as part of the " ./
V
(,)

programming cycle. :; ·40


Q.

.!:
·60
o 1.0 2.0 3.0 4.0 5.0
Input Voltag' (Volts)

2-20 4/91.Rev.A
Specifications GAL 16V8B
.l.J COl'poration
SemJronducwr
GAL 16V8A
POWER-UP RESET

Vee
OV
V IH rT"...-tt...--.-rrrr"\lr---------
CLK VALID CLOCK SIGNAL
Vil

INTERNAL INTERNAL REGISTER


REGISTER RESET TO LOGIC 0
a·OUTPUT

FE EDBACK/E XTE RNAL EXTERNAL REGISTER


OUTPUT REGISTER OUTPUT = LOGIC 1

within the GAL 16V8A and GAL 16V8B provides a reset The timing diagram for power-up is shown above. Because of
,ignalto all registers during power-up. All internal registers will the asynchronous nature of system power-up, some conditions
lave their Q outputs set low after a specified time (t RESET' 45115 must be met to guarantee a valid power-up reset of the
\/lAX). As a result, the state on the registered output pins (if they GAL 16V8A and GAL 16V8B. First, the Vee rise must be mono-
ue enabled through OE) will always be high on power-up, re- tonic. Second, the clock input must become a proper TTL level
Jardless of the programmed polarity of the output pins: This within the specified time (tPR' lOOns MAX). The registers will reset
'eature can greatly simplify state machine design by providing a within a maximum time. As in normal system operation,
mown state on power-up. avoid clocking the device until all input and feedback path setup
times have been met.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN

Feedback
Active Pull-up
Vee
CircuM ActivePull-tJp
(GALI6V8B only) Cil'aJit
(GAL16V88 only)
-------------- --- _., ....y.... ...y.....
Trl-State i Vret i
Control
: ESD
: Protection
i ClrcuR
:----------------- _eo!
Data
!lIN PIN
Output
,.---------------- __ e.
: ESD :
: Protection :
l
··
CircuM l
.
··.----.-------.-.- ----... Feedback
(To Input Buffer)
Typ. Vref = 3.2V Typ. Vref = 3.2V

Typical Input Typical Output

2-21 4191.Rev.A
Specifications GAL 16V8B
Typical Characteristics
Normalized Tpd vs Vee Normallzad Teo vs Vee Normallzad Tsu vs Vee

t .•
J..... ,I--FALL
u t.'

i---t---t-i
PTH..L
.....
!-
t.t
......... 1-- J!
t.t
,!!
t.t

1 +1--====1=' ]t --- -" ....... ]t


II--PTL..H

J
]
-'- ........
J 0.'
. ...... ............
J 0.'
0.' t---t--+.,--t---;

.... .... .... ....


•.• + - - - - 1 - - 4 - - - - 1 - - - - 1
.... •...... .... .... ....
".75
0 .•
4.711 .... .... ...0 4.711
Supply Voltage (V) Supply Voltage (V) Supply Vohage (V)

Normalized Tpd vs Temp Normalized Teo vs Temp Normellzad Tsu vs Temp

t.3 t.3
t.'
••••. PTH..L I
t.' t.3 ••••. PTH..L I L
.., ./ /'

-- .. ..
o
,.2-1.1 --PTL->HI 1.1 .' iii t ••
--PTL.. HI
/
1 /'
0- '
] "i
:os 1 ,.,..
1
t.t
.. ' .'
/.-
J . 0.•
'
t

0.'
Z
t
0.'
....... . /
0.8 0.'
0.' /"
......
0.1
... ..
Temperature (deg. C)
to t ..
0.1
... .. to t ..
0.1
... .. to t ..
Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Teo vs # of Outputs


Switching Switching

:.:-
.. , .. ' ;;.:.. p .. .' .
'
pr""
] : -0.5

..,
.'
.'
/
i-"'"
_-0.5
..s. .. '
.'
/
.-'
.e- ., ./ J! ·t ./

c!'l .t .•
V ••••• RISE} /" ..... RISJ
c!'l .t.'
--FALL FALL
.. ..
Number of Outputs SwUching Number of Outputs SwUching

Delta Tpd vs Output Loading Delta Teo VI Output loading

to

j ..... RISE I
/
to

••••. I
V
g' --FALLI
/,.
--FALLI
..'
1--;':".,
L /.
.' .'
/- L
-. 50 tOO 150 200 29 300
.. 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

2-22 4191.Rev.A
Specifications GAL 16V8S
.l.J Corporation
Semiconductor
Typical Characteristics
I'

Vol vs 101 Voh VI Ioh Voh VI loh

....
0.75

.... ,/
,/
,/'
/
/ ........
""-
--- r- r--
42'

'.75
"'- r-.
---r---
V ....
0.00 20.00 40.00 10.00 '0.00 100.00 0.00 10.00 20.00 30.00 CO.OO 50.00 10.00 0.00 .... .... 3.00 4.00

101 (mA) Ioh(mA) 10h(mA)

Normalized Icc vs Vee Normalized Icc vs Temp Normalized Icc vs Fraq.

12. 12. u.
I'-.. ....
1.10

V
1.10

I'--- .l;l L V
"il "il I'-.. "2 1.10
.......
----- 1,·00 V L
1.00 1.00

1 0.80
1.... 1""- I'..
....
f'-, .A.
0.80
.... 4.75

Supply
5.00 5.25

(V)
.... 0.80
Z5

Temperature (deg. C)
1'5 tOO 125 . .
Frequency (MHz)
...

Delta Icc vs Vin (1 input) Input Clamp (Vik)

.....
•• /
••
3D /
<-,40 1/
/1\ .§. ..
60 /

II
J \ .....
I'-
..
70

1/
/
/

• 00
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ·2.00 ·1.$0 -1.00 -0.50 0.00

Vin(V) Vik(V)

2·23 4191.Rev.A
[J;J
.l..i
'Lattice@
Semiconductor
CorporaUon
Specifications GAL 16V8A
Typical Characteristics
Normalized Tpd VS. Vee Normalized Tsu vs. Vee Normalized Tco vs. Vee
"- 1.3

--- -
1.'

0
Oil

- r--
1 1.1
1-

-
'0
al

1'"
1 1.0
OJ
E
o 0 0.'
Z

0.'

t1'74-!:
.. ... .. 0.7
.5O 4.76 5.00 5.25
'.SO 4.75 6.00 5.25 5,SO
Supply Voltage (V) Supply Voltage (V) Supply Vonage (V)

Normalized Tpd vs. Temperature Normalized Tsu vs. Temperalure Normalized Teo vs.
1.3 1.3 I.,

-
1.2 12

'0 1.1
0..
. . .v '"
III
1.1
. . .v I.'
1-
V 1-
V 0
0 1.1

.. . /V
I-
a1 1.0 a1 1.0
.to!

E 0.' V IV

§ 0.'
V al
.!:! 1.0
g V
0
z V Z V 5
z
0.'
./
V
0.• 0.8

0.7 / 0.7 / 0.'

0 .•
·so ·25 25 50 75 100 '25
0.•
·.0 ·25 0 2S 50 7S 100 125
0.7
.., ·25 "0 '25
Ambient Temperalure (OC) Ambient Temperature (0C) Ambient ('C)

Normalized Tpd .s.• of Outputs Swhching Delta Tpd vs. Output Loading Normalized Icc vs. Vcc

"
/
1.00

V 12

R
0.98 L /
V
............
/
'.1

/
1-
'0

'iii 0.95 ./ <D


.!:i 1.0
E
/ 'iii
E 0.' " ...............
.... , /
Z
a

0.'
...........
,/ ., /'
.92
100 200 300
0.7
•.SO 4.75 5.00 5.25 ....
• of Outputs Output Loading Capacitance (pQ Supply Voltage (V)

IOL vs. VOL IOH VS. VOH Normalized Icc vs. Temperature

-
2SO ·150
'.3

200
,.- '2

<" 150
.s
-'
12 100

/
V :?
.s
::t
.Q
·'00

·50
'" " ""'" ........
a1N
1ij
E
1.1

1.0

...
--r-- I'--..
......
i'--
r-....
""
a
Z
so

V
0.'

•. 7
-50 -25 25 50 75 100 125

VOL (V) VOH(V) Ambienl Temperature (0C)

2-24 4/91.Rev.A
i J; lLatUoo"
Semiconductor
Corporation
GAL20V8B
GAL20V8A
High Performance E2CMOS PLD
FEATURES FUNCTIONAL BLOCK DIAGRAM
• HIGH PERFORMANCE TECHNOLOGY
-7.5 ns Maximum Propagation Delay
- Fmax = 100 MHz
- 5 ns Maximum from Clock Input to Data Output
- TTL Compatible 24 mA Outputs
- Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75mA lYP Icc on Low Power Device
- 45mA lYP Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS (GAL20V8B)
• E2 CELL TECHNOLOGY
- Reconflgurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 24-pln Devices with Full Func-
tion/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION PIN CONFIGURATION
DESCRIPTION
The GAL20V8B, at 7.Sns maximum propagation delay time, com- DIP
bines a high performance CMOS process with Electrically Eras- PLCC
able (E2) floating gate technology to provide the highest speed IICLK Vee
performance available in the PLD market. High speed erase times
«1 OOms) allow the devices to be reprogrammed quickly and ef- g !11 >8 -
ficiently. 1/0/0
2.
The generic architecture provides maximum design flexibility by VOIQ 1/0/0
allowing the Output Logic Macrocell (OLMC) to be configured by 110/0
110/0
the user. An important subset of the many architecture con- GAL20VSAlB IIO/Q

figurations possible with the GAL20V8A1B are the PAL architec- NC NC 1/0/0
tures listed in the table of the macrocell description section. Top View 110/0
110/0
GAL20V8A1B devices are capable of emulating any of these PAL UOIO

architectures with full functionlfuse map/parametric compatibility. 1I0/Q 110/0

1/0/0
Unique test circuitry and reprogram mabie cells allow complete 0
-
AC, DC, and functional testing during manufacture. As a result,
z
" '" " 1/0/0
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years. GND IIOE

Copyright e1991 Lattice Semicondudor Corp. GAL. PCMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc·
tor Corp. PAl is a registered trademark of Advanced Micro Devices, Inc. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A. May 1991.Rev.A
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037
2-25
!lJtattiOOGl
.l.J Corporation
Semironducwr
Specifications GAL20V8B
GAL20V8A
GAL20V8A/B ORDERING INFORMATION

Commercial Grade Specifications


Tpd (ns) Tsu (n8) Tco (ns) Icc (mA) Ordering # Package

7.5 7 5 115 GAL20V8B-7W 28-Lead PLCC


10 10 7 115 GAL20V8B-l0W 28-Lead PLCC
115 GAL20VSA-l0LP 24-Pin Plastic DIP
115 GAL20V8A-l0LJ 28-Lead PLCC
15 12 10 55 GAL20VSA-15QP 24-Pin Plastic DIP
55 GAL20V8A-I5QJ 2B-Lead PLCC
115 GAL20V8A-15LP 24-Pin Plastic DIP
115 GAL20V8A-15LJ 28-Lead PLCC
25 15 12 55 GAL20V8A-25QP 24-Pin PlastK: DIP
55 GAL20V8A-25QJ 28-Lead PLCC
90 GAL20V8A-25LP 24-Pin Plastic DIP
90 GAL20V8A-25LJ 28-Lead PLCC

Industrial Grade Specifications


Tpd (n5) T5U (n5) Tco (n5) Icc (mA) Ordering # Package

15 12 10 130 GAL20V8A-15LPI 24-Pin Plastic DIP


130 GAL20V8A-15WI 28-Lead PLCC
20 13 11 65 GAL20V8A-200PI 24-Pin Plastic DIP
65 GAL20V8A-200JI 28-Lead PLCC
25 15 12 65 GAL20V8A-25QPI 24-Pin Plastic DIP
65 GAL20V8A-25OJ1 28-Lead PLCC
130 GAL20V8A-25LPI 24-Pin Plastic DIP
130 GAL20V8A-25WI 28-Lead PLCC

PART NUMBER DESCRIPTION

xxxxxxxx - xx X X X

GAL20V8A Device N,me


GAL20V8B

Speed (n5) ' - - - - - Grade Blank = Commercial


I = Industrial

L = Low Power Power L -_ _ _ _ Package P =Plastic DIP


Q = Quarter Power J = PLCC

2-26 4191.Rev.A
Serniconducwr
Specifications GAL20V8B
Corporation GAL20V8A
OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic


macrocell. It should be noted that actual implementation is ac- PAL Architectures GAL20V8A1B
complished by development soflwarelhardware and is completely Emulated by GAL20V8A1B Global OlMC Mode
transparent to the user.
20R8 Registered
There are three global DLMC configuration modes possible: 20R6 Registered
simple, complex, and registered. Details of each of these 20R4 Registered
modes is illustrated in the following pages. Two global bits, SYN 20RP8 Registered
20RP6 Registered
and ACO, control the mode configuration for all macrocells. The 20RP4 Registered
XDR bit of each macrocell controls the polarity of the output in any
of the three modes, while the ACI bit of each of the macrocells 2018 Complex
controls the input/output configuration. These two global and 16 20H8 Complex
individual architecture bits define all possible configurations in a 20P8 Complex
GAL20V8A1B. The information given on these architecture bits l4l8 Simple
is only to give a better understanding of the device. Compiler soft- l6l6 Simple
ware will transparently set these architecture bits from the pin l8l4 Simple
definitions, so the user should not need to directly manipulate 2012 Simple
these architecture bits. l4H8 Simple
l6H6 Simple
l8H4 Simple
The following is a list of the PAL architectures that the GAL20V8A 20H2 Simple
and GAL20V8B can emulate. It also shows the DLMC mode un- l4P8 Simple
der which the devices emUlate the PAL architecture. l6P6 Simple
l8P4 Simple
20P2 Simple

COMPILER SUPPORT FOR OLMC


Software compilers support the three different global DLMC In registered mode pin 1 and pin 13 are permanently configured
modes as different device types. These device types are listed as clock and output enable, respectively. These pins cannot be
in the table below. Most compilers have the ability to automati- configured as dedicated inputs in the registered mode.
cally select the device type, generally based on the register usage
and output enable (DE) usage. Register usage on the device In complex mode pin 1 and pin 13 become dedicated inputs and
forces the software to choose the registered mode. All combi- use the feedback paths of pin 22 and pin 15 respectively. Because
natorial outputs with DE controlled by the product term will force of this feedback path usage, pin 22 and pin 15 do not have the
the software to choose the complex mode. The software will feedback option in this mode.
choose the simple mode only when all outputs are dedicated
combinatorial without DE control. The different device types listed In simple mode all feedback paths of the output pins are routed
in the table can be used to override the automatic device selection via the adjacent pins. In doing so, the two inner most pins ( pins
by the software. For further details, refer to the compiler software 18 and 19) will not have the feedback option as these pins are
manuals. always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user


must pay special attention to the following restrictions in each
mode.

Registered Complex Simple Auto Mode Select


ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/IC GAL20V8 R GAL20V8 C7 GAL20V8 C8 GAL20V8
OrCAD-PLD "Registered"' "Complex"' "Simple"' GAL20V8A
PLDeslgner P20V8R2 P20V8C2 P20V8C2 P20V8A
TANGO-PLD G20V8R G20V8C G20V8AS3 G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
2-27 4/91.Rev.A
[JJ
1.J
LattiOO@
Semironductor
Corporation
Specifications GAL20V8B
GAL20V8A
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated mode. Dedicated input or output functions can be implemented
registered outputs or as 110 functions. as subsets of the VO function.

Architecture configurations available in this mode are similar to Registered outputs have eight product terms per output. I/O's
the common 20R8 and 20RP4 devices with various permutations have seven product terms per output.
of polarity, I/O and register placement.
The JEDEC fuse numbers, including the User Electronic Signature
All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are
control pins. Any macrocell can be configured as registered or shown on the logic diagram on the following page.
I/O. Up to eight registers or up to eight I/O's are possible in this

elK

Registered Configuration for Registered Mode

-SYN=O.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE.
'.. ... - .. ,_._----------------------------------,
OE

Combinatorial Configuration for Registered Mode

- SYN=O.
-ACO:1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE.
'..----------------------.---------------------,

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

2-28 4/91.Rev.A
Specifications GAL20V8B
GAL20V8A
REGISTERED MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts

....
".
1(2) D ....
0 • B ,. 11 20 .. 211
" " Pro
2(3) D -CJ23(27)

rr'
0000
OLMC 22
2(26)
0210 XDR·2560
3(4) D AC1·2632

tr"
03,.
OLMC 21
(25)
06DO XOR·2561
4(5) D AC1·2633

0='
"'0 OLMC 20
0(24)
0920
== 3=f XOR·2562
5(6) AC1·2634

0='
09S0
-0- OLMC 19
9(23)
1240 XDR·2563
6(7) AC1·2635

1280
OLMC 18 rJ 8(21)

7(9)8
1560 XOR·2564
AC1·2636 [J
1600
.r, OLMC 17 rJ 7(20)

8(10)8
"10 3=f XDR·2565
AC1·2637 [J
1920
OLMC 16 11 16(19)

9(11
22DO XOR·2566
AC1·2638 [J
2240
-0 OLMC 15 rJ 15(18)

10{12) 0
2520 XDR·2567
AC1·2639 [J
11(13) 0 -CJ 14(17)
DE
"03 13(16)

SYN·2704
ACO·2705

2-29 4/91.Rev.A
.l..J Corporation
Semioonductor
Specifications GAL20VBB
GAL20VBA
COMPLEX MODE
In the Complex mode, macrocells are configured as output only pability. Designs requiring eight IIO's can be implemented in the
or 1/0 functions. Registered mode.

Architecture configurations available in this mode are similar to All macrocells have seven product terms per output. One product
the common 20L8 and 20P8 devices with programmable polarity term is used for programmable output enable control. Pins 1 and
in each macrocell. 13 are always available as data inputs into the AND array.

Up to six IIO's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.
two outer most macrocells (pins 15 & 22) do not have input ca-

................... _------_ ..... _............ Combinatorial 1/0 Configuration for Complex Mode

J -SYN-1.
-ACO.. 1.
- XOR.O defines Active Low Output.
- XOR=1 defines Active High Output.
-AC1=1.
- Pin 16 through Pin 21 are configured to this function .

...... -............ -- ................................

po . . . - . . . . . . . . . . _ - . . . . - - • • - - . . . . . . . - - . - - - _ . . . - . . .

Combinatorial Output Configuration for Complex Mode

i; P-r,D XOR
Cl--o -SYN=1.
-ACO.. 1.
- XOR..Odefines Active Low Output.
- XOR=1 defines Active High Output.
-AC1-1.
- Pin 15 and Pin 22 are to this function.
-- .... ---.-.. _-_ ...... __ ._------------_ ...

Note: The development software configures all of the architecture control bits.and checks for proper pin usage automatically.
!
/

2-30 4191.Rev.A
!lJ tBttice
Semironductor
Corporation
®

Specifications GAL20V8B
GAL20V8A
COMPLEX MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts

.. .. ....
1(2)

2(3) L.>---
• • • 12 11 10 14 21 PlD

.A
j 23(27)

.,,,
a=
:a= OLMC 22 0 ... -r122(26)
0280 'tj= XOR-2560
3(4) ACl-2632

"" J
OLMC 21 ,..r,21 (25)

4(5) .--..
"., "'--': XOR-2561
ACl-2633

"40
:a= OLMC 20 =:l
--.::J 02
0(24)
XOR-2562
5(6) D "" ACl-2634

,."
OLMC 19 n v
J-G1
9(23)
-=-
-
1240 XOR-2563
6(7)
.---.. ACl-2635

"80

7(9)0
1580
OLMC 18
XOR-2564
ACl-2636 M 18(21)

"" .0-
OLMC 17 -Y"'l1 7(20)
v

8(10)D
1880 XOR-2565
ACl-2637 J
""
OLMC 16 v 16(19)
22" =8= XOR-2566
9(11 )8 ACl-2638

2240

OLMC 15 15(18)

10(12)
,--,. .." XOR-2567
ACl-2639
I -a 14(17)
11(13),--,. .....
-a 13(16)
1113
fI4.U8EII B.fCIlIONIC 8IGNAlURE FU8EB

l&:7iC.·....
M L
. . _,:01 SYN-2704
ACO-2705

8 8
B B

2-31 4/91_Rev.A
Specifications GAL20VBB
GAL20VBA
SIMPLE MODE
In the Simple mode, pins are configured as dedicated inputs or Pins 1 and 13 are always available as data inputs into the AND
as dedicated, always active, combinatorial outputs. array. The "center" two macrocells (pins 18 & 19) cannot be used
in the input configuration.
Architecture configurations available in this mode are similar to
the common 14L8 and 16P6 devices with many permutations of The JEDEC fuse numbers including the UES fuses and PTD fuses
generic output polarity or input choices. are shown on the logic diagram on the following page.

All outputs in the simple mode have a maximum of eight product


terms that can control the logic. In addition, each output has
programmable polarity.

...... _--------------_. __ ._------.----------


Combinatorial Output with Feedback Configuration
Vee for Simple Mode

- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1 =0 defines this configuration.
- All OLMC except pins 18 & 19 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR= 1 defines Active High Output.
- AC1 =0 defines this configuration.
- Pins 18 & 19 are permanently configured to this
.'-------._.---------------------------------_.: function.

Dedicated Input Configuration for Simple Mode

-SYN .. 1.
-ACO-O.
- XOR..Odefines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this configuration.
.._---------------------------.--------------,. - All OLMC except pins 18 & 19 can be configured to
this function .

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

2-32 4f91.Rev.A
I,
::j
I.;
Semironductor
Specifications GAL20V8B 1.1

Corporation GAL20V8A Ii

SIMPLE MODE LOGIC DIAGRAM


DIP (PlCC) Package Pinouts

. ....
1(2) LJ

2(3) LJ
, • • ,.
" .. 1M 211
II
.A
j rCJ23( 27)

.... OLMC 22 b
.... ::a=:::t XOR·2560
AC1·2632
J ... -cl22(26)

.A
3(4) 0

".. OLMC 21
XOR·2561
n
J .. -cl21 (25)
.... ::::a=:::::::I
....
AC1·2633
4(5) LJ

....
....
.0. OLMC 20
XOR·2562
AC1·2634 J
n n20(24)

5(6)L..J .....

.... OLMC 19 h
XOR·2563 0 1 9(23)
'240
::a=:::t
::;,
AC1-2635 J
6(7) D

Jb..
'2" OLMC18
XOR·2564 """'1 8(21)

7(9) L....J
".. ::::a=:::::::I AC1·2636

".. -0- OLMC 17


XOR·2565
n -C"] 17(20)
"SO AC1-2637 J
8(10)

""
==
OLMC 16
XOR·2566
AC1-2638
n
J ... -nl 6(19)
22,.
9(1 1)

Jb,. . . .-
2240
OLMC 15
9::::::=1 XOR·2567 15(18)
AC1-2639
25" .A
10(1 2)D
I -CJ 14(17)
11(1 3) ....
13(16)

84-USER ElECI'RONIC SIGNATURE FUSSS


2'"
1:\=,··....
101 L
.. . SYN·2704
ACO·2705

8 S
B B

2-33 4191.Rev.A
[JJ
.l.I
tattice®
Semiconductor
Corporation
Specifications GAL20V8B
Commercial
ABSOLUTE MAXIMUM RATINGS(l) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -0.5 to +7V Commercial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Off-state output voltage applied ........ ,. -2.5 to Vee +1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss-0.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
ilL' Input or 1/0 Low Leakage Current OV VIN VIL (MAX.) - - -100 !LA
IIH Input or 1/0 High Leakage Current 3.5V VIN Vee - - 10 !LA
VOL Output Low Voltage 10L=MAX. Yin = VIL or VIH - - 0.5 V
VOH Output High Voltage 10H = MAX. Vin = VIL or VIH 2.4 - - V
10L Low Level Output Current - - 24 mA
10H High Level Output Current - - -3.2 mA
los2 Output Short Circuit Current Vcc=5V VOUT= 0.5V TA= 25°C -30 - -150 mA
Icc Operating Power Supply Current VIL= 0.5V VIH = 3.0V ftoggle = 25MHz - 75 115 mA
Outputs Open (no load)
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for moreJnformation.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee =5.0V, V, = 2.0V

CliO 1/0 Capacitance 8 pF Vcc = 5.0V, V'iO = 2.0V


"Guaranteed but not 100% tested.

2-34 4/91.Rev.A
flJ UJtticeGP
Semironductor
C0i'p(X'8t/01l

AC SWITCHING CHARACTERISTICS
Specifications GAL20V8B
Commercial

OVer Recommended Operating Conditions

TEST ·7 ·10
PARAMETER DESCRIPTION UNITS
COND'. MIN. MAX. MIN. MAX.
tpd 1 Input or 110 to Combinational Output I 8 outputs switching 3 7.5 3 10 ns
I 1 output switching - 7 - - ns

tco 1 Clock to Output Delay 2 S 2 7 ns


tcf2 - Clock to Feedback Delay - 3 - 6 ns
tsu - Setup lime, Input or Feedback before Clockt 7 - 10 - ns
th - Hold lime, Input or Feedback after Clockt 0 - 0 - ns
1 Maximum Clock Frequency with 83.3 - S8.8 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with


Internal Feedback, 1/(tsu + tcf)
100 - 62.S - MHz

1 Maximum Clock Frequency with 100 - 62.S - MHz


No Feedback

twh4 - Clock Pulse Duration, High S - 8 - ns

twt' - Clock Pulse Duration, Low S - 8 - ns


ten 2 Input or 110 to Output 3 9 3 10 ns
2 OE.!. to Output 2 6 2 10 ns

tdis 3 Input or 1/0 to Output 2 9 2 10 ns


3 OEt to Output 1.S 6 1.S 10 ns
1) Refer to Switching Test Conditions sectIOn.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS

Input Pulse Levels GNDt03.0V +5V


Input Rise and Fall limes 3ns 10%-90%
Input Timing Reference Levels 1.SV
OutpU1liming Reference Levels 1.SV
Output Load See Figure
3-state levels are measured O.SV from steady-state active
level.
FROM OUTPUT (010) --+---..- TEST POINT
UNDER TEST
Output Load Conditions (see figure) CL
R2
Test Condition RI R2 CL
1 2000 3900 SQpF
2 Active High 00 3900 SOpF

3
Active Low
Active High
Active Low
-
2000

2000
3900
3900
3900
50pF
SpF
5pF
C LlNCLUDESJIG AND PROBE TOTAL CAPACITANCE

2-35 4/91.Rev.A
1£ SemiconduGwr
Corporation
Specifications GAL20V8A
Commercial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo
Supply voltage vee ....................................... -0.5 to +7V Commercial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Off-state output voltage applied .......... -2.5 to Vee +1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ........................................-55 to 125°C
1.Stresses above those listed under the· Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.2 MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - VcC+1 V

IlL input or 1/0 Low Leakage Current OV VIN VIL (MAX.) - - -10 J.lA
IIH Input or 110 High leakage Current VIH VIN Vee - - 10 J.lA
VOL Output Low Voltage 10L =MAX. Yin =VIL or VIH - - 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 - - V

10l low Level Output Current - - 24 rnA

10H High level Output Current - - -3.2 rnA

los' Output Short Circuit Current Vcc=5V VOUT= 0.5V TA = 25°C -30 - -150 rnA
Operating Power VIL = 0.5V VIH = 3.0V f,oggl8 = 15MHz L·25 - 75 90 rnA

Icc Supply Current Outputs Open (no load) flO9gl8 = 25MHz L -101-15 - 75 115 rnA
f'099I8 = 15MHz 0·15/-25 - 45 55 rnA

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc =5V and TA = 25 ·C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM- UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vcc = 5.0V, V, = 2.0V

ClIO 1/0 Capacitance 10 pF Vee = 5.0V, VIIO = 2.0V


'Guaranteed but not 100% tested.

2-36 4191.Rev.A
Specifications GAL20V8A
.lJ CorporaUon
SemioonducUJr
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

TEST -10 -15 -25


PARAMETER DESCRIPTION UNITS
COND'. MIN. MAX. MIN. MAX. MIN. MAX.
tpd 1 Input or va to Combinational Output 3 10 3 15 3 25 ns

teo 1 Clock to Output Delay 2 7 2 10 2 12 ns

tel2 Clock to Feedback Delay - 7 - 8 - 10 ns

tsu Setup Time, Input or Feedback before Clocki 10 - 12 - 15 - ns

th Hold Time, Input or Feedback after Clocki 0 - 0 - 0 - ns


1 Maximum Clock Frequency with 58.8 - 45.5 - 37 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with 58.8 - 50 - 40 - MHz


Internal Feedback, 1/(tsu + tel)
1 Maximum Clock Frequency with 62.5 - 62.5 - 41.7 - MHz
No Feedback

twh4 Clock Pulse Duration, High B - 8 - 12 - ns


twl4 Clock Pulse Duration, Low B - 8 - 12 - ns

ten 2 Input or va to Output Enabled - 10 - 15 - 25 ns


2 OE.!. to Output Enabled - 10 - 15 - 20 ns

tdis 3 Input or va to Output Disabled - 10 - 15 - 25 ns


3 OEi to Output Disabled - 10 - 15 - 20 ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to Imax Descriptions llection.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS

Input Pulse Levels GNDto 3.0V +5V


Input Rise and Fall Times 3ns 10%-90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
FROM OUTPUT (010) ---+----+--TEST POINT
level.
UNDER TEST
Output Load Conditions (see figure)
Cl
Test Condition R, Rz CL
1 2000 3900 500F
2 Active High 00 3900 50pF
Active Low 2000 3900 50pF
3 Active High 00 3900 5pF CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
Active Low 2000 3900 5pF

2-37 4191.Rev.A
Specifications GAL20V8A
.l..J Corporation
Scmiconductnr
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -{).5 to +7V Industrial Devices:
Input voltage applied ........................... -2.5 to vee + 1.0V Ambient Temperature (TA) ............................ -40 to 85°C
Off-state output voltage applied .......... -2.5 to Vee + 1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.50 to +5.50V
Ambient Temperature with
Power Applied ........................................-55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss-O.S - 0.8 V


VIH Input High Voltage 2.0 - VcC+1 V
IlL Input or 110 Low Leakage Current OV S VIN S Vil (MAX.) - - -10 J-lA
IIH Input or VO High Leakage Current VIH S VIN S Vee - - 10 J-lA
VOL Output Low Voltage 101. - MAX. Yin - Vil or VIH - - 0.5 V
VOH Output High Voltage IOH .. MAX. Vin. VIL or VIH 2.4 - - V
10L Low Level Output Current - - 24 mA
10H High Level Output Current - - -3.2 mA
los' . Output Short Circuit Current Vccz 5V YOUTz 0.5V TA- 25·C -30 - -150 mA
Operating Power VIL= 0.5V VIH=3.0V floggle = 25MHz L ·15/-25 - 75 130 mA

Icc Supply Current Outputs Open (no load) floggle .. 15M Hz a -20/-25 - 45 65 mA
1) One output at a time for a maximum duration of one second. Vout .. 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc - 5V and TA" 25 ·C

CAPACITANCE (TA =25°C, f = 1.0 MHz)


SYMBOL PARAMETER MAXIMUM- UNITS TEST CONDITIONS
C, Input Capacitance 8 pF Vee = 5.0V, V, = 2.0V
Coo 110 Capacitance 10 pF Vee = 5.0V, VIIO= 2.0V
.Guaranteed but not 100% tested .

2-38 4/91.Rev.A
[JJ
.l..tI
:Lattice
Semiconductor
Corporation
GD
Specifications GAL20V8A
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
·15 ·20 -25
TEST OESCRIPnON UNITS
CONO'. MIN. MAX. MIN. MAX. MIN. MAX.
tpd 1 Input or I/O to Combinational Output 3 15 3 20 3 25 ns

teo 1 Clock to Output Delay 2 10 2 11 2 12 ns

tcf2 Clock to Feedback Delay - 8 - 9 - 10 ns

tsu Setup lime, Input or Feedback before Clocki 12 - 13 - 15 - ns


th Hold lime, Input or Feedback after Clocki 0 - 0 - 0 - ns
1 Maximum Clock Frequency with 45.5 - 41.6 - 37 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with


Internal Feedback, 1/(tsu + tel)
50 - 45.4 - 40 - MHz

1 Maximum Clock Frequency with 62.5 - 50 - 41.6 - MHz


External Feedback

twh' Clock Pulse Duration, High 8 - 10 - 12 - ns


twt' Clock Pulse Duration, Low 8 - 10 - 12 - ns

ten 2 Input or I/O to Output - 15 - 20 - 25 ns


2 OEJ.to Output - 15 - 18 - 20 ns

tdis 3 Input or 110 to Output - 15 - 20 - 25 ns


3 OEi to Output - 15 - 18 - 20 ns
) Refer to Switching Test Conditions section.
Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
i) Refer to fmax Descriptions section .
.) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS


Input Pulse Levels GNDt03.0V +5V
Input Rise and Fall Times 3ns 10%-90%
Input liming Reference Levels 1.5V
Output liming Reference Levels 1.5V
Output Load See Figure
i·state levels are measured O.SV from steady-state active
FROM OUTPUT (0/0) - - - . . - - -......- TEST POINT
weI.
UNDER TEST
>utput Load Conditions (see figure)
CL
Test Condition Rl R2 CL
1
2 Active High ..
2000 3900
3900
50DF
50pF

3
Active
Active
Active
Low
High
Low
..
2000

2000
3900
3900
3900
SOpF
5pF
5pF
CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE

2-39 4/91.Rev.A
!lJ:Lattice-
1.1 Corporation
Semiconducwr
Specifications GAL20V8B
GAL20V8A
SWITCHING WAVEFORMS

INPUT or
LIO FEEDBACK

INPUT or
LIO FEEDBACK
\\\\\\\ ClK

\\\\\\\\\\\\\\il==
REGISTERED
OUTPUT
COMBINATORIAL
OUTPUT

Combinatorial Output Registered Output

INPUT or
OE
110 FEEDBACK

OUTPUT

- Input QrllOto $utput EioableJDlsable OE to Output Enable/Disable

elK

elK
REGISTERED
FEEDBACK
Clock Width

fmax with Feedback

4/91.Rev.A
flJ'Lattioo*
SemioonductlJr
Corporauon
Specifications GAL20V8B
GAL20V8A
fmax DESCRIPTIONS

elK
····
, • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • __

..
• • • _o __ o _ . _ _ _ ,

· elK

LOGIC REGISTER
ARRAY

·'.. ---_ ... __ ..................... _---_ ............ ..


I0Il1"1---10 u---."II4"f---- Ico---.t

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured


lsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from


CLK
[................................. ·············1 the period of fmax w/internal feedback (tcf - 1lfmax - tsu). The
value of tcf is used primarily when calculating the delay from
· . clocking a register to a combinatorial output (through registered
LOGIC feedback), as shown above. For example, the timing from clock
REGISTER
ARRAY to a combinatorial output is equal to tcf + tpd.

• • • • • • • • 00 _ •• _ ••••••••• _ • • • • • _. _____ • _. _ ••••• _.'

fmax Without Feedback

Note: fmax with no feedback may be less than 1ltwh + twl. This
is to allow for a clock duty cycle of other than 50%.

2-41 4191.Rev.A
VI:!!!!!/
horporatJon
Specifications GAL20V8B
GAL20V8A
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD

An electronic signature (ES) is provided in every GAL20V8AIB When testing state machine designs, all possible states and state
device. It contains 64 bits of reprogram mabie memory that can transitions must be verified in the design, not just those required
contain user defined data. Some uses Include user 10 codes, in the normal machine operations. This is because, in system
revision numbers, or inventory control. The signature data is operation, certain events occur that may throw the logic into an
always available to the user independent of the state of the se- illegal state (power-up, line voltage glitches, brown-outs, etc.). To
curitycell. test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
NOTE: The ES is included in checksum calculations. Changing (i.e., illegal) state into the registers. Then the machine can be
the ES will alter checksum. sequenced and the outputs tested for correct next state conditions.

SECURITY CELL GAL20V8AIB devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
The security cell is provided on all GAL20V8AIB devices to pre-
necessary, approved GAL programmers capable of executing text
vent unauthorized copying of the array patterns. Once pro-
vectors perform output register preload automatically.
grammed, the circuitry enabling array is disabled, preventing
further programming or verification of the array. The cell can only
be erased by re-programming the device, so the original configu- INPUT BUFFERS
ration can never be examined once this cell is programmed. Sig-
nature data is always available to the user. GAL20V8A and GAL20V8B devices are designed with TTL level
compatible input buffers. These buffers have a characteristically
high impedance, and present a much lighter load to the driving
LATCH-UP PROTECTION logic than bipolar TTL devices.

GAL20V8AIB devices are designed with an on-board charge The GAL20V8B input and I/O pins have built-in active pull-ups.
pump to negatively bias the substrate. The negative bias is of suf- As a result, unused inputs and I/O's will float to a TTL "high" (logi-
ficient magnitude to prevent input undershoots from causing the cal "1"). In contrast, the GAL20V8A does not have active pull-
circuitry to latch. Additionally, outputs are designed with n-<:hannel ups within their input structures. Lattice recommends that all un-
pull-ups instead of the traditional p-<:hannel pull-ups to eliminate used inputs and tri-stated 110 pins for both devices be connected
any possibility of SCR induced latching. to another active input, Vce' or Ground. Doing this will tend to im-
prove noise immunity and reduce Ice for the device.
DEVICE PROGRAMMING
"lYplcallnput Pull-up Characteristic
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers. Com-
plete programming of the device takes only a few seconds. Eras-
./
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle. . L
.
u
·20
./
i ./
.5
-40

-60 ----
o 1.0 2.0
Input Voltag' (Volts)

2-42 4191.Rev.A
Semironductor
Specifications GAL20V8B
Corporation GAL20V8A
POWER-UP RESET

Vee
OV

VIH ...-......-+"',....-,-,--,.1,---------
elK VALID CLOCK SIGNAL
VIL

INTERNAL INTERNAL REGISTER


REGISTER RESET TO LOGIC 0
Q·OUTPUT

FE EDBACK/EXTERNAl EXTERNAL REGISTER


OUTPUT REGISTER OUTPUT = LOGIC 1

Circuitry within the GAL20V8A and GAL20V8B provides a reset The timing diagram for power-up is shown above. Because of
signal to all registers during power-up. All internal registers will the asynchronous nature of system power-up, some conditions
a
have their outputs set low after a specified time (t RESET ' must be met to guarantee a valid power-up reset of the
MAX). As a result, the state on the registered output pins (if they GAL20V8A and GAL20V8B. First, the Vee rise must be mono-
are enabled through OE) will always be high on power-up, regard- tonic. Second, the clock input must become a proper TIL level
less of the programmed polarity of the output pins. This feature within the specified time (tpR ' 100ns MAX). The registers will reset
can greatly simplify state machine design by providing a known within a maximum of tRESET time. As in normal system operation,
state on power-up. avoid clocking the device until all input and feedback path setup
times have been met.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN

Feedback

Vee Active Pull-up


Chait
(GAL20VSB only)
.__y. __ __
Vee
l Vref l
Control

: ESD
: Pro1ection

.i---------.------ --.'. Data


I I
':._--- _eo!
PIN
PIN Output

: ESD
j Protection
:

..
._-----------_.-
Feedback
(To Input Buffer)
Typ. Vref =3.2V Typ. Vref • 3.2V

lYpicallnput Typical Output

2-43 4/91.Rev.A
[JJ:LattiOO@ Semironductor
C<KpcratkJn
Specifications GAL20V8B
Typical Characteristics
Normalized Tpd vs Vee Normalized Teo VB Vee Normalized Tsu vs Vee

r-T-i-;:::=r=::J 1.2 1.2

I·····
1.2

--+--+-1
1--
PTH·>L
I····· II""" PTH.>L}

Il
1.1 ....... 1.1
I
1.1
I
J!
N
PTL->H FAle
PTL·>H

!. . . tr-===::j::',;';;' ]
'" '"
.......... . ......
l'
1
......
r- ..........
j ", ",
:1€
•. 9 +-----jf__--+---f----l •.9 •. 9

•.•
... 4.75 5.00 525
•.• +---f__---+---+----l ...
4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25

Supply Voltage (V) Supply VoHage (V) Supply VoHage (V)

Normalized Tpd vs Temp Normalized Teo vs Temp Normalized Tsu vs Temp

1.3 1.3 1.4

1.2 ••••. PTH.>L I 1.2 1.3 ......... PTH->L l /


,;;:2" o L
/ .." ,
"0
--PTL.>HI 1.2
1.1
.,;.;- " --PTL.>HJ
-g / -g 1l 1.1
1

V §
1
r-- ,.'

. ........ . /
...
1
0.9 ", 0.9

... ..• :z 0.9

I-'
L
0.7
·55 2.
Temperature (deg. C)
9. 12'
•.7
.s. 25

Temperature (deg. C)
. 125
•.7
.s. 25 . 12.

Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Teo vs # of Outputs


Switching Switching

p I-"""
_ -0.5 ,.'
,.'
V
] : -0.5
.'
.. , ,.'
c:.:- P
g " V
V
... f/"
"
"0
-, ./ -1
./
13
-1.5
V 0 _ 1.5
V ••••. RISE}

--FAeL --FALL

-2 -2

Number of Outputs Number of Outputs

Delta Tpd vs Output Loading Delta Teo vs Output Loading

,.
10

j..... RISEl

/'
••••. RISE I
/'
£.6 --FALLI
g6 --FALLl
,
V o
4 -:-;.,
J;! /.
/. 2

/- " /.
-2 -2

50 100 150 200 250 300 50 tOO 150 200 250 300

Output Loading (pF) Output Loading (pF)

2-44 4/91.Rev.A
!JJ
.l.J
:LattiOO@
Semiconductor
Corporation
Specifications GAL20V8B
Typical Characteristics ,

Volvs 101 Vohvs Ioh Vohvs loh


at
/ ,-
- ---
.......... 4.25

---
O.7e,

:E L t-.
r- :E 4.00

---
0.5 .J:

./
/' :fZ
3.75
0.25
,/

L 3.50
0.00 20.00 40.00 60.00 80.00 100.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0.00 1.00 2.00 3.00 4.00

101 (mA) 10h(mA) 10h(mA)

Normalized Icc vs Vee Normalized Icc vs Temp Normalized Icc vs Freq.

1.20 1.20 1.30

"""- .......... 1.20

--
1.10 1.10
,,/'
11 V 11 L
""- 1.10

I""
'"C
al
] 1.00
al
] 1.00
/r'
E 1.00

0.90 0.90
:!i!
0.90
V
,.0
4.50 4.75 5.00

Supply Vottage (V)


5.25 5.50
0.80
25

Temperature (deg. C)
75

'"
100 125 25 50

Frequency (MHz)
75 100

Delta Icc vs Yin (1 input) ·Input Clamp (Vlk)

10
20
/
30
/
<-40 /
I\ .§."
60 /
J \ 70
80
/
/
"-
J r--.. 90
1/
100
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 -2.00 -1.50 -1.00 -0.150 0.00

VineY) Vik(V)

2-45 4/91.Rev.A
[JJ
.l.J
LB.tuce
Semlronductor
CorporaUon
e
Specifications GAL20V8A
Typical Characteristics
Nonnalized Tpd vs. Vee Normalized Tsu va. Vee Normalized Tco YS. Vee

- - -- ----- !
...
'.0
u
- -
.,... 4.75 &.00
Supply Voltage (V)
IJIi . .. o
. ... ..7$ 1.00 6.25
Supply Voltage (V)
.... 4.71 ..00
Supply Voltage (V)
... ....

Normalized Tpd VS. Temperature NonnaJized Tsu VB. Temperlllure Normalized Teo YS. Te"ll8rature
• .3 '.3

.,..,.... 1.2
.,..,.... '.2
... ., .---
V "' "'
"&. •.• :.
f!!. 8 •.•
I-
1.0 i.!::! '.0
/ I- /
/ / L
I
16
O.t
/
iii

Z
E
0
u
/
u

... L
V
0.8 0 ..

/ / /'
.
0.7 0.7

0.6 0.6 '.1


-50 -25 0 25 .. 75 ,00 '25 ..5() .a 0 2S 50 75 100 125
Ambient Temperature (OC) Ambient Temperlllure (OC) Ambient Te"ll8rature (OC)

Delta Tpd vs. Output Loading Nonnalized Icc YS. Vee


Normalized Tpd VI. , or OUlPU11 Swhchlng
Il

/
1.00

/ '.2

"8.
l-
0.18

V
/
-.E-.. . /
/ !l
'0
... ./

I .... ./ X. i '.0
/
I-
§

,V
D.t

.... V" Z V
/ 0"
V /'
0.12

'oIOUIPUlI

IOLVS. VOL
100 200
Output Loading Capacitance (pI)

ICIt vs. VOH


300
- 0.7
'.50 us 5.00

Supply Voltage (V)

Normalized Icc YS' Temperature


5.50

-
250 ·.10
13

200 u

---r-. - -- r---.. . . .
<" .50 / <"
·'00
....... .!l
1.1

.§.
...
.2100
)V §
§.
"-
.........
i
..E ...
50
/ ·10

:---.....
V
OJ

o
o
"-.. '.7
...... IH 50 7'$ 100 12$

VOL (V) VCIt(V) Ambient Temperature (OC)

2-46 4/91.Rev.A
a;J
,lJ
tattice®
Semiconductor
Corporation
GAL 18V10
High Performance EZCMOS PLD
Generic Array Logic™

FEATURES FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE ElCMOS- TECHNOLOGY


- 15 ns Maximum Propagation Delay IICLK

=
- Fmax 62.5 MHz
I/OIQ
-10ns Maximum from Clock Input to Data OUtput
- TIL Compatible 16 mA Outputs
- UHraMOS- Advanced CMOS Technology INPUT
I/O/a
• LOW POWER CMOS
- 75 mA lYplcallcc
I/OIQ
• ACTIVE PULL-UPS ON ALL PINS INPUT

• EI CELL TECHNOLOGY
- Reconflgurable logic I/OIQ
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields INPUT
- High Speed Electrical Erasure (SOms) I/OIQ
- 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS INPUT I/OIQ
- Uses Standard 22V10 Macrocells
- Maximum FlexlbllHy for Complex logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS 110/0
-100% Functional TestabllHy INPUT

• APPLICATIONS INCLUDE: IIO/Q


- DMA Control
- State Machine Control
INPUT
- High Speed Graphics Processing I/OIQ
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION I/OIQ
INPUT

DESCRIPTION
PACKAGE DIAGRAMS
The GAL18V1 0, at 15 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (1:2) floating gate technology to provide the highest perform-
ance 20 pin PLD available on the market. CMOS circuitry al-
lows the GAL18V1 0 to consume much less power when com- PLCC DIP
pared to its bipolar counterparts. The E2 technology offers high
I/CLK Vee
speed (50ms) erase times, providing the ability to reprogram or
I WCLX v.. IiOIQ
reconfigure the device quickly and efficiently. I/OIQ
2 20
By building on the popular 22V1 0 architecture, the GAL 18V1 0 IiOIQ IIO/Q
allows the designer to be immediately productive, eliminating the
learning curve. The generic architecture provides maximum de- IIO/Q I/O/Q
sign flexibility by allowing the Output Logic Macrocell (OLMC) GAL18V10 IiOIQ I/O/a
to be configured by the user. The GAL18V1 0 OLMC is fully com-
Top View IIO/Q
patible with the OLMC in standard bipolar and CMOS 22V1 0 de- IiOIQ

vices. IiOIQ
IIO/Q

Unique test circuitry and reprogram mabie cells allow complete 110/0
AC, DC, and functional testing during manufacture. As a result, IiOIQ CIIID IIO/Q IIO/Q IiOIQ
I/O/a IIO/Q
LATIICE is able to guarantee 100% field programmability and
functionality of all GAL- products. LATIICE also guarantees 100 aND
erase/rewrite cycles and data retention in excess of 20 years.

copyright 01991 Lattice Semiconductor Corp. GAL and UnraMOS are ragiltered trademarlca of Lattice Semiconductor Corp. Generic Array Logic and E'CMOS are tr&damar"" of Lattice
Semiconductor Corp. The opecllcatlons herein are subject to change wIthou1 notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. April 1991.Rev.A
Tel. (503) 681-01180r 1-800-FASTGAL; FAX (503) 681-3037
2-47
[jJ
'L Lattire Semironductor
Corporation
4D

Specifications GAL 18V1 0

GAL18V10 ORDERING INFORMATION

Commercial Grade Specifications


Tpd (ns) Tsu (ns) Teo (ns) Icc (mA) Ordering # Package
15 10 10 115 GAL 18V10-15LP 20-Pin Plastic DIP
115 GAL 18V10-15LJ 20-Lead PLCC
20 12 12 115 GAL18V10-20LP 20-Pin Plastic DIP
115 GAL18V10-20LJ 20-Lead PLCC

Industrial Grade Specifications


Tpd (ns) Tsu (ns) Teo (ns) Icc (mA) Ordering # Package
20 12 12 125 GAL18V10-20LPI 20-Pin Plastic DIP
125 GAL18V10-20LJI 20-Lead PLCC

PART NUMBER DESCRIPTION

xxxxxxxx - xx. X X X

GAL18V10 Device Name

Speed (ns) L...-_ _ _ Grade Blank = Commercial


I = Industrial

L = Low Power Power L...-_ _ _ _ Package P = Plastic DIP


J = PLCC

2-48 4J91.Rev.A
[JJ'LllttiooQP
SeIIlironductor
Corporation
Specifications GAL 18V1 0

OUTPUT LOGIC MACROCELL (OLMC)


The GAL 18V1 0 has a variable number of product terms per The GAL18V1 0 has a product term for Asynchronous Reset (AR)
OLMC. Of the ten available OLMCs, two OLMCs have access and a product term for Synchronous Preset (SP). These two
to ten product terms (pins 14 and 15), and the other eight OLMCs product terms are common to all registered OLMCs. The Asyn-
have eight product terms each. In addition to the product terms chronous Reset sets all registered outputs to zero any time this
available for logic, each OLMC has an additional product-term dedicated product term is asserted. The Synchronous Preset sets
dedicated to output enable control. all registers to a logic one on the rising edge of the next clock
pulse after this product term is asserted.
The output polarity of each OLMC can be individually pro-
grammed to be true or inverting, in either combinatorial or reg- NOTE: The AR and SP product terms will force the Q output of
istered mode. This allows each output to be individually config- the flip-flop into the same state regardless of the polarity of the
gured as either active high or active low. output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.

AR

o
4 TO 1
Q
MUX

SP

2 TO 1 I - - - - - - - - - - - - - l
MUX

GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS


Each of the Macrocells of the GAL 18V1 0 has two primary func- NOTE: In registered mode, the feedback is from the /0 output
tional modes: registered, and combinatorial 110. The modes and of the register, and not from the pin; therefore, a pin defined as
the output polarity are set by two bits (SO and S 1), which are registered is an output only, and cannot be used for dynamic
normally controlled by the logic compiler. Each of these two pri- 110, as can the combinatorial pins.
mary modes, and the bit settings required to enable them, are
described below and on the the following page. COMBINATORIAL //0
In combinatorial mode the pin associated with an individual OLMC
REGISTERED is driven by the output of the sum term gate. Logic polarity of the
In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the
OLMC is driven by the 0 output of that OLMC's D-type flip-flop. output buffer drive either true (active high) or inverted (active low).
Logic polarity of the output signal at the pin may be selected by Output tri-state control is available as an individual product-term
specifying that the output buffer drive either true (active high) for each output, and may be individually set by the compiler as
or inverted (active low). Output tri-state control is available as either "on" (dedicated output), "off" (dedicated input), or "product-
an individual product-term for each OLMC, and can therefore term driven" (dynamic 110). Feedback into the AND array is from
be defined by a logic equation. The D flip-flop's /0 output is fed the pin side of the output enable buffer. Both polarities (true and
back into the AND array, with both the true and complement of inverted) of the pin are fed back into the AND array.
the feedback available as inputs to the AND array.

2-49 4/91.Rev.A
[JJLatticeSemioonductor
Corporation
GP

Specifications GAL 18V1 0

REGISTERED MODE

AR AR

o Q o Q

SP SP

ACTIVE LOW ACTIVE HIGH

So = 0 So = 1

COMBINATORIAL MODE

ACTIVE LOW ACTIVE HIGH

So = 0 So = 1
=
S, 1 =
S, 1

2-50 4/91.Rev.A
[J
.l.t
tl1ttiOO®
Semiconductor
Corporation
Specifications GAL 18V1 0

GAL 18V10 LOGIC DIAGRAM / JEDEC FUSE MAP

0 4
• '2 .
, 20 24 28 32

0000 AS'lNCHRONOUS RESET


(TO.AU. REGISTERS)
0036
OlMC 19

0324
= 3457
19

0360
:§:::t -OLMC '8 J 18

2
0648

!LJ
'-----

4r}J
0684

17
3
0972

'008
=tiP
..., 5'

-OLMC '8
=.>-- J 16
'296 0-
5'
4
- ""'"
'332 -OLMC '7
J 15

5
'892 0-

-
....
'728
-0l.MC ,.
so
1 14
:R: 3488
2088 5'
. .67

6
2'"
-OLMC 13
=>-- J
2412
.,
..88

. .69
13

7 -
2448
-
=- OLMC 12 J 12
2736
:B:
.,
347'
8 -
2m
jW.4C11l J 11

liP
3080
J::8""
3473

J
3096

OLMC.
t:l--I
9
3384

. .75

3420 SYNCHRONOUS PRESET


(TO Al..L REGISTERS)

3476,3477 ... Electronic Signature ... 3538,3539

·· .,
2-51 4191.Rev.A
[JJ
1..1
'Lattlce
Semironductor
Corporation
qp
Specifications GAL 18V1 0
Commercial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING COND_

Supply voltage Vee ........................................ -0.5 to +7V Commercial Devices:


Input voltage applied ............................ -2.5 to Vee +1.0V Ambient Temperature (TA) ............................. 0 to +75°C
Off-state output voltage applied ........... -2.5 to Vee +1.0V Supply voltage (Vee)
Storage Temperature .................................. -65 to 150°C with Respect to Ground ..................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings' may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP" MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - Vcc+1 V

IlL' Inp'Jt or 1/0 Low Leakage Current OV S Y,N S V,L (MAX.) - - -100

IiH Input or 1/0 High Leakage Current 3.5V :;; Y,N :;; Vee - - 10

VOL Output Low Voltage MAX. Yin ., V,L or V,H - - 0.5 V

VOH Output High Voltage 10H= MAX. Yin = V,L or V,H 2.4 - - V

10L Low Level Output Current - - 16 mA

10H High Level Output Current - - -3.2 mA

los2 Output Short Circuit Current Vee =5V VOUT = 0.5V TA = 25·C -50 - -135 mA
-
Icc Operating Power Supply Current V,L= 0.5V V,H=3.0V - 75 115 mA
ftoggle =15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 ·C

CAPACITANCE (TA =25°C, f = 1.0 MHz)


SYMBOL PARAMETER MAXIMUM' UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vcc = 5.0V, V, = 2.0V

ClIO 110 Capacitance 10 pF Vee = 5.0V, VIJO - 2.0V


"Guaranteed but not 100% tested.

2-52 4/91.Rev.A
Specifications GAL 1 BV1 0
Semiconductor
Corporation Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

TEST
-15 -20
PARAMETER DESCRIPTION UNITS
COND.' MIN. MAX. MIN. MAX.
tpd 1 Input or I/O to Combinatorial Output - 15 - 20 ns

tco 1 Clock to Output Delay - 10 - 12 ns

tcf2 - Clock to Feedback Delay - 7 - 10 ns

tsu - Setup Time, Input or Feedback before Clocki 10 - 12 - ns

th - Hold Time, Input or Feedback after Clocki 0 - 0 - ns


1 Maximum Clock Frequency with 50 - 41.6 - MHz
External Feedback, 1/(tsu +tco)
fmax 3 1 Maximum Clock Frequency with 58.8 - 45.4 - MHz
Internal Feedback, 1/(tsu + tet)
1 Maximum Clock Frequency with 62.5 - 62.5 - MHz
No Feedback
twh4 - Clock Pulse Duration, High 8 - 8 - ns
twl4 - Clock Pulse Duration, Low 8 - 8 - ns

ten 2 Input or 110 to Output Enabled - 15 - 20 nli


tdis 3 Input or 110 to Output Disabled - 15 - 20 ns

tar 1 Input or 110 to Asynchronous Reset of Register - 20 - 20 ns

tarw - Asynchronous Reset Pulse Duration 10 - 15 - ns

tarr - Asynchronous Reset to Clocki Recovery Time 15 - 15 - ns

tspr - Synchronous Preset to Clocki Recovery Time 10 - 12 - ns

) Refer to Switching Test Conditions section.


) Calculated from fmax with internal feedback. Refer to fmax Description section.
) Refer to fmax Description section.
) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-53 4191.Rev.A
rIJ Lature
SemiaHlducwr
CorporaUOn
qp
Specifications GAL 18V1 0
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo

Supply voHage V co ........................................ -0.5 to + 7V Industrial Devices:


Input voltage applied .•.....•.......•........•.•. -2.5 to Vee +1.0V Ambient Temperature (TA) ..........•..•.......•...... -40 to 85°C
Off·state output voltage applied .........•. -2.5 to Vee + 1.0V Supply voltage (Vee)
Storage Temperature •................•.............•.. -65 to 150°C with Respect to Ground .................•..•. +4.50 to +5.50V
Ambient Temperature with
Power Applied ................................•......•. -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.' MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - Vcc+1 V

IlL' Input or 110 Low Leakage Current OV S Y,N S V,l (MAX.) - - -100 !LA
IIH Input or VO High Leakage Current 3.SV S Y,N S Vee - - 10 !LA
VOL Output Low Voltage 10l .. MAX. Yin =V,l or V,H - - 0.5 V

VOH Output High Voltage 10H= MAX. Yin = V,l or V,H 2.4 - - V

10L Low Level Output Current - - 16 mA

10H High Level Output Current - - -3.2 mA

1052 Output Short Circuit Current Vee = SV VOUT = O.SV TA= 25°C -50 - -135 mA

Icc Operating Power Supply Current V,l= O.SV V,H = 3.0V - 90 125 mA
floggle =15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = SV and TA = 25°C

CAPACITANCE (TA = 25°C, f = 1.0 MHz)


SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee = S.OV. V, =2.0V


ClIO I/O Capacitance 10 pF Vee = S.OV. Vue = 2.0V
*Guaranteed but not 100% tested.

2-54
Specifications GAL 18V1 0
Semiconductor
Corporation Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-20
TEST DESCRIPTION
PARAMETER UNITS
COND.' MIN. MAX.
tpd 1 Input or I/O to Combinatorial Output - 20 ns

tco 1 Clock to Output Delay - 12 ns


tcf2 - Clock to Feedback Delay - 10 ns

tsu - Setup lime, Input or Feedback before Clocki 12 - ns

th - Hold lime, Input or Feedback alter Clocki 0 - ns


1 Maximum Clock Frequency with 41.6 - MHz
External Feedback, 1/(tsu + tco)

fmax 3 1 Maximum Clock Frequency with 45.4 - MHz


Internal Feedback, 1/(tsu + tcf)

1 Maximum Clock Frequency with 62.5 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 8 - ns


twl4 - Clock Pulse Duration, Low 8 - ns

ten 2 Input or I/O to Output Enabled - 20 ns


tdis 3 Input or 110 to Output Disabled - 20 ns

tar 1 Input or 110 to Asynchronous Reset of Register - 25 ns

tarw - Asynchronous Reset Pulse Duration 15 - ns

tarr - Asynchronous Reset to Clocki Recovery Time 15 - ns

tspr - Synchronous Preset to Clocki Recovery lime 12 - ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-55 4/91.Rev.A
GD

.l.J CorporaUon Specifications GAL 18V1 0

SWITCHING WAVEFORMS

INPUT 01
110 FEEDBACK \\\\\\\ INNT
INPUT or
110 FEEDBACK

ClK
COMBINATORIAL
OUTPUT
: REGISTERED
OUTPUT
Combinatorial Output

Reg Istered Output

INPUT 01
110 FEEDBACK

OUTPUT
ClK

Input or I/O to Output Enable/Disable


REGISTERED
FEEDBACK

fmax with Feedback

twl

ClK

Clock Width
INPUT 01
110 FEEDBACK
DRIVING SP

INPUT or

tc0m=
VOFEEDBACK CLK
DRIVINGAR

REGISTERED
OUTPUT
REGISTERED
OUTPUT \\
Synchronous Preset

ClK

Asynchronous Reset

2-56 4/91.Rev.A
J,.,J SemironduGtor Specifications GAL 18V1 0 I
Corporation
I,
fmax DESCRIPTIONS

lOGIC
ARRAY
elK
, _____ . ___________ .. ___________ .... -0--------.-

REGISTER
roo
elK
-------------------------------

REGISTER
------------:

- !

1oI1..1----lou---+.I.....I - - - - .,------------------ ... ---------------.-._----_ ...


fmax with External Feedback 1/(1su+tco)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with Internal Feedback 1/(1su+tcf)

elK Note: tcf is a calculated value, derived by sub-


,.. -------------------------------- ------------,. tracting tsu from the period of fmax w/internal
··· .. feedback (tet = 1lfmax - tsu). The value of tet
is used primarily when calculating the delay from
lOGIC clocking a register to a combinatorial output
REGISTER
ARRAY f--+-"-' (through registered feedback), as shown above.
For example, the timing from clock to a com-
·---------._._-------_ ... _---_._---------.-------. binatorial output is equal to tet + tpd.

fmax With No Feedback


Note: fmax with no feedback may be
less than 1ltwh + twl. This is to allow for
a clock duty cycle of other than 50%.

SWITCHING TEST CONDITIONS

Input Pulse Levels GNDt03.0V +5V


Input Rise and Fall Times 3ns 10%-90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V FROM OUTPUT (O/Q) TEST POINT
Output Load See Figure UNDER TEST
3-state levels are measured 0.5V from steady-state active Cl
level.

Output Load Conditions (see figure)


Test Condition Rl R2 CL

1 300n 390n 50pF CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE


2 Active High 00 390n 50pF
Active Low 300n 390n 50pF
3 Active High 00 390n 5pF
Active Low 300n 390n 5pF

2-57 4!91.Rev.A
Specifications GAL 18V1 0

ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD

An electronic signature (ES) is provided in every GAL 18Vl0 When testing state machine designs, all possible states and state
device. It contains 64 bits of reprogram mabie memory that can transitions must be verified in the design, not just those required
contain user-defined data. Some uses include user 10 codes, in the normal machine operations. This is because certain events
revision numbers, or inventory control. The signature data is may occur during system operation that throw the logic into an
always available to the user independent of the state of the illegal state (power-up, line voltage glitches, brown-outs, etc.).
security cell. To test a design for proper treatment of these conditions, a way
must be provided to break the feedback paths, and force any
desired (i.e., illegal) state into the registers. Then the machine
SECURITY CELL can be sequenced and the outputs tested for correct next state
conditions.
A security cell is provided in every GAL18Vl 0 device to prevent
unauthorized copying of the array patterns. Once programmed, The GAL 18Vl 0 device includes circuitry that allows each reg-
this cell prevents further read access to the functional bits in the istered output to be synchronously set either high or low. Thus,
device. This cell can only be erased by re-programming the any present state condition can be forced for test sequencing.
device, so the original configuration can never be examined once If necessary, approved GAL programmers capable of execut-·
this cell is programmed. The Electronic Signature is always avail- ing test vectors perform output register preload automatically.
able to the user, regardless of the state of this control cell.

INPUT BUFFERS
LATCH-UP PROTECTION
GAL18Vl 0 devices are designed with TIL level compatible input
GAL18Vl 0 devices are designed with an on-board charge pump buffers. These buffers have a characteristically high impedance,
to negatively bias the substrate. The negative bias is of sufficient and present a much lighter load to the driving logic than bipo-
magnitude to prevent input undershoots from causing the cir- lar TIL devices.
cuitry to latch. Additionally, outputs are designed with n-channel
pullups instead of the traditional p-channel pullups to eliminate The input and 110 pins also have built-in active pull-ups. As a
any possibility of seR induced latching. result, floating inputs will float to a TIL high (logic t). However,
Lattice recommends that all unused inputs and tri-stated 110 pins
be connected to an adjacent active input, Vcc, or ground. Do-
ing so will tend to improve noise immunity and reduce Icc for the
DEVICE PROGRAMMING device.

GAL devices are programmed using a Lattice-approved Logic


Programmer, available from a number of manufacturers (see the typical Input Current
the GAL Development Tools section). Complete programming
of the device takes only a few seconds. Erasing of the device
is transparent to the user, and is done automatically as part of .:!. /'
the programming cycle. ;;;
·20
./
"
u
./
/'
... ·40 ...-
= ·60
o 1.0 2.0 3.0 4.0 5.0
Input Valtage (Va Its)

2-58 4191.Rev.A
[JJ
'L LaWOOQP
Semiconducwr Specifications GAL 18V1 0

..,
Corporation

POWER-UP RESET

Vee
OV
nJ.
i
i

V IH t'"TT"T"mCT""T-rTT""\Ir---------
ClK VALID ClOCK SIGNAL
VIL

INTERNAL INTERNAL REGISTER


REGISTER RESET TO LOGIC 0
Q·OUTPUT

ACTIVE lOW
OUTPUT REGISTER

ACTIVE HIGH
OUTPUT REGISTER

Circuitry within the GAL 18V1 0 provides a reset signal to all must be met to guarantee a valid power-up reset of the
registers during power-up. All internal registers will have theira GAL18V1 o. First, the VIX rise must be monotonic. Second, the
outputs set low after a specified time (t IIESET ' 45I1S MAX). This clock input must become a proper TTL level within the specified
feature can greatly simplify state machine design by providing time (tpR ·, 100ns MAX). The registers will reset within a maxi-
a known state on power-up. mum of tRESET time. As in normal system operation, avoid clocking
the device until all input and feedback path setup times have been
The timing diagram for power-up is shown above. Because of met.
the asynchronous nature of system power-up, some conditions

INPUT/OUTPUT EQUIVALENT SCHEMATICS

outPut _ _ _
Dltl V I PIN

Feedblck ..
Vee AClive Pull·up
Circuh
..:r.....
i Vraf i
Tri·Stata (VroITypicol.UV)

ll l;
Control

: :
Output t..... j PIN
Dill
PIN

Feedback
(To Input

Input Output

2-59 4191.Rev.A
'L Sem/conductor
Corporation
Specifications GAL 18V1 0
Typical Characteristics
Normalized Tpd vs. Vcr; Normalized Tsu vs. Vcr; Normalized Teo VI. Voc
•.3,....---r----.----r--...., 1.3

1.2+-_ _ -+-__+ __-+__-i 1.2

). =
X'''
F
1,
..
b-
- - --
iil
I-
) ,
1.1 :.r:---+----+---+---;
•••••••••

0.9-1---+--+---+----l
........ ......
.......... - 81.1
l-
i
,!!!

1

0.'
... - r
I·····
PT H·.L
PT L->H
O•• .•;Hlr
II·····PTH .• I L
0.1
0.7
4,75 5 5.25 0.7L---l...--JL==4==::..J 0.7
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
Supply Vollage (V)
Sl4JPly Voltage (V) Supply VoI1age (V)

,.. Normalized Tpd va. Temperalure


... Normalized Tou VI. Temperalure ,.. Normalized Teo vs. Temperature

'.2 V '.2
......
./V
/'
::::I 1.1 L 8 ,.• k--'"
./ V {!
lL
I-
] , L
V"

./ V 1V 0.• ./ V 10.
z
I L
V-

0.1 V 0.1 0.1 V


0.7 0.7 o.'7
-50 .25 0 25 50 75 100 t25 ·55 -25 0 25 10 71 tOO 125 -55 .zs 0 25 so 75 100 125
Ambient Temperature (OC) Ambient Temperalure (OC) Ambient Temperature (OC)

Della Tpd VI. II 01 Outputs Swilching


DeRa Tpd vs. Output Lolding Normalized Ia: VI. Va:
.0 '.3

V v /' 1.2

- / 10'
., -'" ./ ...
V 1 • IL:
/ lZ
o 0.'

/ 0 ..

.......
/I 01 OIAputs
...... ..... .V 100 200
OUlpui Loalng Capacitance (pf)
300
- 0.7
4.5 .US 5
Supply VoRage (V)
525 5.5

... IOLVS. VOL


·'50 ...-_ _-.-_'O_H_VS.-.V_O_H_-r_ _....,
'.3
Normalized Icc va. Tempereture

200 .... .....".........


_"..T........

<.50 .",-- -- ·'00


"-.
..
1
!.
V
oJ
.2'"
50 /
! ............
- ....
.....
V 2

0.7
.u .zs 0 IS 10 71 100 U!&
VOL (V) VOH(V) Ambient Temperature (OC)

2-60 4J91.Rev.A
fIJ
J.."
Lattice
Semiconductor
Corporation
®
GAL22V10B
GAL22V10
High Performance E2CMOS PLD
FEATURES FUNCTIONAL BLOCK DIAGRAM
• HIGH PERFORMANCE E2CMOS·TECHNOLOGY
IICLK I
- 10 ns Maximum Propagation Delay I'

- Fmax =105 MHz 1I0IO


- 7 ns Maximum from Clock Input to Data Output INPUT
- TTL Compatible 16 mA Outputs
- UHraMOS· Advanced CMOS Technology 11010
INPUT
• ACTIVE PULL·UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES INPUT 1I0I0
- Fully Function/Fuse·Map/Parametrlc Compatible
with Bipolar and UVCMOS 22V10 Devices
INPUT 1/010
• 50% REDUCTION IN POWER VERSUS BIPOLAR
• E2 CELL TECHNOLOGY
INPUT 1/010
- Reconflgurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields INPUT 1/010
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
INPUT
• TEN OUTPUT LOGIC MACROCELLS 11010
- Maximum Flexibility for Complex Logic Designs
INPUT
• PRELOAD AND POWER·ON RESET OF REGISTERS 11010
- 100% Functional Testability
INPUT
• APPLICATIONS INCLUDE: 1/010
- DMA Control
- State Machine Control INPUT
- High Speed Graphics Processing 1/010
- Standard Logic Speed Upgrade INPUT
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION
PACKAGE DIAGRAMS
The GAL22V1 OB, at 10ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest perform- DIP
ance available of any 22V10 device on the market. CMOS cir-
PLCC
cuitry allows the GAL22V1 0 to consume much less power when
Vcc
compared to bipolar 22Vl 0 devices. E2 technology offers high
IIO/Q
speed «lOOms) erase times, providing the ability to reprogram 0
or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
!!
.. IIOIQ
IIO/Q
IIO/Q
allowing the Output Logic Macrocell (OLMC) to be configured by IIOIQ IIO/Q
the user; The GAL22V1 0 is fully function"use map/parametric IIOIQ IIO/Q
Me GAL22V10/B
compatible with standard bipolar and CMOS 22Vl0 devices. Me
IIO/Q
IIOIQ
Top View
Unique test circuitry and reprogram mabie cells allow complete IIOIQ
IIO/Q
AC, DC, and functional testing during manufacture. As a result, IIOIQ IIO/Q
LATTICE is able to guarantee 100% field programmability and IIO/Q
functionality of all GAL· products. LATTICE also guarantees 100 K !1 IIO/Q
erase/rewrite cycles and data retention in excess of 20 years.

Copyright CI991 Lattice Semiconductor Corp. GAL. E'CMOS and UhraMOS are registered trademarks of Lattice Semicor1ductor Corp. Generic Array logic Is a trademark of Lattice Seniconduc·
tor Corp. The apecllcationa herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. April 1991.Rev.A
Tel. (503) 681'()118 or 1-800-FASTGAL; FAX (503) 681-3037
2·61
fJJ
1..J
tatticeGl
Semiconductor
Corporation
Specifications GAL22V10B
GAL22V10
GAL22V10/B ORDERING INFORMATION

Commercial Grade Specifications


Tpd (ns) Tsu (ns) Teo (ns) Icc (rnA) Ordering # Package
10 7 7 130 GAL22V1 OB-1 OLP 24-Pin Plastic DIP
130 GAL22V10B-10W 28-Lead PLCC
15 10 8 130 GAL22Vl0B-15LP 24-Pin Plastic DIP
130 GAL22V10B-15W 28-Lead PLCC
15 12 8 130 GAL22V10-15LP 24-Pin Plastic DIP
130 GAL22V10-15W 28-Lead PLCC
25 15 15 130 GAL22V10-25LP 24-Pin Plastic DIP
130 GAL22V10-25W 28-Lead PLCC

Industrial Grade Specifications


Tpd (ns) Tsu (ns) Tco (ns) Icc (rnA) Ordering # Package
15 10 8 150 GAL22V10B-15LPI 24-Pin Plastic DIP
150 GAL22V10B-15LJI 28-Lead PLCC

20 14 10 150 GAL22V10-20LPI 24-Pin Plastic DIP


150 GAL22V10-20LJI 28-Lead PLCC
25 15 15 150 GAL22V10-25LPI 24-Pin Plastic DIP
150 GAL22Vl0-25LJI 28-Lead PLCC

PART NUMBER DESCRIPTION

xxxxxxxx - xx X XX

GAL22V10
Device Name -
GAL22V10B

Speed (ns) ' - - - - - - Grade Blank = Commercial


I = Industrial

L = Low Power Power _ _ _ _ _ _ _ _---1 1...------ Package P = Plastic DIP


J= PLCC

2-62 4191.Rev.A
[JJ
1.J
LatticeGD
Semiconducwr
Corporation
Specifications GAL22V10B
GAL22V10
OUTPUT lOGIC MACROCEll (OlMC)
The GAL22V10 has a variable number of product terms per The GAl22V1 0 has a product term for Asynchronous Reset (AR)
OLMC. Of the ten available OLMes, two OLMCs have access to and a product term for Synchronous Preset (SP). These two
eight product terms (pins 14 and 23), two have ten product terms product terms are common to all registered OLMCs. The Asyn-
(pins 15 and 22), two have twelve product terms (pins 16 and 21), chronous Reset sets all registers to zero any time this dedicated
two have fourteen product terms (pins 17 and 20), and two product term is asserted. The Synchronous Preset sets all reg-
OLMCs have sixteen product terms (pins 18 and 19). In addition isters to a logic one on the rising edge of the next clock pulse after
to the product terms available for logic, each OLMC has an ad- this product term is asserted.
ditional product-term dedicated to output enable control.
NOTE: The AR and SP product terms will force the a output of
The output polarity of each OLMC can be individually programmed the flip-flop into the same state regardless of the polarity of the
to be true or inverting, in either combinatorial or registered mode. output. Therefore, a reset operation, which sets the register output
This allows each output to be individually configured as either to a zero, may result in either a high or low at the output pin,
active high or active low. depending on the pin polarity chosen.

AR

o
4 TO t
a MUX

SP

2 TO t ( -_ _ _ _ _ _ _ _ _ _....1

MUX

GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT lOGIC MACROCEll CONFIGURATIONS


Each of the Macrocells of the GAl22V10 has two primary NOTE: In registered mode, the feedback is from the 10 output of
functional modes: registered, and combinatorialI/O. The modes the register, and not from the pin; therefore, a pin defined as
and the output polarity are set by two bits (SO and S1), which are registered is an output only, and cannot be used for dynamic
normally controlled by the logic compiler. Each of these two 110, as can the combinatorial pins.
primary modes, and the bit settings required to enable them, are
described below and on the following page. COMBINATORIAL 110
In combinatorial mode the pin associated with an individual OLMC
REGISTERED is driven by the output of the sum term gate. Logic polarity of the
In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the
OLMC is driven by the a output of that OLMC's Ootype flip-flop. output buffer drive either true (active high) or inverted (active low).
Logic polarity of the output signal at the pin may be selected by Output tri-state control is available as an individual product-term
specifying that the output buffer drive either true (active high) or for each output, and may be individually set by the compiler as
inverted (active low). Output tri-state control Is available as an either "on" (dedicated output), "off" (dedicated input), or "product-
individual product-term for each OLMC, and can therefore be term driven" (dynamic I/O). Feedback into the AND array is from
defined by a logic equation. The 0 flip-flop's /Q output is fed back the pin side of the output enable buffer. Both polarities (true and
into the AND array, with both the true and complement of the inverted) of the pin are fed back into the AND array.
feedback available as inputs to the AND array.

2-63 4191.Rev.A
U
..l..J lLatlioo°
SemiconducUJr
Corporation
Specifications GAL22V10S
GAL22V10
REGISTERED MODE

AR AR

o Q o Q

o
SP SP

ACTIVE LOW ACTIVE HIGH

5.=0 5 0 =1
5, =0 5, =0

COMBINATORIAL MODE

ACTIVE LOW ACTIVE HIGH

50 = 0 50 =1
5, = 1 5, = 1

2-64 4/91.Rev.A
Specifications GAL22V10B
Semiconductor
Corporation GAL22V10

GAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP


DIP (PLCC) Package Pinouts
1 (2)

::
ASYNCHRONOUS RESET
ITO ALL AEQlSTERS)

1
.... 23 (27)

!WI'
22 (26)
.... .."
2 (3)
0124

... 1 21 (25)

LJ
..II
51
1"; OIlS

3 (4) '--
1416

ra:;o;o 1
:'LJ
20(24)

2";!
..,.
51

J-=
4 (5) '--

J
:"U
51
19(23)

5(6) 1--
" .
:..'"' U1
51
18 (21)

"'"
6(7)
.
,,
J
......, 17 (20)

7 (9)
"'.
i=1 S1
5." U
-
43"
fi a;c;; 1
so,
... 16 (19)
.... 81
LJ
-
...3
IIII 1111 lit 1111
8(10)
-
J 15(18)

9 (11)
5'"
....
-t!U
".; =I'B
1 14 (17)

10(12) ."
11 (13) 13(16)

2-65 4/91.Rev.A
jllLattJoo"
.l...I Semi(X)lJductor
Corporation
Specifications GAL22V10B
Commercial

ABSOLUTE MAXIMUM RATINGS(l) RECOMMENDED OPERATING CONDo


Supply voltage Vee ........................................ -0.5 to +7V Commercial Devices:
Ambient Temperature (TA ) ••••.••••••••••••••••.••••••• 0 to +75°C
Input voltage applied ............................ -2.5 to Vee + 1.0V
Supply voltage (Vee)
Off-state output voltage applied ........... -2.5 to Vee + 1.0V
with Respect to Ground ...................... +4.75 to +5.25V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stres:: only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.' MAX. UNITS

VIL Input Low Voltage Vss -0.5 - 0.8 V

VIH Input High Voltage 2.0 - Vcc+l V

IlL' Input or 1/0 Low Leakage Current OV:s; V,N:S; V,L (MAX.) - - -100 J.lA
I
IIH Input or 110 High Leakage Current 3.5V:s; Y,N :s; Vcc - - 10 J.lA

VOL Output Low Voltage 10L = MAX. Yin = V,L or V,H - - 0.5 V

VOH Output High Voltage 10H = MAX. Yin = V,L or V,H 2.4 - - V

10L Low Level Output Current - - 16 mA

10H High Level Output Current - - -3.2 mA

los2 Output Short Circuit Current Vcc = 5V VOUT = 0.5V TA = 25°C -30 - -130 mA
ICC Operating Power Supply Current VIL = 0.5V VIH =3.0V - 90 130 mA
floggle = 25Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 ·C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee = 5.0V. V, = 2.0V

ClIO 110 Capacitance 8 pF Vee = 5.0V. V,/o = 2.0V

"Guaranteed but not 100% tested.

2-66 4/91.Rev.A
[JJ
1.J
LattiOO-
Semironducwr
CorporaUon
Specifications GAL22V1 DB
Commercial
I
I

AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
-10 -15
TEST DESCRIPTION UNITS
PARAMETER
COND.' MIN. MAX. MIN. MAX.
tpd 1 Input or 110 to Combinatorial Output 3 10 3 15 ns

teo 1 Clock to Output Delay 2 7 2 8 ns

tcf2 - Clock to Feedback Delay - 2.5 - 2.5 ns

tsu - Setup Time, Input or Feedback before Clocki 7 - 10 - ns

tsu. - Setup Time, SP before Clocki 10 - 10 - ns

th - Hold Time, Input or Feedback after Clocki 0 - 0 - ns


1 Maximum Clock Frequency with 71.4 - 55.5 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with 105 - 80 - MHz


Internal Feedback, 1/(tsu + tcf)
1 Maximum Clock Frequency with 105 - 83.3 - MHz
No Feedback

twh4 - Clock Pulse Duration: High 4 - 6 - ns


twt' - Clock Pulse Duration, Low 4 - 6 - ns

ten 2 Input or VO to Output Enabled 3 10 3 15 ns

tdis 3 Input or VO to Output Disabled 3 9 3 15 ns

tar 1 Input or I/O to Asynchronous Reset of Register 3 13 3 20 ns

tarw - Asynchronous Reset Pulse Duration 8 - 15 - ns

tarr - Asynchronous Reset to Clocki Reeovery Time 8 - 10 - ns

tspr - Synchronous Preset to Clocki Recovery Time 10 - 10 - ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-67 4/91.Rev.A
/lJ
.l..J Lattice·SemiconducWi'
Corporation
Specifications GAL22V10
Commercial

ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo


Supply voltage Vee ........................................ -0.5 to +7V Commercial Devices:
Input voltage applied ............................ -2.5 to Vee + 1.0V Ambient Temperature (TA) ••••••••••••••••••••••••••••• 0 to +75°C
Off-state output voltage applied ........... -2.5 to Vee + 1.0V Supply voltage (Vee)
Storage Temperature .................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.. MAX. UNITS

VIL Input Low Voltage Vss - 0.5 - 0.8 V

VIH Input High Voltage 2.0 - VcC+1 V

IlL' Input or 110 Low Leakage Current OV:;; VIN :;; Vil (MAX.) - - -150

IiH Input or 110 High Leakage Current 3.5V:;; VIN :;; Vcc - - 10

VOL Output Low Voltage 10l= MAX. Yin = Vil or VIH - - 0.5 V

VOH Output High Voltage 10H = MAX. Yin = Vilor VIH 2.4 - - V

IOL Low Level Output Current - - 16 mA

10H High Level Output Current - - -3.2 mA

los2 Output Short Circuit Current Vcc = SV VOUT = O.SV TA = 25°C -so - -135 mA
ICC Operating Power Supply Current VIL = 0.5V VIH =3.0V - 90 130 mA
ftoggle = 15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (TA =25 C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vcc = 5.0V. V, = 2.0V

ClIO 110 Capacitance 10 pF Vee = 5.0V, VI10 = 2.0V

·Guaranteed but not 100% tested.

2-68 4/91.Rev.A
[JJ
.I..J
:LatticeGl
Semioonductor
Corporation
Specifications GAL22V10
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
·15 ·25
TEST DESCRIPTION UNITS
PARAMETER
COND.' MIN. MAX. MIN. MAX.
tpd 1 Input or 110 to Combinatorial Output 3 15 3 25 ns

tco 1 Clock to Output Delay 2 8 2 15 ns

tcf2 - Clock to Feedback Delay - 5 - 13 ns

tsu - Setup Time, Input or Feedback before Clocki 12 - 15 - ns


th - Hold Time, Input or Feedback after Clocki 0 - 0 - ns
1 Maximum Clock Frequency with 50 - 33.3 - MHz
External Feedback, 1/(tsu + tco)

fmax 3 1 Maximum Clock Frequency with


Internal Feedback, 1/(tsu + tcf)
58.8 - 35.7 - MHz

1 Maximum Clock Frequency with 62.5 - 38.5 - MHz


No Feedback

twh' - Clock Pulse Duration, High 8 - 13 - ns

twl' - Clock Pulse Duration, Low 8 - 13 - ns

ten 2 Input or 110 to Output Enabled 3 15 3 25 ns


tdis 3 Input or 110 to Output Disabled 3 15 3 25 ns

tar 1 Input or 110 to Asynchronous Reset of Register 3 20 3 25 ns

tarw - Asynchronous Reset Pulse Duration 15 - 25 - ns

tarr - Asynchronous Reset to Clocki Recovery Time 15 - 25 - ns

tspr - Synchronous Preset to Clocki Recovery Time 12 - 15 - ns

1).Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

2·69 4191.Rev.A
fM Lattioo 'Semiconductor
Corporation
e
Specifications GAL22V10B
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo

Supply voltage Vee ........................................ -0.5 to +7V Industrial Devices:


Input voltage applied ....•.•....•••.••.••...•..•. -2.5 to Vee + 1.0V Ambient Temperature (TA) ............•...•.....•..•.. -40 to 85°C
Off-state output voltage applied ..•......•• -2.5 to Vee + 1.0V Supply voltage (Vee)
Sto rage Temperature ...........••.•....•.••........... -65 to 150°C with Respect to Ground •...............•..... +4.50 to +5.50V
Ambient Temperature with
Power Applied ..•.............•....•.•...•.•........... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specificatiol'1s).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.s MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
IlL' Input or 1/0 Low Leakage Current OV::s; VIN::S; VIL (MAX.; - - -100 IlA
IIH Input or 110 High Leakage Current 3.5V::s; VIN : s; Vee - - 10 IlA
VOL Output Low Voltage 10L .. MAX. Vin .. VIL or VIH - - 0.5 V
VOH Output High Voltage 100 .. MAX. Vin = VIL or VIH 2.4 - - V
lOll Low Level Output Current - - 16 mA
10H High Level Output Current - - -3.2 mA
los2 Output Short Circuit Current Vee- SV VOUT = 0.5V TA = 25°C -30 - -130 mA
ICC Operating Power Supply Current VIL=0.5V VIH =3.0V - 90 150 mA
ftoggle = 25Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout =O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. 5V and TA .. 25°C

CAPACITANCE (TA =25 C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM' UNITS TEST CONDITIONS
C, Input Capacitance 8 pF Vee = 5.0V, V, = 2.0V
110 Capacitance pF
. ClIO 8 Vcc = 5.0V, V'IO = 2.0V
Guaranteed but not 100% tested.

2-70 4191.Rev.A
Specifications GAL22V10B
l..J Corporation
Semloonductor
Industrial
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
-15
TEST DESCRIPnON UNITS
PARAMETER
COND.' MIN. MAX.
tpd 1 Input or I/O to Combinatorial Output 3 15 ns

tco 1 Clock to Output Delay 2 8 ns

tcf2 - Clock to Feedback Delay - 5 ns i

tsu - Setup lime, Input or Feedback before Clocki 10 - ns I


tsu. - Setup lime, SP before Clocki 12 - ns

th - Hold lime, Input or Feedback after Clocki 0 - ns


1 Maximum Clock Frequency with 55.5 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with


Internal Feedback, 1/(tsu + tel)
66.6 - MHz

1 Maximum Clock Frequency with 66.6 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 6 - ns

twt' - Clock Pulse Duration, Low 6 - ns

ten 2 Input or 110 to Output Enabled 3 15 ns

tdis 3 Input or I/O to Output Disabled 3 15 ns

tar 1 Input or 1/0 to Asynchronous Reset of Register 3 20 ns

tarw - Asynchronous Reset Pulse Duration 15 - ns

tarr - Asynchronous Reset to Clocki Recovery lime 10 - ns

tspr - Synchronous Preset to Clocki Recovery lime 12 - ns

1) Refer to SWitching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-71 4191.Rev.A
[JJ
.J"J
'Lattioo*
Semiconducwr
CorporaUolJ
Specifications GAL22V10
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo

Supply voltage Vee ........................................ -0.5 to +7V Industrial Devices:


Input voltage applied ......................... '" -2.5 to Vee +1.0V Ambient Temperature (TA ) •••••••••••••••••••••••••••• -40 to 85°C
Off-state output voltage applied ........... ·2.5 to Vee + 1.0V Supply voltage (Vee)
Storage Temperature .................................. -65 to 150°C with Respect to Ground ...................... +4.50 to +5.50V
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.' MAX. UNITS

VIL Input Low Voltage Vss-O.S - 0.8 V

VIH Input High Voltage 2.0 - VCC+1 V

tiL' Input or 110 Low Leakage Current OV S Y,N S V,L (MAX.) - - -150 itA
ilH Input or 110 High Leakage Current 3.5V s Y,N S Vee - - 10 itA
VOL Output Low Voltage 10L= MAX. Yin = V,L or V,H - - 0.5 V

VOH Output High Voltage IOH = MAX. Vin = V,L or V,H 2.4 - - V

tOL Low Level Output Current - - 16 mA

tOH High Level Output Current - - -3.2 mA


los2 Output Short Circuit Current Vee=5V VOUT =0.5V TA =25°C -50 - -135 mA
ICC Operating Power Supply Current VIL=0.5V VIH =3.0V - 90 150 mA
ftoggle = 15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) 'One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25 ·C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee - 5.0V, V, - 2.0V

Coo 1/0 Capacitance 10 pF Vee = 5.0V, VIIO = 2.0V

'Guaranteed but not 100% tested.

2-72 4/91.Rev.A
Specifications GAL22V10
l.J Corporation
SemiconducUJl'
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-20 -25
TEST DESCRIPTION
PARAMETER UNITS
COND.' MIN. MAX. MIN. MAX.
tpd 1 Input or 110 to Combinatorial Output - 20 - 25 ns

tco 1 Clock to Output Delay - 10 - 15 ns

tcf2 - Clock to Feedback Delay - 8 - 13 ns

tsu - Setup lime, Input or Feedback before Clocki 14 - 15 - ns

th - Hold lime, Input or Feedback after Clocki 0 - 0 - ns


1 Maximum Clock Frequency with 41.6 - 33.3 - MHz
External Feedback, 1/(tsu + tco)

fmax 3 1 Maximum Clock Frequency with 45.4 - 35.7 - MHz


Internal Feedback, 1/(tsu + tet)

1 Maximum Clock Frequency with 50 - 38.5 - MHz


No Feedback

twh" - Clock Pulse Duration, High 10 - 13 - ns

twl" - Clock Pulse Duration, Low 10 - 13 - ns

ten 2 Input or 110 to Output Enabled - 20 - 25 ns

tdis 3 Inpu1 or 1/0 to Output Disabled - 20 - 25 ns

tar 1 Input or 1/0 to Asynchronous Reset of Register - 25 - 25 ns

tarw - Asynchronous Reset Pulse Duration 20 - 25 - ns

tarr - Asynchronous Reset to Clocki Recovery lime 20 - 25 - ns

tspr - Synchronous Preset to Clocki Recovery lime 14 - 15 - ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-73 4191.Rev.A
[jJ
1..;
'Latlice
SemiconductJJr
Corporation
Specifications GAL22V10B
GAL22V10
SWITCHING WAVEFORMS

INPUT Dr
INPUT Dr
VO FEEDBACK \\\\\\\\\{AW",," VOFEEDBACK

\\'J\\';= :
COMBINATORIAL ClK
OUTPUT
REGISTERED
OUTPUT
Combinatorial Output

Registered Output

INPUT Dr
VOFEEDBACK

OUTPUT
ClK

Input or 1/0 to Output Enable/Disable


REGISTERED
FEEDBACK

fmax with Feedback


twl

ClK

Clock Width

INPUT Dr INPUT or
VOFEEDBACK VO FEEDBACK
DRIVINGAR DRIVING SP

ClK
REGISTERED
OUTPUT
REGISTERED
OUTPUT \\\\\\\\\\\\\\
ClK
Synchronous Preset

Asynchronous Reset

2-74 4191.Rev.A
i

[JJ
!

.l.J
'Lattice
Semironductor
e
Specifications GAL22V10S
Corporation GAL22V10

fmax DESCRIPTIONS
ClK elK
,._----------_ ..... _- --_ ... _------- ._._--.. ----

lOGIC
REGISTER
ARRAY

""I
..I----Isu

fmax with External Feedback 1/(1su+tco)


Note: fmax with external feedback is
calculated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)

ClK Note: tcf is a calculated value, derived by


subtracting tsu from the period of fmax wI
internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the
lOGIC delay from clocking a register to a combinato-
ARRAY rial output (through registered feedback), as
shown above. For example, the timing from
.-----------------------_._._----------_._-------. clock to a combinatorial output is equal to tcf +
tpd.
fmax With No Feedback
Note: fmax with no feedback may be less
than 1ltwh + twl. This is to allow for a clock
duty cycle of other than 50%.

SWITCHING TEST CONDITIONS

Input Pulse Levels . GNDto 3.0V +5V


Input Rise and Fall Times 3ns 10%-90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V FROM OUTPUT (O/Q) TEST POINT
Output Load See Figure UNDER TEST
3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (see figure)


Test Condition R1 R2 CL

1 300n 390n 50pF Cl INCLUDES JIG AND PROBE TOTAL CAPACITANCE


2 Active High 390n 50pF
Active Low 300n 390n 50pF
3 ,Active High 390n 5pF
Active Low 300n 390n 5pF

2-75 4/91.Rev.A
[D;
.l..J
tattiOO®
Semironductor
Corporation
Specifications GAL22V10B
GAL22V10
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD

An electronic signature (ES) is provided in every GAL22V1 0 When testing state machine designs, all possible states and state
device. It contains 64 bits of reprogram mabie memory that can transitions must be verified in the design, not just those required
contain user-defined data. Some uses include user ID codes, in the normal machine operations. This is because certain events
revision numbers, or inventory control. The signature data is may occur during system operation that throw the logic into an
always available to the user independent of the state of the se- illegal state (power-up, line voHage glitches, brown-outs, etc.). To
curity cell. test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
The electronic signature is an additional feature not present in (Le., illegal) state into the registers. Then the machine can be
other manufacturers' 22V1 0 devices. To use the extra feature of sequenced and the outputs tested for correct next state conditions.
the user-programmable electronic signature it is necessary to
choose a Lattice 22V1 0 device type when compiling a set of logic The GAL22V10 device includes circuitry that allows each reg-
equations. In addition, many device programmers have two istered output to be synchronously set either high or low. Thus,
separate selections for the device, typically a GAL22V1 0 and a any present state condition can be forced for test sequencing. If
GAL22V10-UES (UES = User Electronic Signature) or necessary, approved GAL programmers capable of executing test
GAL22V1 O-ES. This allows users to maintain compatibility with vectors perform output register preload automatically.
existing 22V1 0 designs, while still having the option to use the GAL
device's extra feature. INPUT BUFFERS
The JEDEC map for the GAL22V1 0 contains the 64 extra fuses GAL22V10 devices are designed with TTL level compatible in-
for the electronic signature, for a total of 5892 fuses. However, put buffers. These buffers have a characteristically high im-
the GAL22V10 device can still be programmed with a standard pedance, and present a much lighter load to the driving logic than
22V1 0 JEDEC map (5828 fuses) with any qualified device pro- bipolar TTL devices.
grammer.
The input and I/O pins also have built-in active pull-ups. As a
result, floating inputs will float to a TTL high (logic 1). However,
SECURITY CELL Lattice recommends that all unused inputs and tri-stated I/O pins
be connected to an adjacent active input, Vcc, or ground. Doing
A security cell is provided in every GAL22V1 0 device to prevent so will tend to improve noise immunity and reduce Icc for the
unauthorized copying of the array patterns. Once programmed, device. (See equivalent input and I/O schematics on the following
this cell prevents further read access to the functional bits in the page.)
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always
Typical Input Current
available to the user, regardless of the state of this control cell.

;(
LATCH-UP PROTECTION -=- /"
./

--
" ·20
GAL22V10 devices are designed with an on-board charge pump "
<J
./
to negatively bias the substrate. The negative bias is of sufficient
·40
/"
magnitude to prevent input undershoots from causing the circuitry "c.
to latch. Additionally, outputs are designed with n-channel pullups "
-60
instead of the traditional p-channel pull ups to eliminate any
o 1.0 2.0 3.0 4.0 5.0
possibility of SCR induced latching.
Input Voltage (Volts)

DEVICE PROGRAMMING

GAL devices are programmed using a Lattice-approved Logic


Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming of
the device takes only a few seconds. Erasing of the device is
transparent to the user, and is done automatically as part of the
programming cycle.

2-76 4/91.Rev.A
I,
I,.'

[JJ
I

1A1ttiOO- Specifications GAL22V10S I


.l..J Semiconductor
Corporation GAL22V10 !

POWER-UP RESET

OV
VIH
CLK VALID CLOCK SIGNAL
VIL

INTERNAL INTERNAL REGISTER


REGISTER RESET TO LOGIC 0
Q.OUTPUT

ACTIVE LOW
OUTPUT REGISTER

ACTIVE HIGH
OUTPUT REGISTER

Circuitry within the GAL22V10 provides a reset signal to all be met to guarantee a valid power-up reset of the GAL22V1 o.
registers during power-up. All internal registers will have their Q First, the Vee rise must be monotonic. Second, the clock input
outputs set low after a specified time (t RESET' 45I1S MAX). This must become a proper TIL level within the specified time (tpR'
feature can greatly simplify state machine design by providing a 100ns MAX). The registers will reset within a maximum of tRESET
known state on power-up. time. As in normal system operation, avoid clocking the device
until all input and feedback path setup times have been met.
The timing diagram for power-up is shown above. Because of the
asynchronous nature of system power-up, some conditions must

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Output _ _ _ _
PINe>--f6= Data V I PIN

Feedback ..
Vee Adive Pull·up
Circuit
(Yror Typica' .3.2V)
Vee .. .Y. ....
T ri·State vrel! (Vref Typicat. 3.2V)
Control

PIN
f Output
Data PIN

Feedback
(To Input Buffer)

Input Output

2-77 4/91.Rev.A
[JJ
.l.J
tatUOOGl
SemicondUCUJr
CorporatiOn
Specifications GAL22V1 DB
Typical Characteristics
Normalized Tpd vs Vee Normalized Teo vs Vee Normalized Tsu VI Vee

•., '.2
I····· PTH·.L I····· . I·····
--
1
I
ROlE
... l--PTL.•H
r---k·
1.1
". PTL->H
1.1
". " . I FALLJ .!!
...... ".

]' •.• +---If---+---+----I


'" '" '"
]
j
•.• +---If---+--+---I
". ".
". l'... .-=:--
'. :--
'.
'"

•.•
u.
__I__--I----+----l
4.75 5.00

Supply Voliage (V)


u.
•.•
u. '.711 5.00

Supply Voliage (V)


u.
...
".50 4.75 5.00

Supply Voliage (V)


....
Normalized Tpd vs Temp Normalized Teo vs Temp Normalized Tsu vs Temp

1.3 rr==::r:::::::;;T-i-i 1.3


1.4 rr==:r:::::::;;T-i-,
1.' ••••• PTH·.L [H---+--..-l '.2 1.3 I .,:;..
_ ....... PTH-:..L

....
"&. 1.1 11IL Irt-:::;:;:::t·...··..;......-"'·1 1.1
/- .!! 1.2 __ PTL.• ,H---. ••'-7-"'-1
H

,./"
il
,g.
•.• ..• ..-- il
E
1.1

1 +---If---o:::.of""'---+---l
.:."

... .. '
:li! •.• +--,:,;:;:r---t--i--l
•.• +---1---+---+---1 •.• +---If---+---+---I
... .. .. ...
•.7 - I - - - I - - - - 4 - - - I - - - - l

TemperBlure (deg. C)
•.7
... . . ,..
Temperalure (deg. C)
.•.
•.7 -1---11----4---1----1
.. . ...
Temperalure (deg. C)

Delta Tpd vs # of Outpuis Delta Teo vs # of Outputs


Switching Switching

,.,--- ,/
"..-

_.0.5 _-0.5
g
'" ......- .' g
o
., k-:' .' --::
..2-
.g
.,
.. '
!1·····Rlse} .g
II'"'' Rise}
c!: .1 .• c!: .1.'
II--FALL II--FALL
·2
3 4

Number of Oulpuls Swhching


• 1.
.,
2 3 .. 5 a
Number of Outpuls Swhching
. ,.
Delta Tpd vs Output Loading Defta Teo vs Output Loading

"
1. ..... Rise ./ ,.
12

LV
./

--FALL ./
./
--FALL, V .
V .. V ..
V. /.
/-" L'
., :/ ·2 :/
50 100 150 200 250 300 50 100 150 200 2SO 300

Outpul Loading (pF) Output Loading (pF)

2-78 4191.Rev.A
flJ'Lattioo·
i

Specifications GAL22V10B
.J..J Corporation
Semiconductor Typical Characteristics
I

Vol VB 101 Voh vs Ioh Vohvsloh

.... I
• .5

v ....

--
I ' r--.....
V .........
r-- \ ......
//
r----. :--
I-'
... V
V ...... ....
0,00 20.00 40.00 10.00 10.00 100.00 0.00 10.00 10.00 30.00 40.00 50.00 10.00 0.00 1.00 2.00 1.00 4.00

101 (mA) loh(mA) loh(mA)

Normalized Icc vs Vee Normalized Ice vs Tamp Normalized Icc vs Freq.

....
l!
1.20

1.10
/ l!
u.

1.10
......... V
/v
/
/
'" ""-
il il
] '.0. 1.00

./ i ./
0.10
./ 0.10
........ 0.'0

0.10
4.50 4.75 5.00

Supply Voltage (V)


5.25 ,.50
u.
... ...
Temperature (deg. C)
25 1$
"
100 125
u.
.. 50

Frequency (MHz)
'00

Delta Ice vs Vin (1 Input) Input Clamp (Vlk)

f"'""
••
20 /
30 /
/
'1"50
.9 2
\ !l!! eo /
\ /
, r-
70
J eo /
.....

0.00 0.50
/
1.00 1.50 2.00 2.50 3.00 3.50 ··4.00
..
to
,
L

-2.00 -1.50 -1.DO -0.50 0.00

Vin(V) Vik(V)

2-79 4191.Rev.A
Specifications GAL22V10
.l.J Corporation
SemiconducUJr
Typical Characteristics
Normalized Tpd vs Vee Normalized Tsu vs. Vee Normalized vs._
13 1.3 1.3,_ _- ._ _ _.Teo -_ Va;
- ._ _- - ,

12 1.2
t2t_--_+---t_--_+--_;

-
"&. 1.1
fE"

-
1.1
.......... ,,;---+---t---t----;

- r---
I-
], ] .........
15 'fa ....... .......... I P=9---t----;;:;f;=:;;::;;J
E
l5 0.' § r--
r
0.9
z Z
0 0.9t_--_+---t_--_+--_;
0.8
--
I·····
PT H·,L 0.8 t----t----H -- PT t·, H l-
.. I.....
PT l·)oH
PTH·, L I
0.7
04.75 , 5%1 ,., O.7L--L_-t=:::r=:=J
4.5 4.75 5 5.25 5.5
0.7'":-_ __:':::---"':---_:':::---:<
4.5 4.75 5 5.2S 5.5
Supply Voltage (V)
Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs. Temperature NormaJized Tsu vs. Temperature Normalized Teo va. Temperature
1.3 1.3 1.3

1.2 V 1.2

"8.1. I ./
V 1. I ./
V 8 I. I
,/
I-'
I-
V ,..,
, ./ I
V" >-
] I ./
V ,/
j o.• . /V
0.9

o. .V
./ (; o.
z
o. .•. / ./
o. .V

o. 7 O. 7 o. 7
.5O ·25 0255075 100 125 ·55 -25 o 25 50 75 100 125 ·55 ·25 75 100 125
Ambient Temperature (oG) Ambient Temperature tOe) Ambient Temperature (OC)

Delta Tpd vs.# of Outputs Switching


Delta Tpd vs. Output Loading Normalized Icc YS. Vee
10 1.3

V v :/
/ 12

- .-" V ....
.s
....'!!
"8.'
,/'
V
/
.ll
"0
1.1

1
L
2 o 0.9
Z

L 0 .•

·2
V 7
Max.·8 Max.' 4 100 200 300 4.5 ".75 5 525 5.5
#of Outputs Output Loading Capacitance (pf) Supply Voltage (V)

IOL VS. VOL


250 .ISO . -_ _ _,--_IO_H_V_S , _V_O_H_--,,--_ _-, Normalized Icc vs. Temperature
T

j-
--
IceVS.T ..........

:;(150
200

".--
1
·100
.l.!
o
U

1.1
."',
-P'..,-.-t---+-..; .....

p-.c:t-""<:-t---+---i--t--+---t
•••••
lab n. TM!peI"ature

.s
-'
.Q1oo V l,··,
t. t--+--t--t--1r-..:.i-"':.!'.F.?''t---t
50 / ·50
....
.....
V ,
O't----j----t---t--__ir_--t---f---,
0.7 +-_+-_-+_-+_......__1-_+-_-1
·5$ .2$ 0 2S 50 7& 100 \25
VOL (V) VOH (V) Ambient Temperature (OC)

2-80 4/91.Rev.A
[JJLatUce®
Ii
GAL26CV12
Semiconductor High Performance E2CMOS PLD
Corporation Generic Array Logic™

FEATURES FUNCTIONAL BLOCK DIAGRAM

"'-" INPUT
• HIGH PERFORMANCE ElCMOS· TECHNOLOGY
-15 ns Maximum Propagation Delay .,.,
- Fmax = 62.5 MHz IFUT
-10ns Maximum from Clock Input to Data Output
- TTL Compatible 8 mA Outputs .,.,
IFUT
- UltraMOS· Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS .,.,
N'UT
• LOW POWER CMOS
- 90 mA Typlcellcc .,.,
N'UT

• E2 CELL TECHNOLOGY
- Reconflgurable logic
.,.,
N'UT
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields IIQQ
- High Speed Electrical Erasure (50ms) IFUT

- 20 Year Data Retention


.,.,
• TWELVE OUTPUT LOGIC MACROCELLS IFUT

- Uses Standard 22V10 Macrocells


- Maximum Flexibility for Complex Logic Designs
.,.,
INPUT

• PRELOAD AND POWER-ON RESET OF REGISTERS


-100% Functional Testability INPUT "'"
• APPLICATIONS INCLUDE:
- DMA Control ....T "'"
- State Machine Control
- High Speed Graphics Processing IIQQ

- Standard Logic Speed Upgrade INPUT

• ELECTRONIC SIGNATURE FOR IDENTIFICATION


INPUT "'"
DESCRIPTION
PACKAGE DIAGRAMS
The GAL26CV12, at 15 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest per- DIP
formance 28 pin PlD available on the market. E2 technology of·
fers high speed (50ms) erase times, providing the ability to repro· PLCC
gram or reconfigure the device quickly and efficiently. 1/0/0
By building on the popular 22V1 0 architecture, the GAL26CV12 :s Q Q 1/0/0
allows the designer to be immediately productive, eliminating the ---g-gg 1/0/0
learning curve. The generic architecture provides maximum de·
/ 2 28 1/0/0
sign flexibility by allowing the Output logic Macrocell (OlMC)
1/0/0
to be configured by the user. The GAl26CV12 OlMC is fully vo/O
1/0/0
compatible with the OlMC in standard bipolar and CMOS 22V1 0 vcc Vee vOla
1/0/0
devices. GAL26CV12 GND
1/0/0
Unique test circuitry and reprogram mabie cells allow complete Top View GNO vo/O
AC, DC, and functional testing during manufacture. As a result, 1/0/0 vo/O
LATTICE is able to guarantee 100% field programmability and 1/0/0
1/0/0
functionality of all GAL· products. LATTICE also guarantees 100 ---QQQQ vOla
erase/rewrite cycles and data retention in excess of 20 years. gggg 1/0/0

" -_ _----T" 1/0/0

copyright C1991 Lattice Semlccnductor CCIp. GAL and UkraMOS are registered trademarks of lattice Semicondudor Corp. Generic Array Logic and E'CMOS are trademarks of lattice
SemlcondUdor Corp. The opecWlcatlons herein are subJOd to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. April 1991.Rev.A
Tel. (503) 681-0118or 1-800-FASTGAL; FAX (503) 681-3037
2-81
fIJ
.1J
tatlioo"'
SemiamqucWr
Corporation
Specifications GAL26CV12

GAL26CV12 ORDERING INFORMATION

Commercial Grade Specifications


Tpd (n5) T5U (n5) Tco (n5) Icc (mA) Ordering # Package
15 10 10 130 GAL26CV12-15LP 28-Pin Plastic DIP
130 GAL26CV12-15LJ 28-Lead PLCC

20 12 12 130 GAL26CV12-20LP 28-Pin Plastic DIP


130 GAL26CV12-20LJ 28-Lead PLCC

Industrial Grade Specifications


Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
20 12 12 150 GAL26CV 12-20LPI 28-Pin Plastic DIP
150 GAL26CV12-20lJI 28-lead PlCC

PART NUMBER DESCRIPTION

xxxxxxxx - xx

GAL26CV12 Device Name

Speed (n5) ' - - - - - Grade Blank = Commercial


I = Industrial

L = Low Power Power ' - - - - - - Package P = Plastic DIP


J= PLCC

2-82 4/91.Rev.A
Specifications GAL26CV12

OUTPUT LOGIC MACROCELL (OLMC)


The GAL26CV12 has a variable number of product terms per The GAL26CV12 has a product term for Asynchronous Reset
..J
OLMC. Of the twelve available OLMCs, two OLMCs have ac- (AR) and a product term for Synchronous Preset (SP). These i'\
cess to twelve product terms (pins 20 and 22), two have access two product terms are common to all registered OLMCs. The
to ten product terms (pins 19 and 23), and the other six OLMCs Asynchronous Reset sets all registered outputs to zero any time
have eight product terms each. In addition to the product terms this dedicated product term is asserted. The Synchronous Preset
available for logic, each OLMC has an additional product-term sets all registers to a logic one on the rising edge of the next clock
dedicated to output enable control. pulse after this product term is asserted.

The output polarity of each OLMC can be individually pro- NOTE: The AR and SP product terms will force the a output of
grammed to be true or inverting, in either combinatorial or reg- the flip-flop into the same state regardless of the polarity of the
istered mode. This allows each output to be individually config- output. Therefore, a reset operation, which sets the register output
gured as either active high or active low. to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.

AR

D
4 TO 1
Q
MUX
a
SP

2 TO 1 t-------------'
MUX

GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS


Each of the Macrocells of the GAL26CV12 has two primary func- NOTE: In registered mode, the feedback is from the /Q output
tional modes: registered, and combinatorialI/O. The modes and of the register, and not from the pin; therefore, a pin defined as
the output polarity are set by two bits (SO and S1), which are registered is an output only, and cannot be used for dynamic
normally controlled by the logic compiler. Each of these two pri- VO, as can the combinatorial pins.
mary modes, and the bit settings required to enable them, are
described below and on the the following page. COMBINATORIAL 1/0
In combinatorial mode the pin associated with an individual OLMC
REGISTERED is driven by the output of the sum term gate. Logic polarity of the
In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the
OLMC is driven by the a output of that OLMC's Ootype flip-flop. output buffer drive either true (active high) or inverted (active low).
Logic polarity of the output signal at the pin may be selected by Output tri-state control is available as an individual product-term
specifying that the output buffer drive either true (active high) for each output, and may be individually set by the compiler as
or inverted (active low). Output tri-state control is available as either ·on" (dedicated output), "off" (dedicated input), or "product-
an individual product-term for each OLMC, and can therefore term driven" (dynamic I/O). Feedback into the AND array is from
be defined by a logic equation. The 0 flip-flop's 10 output is fed the pin side of the output enable buffer. Both polarities (true and
back into the AND array, with both the true and complement of inverted) of the pin are fed back into the AND array.
the feedback available as inputs to the AND array.

2-83 4/91.Rev.A
flJ
.l.J
'Lattice
SemiconducUJr
Corporation
e
Specifications GAL26CV12

REGISTERED MODE

AR AR

o Q o Q

SP SP

ACTIVE LOW ACTIVE HIGH

So =0 So =1
S, =0 S, =0

COMBINATORIAL MODE

ACTIVE LOW ACTIVE HIGH

So =0 So 1 =
S, =1 S, 1 =

2-84 4/91.Rev.A
[JJ
'L 'Lattice
Semiconductor
Corporation
oo
Specifications GAL26CV12

GAL26CV12 LOGIC DIAGRAM I JEDEC FUSE MAP

9 _ _ 1III.=Jrrc-- 20

••••••••
H:::lo-t---18

8282 -Itti-tttt-ttlt--tItt-IItt-#!t--t/tl--tttt-tttI-tlift-t1f1t--iffl--ttlt---<>----- SVNCHRONOUSPRE8ET


(TOAlLREQlBTERSf

1I'I8,UU . . EtectronicSi;na1ure
11Br1tIIBr1rSIa,.419r1131a,. 21.".' tBraD

i :

2-85 4/91.Rev.A
e Specifications GAL26CV12
CorporatiOn Commercial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo

Supply voltage V cc ........................................ -0.5 to + 7V Commercial Devices:


Ambient Temperature (TA) ............................. 0 to +75°C
Input voltage applied ...........•.•••.•.......... -2.5 to Vee + 1.0V
Supply voltage (Vee)
Off-state output voltage applied ..•........ -2.5 to Vee +1.0V
with Respect to Ground .......•............. +4.75 to +5.25V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ........•..•..•........•......••...•..... -55 to 125°C
1. Stresses above those listed under the·Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - Vcc+1 V

ilL' Input or 110 Low Leakage Current OV S VIN S VIL (MAX.) - - -100 J.LA
IiH Input or 110 High Leakage Current 3.5V S VIN S Vee - - 10 J.LA
VOL Output Low Voltage 10L= MAX. Yin = VIL or VIH - - 0.5 V

VOH Output High Voltage 10H= MAX. Yin = VIL or VIH 2.4 - - V

10l Low level Output Current - - 8 mA

10H High Level Output Current - - -3.2 mA


los2 Output Short Circuit Current Vcc =5V VOUT = 0.5V TA = 25·C -50 - -135 mA
ICC Operating Power Supply Current VIL=0.5V VIH -3.0V - 90 130 mA
ftoggle =15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25 ·C

CAPACITANCE (TA =2SoC, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee = 5.0V. V, = 2.0V

C"" 110 Capacitance 10 pF Vee = 5.0V. VIlO = 2.0V


"Guaranteed but not 100% tested.

2-86 4/91.Rev.A
/llLattice·
.1..; Semiconductor
Corporation
Specifications GAL26CV12
Commercial
AC SWITCHING CHARACTERISTICS .
Over Recommended Operating Conditions
-15 -20
PARAMETER
TEST DESCRIPTION UNITS
COND.' MIN. MAX. MIN. MAX.
tpd 1 Input or 1/0 to Combinatorial Output - 15 - 20 ns

tco 1 Clock to Output Delay - 10 - 12 ns


tcf2 - Clock to Feedback Delay - 7 - 10 ns

tsu - Setup lime, Input or Feedback before Clocki 10 - 12 - ns

th - Hold lime, Input or Feedback after Clocki 0 - 0 - ns


1 Maximum Clock Frequency with 50 - 41.6 - MHz
External Feedback, 1/{tsu + tco)

fmax 3 1 Maximum Clock Frequency with 58.8 - 45.4 - MHz


Internal Feedback, 1/{tsu + tcf)

1 Maximum Clock Frequency with 62.5 - 62.5 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 8 - 8 - ns


twl4 - Clock Pulse Duration, Low 8 - 8 - ns

ten 2 Input or I/O to Output Enabled - 15 - 20 ns


tdis 3 Input or I/O to Output Disabled - 15 - 20 ns

tar 1 Input or I/O to Asynchronous Reset of Register - 20 - 20 ns

tarw - Asynchronous Reset Pulse Duration 10 - 15 - ns

tarr - Asynchronous Reset to Clocki Recovery Time 15 - 15 - ns

tspr - Synchronous Preset to Clocki Recovery lime 10 - 12 - ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

I,
I

2-87 4/91.Rev.A
!IJ tattJooe
SemiconducUJr
Corporation
Specifications GAL26CV12
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo

Supply voltage Vee ........................................ -0.5 to +7V Industrial Devices:


Input voltage applied ............................ -2.5 to Vee + 1.0V Ambient Temperature (TA) ••••••••••••••••••••••••••• -40 to 85°C
Ott-state output voltage applied ........... -2.5 to Vee +1.0V Supply voltage (Vee)
Storage Temperature .................................. -65 to 150°C with Respect to Ground ...................... +4.50 to +5.50V
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or' at any. pther conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voliage 2.0 - Vcc+1 V

IlL' Input or 110 Low Leakage Current OV $ VIN $ VIL (MAX.) - - -100

IIH Input or 1/0 High Leakage Current 3.5V $ VIN $ Vcc - - 10

VOL Output Low Voltage 10L= MAX. Yin = VIL or VIH - - 0.5 V

VOH Output High Voltage 10H= MAX. Yin = V'L or V'H 2.4 - - V

10L Low Level Output Current - - 8 mA

10H High Level Output Current - - -3.2 mA

los· Output Short Circuit Current Vee =5V VOUT = 0.5V TA = 25°C -50 - -135 mA
ICC Operating Power Supply Current VIL = O.SV VIH =3.0V - 90 150 mA
ftoggle = 1SMhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = SV and TA = 25°C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vee = S.OV, V, =2.0V


Coo 110 Capacitance 10 pF Vee = 5.0V, V,/O =2.0V
"Guaranteed but not 100% tested.

2-88 4191.Rev.A
Ii
[J;l
.l.J
lxlttiooe
Semiconductor
Corporation
Specifications GAL26CV12
Industrial
!

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

TEST
-20
PARAMETER DESCRIPTION UNITS
COND.' MIN. MAX.
tpd 1 Input or I/O to Combinatorial Output - 20 ns
tco 1 Clock to Output Delay - 12 ns
tcf2 - Clock to Feedback Delay - 10 ns
tsu - Setup lime, Input or Feedback before Clocki 12 - ns

th - Hold lime, Input or Feedback after Clocki 0 - ns


1 Maximum Clock Frequency with 41.6 - MHz
External Feedback, 1/(tsu + tco)

fmax 3 1 Maximum Clock Frequency with 45.4 - MHz


Internal Feedback, 1/(tsu + tcf)

1 Maximum Clock Frequency with 62.5 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 8 - ns


twt' - Clock Pulse Duration, Low 8 - ns

ten 2 Input or 110 to Output Enabled - 20 ns


tdis 3 Input or 1/0 to Output Disabled - 20 ns

tar 1 Input or VO to Asynchronous Reset of Register - 25 ns

tarw - Asynchronous Reset Pulse Duration 15 - ns


tarr - Asynchronous Reset to Clocki Recovery Time 15 - ns
tspr - Synchronous Preset to Clocki Recovery lime 12 - ns

1) Refer to Switching Test Conditions section.


2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-89 4/91.Rev.A
Specifications GAL26CV12

SWITCHING WAVEFORMS

INPUT or
INPUT or
110 FEEDBACK
\\\\\\\\\["'''"M 110 FEEDBACK

ClK
COMBINATORIAL
OUTPUT \\\\\\\\S\\S\-s= : REGISTERED
OUTPUT
Combinatorial Output

Reg Istered Output

INPUT or
110 FEEDBACK

OUTPUT
ClK
11 fmax (Internal fdbk)
Input or 1/0 to Output EnablelDlsable
REGISTERED
FEEDBACK

fmax with Feedback

twl

ClK

Clock Width

INPUT or
VO FEEDBACK
DRIVING SP
INPUT 0/
VOFEEDBACK ClK
DRIVINGAR

REGISTERED
REGISTERED
OUTPUT \\\\\\\\\\\\\\
OUTPUT
Synchronous Preset

ClK

Asynchronous Resat

2-90 4/91.Rev.A
.1.J Corporation
SemioonducUJr Specifications GAL26CV12

fmax SPECIFICATIONS
ClK CLK
.J
··................................ -_ ..._......... _...............
· .
lOGIC
REGISTER
ARRAY

·................................................................... _...
.. ••
... -...... -........................................................... .
fmax with External Feedback 1/(tsu+tco)
Note: fmax with extemal feedback is cal-
culated from measured tsu and teo.
fmax with Internal Feedback 1/(tsu+tcf)

ClK Note: tef is a calculated value, derived by sub-


................ _... __ ........................................... .
·· . ..
tracting tsu from the period of fmax wlintemal

....
feedback (tef - 1lfmax - tsu). The value of tef
·· is used primarily when calculating the delay from
i. LOGIC REGISTER i. clocking a register to a combinatorial oUtput
ARRAY
(through registered feedback), as shown above•
.For example, the timing from clock to a com-
·......................................................................... binatorial output is equal to tef + tpd.

fmax With No Feedback


Note: fmax with no feedback may be
less than 1ltwh + twl. This is to allow for
a clock duty cycle of other than 50%.

SWITCHING TEST CONDITIONS

Input Pulse Levels GNDt03.0V


Input Rise and Fall limes 3ns 10%-90%
Input liming Reference Levels 1.5V
Output liming Reference Levels 1.5V FROM OUTPUT (QlQ) TEST POINT
Output Load See Figure UNDER TEST
3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (see figure)


Test Condition R1 Rz CL
1 4700 3900 50pF Cl INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2 Active High 00 3900 50pF
Active Low 4700 3900 50pF
3 Active High 00 3900 5pF
Active Low 4700 3900 5pF

2-91 4191.Rev.A
Specifications GAL26CV12
.l..J Corporation
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD

An electronic signature (ES) is provided in every GAL26CV12 When testing state machine designs, all possible states and state
device. It contains 64 bits of reprogram mabie memory that can transitions must be verified in the design, not just those required
contain user-defined data. Some uses include user 10 codes, in the normal machine operations. This is because certain events
revision numbers, or inventory control. The signature data is may oocur during system operation that throw the logic into an
always available to the user independent of the state of the illegal state (power-up, line voltage glitches, brown-outs, etc.).
security cell. To test a design for proper treatment of these conditions, a way
must be provided to break the feedback paths, and force any
desired (i.e., illegal) state into the registers. Then the machine
SECURITY CELL can be sequenced and the outputs tested for correct next state
conditions.
A security cell is provided in every GAL26CV12 device to pre-
vent unauthorized copying of the array patterns. Once pro- The GAL26CV12 device includes circuitry that allows each reg-
grammed, this cell prevents further read access to the functional istered output to be synchronously set either high or low. Thus,
bits in the device. This cell can only be erased by re-program- any present state condition can be forced for test sequencing.
ming the device, so the original configuration can never be ex- if necessary, approved GAL programmers capable of execut-
amined once this cell is programmed. The Electronic Signature ing test vectors perform output register preload automatically.
is always available to the user, regardless of the state of this
control cell.
INPUT BUFFERS
LATCH-UP PROTECTION
GAL26CV12 devices are designed with TTl level compatible input
buffers. These buffers have a characteristically high impedance,
GAL26CV12 devices are designed with an on-board charge
and present a much lighter load to the driving logic much less
pump to negatively bias the substrate. The negative bias is of
than bipolar TTL logic.
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with n-
channel pullups instead of the traditional p-channel pullups to The input and I/O pins also have built-in active pull-ups. As a
result, floating inputs will float to a TTL high (logic 1). However,
eliminate any possibility of SCA induced latching.
Lattice recOmmends that all unused inputs and tri-stated 110 pins
be connected to an adjacent active input, Vee, or ground. Do-
ing so will tend to improve noise immunity and reduce Icc for the
DEVICE PROGRAMMING device.

GAL devices are programmed using a Lattice-approved Logic


Programmer, available from a number of manufacturers (see the Typical Input CUrrent
the GAL Development Tools section). Complete programming
of the device takes only a few seconds. EraSing of the device
is transparent to the user, and is done automatically as part of /"
the programming cycle. ./
/'
/"

-60
o 1.0 2.0 3.0 4.0 5.0
Input Voltag' (Voltl)

2-92 4191.Aev.A
[JJ
.l.J
:LaUiOOC
Semioonduewr
Corporation
Specifications GAL26CV12

POWER-UP RESET

Va:
OV
V IH rT"T"T"rh'TT"T'T"......I I , . - - - - - - - -
CLK VAUD CLOCK SIGNAL
VIL ...l...I...l..I-+'-'L...L.l.J..l..lI,'-_ _ _ _ _ _ __

INTERNAL INTERNAL REGISTER


REGISTER RESET TO LOGIC 0
Q-OUTPUT

ACTIVE LOW
OUTPUT REGISTER

ACTIVE HIGH
OUTPUT REGISTER

Circuitry within the GAL26CV12 provides a reset signal to all reg- must be met to guarantee a valid power-up reset of the
isters during power-up. All internal registers will have their Q GAL26CV12. First. the Vcc rise must be monotonic. Second.
outputs set low after a specified time (t RESET' 45JLS MAX). This the clock input must become a proper TIL level within the speci-
feature can greatly simplify state machine design by providing fied time (tPR • 100ns MAX). The registers will reset within a maxi-
a known state on power-up. mum of!";sETtime.Asin normal system operation. avoid clocking
the device until all input and feedback path setup limes have been
The timing diagram for power-up is shown above. Because of met.
the asynchronous nature of system power-up. some conditions

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN e>----f6= 0.1.

Flldb.ek
Vee Acive Pull-up
Cicuit
(VroITypiell.3.2V)
Vee •.. Y.....
........... .-.................
i
:
Vee:
:
I I Viti
('Irel Typieli. 3.2V)

:: ::
i CIIcI*
:
:
i
:........::
: : Oulpul
PIN
: •• u .................... :
Dill
PIN

FIIcIIIck
(To InpuiBuIlar)

Input Output

2-93 4191.Rev.A
[J;1:LaWcc Semironductor
CorporaUon
e
Specifications GAL26CV12
Typical Characteristics
NormaUzed Tpd YS Vee 1.3 . ._ _Normalized
-,-_ _--rTsu
__ Vee
YS. _ . -_ _, Normalized TCD VI. Vee
1.3

1.2+----i---+---t---i 12

- "--
1 .........
....iil

I
m
1.1

1
m::-:---t---t---t-----j

D.9+----+---f---i---i
••••••••
-
••••••••••••••••
8 1.1
iJ:j 1
1i
L.8
Z
0.1 'T H.,.L t- .•HHlr 0.8
I····· PT L-:.oH
Il····· PTH·.L J
0.7
4.75 5
Supply Voltage (V)
S.2!5 ... 4.5 4.75 5 5.25 5.5
0.7
4.5 4.75 5 5.25 5.5
S\4lPly Voltage (V) Supply Voltage (V)

.. 3
Normalizad Tpd vs. Temperature
'.3
Normalized Tsu lIS. Temperalura
1.3
Normalized Teo VI. Temperalure

:/ ,...
..,. V
'.2 1.2 1.2

"8. •.• ./
V 8 •.•
V l/
l-

L
V'
1' ./

o.t ./
V ./
V .L.
V
IV V
Z

D. ..I V 0.'

o.7 0.7 0.1


-SO ·25 0 2S 50 75 100 125 ..ss -25 0 25 so 75 100 125 -55 ·25 0 25 50 75 100 125
Ambient Temperalure (OC) Ambienl Temperature (OC) Ambient Temperature (OC)

Oeha Tpd ... 11 of Outputs s..nching


Oehe Tpd VI. Output Loading Normalizad lee lIS. Vee
.0 1.3

v L
V V
12

.. , ..... /'
V
.., V
---- !
"8.4
I-
V . /
:
d 2 / 1z o.
o t

/' 0.8

V
-3
M.... ••
• of Outputs
.... ••• Mo,.
·2
100 200
OutpoA Loading Capacitance (pi)
300
o.7
4 .• 4.75 5
Suppty Vohage (V)
5.25 ...
IOl YS. VOL ., .. . -_ _--r_I_O_H_VS.,._V_O_H_..._ _- . Normalized k::c VI. Temperature
250

200 .... klc va. T-,,*Mln


lab va. T.............


"00 i"'o,..---+----t---t----1 II ,.,
"' ...
' .i"o..
1 ...........

. ...,,- -60+----+---""'d---t----1 .•
" .... .....
/
0.'

•.7
2 2 ·&5 -25 0 2S so 75 100 125
VOL (V) VOH(V) Ambient Temperature (OC)

2-94 4191.Rev.A
!llLatUce
1..1 SemiconduGUJr
Corporation
s GAL20RA10
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic1'M
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• HIGH PERFORMANCE ElCMOS· TECHNOLOGY
-12 ns Maximum Propagation Delay
- Fmax =71.4 MHz I
- 12 ns Maximum from Clock Input to Data Output
- TTL Compatible 8 rnA Outputs INPUT
- UHraMOS- Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR INPUT
- 75rnA Typ Icc
• ACTIVE PULL-UPS ON ALL PINS
INPUT I......'I-C!-..,.....O LOIQ
• E2 CELL TECHNOLOGY
- Reconflgurable logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
INPUT =l....
- High Speed Electrical Erasure «50 ms)
- 20 Year Data Retention INPUT

• TEN OUTPUT LOGIC MACROCELLS


-Independent Programmable Clocks INPUT
- Independent Asynchronous Reset and Preset
- Registered or Combinatorial wHh Polarity
- Full Function and Parametric Compatibility with INPUT
PAL20RA10
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS INPUT
-100% Functional TestabllHy
• APPUCATIONS INCLUDE: INPUT
- State Machine Control
- Standard logic Consolidation
- MuHlple Clock logic Designs INPUT 1......'t-C'""r"iO IIOoQ

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION
PIN CONFIGURATION
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (f?) floati{lg gate technology to provide
the highest speed performance available in the PlD market. DIP
Lattice's !?CMOS circuitry achieves power levels as low as 75mA
typical Icc which represents a substantial savings in power when PLCC
compared to bipolar counterparts. E2 technology offers high Vee
speed (<SOms) erase times providing the ability to reprogram, I/0IO
reconfigure or test the devices quickly and efficiently.
...
II: IIO/Q
21
The generic architecture provides maximum design flexibility by VOIQ I/0IO

allowing the Output logic Macrocell (OlMC) to be configured by VOIQ I/0IO


the user. The GAL20RA 10 is a direct parametric compatible '010 I/0IO
GAL20RA10
CMOS replacement for the PAL20RA 10 device. NC NC I/0IO
Top View VOIQ
Unique test circuitry and reprogram mabie cells allow complete IIOIQ
VOIQ
AC,DC, and functional testing during manufacturing. Therefore, I/0IO
VOIQ
LAmCE guarantees 100% field programmability and functionality
of all GAL products. LATTICE also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.
. ..
z
0
(!
Il0l0
I/O/Q

GND /OE

Ccpyright 01991 Lattice Semiconductor Corp. GAl. E'CMOS and UltraMOS are regllta..., _ 01 Laniel SamiconductDfCorp. Generic Alray Logic Is a trademark 01 Lanice
Serricondu_ Corp. PAL Is a reglsle"" trademark 01 Advanced Mitro DavIces. Inc. The spocIIcatlons and Inlormalion herein are subject to change wRhout notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A. April 1991.Rev.B
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037
2-95
[]JLattiooSemiconductor
Corporation
e
Specifications GAL20RA 10

GAL20RA10 ORDERING INFORMATION


Commercial Grade Specifications

Tpd (ns) Tsu (ns) Teo (ns) Icc (mA) Ordering # Package
12 4 12 100 GAL20RA 10-12LP 24-Pin Plastic DIP
100 GAL20RA 10-12W 28-Lead PLCC
15 7 15 100 GAL20RA 10-15LP 24-Pin Plastic DIP
100 GAL20RA10-15W 28-Lead PLCC
20 10 20 100 GAL20RA 10-20LP 24-Pin Plastic DIP
100 GAL20RA10-20W 28-Lead PLCC
30 20 30 100 GAL20RA 1O-3OLP 24-Pin Plastic DIP
100 GAL20RA1O-3OW 28-Lead PLCC

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Teo (ns) Icc (mA) Ordering # Package
20 10 20 120 GAL20RA 10-20LPI 24-Pin Plastic DIP
120 GAL20RA 1O-20LJI 28-Lead PLCC

PART NUMBER DESCRIPTION

XXXXXXXX - XX X X X

GAL20RA10 DevJee Name

Speed (ns) L...-_ _ _ Grade Blank = Commercial


I = Industrial

L = Low Power Power L...-_ _ _ _ Package P = Plastic DIP


J = PLCC

2-96 4/91.Rev.B
.l.J CorporaUon
Semiconductor Specifications GAL20RA 10

OUTPUT LOGIC MACROCELL (OLMC) ASYNCHRONOUS RESET AND PRESET


The GAl20RA10 consists of 10 D flip-flops with individual Each GAL20RA10 macrocell has an independent asynchronous
asynchronous programmable reset, preset and clock product reset and preset control product term. The reset and preset
terms. The sum of four product terms and an Exclusive-OR product terms are level sensitive, and will hold the flip-flop in the
provide a programmable polarity D-inputto each flip-flop. An reset or preset state while the product term is active independ-
output enable term combined with the dedicated output enable ent of the clock or D-inputs. It should be noted that the reset and
pin provides tri-state control of each output. Each OlMC has a preset term alter the state of the flip-flop whose output is inverted
flip-flop bypass, allowing any combination of registered or com- by the output buffer. A reset of the flip-flop will result in the output
binatorial outputs. pin becoming a logic high and a preset will result in a logic low.
The GAL20RA 10 has 10 dedicated input pins and 10 program-
mable 110 pins, which can be either inputs, outputs, or dynamic RESET PRESET FUNCTION
I/O. Each pin has a unique path to the logic array. All macrocells 0 0 Registered function of data product term
have the same type and number of data and control product terms, 1 0 Reset register to "0" (device pin - "1")
allowing the user to exchange IIOpin assignments without restric- 0 1 Preset register to "1" (device pin = "0")
tion. 1 1 Register-bypass (combinatorial output)

INDEPENDENT PROGRAMMABLE CLOCKS COMBINATORIAL CONTROL


An independent clock control product term is provided for each The register in each GAl20RA 10 macrocell may be bypassed
GAl20RA 10 macrocell. Data is clocked into the flip-flop on the by asserting both the reset and preset product terms. While both
active edge of the clock product term. The use of individual clock product terms are active the flip-flop is bypassed and the 0- input
control product terms allow up to ten separate clocks. These is presented directly to the inverting output buffer. This provides
clocks can be derived from any pin or combination of pins and! the designer the ability to dynamically configure any macrocell
or feedback from other flip-flops. Multiple clock sources allow a as a combinatorial output, or to fix the macrocell as combinatorial
number of asynchronous register functions to be combined into only by forcing both reset and preset product terms active. Some
a single GAL20RA1 O. This allows the designer to combine dis- logic compilers will configure macrocells as registered or com-
crete logic functions into a single device. binatorial based on the logic equations, others require the de-
signer to force the reset and preset product terms active for
PROGRAMMABLE POLARITY combinatorial macrocells.
The polarity of the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with PARALLEL FLIP-FLOP PRELOAD
a programmable Exclusive-OR gate on the D-input of each flip-
flop. While anyone of the four logic function product terms are The flip-flops of a GAl20RA 10 can be reset or preset from the
active the D-input to the flip-flop ,will be low if the Exclusive-OR 110 pins by applying a logic low to the preload pin (1) and applying
is set to zero(O) and high if the Exclusive-OR bit is set to one(1 ). the desired logic level to each I/O pin. The 110 pins must remain
It should be noted that the programmable only affects the valid for the preload setup and hold time. All 10 flip-flops are reset
data latched into the flip-flop on the active edge of the clock product or preset during preload, independent of all other OlMC inputs.
term. The reset, preset and preload will alter the state of the flip-
flop independent of the state of programmable polarity bit. The A logic low on an I/O pin during preload will preset the flip-flop,
ability to program the active polarity of the D-inputs can be used a logic high will reset the flip-flop. The output of any flip-flop to be
to reduce the total number of product terms used, by allowing the preloaded must be disabled. Enabling the output during preload
DeMorganization of the logic functions. This logic reduction is will maintain the current logic state. It should be noted that the
accomplished by the logic compiler, and does not require the preload alters the state of the flip-flop whose output is inverted by
designer to define the polarity. the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin (13) will disable all 10 outputs
OUTPUT ENABLE of the GAl20RA 10 when held high.
The output of each GAl20RA 10 macrocell is controlled by the
"AND'ing" of an independent output enable product term and a
common active low output enable pin(13). The output is enabled
while the output enable product term is active and the output
enable pin(13) is low. This output control structure allows several
output enable alternatives.

2-97 4/91.Rev.B
Specifications GAL20RA 10

OUTPUT lOGIC MACROCEll DIAGRAM

XOR (n)

OUTPUT lOGIC MACROCEll CONFIGURATION (REGISTERED with POLARITY)

PL t - - - - - - - - - - ,
oet-----I

AR
PL PO 1-----+-<

OUTPUT lOGIC MACROCEll CONFIGURATION (COMBINATORIAL with POLARITY)

XOR (n)

2-98 4/91.Rev.B
[fJ
.LJ
'LlltIiOOGl
Semironductor
CorporaUon
Specifications GAL20RA 10

GAL20RA10 LOGIC DIAGRAM


DIP (PLCC) Package Pinouts
1 (2) ........ -'"
::::: "" 0 4 8 12 16 20 24 28 32 36
PL 0

2 (3) r--..

-.... 280

320
OLMC • 23
XOR • 3200 f2:ra 23 (27)

OLMC • 22 I.J. -a 22 (26)


-
3 (4) ........
600
XOR ·3201 W
640
OLMC . 21 I.:l - 21 (25)
820
(5) ........
4
- XOR • 3202

uo
i"OLMC • 20 r.:l - 20 (24)
1240
5 (6) D XOR • 3203

1280
OLMC·19 """J - 19 (23)
6 (7) D
1560
XOR ·3204
-=.J-
1600

-=.J -.... 18 (21)


>OLMC·18 r.:1
1880
7 (9) XOR • 3205
D-
H2O
>OLMC . 17
17 (20)
(10) .........
2200 -=:J
8
- XOR • 3206

2240
a= OLMC . 16 r.:1 -a 16 (19)
2520
-=:J
-
9 (11) .........
2560
XOR ·3207

OLMC·15 r.:1 -a 15 (18)


2840
-=:J
10 (12)
-........ 2880
XOR • 3208

OLMC·14 14 (17)
r>-
-
3160
11 (13) XOR • 3209

A
'V a 13 (16)

64-USER ELECllIONIC SIGNATURE FUSES


13210.3211 ..... •... 3272, 32731
Byte 71 Byte 6 .... •... Byte 11 Byte 0
M L
S S
B B
2-99 4/91.Rev.B
Specifications GAL20RA 10
Commercial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -0.5 to +7V Commercial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TA) ••••••••••••••••••••••••••••• 0 to +75°C
Off-state output voltage applied .......... -2.5 to Vee +1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings' may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYp.a MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
IlL' Input or 110 Low Leakage Current OV S VIN S VIL (MAX.) - - -100 J.lA
IIH Input or 110 High Leakage Current 3.5V S VIN S Vee - - 10 J.tA
VOL Output Low Voltage lot. .. MAX. Vin .. VIL or VIH - - 0.5 V
VOH Output High Voltage IoH .. MAX. Vin .. VIL or VIH 2.4 - - V
10L Low Level Output Current - - 8 mA
10H High Level Output Current - - -3.2 mA
1052 Output Short Circuit Current Vee-5V VOUT .. 0.5V TA .. 25°C -SO - -135 mA
ICC Operating Power Supply Current VIL-0.5V VIH -3.0V - 75 100 mA
ftoggle .. 15Mhz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout .. 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. 5V and TA .. 25°C

CAPACITANCE (TA = 25 C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS


CI Input Capacitance 8 pF Vee - 5.0V. VI - 2.0V
CliO VO Capacitance 10 pF Vee" 5.0V. VIiO '" 2.0V
"Guaranteed but not 100% tested.

2-100 4J91.Rev.B
Specifications GAL20RA 10
LJ Corporation
SemiwnductiJr
Commercial
I

AC SWITCHING CHARACTERISTICS

PARAMETER
TEST
COND.'
DESCRIPTION
OVer Recommended Operating Conditions
-12 -15 -20
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
-30
UNITS
.,
.J..
tpd 1 Input or I/O to Combinatorial Output - 12 - 15 - 20 - 30 ns

tco 1 Clock to Output Delay - 12 - 15 - 20 - 30 ns


tsu - Setup Time, Input or Feedback before Clock 4 - 7 - 10 - 20 - ns
th - Hold Time, Input or Feedback after Clock 3 - 3 - 3 - 10 - ns
1 Maximum Clock Frequency with 62.5 - 45.0 - 33.3 - 20.0 - MHz
External Feedback, 1/(tsu + tco)
fmax 2
1 Maximum Clock Frequency without 71.4 - 50.0 - 41.7 - 25.0 - MHz
Feedback

twh 3 - Clock Pulse Duration, High 7 - 10 - 12 - 20 - ns

twl3 - Clock Pulse Duration, Low 7 - 10 - 12 - 20 - ns


ten / tdis 2,3 Input or I/O to Output Enabled / Disabled - 12 - 15 - 20 - 30 ns
ten / tdis 2,3 OE to Output Enabled / Disabled - 9 - 12 - 15 - 20 ns

tar/tap 1 Input or I/O to Asynchronous. Reset / Preset - 12 - 15 - 20 - 30 ns

tarw/tapw - Asynchronous Reset / Preset Pulse Duration 12 - 15 - 20 - 20 - ns


tarr /tapr - Asynchronous Reset / Preset Recovery Time 7 - 10 - 12 - 20 - ns

twp - Preload Pulse Duration 12 - 15 - 20 - 30 - ns

tsp - Preload Setup Time 7 - 10 - 15 - 25 - ns

thp - Preload Hold Time 7 - 10 - 15 -. 25 - ns

1) Refer to Switching Test Conditions sectIOn.


2) Refer to fmax Descriptions section.
3) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS

Input Pulse. Levels GNDt03.0V +5V


Input Rise and Fall Times 3ns 10%-90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
FROM OUTPUT (0/0) - -.....- -.....-TESTPOINT
level.
UNDER TEST
Output Load Conditions (see figure)
Test Condition
1
2 Active High
Active Low
R1
4700
00

4700
R2
3900
3900
3900
CL
50DF
50pF
50pF
f'
3 Active High 00 3900 5pF
-
CllNClUOES JIG AND PROBE TOTAL CAPACITANCE
Active Low 4700 3900 5pF

2-101 4/91.Rev.B
Specifications GAL20RA 10
Industrial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo
Supply voltage Va; .......................................-o.5 to +7V Industrial Devices:
Input voltage applied ........................... -2.5 to Va; + 1.0V Ambient Temperature (TAl .......................... -40 to +85°C
Off-state output voltage applied .......... -2.5 to Va; + 1.0V Supply voltage (Va;l
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.50 to +5.50V
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
IlL' Input or I/O Low Leakage Current OV S VIN S VIL (MAX.) - - -100 IlA
IIH Input or 110 High Leakage Current 3.5V s VIN S Vex; - - 10 IlA
VOL Output Low Voltage IoL '" MAX. Yin '" VIL or VIH - - 0.5 V
VOH Output High Voltage IoH =MAX. Vin =VIL or VIH 2.4 - - V
10L Low Level Output Current - - 8 mA
10H High Level Output Current - - -3.2 mA
los2 Output Short Circuit Current Va;.5V VOUT - 0.5V TA _ 25·C -50 - -135 mA
ICC Operating Power Supply Current VIL.0.5V VIH=3.0V - 75 120 mA
ftoggle .. 15Mhz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout .. 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vex; .. 5V and TA .. 25 ·C

CAPACITANCE (TA =25 C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS
CI Input Capacitance 8 pF Vcc '" 5.0V, VI" 2.0V
Coo VO Capacitance 10 pF Vcc .. 5.0V, V110 = 2.0V
"Guaranteed but not 100% tested.

2-102 4/91.Rev.B
Specifications GAL20RA 10
Industrial I

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

TEST
-20
PARAMETER DESCRIPTION UNITS
COND.' MIN. MAX.
tpd 1 Input or I/O to Combinatorial Output - 20 ns
teo 1 Clock to Output Delay - 20 ns
tsu - Setup Time, Input or Feedback before Clock 10 - ns
th - Hold Time, Input or Feedback after Clock 3 - ns
1 Maximum Clock Frequency with 33.3 - MHz
External Feedback, 1/(tsu + tco)
fmax 2
1 Maximum Clock Frequency without 41.7 - MHz
Feedback
twh 3 - Clock Pulse Duration, High 12 - ns
twl3 - Clock Pulse Duration, Low 12 - ns
ten/tdis 2,3 Input or I/O to Output Enabled / Disabled - 20 ns
-
ten / tdis 2,3 OE to Output Enabled / Disabled - 15 ns
tar/tap 1 Input or I/O to Asynchronous Reset / Preset - 20 ns
tarw/tapw - Asynchronous Reset / Preset Pulse Duration 20 - ns
tarr /tapr - Asynchronous Reset / Preset Recovery Time 12 - ns
twp - Preload Pulse Duration 20 - ns
tsp - Preload Setup Time 15 - ns
thp - Preload Hold Time 15 - ns
1) Refer to Switching Teat Conditions sectIOn.
2) Refer to 'max Descriptions section.
3) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS

Input Pulse Levels GNDto 3.0V +5V


Input Rise and Fall Times 3ns 10"10 - 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3·state levels are measured 0.5V from steady·state active
FROM OUTPUT (010) POINT
level.
UNDER TEST
Output Load Conditions (see figure)
Teat Condition
1
2 Active High
Active Low
R1
4700
00

4700
Fb
3900
3900
3900
CL
50pF
50pF
50pF
R.
f'
3 Active High 00 3900 5pF
-
CLlNCLUOESJIG AND PROBE TOTAL CAPACITANCE
Active Low 4700 3900 5pF

2-103 4191.Rev.B
[JJ
1..J
'Ll1ttiOO
Semironductor
CorporaUon
4D

Specifications GAL20RA 10

SWITCHING WAVEFORMS

Input or Input or
110 Feedback I/O Feedback

Combinatorial Clock
Output

Registered
CombinatorIal Output
Output

Registered Output

Input or Input or
I/O Feedback 110 Feedback
Asserting Preset Asserting Reset
Regis tered Registered
Output Output

Clock ___XXXX1= Clock ___XXX5<k=


Asynchronous Preset Asynchronous Reset

Input or OE
I/O Feedback

Device Output Device Output

Input or I/O Feedback to Enable I Disable OE to Enable I Disable

Clock
PL
Clock Width
All I/O Pins

Parallel Preload

2-104 4/91.Rev.B
[JJ
.lJ
:Lattice*
Semironductor
Corporation
Specifications GAL20RA 10

fmax DESCRIPTIONS
elK ClK
........................................................
:
:
: .................................................--..
lOGIC LOGIC
REGISTER REGISTER
ARRAY ARRAY

:........................................................ --= .................. -.............. -- ......................... -...................... :


1<11"'--- h u - -.... ..I - - - - t c . - - . t
fmax WHh No Feedback
fmax with External Feedback 1/(tsu+tco) Note: fmax with no feedback may be less
Note: fmax with external feedback is cal- than 1ltwh + twl. This is to allow for a dock
culated from measured tsu and teo. duty cycle of other than 50%.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

outPut _ _ _
Dall V I PIN

Feedback ..
Vee Active PuU·up
Circuit
...+. .... (Vre'Ty_ _ 3.2V)
Trl·State

!'' 'I
Control

Output
Data PIN

Feedback
(To Input Buller)

Input Output

2-105 4/91.Rev.B
Semioonductor Specifications GAL20RA 10
CorporaUon

ELECTRONIC SIGNATURE DEVICE PROGRAMMING


An electronic signature word is provided in every GAL20RA 10 GAL devices are programmed using a Lattice-approved Logic
device. It contains 64 bits of reprogram mabie memory that Programmer, available from a number of manufacturers (see the
contains user defined data Some uses include user ID codes, the GAL Development Tools section). Complete programming of
revision numbers, pattern identification or inventory control codes. the device takes only a few seconds. Erasing of the device is
The signature data is always available to the user independent transparent to the user, and is done automatically as part of the
of the state of the security cell. programming cycle.
NOTE: The electronic signature bits if programmed to any value
other then zero(O) will alter the checksum of the device. INPUT BUFFERS
GA1.20RA10 devices are designed with TTL level compatible input
SECURITY CELL buffers. These buffers have a characteristically high impedance
and present a much lighter load to the driving logic than traditional
A security cell is provided in every GAL20RA 10 devices as a bipolar devices.
deterrent to unauthorized copying of the device pattern. Once
programmed, this cell prevents further read access of the device GA1.20RA 10 input buffers have active pull-ups within their input
pattern information. This cell can be only be reset by repro- structure. As a result, unused inputs and 1I0's will float to a TTL
gramming the device. The original pattern can never be examined "high" (logical "1"). Lattice recommends that all unused inputs
once this cell is programmed. The Electronic Signature is always and tri-stated 110 pins be connected to another active input, Vee,
available regardless of the security cell state. or GND. Doing this will tend to improve noise immunity and
reduce lee for the device.
LATCH-UP PROTECTION "TYPical Input Pull-up Characteristic
GAL20RA10 devices are designed with an on-board charge pump C
to negatively bias the substrate. The negative bias is of sufficient .:. /'
magnitude to prevent input undershoots from causing the circuitry E /'
to latch. Additionally, outputs are designed with n-<:hannel pullups ./
u
instead of the traditional p-channel pull ups to eliminate any i -40
V
possibility of SCR induced latching. .s !---
·60
1.0 2.0 3.0 4.0 5.0
Input Voilig. (VolIl)

POWER-UP RESET
Circuitry within the GAL20RA 10 provides a reset signal to all asynchronous nature of system power-up, some conditions must
registers during power-up. All internal registers will have their a be met to guarantee a valid power-up reset of the GA1.20RA10.
outputs set low after a specified time (t RESET MAX). As a First, the Vee rise must be monotonic. Second, the clock input
result, the state on the registered output pins (if they are enabled) must become a proper TTL level within the specified time (tpR '
will always be high on power-up, regardless of the programmed 1COns MAX). The registers will reset within a maximum of tRESET
polarity of the output pins. This feature can greatly simplify state time. As in normal system operation, avoid clocking the device
machine design by providing a known state on power-up. The until all input and feedback path setup times have been met.
timing diagram for power-up is shown below. Because of the

Vee

Clock

Internal
Register
a-Output
Device Device Pin
Output Pin Logic "1"

2-106 4191.Rev.B
Specifications GAL20RA 10
.l..J Corporauon
SemironductlJr

.,
Typical Characteristics
Normalized Tpc! vs Vee Normalized Teo vs Vee Normallzad Tsu vs Vee

I.' ... ..•


t----+--HJ-.... PT H•• L
I., I····· RSEl

--
1.1 I I
"',,_ I--PTL->H J! I
r:.:.::... ....--V
FALL
11

j
".
..
'" '"
11

j
".
'"
'" "
). f-'"'
0.8 +---11---+--+---1 0.8 0.'

0.8 +---'I----l----I-----l 0.' 0.8


uo 4.75 5.00 ' ..0 4 ..0 ••75 '.00 5.25 5.50 4.50 4.75
'.00 5.50

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpc! vs Temp Normalized Teo vs Temp Normalized Tsu vs Temp

1.3 ... '.4

I.' ••••• PTH••L I ..• ..... RISE I


"0
--m.J ;;:/ --FALL I V' 1.2
./

11 / / ] 1.1
k""
,/"
.... . V V l'
---
1

j 0.9
V Z 0.8

0.8 0.'

.
0.'
0.7
... ,.
Temperature (deg. C)
. .,.
0.7
... ,.
Temperature (deg. C)
. • 20
0.7
..
Temperature (deg. C)
. ...
Delta Tpd vs # of Outputs Delta Teo VI # of Outputs
Switching Switching

..... .' ./ .......


_ -0.5 .'V' 1/ ;., "
_ -0.5
",
V
..5. ,'V ..5. , ," /V
J! .•
./V
"
II·····RISE}
"
1/
V
c -1.5
Il--FALL [--FALL
.,
34' • .0
.. 2 3 " 5 • 7 • , 10

Number of Outputs Swkching Number of Outputs

Delta Tpd vs Output Loading Delta Teo vs Output Loading

".0 ./
'2

I ./
•• ./
--FALLI
. .
./ --FALL I "
/ "
,/ . ,
V"
v.' '/'
.. .y'
·2 '-/
·4 ·4
so 100 150 200 250 300 50 100 150 200 UO 300

Output Loading (pF) Output Loading (pF)

2-107 4/91.Rev.B
Specifications GAL20RA 1 ()
Typical Characteristics

Volvslol Voh VB Ioh Voh vsloh

...
o
/ "- r--... \
r- r-..
-
...........

---
...
:;s 1.5
/v ...:is .... '-....
/' I'---
... V 3.75

0.00
V
20,00 40.00 eo.OO 10.00 0.00 10.00 20.00 10.00 40.00 10.00 10.00
.... 0.00 t.OO 2.00 3.00 4.00

lol(mA) Ioh(mA) loh(mA)

........
Normalized Icc VB Vee Normalized icc VB Tamp Normalized Icc VB Freq.

.... ....

- ---
r-.....
1.10 1.10
./

"
l! Jt
j ..
1J!0
11 .. 11
1.10
V
I I /"
........
""'r-.....
uo
0.'0 0.'0
r-.........
I..........
u.
4.50 4.7& s.oo
Supply Voltage (V)
5.21 $.$0
u.

Temperature (dag. C)
IS 71 100 125 I.
Frequency (MHz)
3D .
Delta Icc VB Vln (1 Input) Input Clamp (Vlk)

• .00

0.00 /'
4.00
1/
!. /
,1\ dl
'.00

'.00
/
j
J "- 10.00

-
V .......... 12.00
'I
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
.........
..... ·2.00 •• .00 ....
Vin (V) Vik (V)

2-108 4/91.Rev.E
[JJ
.l..J
:LB.ttiOO®
Semiconductor
Corporation
GAL6001
High Performance E2CMOS FPLA
Generic Array Logic™
FEATURES FUNCTIONAL BLOCK DIAGRAM
• ELECTRICALLY ERASABLE CELL TECHNOLOGY
- Instantly Reconflgurable Logic
- Instantly Reprogrammable Cells
- Guaranteed 100% Yields
• HIGH PERFORMANCE E·CMOS· TECHNOLOGY
- Low Power: 90mA'TYplcal
- High Speed: 12ns Max. Clock to Output Delay
25ns Min. Setup TIme
30ns Max. Propagation Delay
• UNPRECEDENTED FUNCTIONAL DENSITY
- 78 x 64 x 36 FPLA Architecture
- 10 Output Logic Macrocells
- 8 Burled Logic Macrocells
- 20 Input and 1/0 logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
- Asynchronous or Synchronous Clocking L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ______
- Separate State Register and Input Clock Pins
- Functionally Supersets Existing 24-pln PAL·
and IFL Devices MACROCELL NAMES
• TTL COMPATIBLE INPUTS AND OUTPUTS
ILMC INPUT LOGIC MACROCELL
• SPACE SAVING 24-PIN, 300-MIL DIP 10LMC VO LOGIC MACROCELL
• HIGH SPEED PROGRAMMING ALGORITHM BLMC BURIED LOGIC MACROCELL
• APPLICATIONS INCLUDE: OLMC OUTPUT LOGIC MACROCELL
-Sequencer
- State Machine Control
....,.. Multiple PLD Device Integration PIN NAMES
DESCRIPTION
I. - I,. INPUT 1/010 BIDIRECTIONAL
Using a high performance PCMOS technology, Lattice
Semiconductor has produced a next-generation programmable ICLK INPUT CLOCK Vee POWER (+5)
logic device, the GAL6001. Having an FPLA architecture, known
OCLK OUTPUT CLOCK GND GROUND
for its superior flexibility in state-machine design, the GAL6001
offers the highest degree of functional integration, flexibility, and
speed currently available in a 24-pin, 300-mil package.
PIN CONFIGURATION
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). DIP
In addition, there are 10 Input Logic Macrocel!s (ILMC) and 10
PLCC
110 Logic Macrocells (IOLMC). Two clock inputs are provided for IIICLK 1 Vee
independent control of the input and output macrocells. !5u . 0 0 I vOla
--" l! !
Advanced features that simplify programming and reduce test vOla
28
lime, coupled with E2CMOS reprogram mabie ceHs, enable 100% IIOIQ
vOla
AC, DC, programmability, and functionality testing of each IIOIQ
vOla
GAL6001during manufacture. This allows Lattice to guarantee IIOIQ
NC GAL6001 Me UOIQ
100% performance to specifications. In addition, data retention
of 20 years and a minimum of 100 eraselwrite cycles are Top View IIOIQ vOla
guaranteed. . IIOIQ
vOla
IIOIQ
Programming is accomplished using standard hardware and uO/a
- - D
software tools. In addition, an Electronic Signature is available i§ l! vOla
for storage of user specified data, and a security cell is provided uO/a
to protect proprietary designs.
GND OCLK

Copyright Cl991 Lattice Semiconductor Corp. GAL. E'CMOS and UhraMOS are registered trademarks of Lattice Semiconductor Corp. Go....ie Array logic is a Irade_k of Lattice Serriconduc-
lOr Corp. PAL is a registered trademark of Advanced Micro Devices. inc. iFL is a trademark of Slgnetics. The speeWlcations and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon U.SA April 1991.Rev.A
Tel. (503)681-0118 or 1-800-FASTGAL; FAX (503)681-3037 2-109
[JJ'LatliOO-Semironductor
Corporation
Specifications GAL6001

GAl6001 ORDERING INFORMATION

Commercial Grade Specifications


Tpd (n8) Fclk(MHz) Icc (mA) Ordering # Package

30 27 150 GAL6001-30P 24-Pin Plastic DIP


150 GAL6001-30J 28-Lead PLCC

35 22.9 150 GAL6001-35P 24-Pin Plastic DIP


150 GAL6001-35J 28-Lead PLCC

GAl6001 ORDERING INFORMATION

xxxxxxx - XX X X

GAL6001 L Grade Blank = Commercial

Speed (ns) Package P = Plastic DIP


J= PLCC

2-110 4/91.Rev.A
[JJ
.l.J
Lattlce*
Semironductor
Corporation
Specifications GAL6001
INPUT LOGIC MACROCELL (ILMC) AND 1/0 LOGIC MACROCELL (IOLMC)

rile GAL6001 features two configurable input sections. The ILMC the GAL6001 , external registers and latches are not necessary.
lection corresponds to the dedicated input pins (2-11) and the
OLMC to the I/O pins (14-23). Each input section is configurable Both the ILMC and thelOLMC are block configurable. However,
IS a block for asynchronous, latched, or registered inputs. Pin the ILMC can be configured independently of the 10LMC. The
I (ICLK) is used as an enable input for latched macrocells or as three valid macrocell configurations are shown in the macrocell
I clock input for registered macrocells. Configurable input blocks equivalent diagrams on the following pages.
)rovide systems designers with unparalled design flexibility. With

OUTPUT LOGIC MACROCELL (OLMC) AND BURIED LOGIC MACROCELL (BLMC)


rhe outputs of the OR array feed two groups of macrocells. One When the macrocell is configured as a "D type register with a sum
Iroup of eight macrocells is buried; its outputs feed back directly term clock", the register is always enabled and its "E" sum term
nto the AND array rather than to device pins. These cells are is routed directly to the clock input. This permits asynchronous
:alled the Buried Logic Macrocells (BLMC), and are useful for programmable clocking, selected on a register-by-register basis.
)uilding state machines. The second group of macrocells con-
lists of 10 cells whose outputs, in addition to feeding back into Registers in both the Output and Buried Logic Macrocells feature
he AND array, are available at the device pins. Cells in this group a common RESET product term. This active high product term
ue known as Output Logic Macrocells (OLMC). allows the registers to be asynchronously reset. Registers are
reset to a logic zero. If connected to an output pin, a logic one
rhe Output and Buried Logic Macrocells are configurable on a will occur because of the inverting output buffer.
nacrocell by macrocell basis. Buried and Output Logic Macrocells
nay be set to one of three configurations: combinational, "O-type There are two possible feedback paths from each OLMC. The
egister with sum term (asynchronous) clock", or "DIE-type first path is directly from the OLMC (this feedback is before the
egister." Output macrocells always have 110 capability, with output buffer and always present). When the OLMC is used as
lirectional control provided by the 10 output enable (OE) prod- an output, the second feedback path is through the 10LMC. With
Ict terms. Additionally, the polarity of each OLMC output' is this dual feedback arrangement, the OLMC can be permanently
lelected through the "0" XOR. Polarity selection is available for buried (the associated OLMC pin is an input), or dynamically
3LMCs, since both the true and complemented forms of their buried with the use of the output enable product term.
)utputs are available in the AND array. Polarity of all "E" sum
erms is selected through the "E" XOR. The DIE registers used in this device offer the designer the ul-
timate in flexibility and utility. The DIE register architecture can
IVhen the macrocell is configured as a "DIE type registered", the e!T1ulate RS-, JK-, and T-type registers with the same efficiency
egister is clocked from the common OCLK and the register clock as a dedicated RS-, JK-, or T-register.
mabie input is controlled by the associated "E" sum term. This
:onfiguration is useful for building counters and state-machines The three macrocell configurations are shown in the macrocell
vith state hold functions. equivalent diagrams on the following pages.

2-111 4/91.Rev.A
.J"", SemironductlJr Specifications GAL6001
Corporation
ILMC AND IOLMC CONFIGURATIONS

I IClK

-------------------
:__ ________________
I NC I
E Q
LATCH
D
INPUT I
PINS 2-11 INPUT
OR
IJOPINS
14-23
--.+t-r-;:::==:::::;-,
I 10
MUX
TO
PINS 2·11
OR
I
.
10
I I ' I:L
\lOPINS I
Q AND 14·23 TO
REGISTER ARRAY AND
D ARRAY
L __________________ I

ILMC/IOLMC Asynchronous Input


Generic Block Diagram
LATCH SYN

IClK IClK

Q Q
INPUT E
REGISTER 10 INPUT 10 I
PINS 2·11 I 10 TO PINS 2-11 I LATCH
10 TO
OR D AND OR
I
D AND
\10 PINS I I
ARRAY IJOPINS
I

14·23 ARRAY
14-23

Registered Input Latched Input

LATCH SYN LATCH SYN


o o o

2-112 4191.Rev.A
L.. Corporation
Semiconductor Specifications GAL6001
OLMC AND BLMC CONFIGURATIONS

RES'"

[)o-';-'&-IO
D
FROM t ...... !I... FROM
OR
IUlRAY OR
E ......._ ......../ ARRAY

CUll
OCU< ,_ - - - - - - - - - - - - - - - - - - - - - I

OCLII

OLMC/BLMC DIE Type Registered


Generic Block Diagram
CKS(i) OUTSYN(i)
1 o

TOAND ............... " TO AND


ARRAY: OE ARRAY
Ran PT IOLMC
__ ti _ "
.
I ____________ IOLUe
I - - - - - - - - - - - - _1- - - - - - - .
,
I
I"
... , I " ' ... "''''''''',
OUIC"
, : I"
r.l"""'II'.I,,.I,
I: lOR
OLMC"
ONLY : He
,
,

. ..........
I: XOR ONLY
R
Q ' .. I

FROM
'"""" .. ,,,,,,,,,,,,,, "'I OLMC ONLY
.................. ........................................ FROM ............ ..
OR I lCOR Vee OR I

ARRAY ARRAY
I
E-,- NC

I He
He
'- -- --- - - - - - - - - - - - - - - - -'
OCLK
OCLII

D Type Register
with Sum Term Combinational
Asynchronous Clock

CKS(i) OUTSYN(i) CKS(i) OUTSYN(i)


o o o

2-113 4191.Rev.A
Semiconductor Specifications GAL6001
Corporation

GAL6001 LOGIC DIAGRAM


lelK
...
1
,,.
,
[J-
.
3
"
"

."
.. roJ-
,7 :w-
:: ,,-

,. 10

23

22

21

20

"
18

17

16

"

"
RESET

OCLK ,.
2-114 4/91.Rev.J
[J.J
t
f
LJ
'LattiOO$
Semironductor
CorporaUon
Specifications GAL6001
Commercial
ABSOLUTE MAXIMUM RATINGS(l) RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -0.5 to +7V Commercial Devices:
Input voltage applied ........................... -2.5 to Vee +1.0V Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Off-state output voltage applied .......... -2.5 to Vee + 1.0V Supply voltage (Vee)
Storage Temperature ................................. -65 to 150°C with Respect to Ground ...................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ........................................-55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss -0.5 - 0.8 V


VIH Input High Voltage 2.0 - VcC+1 V
IlL Input or 110 Low Leakage Current OV S Y,N S V,L (MAX.) - - ·10
IIH Input or 110 High Leakage Current V,H S V,N S Vee - - 10
VOL Output Low Voltage 10L. MAX. Yin - V,L or V,H - - 0.5 V
VOH Output High Voltage IOH = MAX. Yin = V,L or V,H 2.4 - - V
10L Low Level Output Current - - 16 mA
10H High Level Output Current - - -3.2 mA

los' Output Short Circuit Current Vcc=5V VOUT = 0.5V -30 - -130 mA
Icc Operating Power Supply Current V,L = 0.5V V,H = 3.0V ftoggle = 15MHz - 90 150 mA
Outputs Open (no load)
1) One output at a time for a maximum duration of one second. Vout =0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc - 5V and TA = 25 ·C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

C, Input Capacitance 8 pF Vcc = 5.0V, V, • 2.0V


C . 110 Capacitance 10 pF Vee = 5.0V, VI/O = 2.0V
I/O
'Guaranteed but not 100% tested.

2-115 4/91.Rev.A
Specifications GAL6001
Commercial
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions

TEST
-30 -35
PARAMETER DESCRIPTION UNITS
COND'. MIN. MAX. MIN. MAX.
tpd1 1 Combinatoriallnpurto Combinatorial Output - 30 - 35 ns

tpd2 1 Feedback or 1/0 to Combinational Output - 30 - 35 ns


tpd3 1 Transparent Latch Input to Combinatorial Output - 35 - 40 ns
tco1 1 Input latch IClKi to Combinatorial Output Delay - 35 - 40 ns
tco2 1 Input Reg. IClKi to Combinatorial Output Delay - 35 - 40 ns

tc03 1 Output DIE Reg. OClKi to Output Delay - 12 - 13.5 ns


tc04 1 Outout 0 Rea. Sum Term ClK"t to Outout Delav - 35 - 40 ns

tsu1 - Setup Time, Input before Input Latch IClK.!. 2.5 - 3.5 - ns

tsu2 - Setup Time, Input before Input Reg. IClKi 2.5 - 3.5 - ns
tsu3 - Setup Time, Input or Feedback before DIE Reg. OClKi 25 - 30 - ns
tsu4 - Setup Time, Input or Feedback before 0 Reg. Sum Term ClKi 7.5 - 10 - ns

tsu5 - Setup Time, Input Reg. IClKi before DIE Reg. OClKi 30 - 35 - ns

tsu6 - Setup Time, Input Reg. IClK"t before 0 Reg. Sum Term ClKi 15 - 17 - ns
th1 - Hold Time, Input after Input latch IClK.!. 5 - 5 - ns

th2 - Hold Time, Input after Input Reg. IClKi 5 - 5 - ns

th3 - Hold Time, Input or Feedback after DIE Reg. OClK"t -5 - -5 - ns

th4 - Hold Time, Input or Feedback after 0 Rea. Sum Term ClKi 10 - 12.5 - ns

fmax - Maximum Clock Frequency, OClK 27 - 22.9 - MHz


twh12 - IClK or OClK Pulse Duration, High 10 - 10 - ns

twh22 - Sum Term ClK Pulse Duration, High 15 - 15 - ns


twl12 - IClK or OClK Pulse Duration, Low 10 - 10 - ns
twl22 - Sum Term ClK Pulse Duration, low 15 - 15 - ns

tarw - Reset Pulse Duration 15 - 15 - ns

ten 2 Input or I/O to Output Enabled - 25 - 30 ns


tdis 3 Input or I/O to Output Disabled - 25 - 30 ns

tar 1 Input or I/O to Asynchronous Reg. Reset - 35 - 35 ns

tarr1 - Asynchronous Reset to OClK Recovery Time 20 - 20 - ns

tarr2 - Asynchronous Reset to Sum Term ClK Recovery Time 10 - 10 - ns

1) Refer to Switching Test Conditions section.


2) Clock pulses of widths less than the specification may be detected as valid clock signals.

2-116 4191.Rev.A
L1III Corporation
SemJronductor Specifications GAL6001

SWITCHING WAVEFORMS

INPUT or
I/O FEEDBACK
\\\\\\\ r- VALID INPUT INPUT or
I/O FEEDBACK
\ \\ \ \ \ rVAlID INPUT

roo-'-------
COMBINATORIAL
OUTPUT \\\\\\\\\\\\\ ICLK (REGISTER)

Combinatorial Output COMBINATORIAL


OUTPUT

INPUT or
110 FEEDBACK OCLK

100'1=
ICLK (LATCH)
Sum Term CLK

COMBINATORIAL Registered Input


OUTPUT

latched Input

. t ._t.:'_
INPUT or
INPUT or
I/O FEEDBACK
\'\\\r VAliD INPUT I \\\\\\ VO FEEDBACK

OCLK
SumTermCLK

REGISTERED
OUTPUT \\\ \\\\\\ REGISTERED
OUTPUT
Registered Output (Sum Term ClK) Registered Output (OClK)

INPUT 01
I/O FEEDBACK

INPUT or
110 FEEDBACK
OUTPUT DRIVINGAR

Input or I/O to Output Enable/Disable REGISTERED


OUTPUT

SumTermCLK
ICLKor
OCLK

OCLK
SumTermCLK

Clock Width Asynchronous Reset

2-117 4191.Rev.A
.l..J ('nporation Specifications GAL6001

SWITCHING TEST CONDITIONS .

Input Pulse Levels GNDto 3.0V


Input Rise and Fall Times 3ns 10%-90%
Input Timing Reference Levels 1.SV
Output Timing Reference Levels 1.SV
Output Load See Figure
3-state levels are measured O.SV from steady-state active
level. FROM OUTPUT (0/0)
- -......- - - - TEST POINT
UNDER TEST
Output Load Conditions (see figure) Cl
R2
Test Condition R1 Fb CL
1 300n 3900 SOpF
2 Active High 00 3900 SOpF
Active Low 300n 3900 SOpF CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
3 Active High 00 390n SpF
Active Low 300n 3900 SpF

2-118 4191.Rev)
I,

Semironductor Specifications GAL6001


Corporation I
ARRAY DESCRIPTION BULK ERASE
The GAl6001 contains two E2 reprogram mabie arrays. The first Before writing a new pattern into a previously programmed part,
is an AND array and the second is an OR array. These arrays are the old pattern must first be erased. This erasure is done
described in detail below. automatically by the programming hardware as part of the pro-
gramming cycle and takes only 50 milliseconds.
ANDARRAY
The AND array is organized as 78 inputs by 75 product term
REGISTER PRELOAD
outputs. The 10 IlMCs, 10 IOlMCs, 8 BlMCfeedbacks, 10
OlMC feedbacks, and IClK comprise the 39 inputs to this array When testing state machine designs, all possible states and state
(each available in true and complement forms). 64 product terms transitions must be verified, not just those required during normal
serve as inputs to the OR array. The RESET product term operations. This is because in system operation, certain events
generates the RESET signal described in the Output and Buried may occur that cause the logic to assume an illegal state: power-
logic Macrocells section. There are 10 output enable product up, brown out, line voltage glitches, etc. To test a design for proper
terms which allow device pins 14-23 to be bi-directional or tri-state. treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (Le., illegal) into
ORARRAY the registers. Then the machine can be sequenced and the
The OR array is organized as 64 inputs by 36 sum term outputs. outputs tested for correct next state generation.
64 product terms from the AND array serve as the inputs to the
OR array. Of the 36 sum term outputs, 18 are data ("0") terms All of the registers in the GAl6001 can be preloaded, including
and 18 are enablelclock ("E") terms. These terms feed into the the IlMC, 10lMC, OlMC, and BlMC registers. In addition, the
10 OlMCs and 8 BlMCs, one "0" term and one "E" term to each. contents of the state and output registers can be examined in a
special diagnostics mode. Programming hardware takes care of
The programmable OR array offers unparalleled versatility in all preload timing and voltage requirements.
product term usage. This programmabili1Y allows from 1 to 64
product terms to be connected to a single sum term. A pro-
grammable OR array is more flexible than a fixed, shared, or LATCH-UP PROTECTION
variable product term architecture.
GAl6001 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
ELECTRONIC SIGNATURE WORD magnitude to prevent input undershoots from causing the circuitry
An electronic signature (ES) is provided with every GAl6001 to latch. Additionally, outputs are designed with n-channel pull-
device. It contains 72 bits of reprogram mabie memory that can ups instead of the traditional p-channel pull-ups to eliminate any
contain user defined data. Some uses include user 10 codes, possibility of SCR induced latching.
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curitycell. INPUT BUFFERS
GAL devices are designed with m level compatible input buffers.
NOTE: The ES is included in checksum calculations. Changing These buffers, with their characteristically high impedance, load
the ES will alter the checksum. driving logic much less than traditional bipolar devices. This
allows for a greater fan out from the driving logic.
SECURITY CELL GAl6001 devices do not possess active pull-ups within their input
A security cell is provided with every GAl6001 device as a de- structures. As a result, lattice recommends that all unused in-
terrent to unauthorized copying of the array patterns. Once puts and tri-stated 1/0 pins be connected to another active input,
programmed, this cell prevents further read access to the AND VCC' or GND. Doing this will tend to improve noise immunity and
and OR arrays. This cell can be erased only during a bulk erase reduce Icc forthe device.
cycle, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always
available to the user, regardless of the state of this control cell.

2-119 4/91.Rev.A
flJ'Lattioo SemkxJnducUJr
Corporation
e

Specifications GAL6001
POWER-UP RESET

Va;
0"----
/-----------------
OCLK VALID CLOCK SIGNAL
VIL ...

INTERNAL INTERNAL REGISTER


REG. 0 RESET TO lOGIC 0

FEEDBACK/EXTERNAL
REG. 0
OUTPUT

within the GAL6001 provides a reset signal to all registers The timing diagram for power-up is shown above. Because of the
during power-up. All internal registers will have their Q outputs asynchronous nature of system power-up, some must
set low after a specified time (tRESET , 45I1S). As a result, the state be met to guarantee a valid power-up reset of the GAL6001. First,
on the registered output pins (if they are enabled) will always be the Vee rise must be monotonic. Second, the clock inputs must
high on power-up, regardless of the programmed of the become a proper TTL level within the specified time (tpR , 1001LS).
output pins. This feature can greatly simplify state ·machine design The registers will reset within a maximum of tREsET time. As in
by providing a known state on power-up. normal system operation, avoid clocking the device until all input
and feedback path setup times have been met.

DIFFERENTIAL PRODUCT TERM SWITCHING (OPTS) APPLICATIONS


The number of Differential Product Term Switching (OPTS) for simultaneously - there is no limit on the number of product terms
a given design is calculated by subtracting the total number of that can be used.
product terms that are switching from a logical HI to a Logical LO
from those switching from a logical LO to a logical HI within a A software is aV!lilable from Lattice Applications Engineering
5ns period. After subtracting take the absolute value. that will perform this calculation on any GAL6001 JEOEC file. This
program, OPTS, and information may be obtained from
OPTS - I(P-Terms)LH - (P-Terms)HL I your local Lattice representative or by contacting Lattice
Applications Engineering Oept. (Tel: 503-681-0118 or 800-
OPTS restricts the number of product terms that can be switched FASTGAL; FAX: 681-3037).

2-120 4191.Rev.A
[JJ:LatUoo® SemiaJnducWr
Corporation
ispGAL16Z8
In-System Programmable
High Performance E2CMOS PlD
FEATURES FUNCTIONAL BLOCK DIAGRAM
IN·SYSTEM·PROGRAMMABLE - 5·VOLTONLY
- Change Logic "On The Fly" In Seconds
- Non·volatlle E2 Technology
MINIMUM 10,000 ERASE/WRITE CYCLES
DIAGNOSTIC MODE FOR CONTROLUNG AND
OBSERVING SYSTEM LOGIC
HIGH PERFORMANCE E2CMOS- TECHNOLOGY
- 20 ns Maximum Propagation Delay
- Fmax = 41.6 MHz
- 90 mA MAX Icc
E2 CELL TECHNOLOGY
-100% Tested/Guaranteed 100% Yields
- 20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 2D-pin PAL- Devices with Full Func·
tlon/Fuse Map/Parametric Compatibility
PRELOAD AND POWER·ON RESET OF REGISTERS
- 100% Functional Testability
APPUCATIONS INCLUDE:
- Reconflgurable Interfaces and Decoders
- "Soft" Hardware (Generic Systems)
- Copy Protection and Security Schemes
- Reconflgurlng Systems for Testing
ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION PIN CONFIGURATION

rile Lattice ispGAL-16Z8 is a revolutionary programmable logic


levice featuring 5-volt only in-system programmability and in-
;ystem diagnostic capabilities. This is made possible by on-chip DIP
:ircuitry which generates and shapes the necessary high volt- PLCC
Ige programming signals. Using Lattice's proprietary UltraMOS-
echnology, this device provides true bipolar performance at
_ 8 "...g
.. DClK
24 Vee
MODE
;ignificantly reduced power levels. u
z ! 1/0/0
28
1/0/0
rhe 24-pin ispGAL 16Z8 is architecturally and parametrically UO/Q

dentical to the 20-pin GAL 16V8, but includes 4 extra pins to UO/Q 1/0/0

:ontrol in-system programming. These pins are not associated UO/Q ispGAL 1/0/0
ispGAL16Z8
'lith normal logic functions and are used only during program- NC NC 16Z8 1/0/0
ning and diagnostic operations. This 4-pin interface allows an Top View UO/Q
110/0
mlimited number of devices to be cascaded to form a serial WO/Q
UO/O
)rogramming and diagnostics loop. WO/Q
00/0
SOl SDO
Jnique test circuitry and reprogrammable cells allow complete
DC, and functional testing during manufacture. Therefore, GND 12 13 I/oE

-ATTICE is able to guarantee 100% field programmability and


unctionalily of all GAL- products.
:opyright CI991 Lattice Semiconductor Corp. GAL. E'CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Goneric Array Logic Is a trademark of Lanico Semlconduc·
"Corp. PAL Is a registerod trademark of Advanced Micro Dovlcos. Inc. The specifications and Information heroin are subject to change without notice.

.ATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro. Oregon 97124, U.S.A. April 1991.Rev.A
reI. (503) 681-0118 or 1-800-FASTGAL; FAX (503) 681-3037
2-121
Semiconductor Specifications ispGAL 16Z8
CorporaUon

ispGAL 16Z8 ORDERING INFORMATION

Commercial Grade Specifications


Tpd (na) Tau (n8) Tco (na) lcc(mA) Ordering' Package
20 15 15 90 ispGAL16Z8-20LP 24-Pin Plastic DIP
90 ispGAL16Z8-20LJ 28-Lead PLCC
25 20 15 90 ispGAL16Z8-25LP 24-Pin Plastic DIP
90 IspGAL16Z8-25LJ 28-Lead PLCC

PART NUMBER DESCRIPTION

xxxxxxxx - xx X X X

ispGAL16Z8 DevIce Name

Speed (ns) 1...-_ _ _ Grade Blank = Commercial

L = Low Power Power - - - - - - - - - ' Package P = Plastic DIP


J = PLCC

2-122 4/91.Rev.A
[jJ
1.J
Lattice Semironducwr
Corporation
Gl

Specifications ispGAL 16Z8


!

OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic


macrocell. It should be noted that actual implementation is PAL Archltactur.. IspGAL16Z8
accomplished by development softwarelhardware and is com- Emulated by IspGALl6Z8 Global OLMC Mode
pletely transparent to the user.
16R8 Reglstared
There are three global OlMC configuration modes possible: 16R6 Reglslared
simple, complex, and registered. Details of each of these 16R4 Reglslared
modes is illustrated in the following pages. Two global bits, SYN l6RP8 Reglalared
16RP6 Reglstared
and ACO, control the mode configuration for all macrocells, the l6RP4 Registered
XOR bit of each macrocell controls the polarity of the output in
any of the three modes, and the AC1 bit of each of the macro- l61.8 Complex
cells controls the inpuUoutput configuration. These two global l6HS Complex
and 16 individual architecture bits define all possible configura- 16P8 Complex
tions in an ispGAl16Z8. The information given on these archi- 101.8 Simple
tecture bits is only to give a better understanding of the device. l2L6 Simple
Compiler software will transparently set these architecture bits l4L4 Simple
from the pin definitions, so the user should not need to directly l6U Simple
manipulate these architecture bits. 10HS Simple
l2H6 Simple
l4H4 Simple
The following is a list of the PAL architectures that the GAL16V8, 16H2 Simple
and therefore the ispGAl16Z8, can emulate. It also shows the 10P8 Simple
OlMC mode under which the ispGAl16Z8 emulates the PAL l2P6 Simple
architecture. l4P4 Simple
16P2 Simple

COMPILER SUPPORT FOR OLMC


Software compilers support the three different global OlMC When using compiler software to configure the device, the user
modes as different device types. These device types are listed must pay special attention to the following restrictions:
in the table below. Most compilers have the ability to automatically
select the device type, generally based on the register usage and In registered mode pin'1 and pin 13 are permanently config-
output enable (OE) usage. Register usage on the device forces ured as clock and output enable, respectively. These pins cannot
the software to choose the registered mode. All combinatorial be configured as dedicated inputs in the registered mode.
outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose In complex mode pin 1 and pin 13 become dedicated inputs and
the simple mode only when all outputs are dedicated combina- use the feedback paths of pin 22 and pin 15 respectively. Be-
torial without OE control. The different device types listed in the cause of this feedback path usage, pin 18 and pin 19 do not have
table can be used to override the automatic device selection by the feedback option in this mode.
the software. For further details, refer to the compiler software
manuals. In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner-most pins ( pins
The ispGAl16Z8 can be treated as a GAL16V8, and tools are 18 and 19) will not have feedback, as these pins are always
provided by lattice to use GAL 16V8 JEDEC files to program configured as dedicated combinatorial output. All macroceUs are
ispGAl 16Z8 devices. always either dedicated inputs or dedicated outputs in this mode.

Registered Complex Simple Auto Mode Select


ABEL P16V8R P16V8C P16V8S P16V8
CUPL G16V8MS G16V8MA G16V8S G16V8
LOG/IC GAL16V8 R GAl16V8 C7 GAL16V8 C8 GAl16V8
OrCAD-PLD "Registered"' "Complex"' "Simple"' GAL16V8A
PLDeslgner P16V8R2 P16V8C2 P16V8C2 P16V8A
TANGo.PLD G16V8R G16V8C G16V8AS3 G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.

2-123 4191.Rev.A
!IJLattiOO-
1.J Corporation
SemironducWr Specifications ispGAL 16ZB

REGISTERED MODE
In the Registered mode, macroceUs are configured as dedicated this mode. Dedicated input or output functions can be Imple-
registered outputs or as 1/0 functions. mented as subsets of the I/O function.

Architecture configurations available in this mode are similar to Registered outputs have eight product terms per output. 1I0's
the common 16R8 and 16RP4 devices with various permuta- have seven product terms per output.
tions of polarity, 110 and register placement.
The JEDEC fuse numbers, including the User Electronic Signa-
All registered macrocells share common clock and output en- ture (UES) fuses and the Product Term Disable (PTD) fuses, are
able control pins. Any macroceU can be configured as registered shown on the logic diagram on the following page.
or I/O. Up to eight registers or up to eight I/O's are possible in

elK
Registered Configuration for Registered Mode

-SYN-O.
-ACO.1.
- XOR-O defines Active Low Output.
- XOR.1 defines Active High Output.
- AC1-0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK
and OE.
:. .....................................................
OE

·...........
·
_- .................................
.. Combinatorial Configuration for Registered Mode

-SYN-O.
-ACO.1.
- XOR.O defines Active Low Output.
- XOR",1 defines Active High Output.
- AC1.1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as ClK
and OE.
....... -...............................................

Note: The development software configures aU of the architecture control bits and checks for proper pin usage automaticaUy.

2-124 4191.Rev.A
Semiconductor Specifications ispGAL 16Z8
Corporation

REGISTERED MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts

1 (2)
.--..
......, .......
0 4 8 12 16 20 24 28

0000
OLMC 22 rJ - 22 (26)

3 (4)
.--..
'--"
... 0224 -=- XOR-2048
ACl-2120

0256

OLMC 21 1 21 (25)

0480 =B= XOR-2049


.--..
......,
4 (5) ACI-2121

0512

OLMC 20 IJ - 20 (24)
I=E
5 (6)
.--..
'--'
... 0736
XOR-2050
ACl-2122

0768
...... l
6 (7) - 0992 -,..,
OLMC 19
XOR-2051
ACI-2123
0- 19 (22)

1024
IJ -
7 (9)
.--..
'--"
1248 -c;,-
OLMC 18
XOR-2052
ACI-2124
0- 18 (21)

1280
"] -
8 (10) - h
1504
OLMC 17
XOR-2053
ACI-2125
0- 17 (20)

1536
-=- IJ
9 (11) .--..
......,
1760
go
a=
OLMC 16
XOR-2054
ACI-2126
0- 16 (19)

1792
1 -
0--
:Q:: OLMC 15 15 (18)
go
10 (12) .--..
'--'
.. 2016

I-FfR
XOA-2055
ACl-2127

64 USER SIGNATURE FUSES 21 91 ........ OE '-' 13 (16)

SYN-2192
ACO-2193
M l
TC - 2194
S S
B B

2·125 4191_Rev_A
[JJ
1...1
LatUce
Semiconductor
Corporation
GP

Specifications ispGAL 16ZB

COMPLEX MODE
In the Complex mode, macrocells are configured as output only pability. Designs requiring eight liO's can be implemented in the
or 1/0 functions. Registered mode.

Architecture configurations available in this mode are similar to All macrocells have seven product terms per output. One product
the common 16L8 and 16P8 devices with programmable polarity term is used for programmable output enable control. Pins 1 and
in each macrocell. 13 are always available as data inputs into the AND array.

Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD
outputs can be implemented as subsets of the I/O function. The fuses are shown on the logic diagram on the following page.
two outer most macrocells (pins 15 & 22) do not have input ca-

...............................................
'
,,,
,
,,, Combinatorial 110 Configuration for Complex Mode

rl - SYN=1.
-ACO.1.
- XOR ..Odefines Active Low Output.
- XOR-1 defines Active High Output.
-AC1=1.
- Pins 16 through Pin 21 are configured to this function.
,........................................................,

f .... ·........ ······· . ·· . ·········· . ······ ......: Combinatorial Output Configuration for Complex Mode

!
;
PeD XOR
· tL-o - SYN-1.
-ACO.1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
-AC1=1.
- Pins 15 and Pin 22 are configured to this function.
t ...............................................!

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

2-126 4191.Rev.A
..LJ CorporaUon
Semiconducwr Specifications ispGAL 16Z8

COMPLEX MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts

1 (2) -- ...
0 4 8 12 t6 20 24 28

I.l...
-
0000 _

OLMC 22 ....... 22 (26)


==
--
0224 XOR-2048
3 (4) AC .'''0

I.l.
0256
.......
ouo==
::8::::::

415) '-"
= OLMC 21
XOR-20H
AC1- 212'
J- 2, (25)

0512
=
=
.;:;
OLMC 20 n. .......- 20 (24)

5 (6) - = XOR·20S0
AC,·2'22

I.l....
0768

OLMC 19 ........... 19 (22)

6 (7) -- 0992= -c- XOR·205'


AC,·2,23

,024 _
.n- h
719) '-"
1248
OLMC 18
XOR-2052
AC1-2'24
U- '8 (2')

h ...
--......
'280 ....
:: OLMC 17 17 (20)
=
, 504= XOR·2053
8110) D AC'·2'25

I.l...
1536
= OLMC 16 -C '6(18)
1760 :: ..... XOR-20S.
AC,·2126
9 (11) '-'

1792

OLMC 15
I.l... -....... 15 (18)
2016 XOR· 2055

Ifl
I!i::'
10 (12) D AC'·2127
.,...., '3 (16)

2'91
U USER SIGNATURE FUSES
SYN-2192
ACO·2193

··• .•
TC • 2194

2-127 4/91.Rev.A
[JJLattiOO*
.J..j Semiconductor
CorporaUon
Specifications ispGAL 16Z8

SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated in- Pins 1 and 13 are always available as data inputs into the AND
puts or as dedicated, always active, combinatorial outputs. array. The center two macrocells (pins 18 & 19) cannot be used
in the input configuration.
Architecture configurations available in this mode are similar to
the common 10L8 and 12P6 devices with many permutations The JEDEC fuse numbers including the UES fuses and PTD
of generic output polarity or input choices. fuses are shown on the logic diagram.

All outputs in the simple mode have a maximum of eight prod-


uct terms that can control the logic. In addition, each output has
programmable polarity.

l·································· __ ····· __ ·· Combinatorial Output Configuration for Simple Mode


Vee
- SYN-1.
-ACO.O.
- XOR.O defines Active Low Output.
- XOR.1 defines Active High Output.
- AC1.0 defines this configuration.
- All OLMCs can be configured to this configuration.
. . - Pins 18 & 19 are permanently configured to this
=---............................................................. .: function.

..- ............ ---- ............................ Dedicated Input Configuration for Simple Mode

- SYN.1.
-ACO.O.
- XOR.O defines Active Low Output.
- XOR.1 defines Active High Output.
- AC1.1 defines this configuration.
- All OLMCs except pins 18 & 19 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

2-128 4/91.Rev.A
.l.J Corporation
Semiconductor Specifications ispGAL 16Z8

SIMPLE MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts I

1 (2)
....... ...
v
0 4 8 12162024 28

0000
OLMC 22
XOR-2048
IJ - 22 (26)
0224 ACl-2120
3 (4) D-

0256
OLMC 21
h... rO
....
13= XOR-2049 21 (25)
0480 ACl-2121
4 (5) D

IJ...
-
0512
;::;. OLMC 20
1-
XOR-2050 20 (24)
0736 ACl-2122
5 (6) 0

I.l -
-
0768
OLMC 19
XOR-2051 v 19 (22)
0992 ACl-2123
6 (7) 0

1024
OLMC 18
XOR-2052
IJ... - 18 (21)
1248 't:J= ACl-2124
7 (9) 0

1280
= OLMC 17
XOR-2053
IJ... ..... 17 (20)
1504 ACl-2125
8 (10) 0

9 (11)
1536

1760
OLMC 16
XOR-2054
ACl-2126
IJ... -
-- 16 (19)

1792
OLMC 15
XOR-2055
11... -..... 15 (18)
2016 ACl-2127
10 (12) I".:) I- '--' 13 (16)

2191
64 USER SIGNATURE FUSES

., .,
SYN-2192
• L ACO-2193
TC - 2194

2-129 4/91_Rev_A
Specifications ispGAL 16Z8
.J"J CorporaUon
Semironductor
Commercial

ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo

Supply voltage Voo ........................................ -0.5 to +7V Ambient Temperature (TAl ............................. 0 to +75°C
Input voltage applied ....................... -2.5 to Vee +1.0V Supply voltage (Veel
Off-state output voltage applied ........... -2.5 to Vee +1.0V with Respect to Ground ..................... +4.75 to +5.25V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1 . Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP." MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V

VIH Input High Voltage 2.0 - Vee+1 V

IlL Input or 110 Low Leakage Current OV S Y,N S V,l (MAX.) - - -10 IlA
IIH Input or VO High Leakage Current V,H S Y,N s Vee - - 10 IlA
VOL Output Low Voltage 10L- MAX. Yin .. V,L or V,H - - O.S V

VOH Output High Voltage 10H-.MAX. Yin =V,L or V,H 2.4 - - V

10L Low Level Output Current - - 24 mA

10H High Level Output Current - - -3.2 mA

los' Output Short Circuit Current Vee =SV VOUT =O.SV TA = 2S·C -30 - -1S0 mA
ICC Operating Power Supply Current VIL.O.SV VIH -3.0V - 7S 90 mA
ftoggle .. 1SMhz Outputs Open
1) One output at a time for a maximum duration of one second. Vout .. O.SV was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vee .. SV and TA - 2S ·C

CAPACITANCE (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS

CI Input Capacitance 8 pF Vee = S.OV, V, = 2.0V

ClIO 1/0 Capacitance 10 pF Vee = S.OV. VIIO = 2.0V


"Guaranteed but not 100% tested.

2-130 4191.Rev.A
'L Semironductor
Corporation
Specifications ispGAL 16Z8
Commercial
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
·20 ·25
TEST DESCRIPTION UNITS
PARAMETER
COND.' MIN. MAX. MIN. MAX.
tpd 1 Input or I/O to Combinational Output 3 20 3 25 ns

teo 1 Clock to Output Delay 2 15 2 15 ns

tsu - Setup lime, Input or Feedback before Clocki 15 - 20 - ns


th - Hold lime, Input or Feedback after Clocki 0 - 0 - ns
1 Maximum Clock Frequency with 33.3 - 28.5 - MHz
fmax 2 External Feedback, 1/(tsu + teo)
1 Maximum Clock Frequency with 41.6 - 33.3 - MHz
No Feedback

twh 3 - Clock Pulse Duration, High 12 - 15 - ns


twl3 - Clock Pulse Duration, Low 12 - 15 - ns
ten 2 Input or 110 to Output Enabled - 20 - 25 ns
2 OE! to Output Enabled - 18 - 20 ns

tdis 3 Input or I/O to Output Disabled - 20 - 25 ns


3 OEi to Output Disabled - 18 - 20 ns

I) Refer to Switching Test Conditions section.


2) Refer to fmax Description section.
3) Clock pulses of widths less than the specification may be detected as valid clock signals.

SWITCHING TEST CONDITIONS

Input Pulse Levels GNDto3.0V


Input Rise and Fall limes 3ns 10%-90%
+5V
Input liming Reference Levels 1.5V
Output liming Reference Levels 1.5V
Output Load See Figure

3-state levels are measured 0.5V from steady-state active


eve!. FROM OUTPUT (0/0) --+---......- TEST POINT
UNDER TEST
:>utput Load Conditions (see figure) Cl
R2
Test Condition RI Rz CL

1 200n 390n 50pF


2 Active High
Active Low
-
200n
390n
390n
50pF
50pF CllNCLUDES JIG AND PR08E TOTAL CAPACITANCE

3 Active High
Active Low
-
200n
390n
390n
5pF
5pF

2·131 4/91.Rev.A
.l..i Corporation
Semironductnr Specifications ispGAL 16Z8

SWITCHING WAVEFORMS

INPUT or INPUT or
110 FEEDBACK 110 FEEDBACK

COMBINATORIAL CLK
OUTPUT \\""I"T"'<""S\
t"T"'I'""T\\

REGISTERED
OUTPUT
Combinatorial Output

INPUT or Reg Istered Output


I/O FEEDBACK

OUTPUT OE

Input or 110 to Output Enable/Disable


OUTPUT

OE to Output Enable/Disable
twl

ClK

Clock Width

fmax DESCRIPTIONS

................................................................ ClK

LOGIC
REGISTER
ARRAY LOGIC
ARRAY

10IIII/00II1---- to u leo--+l
fmax With No Feedback
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is cal·
culated from measured tsu and teo.

2-132 4/91.Rev.A
.l.J Corporation
Semiconductor Specifications ispGAL 16Z8
I

ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD


An electronic signature (ES) is provided as part of the When testing state machine designs, all possible states and state
ispGAL 16Z8 device. It contains 64 bits of reprogrammable mem- transitions must be verified in the design, not just those required
ory that can contain user defined data. Some uses include user in the normal machine operations. This is because, in system
10 codes, revision numbers, or inventory control. The signature operation, certain events occur that may throw the logic into an
data is always available to the user independent of the state of illegal state (power-up, line voltage glitches, brown-outs, etc.).
the security cell. To test a design for proper treatment of these conditions, a way
must be provided to break the feedback paths, and force any
NOTE: The ES is included in checksum calculations. Chang- desired (Le., illegal) state into the registers. Then the machine
ing the ES will alter the checksum. can be sequenced and the outputs tested for correct next state
conditions.
SECURITY CELL The ispGAL 16Z8 devices include circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus,
The security cell is provided on the ispGAL16Z8 device to prevent any state condition can be forced for test sequencing.
unauthorized copying of the logic pattern. Once programmed,
this cell prevents further read access to the functional bits in the
device. The cell can only be erased by re-programming the INPUT BUFFERS
device, so the original configuration can never be examined once
this cell is programmed. Signature data is always available to
The ispGAL16Z8 devices are designed with TIL level compatible
the user.
input buffers. These buffers, with their characteristically high im-
pedance, load the driving logic much less than traditional bipolar
LATCH-UP PROTECTION devices. Because the inputs are connected to a CMOS gate,
there is no inherent pull-up structure, as there is with bipolar de-
The ispGAL16Z8 devices are designed with an on-board charge vices. Therefore, they cannot be depended on to float high (or
pump to negatively bias the substrate. The negative bias is of to any particular state), and must be tied to the desired logic state.
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with n- Unused inputs and tri-stated I/Os should no.t be left floating.
channel pullups instead of the traditional p-channel pullups to Lattice recommends that they be connected to Vee, Ground, or
eliminate any possibility of SCR induced latching. another driven input. Doing so will tend to increase noise immunity
and reduce Icc for the device.

TCCELL
The ispGAL16Z8 devices are equipped with a TC (Tri-State
Control) cell which controls the state of the outputs when the
device is being programmed. Since the device is programmed
while on the circuit board, and connected to other devices, the
state of the outputs is very important. Depending on how the TC
cell is programmed, the outputs will either be tri-stated or latched
upon entering the programming/diagnostic mode.

2-133 4/91.Rev.A
Semiconductor Specifications ispGAL 16Z8
Corporation

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Tri-S1ale
Control

:CIr.... :
i................. .l
u •• PIN
PIN

Feedback
(To Input BuHer)

Input Output

POWER-UP RESET

Vee
ov
VIH
eLK VALID CLOCK SIGNAl
VIL

INTERNAL INTERNAL REGISTER


REGISTER RESET TO LOGIC 0
Q-OUTPUT

OUTPUT PIN

Circuitry within the ispGAL 16Z8 provides a reset signal to all The timing diagram for power-up is shown above. Because of
registers during power-up. All internal registers will have their asynchronous nature 01 system power-up, some conditions must
Q outputs set low after a specified time (t AESIiT ' 45I1S MAX). As be met to guarantee a valid power-up reset. First, the Vex; rise
a result, the state on the registered output PinS (if they are en-' must be monotonic. Second, the clock input must become a
abled through OE) will always be high on power-up, regardless proper TTL level within the specified time 100ns MAX). The
of the programmed polarity 01 the output pins. This feature can registers will reset within a maximum 01 time. As in nor-
greatly simplify state machine design by providing a known state mal system operation, avoid clocking the device until all input
on power-up. and feedback path setup times have been met.

2-134 4191.Rev.A
Section 1: Introduction to Generic Array Logic 1
Introduction to Generic Array Logic 1-1

Section 2: GAL Datasheets 2


Datasheet Levels 2-ii
GAL16V8A1B 2-1
GAL20V8A1B 2-25
GAL18V10 2-47
GAL22V10/B 2-61
GAL26CV12 2-81
GAL20RA10 2-95

..
GAL6001 2-109
ispGAL16Z8 2-121

Section 3: GAL Military Products


Military Program Overview 3-1 I
MIL-STD-883C Flow 3-2
Military Ordering Information 3-3
GAL 16V8A1B Military Datasheet 3-5
GAL20V8A Military Datasheet 3-13
GAL22V10/B Military Datasheet 3-19
GAL20RA 10 Military Datasheet 3-27

Section 4: Quality and Reliability


Quality Assurance Program 4-1 4
Qualification Program 4-3
FCMOS Testability Improves Quality 4-5

Section 5: Technical Notes


GAL Metastability Report 5-1 5
Latch-up Protection 5-17

Section 6: Article Reprints


Avoid the Pitfalls of High-Speed Logic Design 6-1 6
Extending the 22V1 0 EPLD 6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6-9
Multiple Factors Define True Cost of PLDs 6-13

Section 7: General Information


Development Tools 7-1
Copyil\lg PAL, EPLD & PEEL Patterns into GAL Devices 7-3
7
GAL Product Line Cross Reference 7-5
Package Thermal Resistance 7-8
Package Diagrams 7-9
Tape-and-Reel Specifications 7-16
Sales Offices 7-17

3-i
3-ii
Military Program
OvelView
CORPORATE PHILOSOPHY MIL-STD-883C COMPLIANCE
Lattice Semiconductor is committed to leadership in MIL-STD-883C provides a uniform and precise method
performance and quality. Our family of military GAL for environmental, mechanical and electrical testing which
devices is consistent with this philosophy. Lattice ensures the suitability of microelectronic devices for use
manufactures all devices under strict Quality Assurance in military and aerospace systems. Table I summarizes
guidelines. All grades, Commercial through Military 883C, the MIL-STD-883C, Class B flow. Table /I summarizes
are monitored under a quality program conformant to M IL- the conformance testing required by MIL-STD-883C,
M-3851 0 Appendix A with inspections conformant to MIL- Method 5005, for quality conformance testing of Lattice
1-45208. military microcircuits.

Lattice Semiconductor has been manufacturing GAL MIL-M-38510


devices since 1984. The engineering analysis and MIL-M-3851 0, when used in conjunction with MIL-STD-

III
characterization during this time has been focused into 883C, defines design, packaging, material, marking,
our current design, process and manufacturing test sampling, qualification and quality system requirements
procedures to assure superior product which meet all for military devices.
I
datasheet and quality goals.
GROUP DATA
Complete review of the procedures and technical data Group A and B data is taken on every inspection lot per
can be arranged at our facility near Portland, Oregon. MIL-STD-883C, Class B requirements. This data, along
Factory audits of our documentation and processes are with Generic Group C and D data can be supplied, upon
also welcomed. written request, with your device shipment. Your Lattice
sales representative can advise you of charges and
QUALITY AND TESTABILITY leadtime necessary for providing this data.
Lattice Semiconductor processes its GAL devices to strict
conformance with MIL-STD-883C Class B. In conjunction STANDARD MILITARY DRAWINGS
with the military flow, the inherent testability of E2CMOS Lattice actively supports the DESC Standard Military
technology allows Lattice to achieve a quality level superior Drawing (SMD) Program. The SMD Program offers a cost
to other PLD technologies. effective alternative to source control drawings and
provides standardized product
All GAL devices are patterned and tested dozens of times specifications to simplify military procurement.
throughout the manufacturing flow. Every GAL device is
tested under worst case configurations to assure Lattice recognizes the growing demand for SMD qualified
customers achieve 100% yields. Tests are performed devices, and in response, all new 883C product released
using the same E2 cell array that will be used for the final by Lattice will be submitted to DESC for SMD qualification.
patterning of the devices. This 100% "actual test" Customers may facilitate this process by submitting a
philosophy does away with the correlated and simulated "Nonstandard Part Approval Request", DD Form 2052, to
testing that is necessary with bipolar and UV (EPROM) DESC. This form allows you to recommend to DESC the
based PLD devices. qualification of Lattice devices to SMD status.

RELIABILITY A list of currently available SMD qualified devices is


Lattice Semiconductor performs extensive reliability testing provided (see Military Ordering Information). Contact
prior to product release. This testing continues in the form your local Lattice sales representative forthe latest status
of Reliability Monitors that are run on an ongoing basis to of SMD qualifications in process with DESC.
assure continued process integrity. A formal, written
report of these test results is updated regularly and can be
obtained from your local Lattice Sales Representative.

The reliability testing performed includes extensive analysis


of fundamental design and process integrity. The
reprogrammable nature of GAL devices allows for an
inherently more thorough reliability evaluation than other
programmable alternatives.

3-1
Military Program Overview

MILIT ARY SCREENING FLOW MILITARY QUALITY CONFORMANCE


(TABLE I) INSPECTIONS (TABLE II)

Screen Method Requirement Subgroup Method I Sample


I Internal Visual 2010 Cond. B 100% I GROUP A: Electrical ests
Temp. Cycling 1010Cond. C 100% Subgroups " 7, 9 Applicable Device Spec. LTPD = 2
Constant Acceleration 2001 Condo E 100% Electricel Test 25°C
Hermeucity 1014 100% Subgroups 2, 8A, 10 Applicable Device Spec. LTPD= 2
Fine Cond.AorB Electrical Test Max. Operating Temp.
Gross Cond.C Subgroups 3, 88, 11 Applicable Device Spec. LTPD=2
Endurance Test 1033 100% Electrical Test Min. Operating Temp.
Retention Test Unbiased Bake 100% GROUP B: Mechanical Tests
48 HRS. Subgroup 2 4(0)
TA= 150°C Solvent Resistance 2015
Pre Bum-In Electrical Applicable Device 100% Subgroup 3 LTPD=10
Specification Solderability 2003
Tc= 2500 Subgroup 5 LTPD= 15
Dynamic Bum-In 1015Cond. D 100% Bond Strength 2011
Post Bum-In Electrical Applicable Device 100% I GROUP C: Chip Integrity Tests
Specification Subgroup 1
Tc = 2500 Dynamic Ufe Test 1005,1,000 HRS. 12500 LTPD=5
PDA=5% End Point Electrical Applicable Device Spec.
Final Electrical Test Applicable Device 100% Subgroup 2
Specification Unbiased Retention 1,000 HRS. 150·C LTPD=5
Tc= 125°C End Point Electrical Applicable Device Spec.
Final Electrical Test Applicable Device 100% GROUP D: EnvironmentallntearHv
Specification Subgroup 1 LTPD= 15
Tc = -5500 Physical Dimensions 2016
External Visual 2009 100% Subgroup 2 LTPD=5
CCI Sample Selection MIL-M-38510H Sample Lead Integrity 2004, Condo B
Sec. 4.5 and Hermeticity 1014
MIL-STD-883C Subgroup 3 LTPD= 15
Sec. 1.2 Thermal Shock 1011, Condo B, 15 Cycles
Temp. Cycle 1010, Condo C, 100 Cycles
Moisture Resistance 1004
Hermeticity 1014
Visual Examination 1004, 1010
Endpoint Electrical Applicable Device Spec.
Subgroup 4 LTPD = 15
Mechanical Shock 2002,Cond.B
Vibration 2007,Cond.A
Constant Acceleration 2001, Cond. E
Hermeticity 1014
Visual Examination 1010, 1011
Endpoint Electrical Applicable Device Spec.
Subgroup 5 LTPD = 15
Salt Atmosphere l009,Cond.A
Hermeticity 1014
Visual Examination 1009
SubgroupS 3(0)
Intemal Water Vapor 1018 < 5,000 PPM, loo·C
Subgroup 7 LTPD=15
Lead Finish Adhesion 2025
Subgroup 8 5(0)
Lid Torque 2024

3-2
I:
Military Ordering
InfolJnation
Lattice offers the most comprehensive line of military to use the SMD number, where it exists, when ordering
E2CMOS Programmable Logic Devices. Lattice parts. Listed below are Lattice's military qualified devices
,ecognizes the trend in militarydeviceprocurementtowards and their corresponding SMD numbers. Please contact
JsingSMDcompliantdevicesandencouragescustomers your local Lattice representative for the latest product
listing.

Military Products Selector Guide


DEVICE TYPE Tpd Icc PACKAGE LATTICE PART # SMD#
(n8) (mA)
10 130 20-Pin CEROIP GAL 16V8B-l OLOI883C 5962-8983904RA
130 20-Pin LCC GAL16V8B-l OLRl883C 5962-89839042A
15 130 2O-Pin CEROIP GAL 16V8A-15LOI883C 5962-8983903RA
130 20-Pin LCC GAL 16V8A-15LRI883C 5962-89839032A
20 65 20-Pin CEROIP GAL 16VBA-2000/BB3C 5962-8983906RA
65 20-Pin LCC GAL 16VBA-200Rl883C 5962-89839062A
GAL16V8
130 20-Pin CEROIP GAL 16VBA-20LOI883C 5962-8983902RA
130 20-Pin LCC GAL 16V8A-20LRl883C 5962-89839022A
25 65 20-Pin CERDIP GAL 16V8A-25001883C 5962-8983905RA
65 2O-Pin LCC GAL 16V8A-250Rl883C 5962-89839052A
30 130 20-Pin CERDIP GAL 16V8A-30LOI883C 5962-8983901RA
130 20-Pin LCC GAL 16V8A-30LRl883C 5962-89839012A
15 130 24-Pin CERDIP GAL2OV8A-15LOI883C 5962-8984003LA
130 28-Pin LCC GAL20VBA-15LRlB83C 5962-89840033A
20 65 24-Pin CERDIP GAL2OVBA-2000/883C Contact Factory
65 28-Pin LCC GAL2OVBA-200RlBB3C Contact Factory
130 24-Pin CERDIP GAL2OV8A-20LD/B83C 5962-8984002LA
GAL20V8
130 28-Pin LCC GAL2OVBA-20LRlB83C 5962-89840023A
25 65 24-Pin CEROIP GAL2OVBA-2500/BB3C Contact Factory
65 28-Pin LCC GAL2OV8A-250RI8B3C Contact Factory
30 130 24-Pin CEROIP GAL2OV8A-30LD/B83C 5962-8984001 LA
130 28-Pin LCC GAL2OV8A-30LRl883C 5962-89840013A
15 150 24-Pin CERDIP GAL22Vl0B-15LO/BB3C 5962-8984103LA
150 28-Pin LCC GAL22V10B-15LR1883C 5962-89841033A
20 150 24-Pin CEROIP GAL22V10-20L01883C 5962-8984102LA
150 28-Pin LCC GAL22V10-20LRI883C 5962-89841023A
GAL22V10
25 150 24-Pin CEROIP GAL22V10-25LDI883C 5962-8984104LA
150 28-Pin LCC GAL22V10-25LRlB83C 5962-89841043A
30 150 24-Pin CEROIP GAL22Vl0-30LOI883C 5962-B984101 LA
150 28-Pin LCC GAL22Vl0-30LRlB83C 5962-89841013A
20 120 24-Pin CEROIP GAL20RA 10-20L0/883C Contact Factory
120 28-Pin LCC GAL20RA 10-20LRlB83C Contact Factory
GAL20RA10
25 120 24-Pin CEROIP GAL20RA 10-25LO/B83C Contact Factory
120 2B-Pin LCC GAL20RA 10-25LRI883C Contact Factory

3-3
Military Ordering Infonnation
DESC Standard Military Drawing Listing
SMD# LATTICE PART # SMD# LATTICE PART,
5962-89839012A 5962-8984001 LA
5962-8983901 RA 5962-89840023A
5962-89839022A 16VaA-20LRV883C 5962-8984002LA
5962-8983902RA 16VSA-20LD1883C 5962-8984OO33A
5962-89839032A 16VaA-15LRI883C 5962-8984003LA
5962-8983903RA 16VSA-.15LD1883C 5962-89841013A 0-30LRI883C
5962-89839042A 16VSB-10LRl883C 5962-8984101 LA O-30LDI883C
5962-8983904RA 5962-89841023A O-20LRI883C
5962-S9839052A 16VaA-25QRV883C 5962-8984102LA O-20LDI883C
5962-8983905RA 16VaA-25QDI883C 5962-89841033A
5962-S9839062A 16VSA-2OQRV883C 5962-8984103LA GAL22V10B-15LDI8S3C
5962-8983906RA 16VaA-2OQD1883C 5962-89841043A 0-25LRI883C
5962-89840013A 5962-8984104LA 0-25LD1883C

Standard Military Drawing Number Description

f Lead Finish
• A = Solder dipped

Package Type
R = 2O-1ead CERDIP
L 24-lead CERDIP
2 - 2O-pin LCC
3 = 28-pin LCC

Device Type

Drawing Number
• no other lead finish aJrrently available.

3-4
!IJ
l.J
:Lattice®
Semiconductor
Corporation
GAL 16V8BI883C
GAL 16V8AI883C
High Performance E2CMOS PLD
FEATURES FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE EICMOS- TECHNOLOGY


-10 ns Maximum Propagation Delay 20 J
- Fmax =62.5 MHz
- 7 ns Maximum from Clock Input to Data Output 19
- TTL Compatible 24 mA Outputs 2
- UltraMOS- Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR 18
- 7SmA 1\'p Icc on Low Power Device 3
- 4SmA Typ Icc on Quarter Power Device

..
17
• ACTIVE PULL·UPS ON ALL PINS (GAL16V8B)
4
• EI CELL TECHNOLOGY
- Reconflgurable Logic 16
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention 15

• EIGHT OUTPUT LOGIC MACROCELLS


- Maximum FlexlbllHy for Complex logic Designs 14
- Programmable Output Polarity
- Also Emulates 2()..pln PAL- Devices with Full Func· 7
tlon/Fuse Map/Parametric Compatibility
13
• PRELOAD AND POWER·ON RESET OF ALLREGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE: 12
- DMA Control
- State Machine Control 11
- High Speed Graphics Processing
- Stand,ard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION PIN CONFIGURATION
The GAL16V8B1883C and GAL16V8A1883C are high perfor-
mance E2CMOS programmable logic devices processed in full CERDIP
compliance to MIL-STD-883C. These military grade devices
combine a high performance CMOS process with Electrically LCC IICLK Vee
Erasable (E2) floating gate technology to provide the highest
speed/power performance available in the 883C qualified PLD IIOIQ

market. The GAL16V8B1883C, at 1Ons maximum propagation I K:LK Voo rotQ


1/010
delay time, is the world's fastest military qualified CMOS PLD. 10
CMOS circuitry allows the GAL 16V8A quarter power devices to rotQ IIOIQ
consume just 45mA typical Icc, which represents a 75% savings IIOIQ
VOIQ
in power when compared to bipolar counterparts.
GAL16V8A1B VOIQ 110/0
Generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by Top View rotQ IIOIQ
the user. The GAL 16V8A1883C and GAL16V8B/883C are
capable of emulating all standard 20-pin PAL- devices with full VOIQ IIOIQ

functionlfuse map/parametric compatibility. IIOIQ


I GND rOE VOIQ VOIQ
Unique test circuitry and reprogrammable cells allow complete GND v6E
AC, DC, and functional testing during manufacture. Therefore,
Lattice guarantees 100% field programmability and functionality
of all GAL products. Lattice also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.
Copyright CI991 Lattice Semiconductor Corp, GAl, E'CMOS and UhraMOS are registered trademarks 01 Lattice SemiconduC1or Corp. Generic Array Logic is a trademark 01 Lattice Semiconduc·
tor Corp. PAL Is a registered trademark 01 Advanced Micro Devices. Inc. The specifications and Information herein are subject to chango wtthout notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A. April 1991.Rev.A
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503)681-3037
3·5
[lJ
LJ
tatUoo*
Semironductor
Corporation
Specifications GAL 16V8B 1883C

ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDo


Supply voltage Vex; .......................................-0.5 to +7V Case Temperature (Tc> .............................. -55 to 125°C
Input voltage applied .•............•..•......... -2.5 to Vex; +1.0V Supply voltage (Vex;l
Off-state output voltage applied .......... -2.5 to Vex; +1.0V with Respect to Ground ...................... +4.50 to +5.50V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................-55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.· MAX. UNITS

VIL Input Low Voltage Vss-O.5 - 0.8 V


VIH Input High Voltage 2.0 - VCC+1 V
IlL' Input or 110 Low Leakage Current OV S VIN S VIL (MAX.) - - -100
IIH Input or 110 High Leakage Current 3.SV S VIN S Vee - - 10
VOL Output Low Voltage 1oL= MAX. Yin = VIL or VIH - - 0.5 V
VOH Output High Voltage 10H = MAX. Yin = VIL or VIH 2.4 - - V
10L Low Level Output Current - - 12. mA
10H High Level Output Current - - -2 mA
los2 Output Short Circuit Current Vee-SV VOUT .. O.SV T,,_2So C -30 - -150 mA
Icc Operating Power Supply Current VIL= O.SV VIH =3.0V ftoggle = 25 MHz - 75 130 mA
Outputs Open (no load)
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. SV and TA .. 25 °C

CAPACITANCE (TA =25°C, f =1.0 MHz)


SYMBOL PARAMETER MAXIMUM" UNITS TEST CONDITIONS
CI Input Capacitance 10 pF Vcc. S.OV. VI = 2.0V
Coo 110 Capacitance 10 pF Vcc =S.OV. V110 .. 2.0V
'Guaranteed but not 100% tested.

3-6 4191.Rev.A
[IJ
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tattiooGP
Semironductor
Caporat/oo
Specifications GAL 16VBB I883C

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

TEST ·10
PARAMETER DESCRIPTION UNITS
COND'. MIN. MAX.
tpd 1 Input or 110 to Combinational Output 2 ,0 ns

teo 1 Clock to Output Delay 1 7 ns

tcf2 - Clock to Feedback Delay - 7 ns

tsu - Setup 1ime, Input or Feedback before Clockt 10 - ns

th - Hold 1ime, Input or Feedback after Clockt 0 - ns


1 Maximum Clock Frequency with 58.8 - MHz
External Feedback, 1/(tsu + teo)

fmax 3 1 Maximum Clock Frequency with 58.8 - MHz


Internal Feedback, 1/(tsu + tel)

1 Maximum Clock Frequency with 62.5 - MHz


No Feedback

twh4 - Clock Pulse Duration, High 8 - ns

twl' - Clock Pulse Duratioo, Low 8 - ns

ten 2 Input or 110 to Output - 10 ns


2 OEJ.. to Output - 10 ns

tdis 3 Input or 110 to Output