Combinational Logic Design

• Introduction
• Boolean Equations
• Boolean Algebra
• From Logic to Gates
• From Gates to Transistors
• X’s and Z’s
• Karnaugh Maps
• Combinational Building Blocks
• Timing
Chap 2

LINFO 1140 - Combinational Logic Design 1

 Introduction
• A logic circuit is composed of : functional spec
inputs outputs
– Inputs timing spec
– Outputs
– Functional specification Nodes
• Inputs: A, B, C
n1
– Timing specification A E1 • Outputs: Y, Z
• Internal: n1
B E3 Y
Circuit elements
C E2 Z • E1, E2, E3
• Types of Logic Circuits • Each a circuit

– Combinational Logic
» Memoryless
» Outputs determined by current values
of inputs
– Sequential Logic
» Has memory
» Outputs determined by previous and Example of combinational composition
• Every element is combinational
current values of inputs • Every node is either an input or connects
to exactly one output
• The circuit contains no cyclic paths

LINFO 1140 - Combinational Logic Design 2

 Boolean Equations

• Functional specification of outputs in terms of

inputs
A
C S
B L
• Some definitions Cout
Cin
– Complement : variable with a bar over it
S = A ⊕ B ⊕ Cin
» A, B, C
Cout = AB + ACin + BCin
– Literal : variable or its complement
» A, A, B, B, C, C
– Implicant : product of literals
» ABC, AC, BC
– Minterm : product that includes all input variables
» ABC, ABC, ABC

LINFO 1140 - Combinational Logic Design 3

• Sum-of-Products (SOP) Form

– All equations can be written in SOP form

– Each row has a minterm
– A minterm is a product (AND) of literals
– Each minterm is TRUE for that row (and only that row)
– Form function by ORing minterms where output is 1
– Thus, a sum (OR) of products (AND terms)

minterm
A B Y minterm name
0 0 0 A B m0
0 1 1 A B m1
1 0 0 A B m2
1 1 1 A B m3

Y = F(A, B) = AB + AB = Σ(1, 3)

LINFO 1140 - Combinational Logic Design 4

 Boolean Algebra

• Axioms and theorems to simplify Boolean equations

• Like regular algebra, but simpler: variables have only two
values (1 or 0)
• Duality in axioms and theorems:
– ANDs and ORs, 0’s and 1’s interchanged

• Axioms

Number Axiom Dual Name

A1 B = 0 if B ≠ 1 B = 1 if B ≠ 0 Binary Field
A2 0 = 1 1 = 0 NOT
A3 0 • 0 = 0 1 + 1 = 1 AND/OR
A4 1 • 1 = 1 0 + 0 = 0 AND/OR
A5 0 • 1 = 1 • 0 = 0 1 + 0 = 0 + 1 = 1 AND/OR

LINFO 1140 - Combinational Logic Design 5

• Theorems of One Variable

Number Theorem Dual Name

T1 B • 1 = B B + 0 = B Identity
T2 B • 0 = 0 B + 1 = 1 Null Element
T3 B • B = B B + B = B Idempotency
T4 B = B Involution
T5 B • B = 0 B + B = 1 Complements

B B B B
1 = B 0 = 0 B = B B = 0

B B B
0 = B 1 = 1 B = B B
B = 1

B = B

LINFO 1140 - Combinational Logic Design 6

• Theorems of Several Variables

# Theorem Dual Name

T6 B•C = C•B B+C = C+B Commutativity
T7 (B•C) • D = B • (C•D) (B + C) + D = B + (C + D) Associativity
T8 B • (C + D) = (B•C) + (B•D) B + (C•D) = (B+C) (B+D) Distributivity
T9 B • (B+C) = B B + (B•C) = B Covering
T10 (B•C) + (B•C) = B (B+C) • (B+C) = B Combining
T11 (B•C) + (B•D) + (C•D) = (B+C) • (B+D) • (C+D) = Consensus
(B•C) + (B•D) (B+C) • (B+D)

LINFO 1140 - Combinational Logic Design 7

• Prove

– Example : T9 - Covering Number Theorem Name

T9 B• (B+C) = B Covering

» Method 1: Perfect Induction

B C (B+C) B(B+C)
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1

» Method 2: Prove true using other axioms and theorems

B•(B+C) = B•B + B•C T8: Distributivity

= B + B•C T3: Idempotency
= B•(1 + C) T8: Distributivity
= B•(1) T2: Null element
=B T1: Identity

LINFO 1140 - Combinational Logic Design 8

• De Morgan’s Theorem

# Theorem Dual Name

T12 B0•B1•B2… = B0+B1+B2… = DeMorgan’s
B0+B1+B2… B0•B1•B2… Theorem

• Y = AB = A + B A
Y
B

A
Y
B

• Y = A + B = A B A
B
Y

A
Y
B

LINFO 1140 - Combinational Logic Design 9

• De Morgan’s Theorem Examples

Y = (A+BD)C Y = (ACE+D) + B
= (A+BD) + C = (ACE+D) • B
= (A•(BD)) + C = (ACE•D) • B
= (A•(BD)) + C = ((AC+E)•D) • B
= ABD + C = ((AC+E)•D) • B
= (ACD + DE) • B
= ABCD + BDE

LINFO 1140 - Combinational Logic Design 10

• Bubble Pushing

– Backward:
» Body changes A A
Y Y
B B
» Adds bubbles to inputs

– Forward:
» Body changes A A
Y Y
» Adds bubble to output
B B

– Rules
» Begin at output, then work toward inputs
» Push bubbles on final output back
» Draw gates in a form so bubbles cancel

A
B

C Y
D

LINFO 1140 - Combinational Logic Design 11

 A
B

C Y
D

no output
A bubble
B

C Y
D

bubble on
A input and output
B

C Y
D
no bubble on
input and output
A
B

C Y
D
Y = ABC + D

LINFO 1140 - Combinational Logic Design 12

• Simplifying Equations
– Reducing an equation to the fewest number of implicants, where
each implicant has the fewest literals
– Trial and Error approach

– Examples : Recall: A’ = A

Y = A(AB + ABC)
= A(AB(1 + C)) T8: Distributivity
= A(AB(1)) T2’: Null Element
= A(AB) T1: Identity
= (AA)B T7: Associativity
= AB T3: Idempotency

Y = AB’C + ABC + A’BC

= AB’C + ABC + ABC + A’BC T3’: Idempotency
= (AB’C+ABC) + (ABC+A’BC) T7’: Associativity
= AC + BC T10: Combining

LINFO 1140 - Combinational Logic Design 13

 From Logic to Gates
• Two-level logic: ANDs followed by ORs
• Example: Y = ABC + ABC + ABC
A B C

A B C
minterm: ABC

minterm: ABC

minterm: ABC

wires crossing
wires connect wires connect without a dot do
at a T junction at a dot not connect

LINFO 1140 - Combinational Logic Design 14

 A3 A2 A1 A0 Y3 Y2 Y1 Y0
• Example : Priority Circuit 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 0
A3 0 1 0 0 0 1 0 0
Y3
0 1 0 1 0 1 0 0
0 1 1 0 0 1 0 0
A2 Y2
0 1 1 1 0 1 0 0
1 0 0 0 1 0 0 0
A1 Y1
1 0 0 1 1 0 0 0
1 0 1 0 1 0 0 0
A0 Y0
1 0 1 1 1 0 0 0
PRIORITY 1 1 0 0 1 0 0 0
CiIRCUIT 1 1 0 1 1 0 0 0
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0

– Don’t Cares
A 3 A2 A 1 A 0
A3 A2 A1 A0 Y3 Y2 Y1 Y0 Y3
0 0 0 0 0 0 0 0 Y2
0 0 0 1 0 0 0 1
0 0 1 X 0 0 1 0
0 1 X X 0 1 0 0 Y1
1 X X X 1 0 0 0

Y0

LINFO 1140 - Combinational Logic Design 15

 From Gates to Transistor

2 2

1 2
2
1
2

3
2

2 2 3

2
3

LINFO 1140 - Combinational Logic Design 16

 Contention : X

• Contention: circuit tries to drive output to 1 and 0

– Actual value somewhere in between
– Could be 0, 1, or in forbidden zone
– Might change with voltage, temperature, time, noise
– Often causes excessive power dissipation

A=1
Y=X
B=0

• Warnings :
– Contention usually indicates a bug.
– X is used for “don’t care” and contention
» Look at the context to tell them apart.

LINFO 1140 - Combinational Logic Design 17

 Floating : Z

• Floating, high impedance, open, high Z

• Floating output might be 0, 1, or somewhere
in between
E

A Y processor en1
Tristate Buffer to bus
from bus

E A Y
0 0 Z video en2
0 1 Z to bus
1 0 0 from bus

sharedbus
1 1 1

Ethernet en3
to bus
• Floating nodes are used in tristate busses from bus

– Many different drivers

memory en4
– Exactly one is active at once to bus
from bus

LINFO 1140 - Combinational Logic Design 18

 Karnaugh Maps (K-Maps)

• Boolean expressions can be minimized by combining terms

• K-maps minimize equations graphically
• PA + PA = P
A B C Y Y Y
AB AB
0 0 0 1
00 01 11 10 C 00 01 11 10
0 0 1 1 C
0 1 0 0
0 1 1 0 0 1 0 0 0 0 ABC ABC ABC ABC
1 0 0 0
1 0 1 0
1 1 0 0 1 1 0 0 0 1 ABC ABC ABC ABC
1 1 1 0

Y
A B C Y AB
0 0 0 1 00 01 11 10
C
0
0
0
1
1
0
1
0
• Circle 1’s in adjacent squares
0 1 1 0 0 1 0 0 0
1 0 0 0 • In Boolean expression, include only
1
1
0
1
1
0
0
0 1 1 0 0 0
literals whose true and complement form
1 1 1 0 are not in the circle

Y = AB

LINFO 1140 - Combinational Logic Design 19

• K-Map Rules

» Every 1 must be circled at least once

» Each circle must span a power of 2 (i.e. 1, 2, 4) squares in each direction
» Each circle must be as large as possible
» A circle may wrap around the edges
» A “don't care” (X) is circled only if it helps minimize the equation

• Example

Y Truth Table
AB K-Map
C 00 01 11 10 Y
A B C Y AB
0 0 0 0 C 00 01 11 10
0 ABC ABC ABC ABC 0 0 1 0
0 1 0 1 0
0 1 1 1
1 ABC ABC ABC ABC 1 0 0 0
1 0 1 0 1
1 1 0 0
1 1 1 1

LINFO 1140 - Combinational Logic Design 20

• Example of K-Map with 4 variables

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

LINFO 1140 - Combinational Logic Design 21

 A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0 Y = AC + ABD + ABC + BD

LINFO 1140 - Combinational Logic Design 22

• Example of K-Map with Don’t Cares

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

LINFO 1140 - Combinational Logic Design 23

 A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01 0 X X 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 X X
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10 1 1 X X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X Y = A + BD + C

LINFO 1140 - Combinational Logic Design 24

 Combinational Building Blocks
2:1 Mux
• Multiplexer (Mux)
S
– Selects between one of N inputs to connect to output D0 0
– log2N-bit select input – control input D1 1
Y

S D1 D0 Y S Y
– Multiplexer Implementations 0
0
0
0
0
1
0
1
0
1
D0
D1
» Logic gates 0
0
1
1
0
1
0
1
1 0 0 0
» Tristates 1 0 1 0
1 1 0 1
1 1 1 1
Y
D0 D1
00 01 11 10
S
0 0 0 1 1
S
1 0 1 1 0 D0

Y = D 0S + D1S Y

D1
D0

S
D1

LINFO 1140 - Combinational Logic Design 25

• Logic using Multiplexers A B Y
0 0 0
0 1 0
– Using mux as a lookup table 1 0 0
1 1 1
Y = AB
AB
00
01
10
Y
11
– Reducing the size of the mux

A
A B Y A Y
0 0 0
0 0 0
0 1 0 Y
Y = AB 1 0 0 1 B B 1
1 1 1

LINFO 1140 - Combinational Logic Design 26

 2:4
• Decoder Decoder
– N inputs, 2N outputs 11 Y3
A1 10 Y2
– One-hot outputs : only one output HIGH A0 01 Y1
at once 00 Y0

– Implementation A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
A1 A0 1 0 0 1 0 0
1 1 1 0 0 0

Y3 2:4
Decoder Minterm
Y2 11 AB
A 10 AB
Y1 B 01 AB
00 AB

Y0
Y = AB + AB
= A ⊕ B Y

Logic Using Decoders

OR minterms

LINFO 1140 - Combinational Logic Design 27

 Timing

• Propagation & Contamination Delay

– Propagation delay: tpd = max delay from input to output
– Contamination delay: tcd = min delay from input to output

A Y

Critical Path
tpd
A n1
A
B
n2
C
Y
D Y
tcd
Short Path
Time

Critical (Long) Path: tpd = 2tpd_AND + tpd_OR

Short Path: tcd = tcd_AND

LINFO 1140 - Combinational Logic Design 28

• Glitches
– When a single (or more) input change causes an output to change
multiple times

A
B Critical Path
Y
A=0 0 1
C B=1 0 n1
Y=1 0 1
n2
Y
AB C=1 1 0
00 01 11 10
C
0 1 0 0 0 Short Path

1 1 1 1 0 B

Y = AB + BC
n2

n1

Y glitch

Time

LINFO 1140 - Combinational Logic Design 29

 Y
AB
• Fixing the glitch C
00 01 11 10

0 1 0 0 0

1 1 1 1 0

AC Y = AB + BC + AC

A=0
B=1 0
Y=1

C=1

• Glitches don’t cause problems because of synchronous design

conventions (see next chapter )

LINFO 1140 - Combinational Logic Design 30