Wireless Information Transmission System Lab.

IP and Platform for SoC Design

Hung-Chih Chiang

Institute of Communications Engineering National Sun Yat-sen University

 Outline

Primary Concerns of SoC Design

IP Reuse
Definition, IP Integration, IP Reusability
Platform-Based SoC Design
Platform-based design concepts
Application Specific Platform & Platform Examples
Introduction to AMBA Bus Architecture

2
 A Canonical System IC Architecture
Data Instr.
Cache Cache
High Speed
Microprocessor Memory
I/O Ctrl

High Speed Bus

Memory Bus
HS IP
Ctrl Bridge
Peripheral Bus

Intr
Timer GPIO UART LS IP
Ctrl

3
 Primary Concerns of Soc Design

Time to Market
Profit & Territory

Cost Reduction
Profit & Competition

Application Specification
Satisfy current market application & Rapid move to next
generation

IP Reuse
IP Verification, IP Reusability, IP Integration

4
 Market/Product Life Cycle
Product Acceptance/Sales volume

Introduction Grow up Maturity Decline Renew

5
 Fundamental System Design Premises
Discipline:
The design domain need to be restricted to consistently produce scalable,
supportable, and easy to integrate designs.

Simplicity:
All designs have problems. The simpler the design, the easier it is to
find and fix them.

Locality:
Making timing and verification problems local rather than global has a
huge pay-off in reducing design time.

6
 Outline

Primary Concerns of SoC Design

IP Reuse
Definition, IP Integration, IP Reusability
Platform-Based SoC Design
Platform-based design concepts
Application Specific Platform & Platform Examples
Introduction to AMBA Bus Architecture

7
 Silicon IP

Silicon Intellectual Properties

(Silicon IP)

An expression used for the design or

intellectual know-how used to make a
chip (or IC) function in a given way.

8
 Classification of Silicon IP
Software IP
Reusable software/firmware for embedded processors
OS, driver, application program, development tools, debugging tools, …
Hardware IP
Soft IP (soft core/soft macro):
– High level description language (i.e. VHDL or Verilog HDL), Synthesizable RTL.
– Easy to modify functionalities (if well documented).
– Easy to change processes (if well designed).
Firm IP (firm core/firm macro):
– Gate level netlist synthesized for specific library.
– Hard to modify functionalities.
– Easy to change processes (if well designed).
Hard IP (hard core/hard macro):
– Layout level, GDSII.
– Very hard to modify functionalities.
– Fixed processes.

9
 Characteristics of Good Hardware IP

Configurability:
Meet the needs of many different designs.
Standard Interface:
Easy to integrate cores.
Compliance to Defensive Design Practices:
Facilitate timing closure and functional correctness.
Complete Set of Deliverables:
Synthesizable RTL.
Complete test benches.
Synthesis scripts.
Documentation.

10
 Hardware IP Integration

Block-based architecture
No standard interfaces
Not good for SoC design due to extra efforts to design
proprietary interface logic as well as increased complexity to
verify system integration.
Platform-based architecture
Standard interface depending on platform bus system
Plug-n-Play IP
Abundant silicon approved IP resources for popular platforms

11
Block-Based System IC Architecture

IP0 G0 Core0

IP0* G1
IP1*
IP1

IP0 G2 Core0

IP1
IP1/2*

12
IP Reuse in Block-Based Design

G2 Core0
IP0

IP1
IP1/2*

G5 Core0
IP0

IP2
IP1/2**

13
 IP Reuse in Block-Based Design

IP0 G0 Core0

IP0* G1
IP1*
IP1
IP0 G3 Core1

IP0** G4
IP1**
IP1

14
 Block Connection Example-1

IP0

GPIO

IP1 Core
GPIO

IP2 GPIO

• Simple but slow, limited by interface complexity

15
 Block Connection Example-2

IP0

IP1
Core

IP2
register files

IP3

16
 IP Reuse
It takes much more effort to design an IP for reuse than
for casual reuse .

Many existing IPs were not developed for reuse.

Need to develop a process of designing reusable IPs.

IP sources and loyalty.

IP quality and reliability.

17
 Block Reuse-1

a ∈ GF (28 ), to compute a −1 using square units and multipliers

a −1 = a128 ⋅ a 64 ⋅ a 32 ⋅ a16 ⋅ a 8 ⋅ a 4 ⋅ a 2
= ((((((a 2 ) 2 ) 2 ) 2 ) 2 ) 2 ) 2 ⋅ (((((a 2 ) 2 ) 2 ) 2 ) 2 ) 2 ⋅
((((a ) ) ) ) ⋅ (((a ) ) ) ⋅
2 2 2 2 2 2 2 2 2

(( a ) ) ⋅ ( a ) ⋅ a
2 2 2 2 2 2

7 square units and 6 multipliers

+ a huge combinational logic delay !

18
 Block Reuse-2

a ∈ GF (28 ), to compute a −1 using square units and multipliers

a−1 = a2 clock
(a2 )2 ⋅ a2 ↓
((a2 )2 )2 ⋅ (a2 )2 ⋅ a2
(((a2 )2 )2 )2 ⋅ ((a2 )2 )2 ⋅ (a2 )2 ⋅ a2
((((a2 )2 )2 )2 )2 ⋅ (((a2 )2 )2 )2 ⋅ ((a2 )2 )2 ⋅ (a2 )2 ⋅ a2
(((((a2 )2 )2 )2 )2 )2 ⋅ ((((a2 )2 )2 )2 )2 ⋅ (((a2 )2 )2 )2 ⋅ ((a2 )2 )2 ⋅ (a2 )2 ⋅ a2
((((((a2 )2 )2 )2 )2 )2 )2 ⋅ (((((a2 )2 )2 )2 )2 )2 ⋅ ((((a2 )2 )2 )2 )2 ⋅ (((a2 )2 )2 )2 ⋅ ((a2 )2 )2 ⋅ (a2 )2 ⋅ a2

1 square unit1 and 1 multiplier

+ 7 clocks

19
 Outline

Primary Concerns of SoC Design

IP Reuse
Definition, IP Integration, IP Reusability
Platform-Based SoC Design
Platform-based design concepts
Application Specific Platform & Platform Examples
Introduction to AMBA Bus Architecture

20
 Definition of a Platform
A generic platform contains the following components:
Bus system (AMBA, PalmBus, …)
CPU/MCU, DSP
SRAM, DRAM, non-volatile memory, …
Basic I/O functions (UART, SPI, USB, PCI, …)

It’s probably not a good idea to develop an all-purpose

(overkilled) platform for IP integration, since different
applications requires different CPU/DSP powers,
memories, IOs, etc.

21
 Platform-Based System IC Architecture
Data Instr.
Cache Cache
High Speed
Microprocessor Memory
I/O Ctrl

High Speed Bus

Memory Bus
HS IP
Ctrl Bridge
Peripheral Bus

Intr
Timer GPIO UART LS IP
Ctrl

22
 Pros & Cons of Platform-Based Design

Props:
Shorten time to Market.
Easy to locate problems in a complicated system where
major components are already pre-verified.
Easy to extend functions from a basic design.
Several popular platforms are already there for use.
Cons:
Predefined platform restricts design flexibility.
Hardware design converges. Main differentiation is
provided in software.

23
 IP Reuse in Platform-Based Design
Data Instr.
Cache Cache Plug-in and Play
•bus loading
High Speed •performance
Microprocessor Memory
I/O Ctrl limited by the
slowest element

High Speed Bus

Memory Bus
HS IP HS IP
Ctrl Bridge
Peripheral Bus

Intr
Timer GPIO UART
SPI LS IP
Ctrl

24
IP to IP Interface (Point to Point)

Microprocessor Memory

Data Data
I/O Processing Processing
Block1 Block2

Point to Point

25
 IP to IP interface (SoC)

Microprocessor Memory

Data Data
I/O Processing Processing
Block1 Block2

26
Point to Point with Analog Block

Microprocessor Memory

HS IP
USB USB
PHY PIE

Point to Point

27
 Tri-State Bus

Slave
Slave
Master 1
Master 1
A
A
Slave
Slave
2
2
Master
Master
B Slave
B Slave
3
3

Bus
Bus
Controller
Controller
• Need to guarantee only one master is active at the same time during operation
• Special cares need to be taken in DFT program.
• Bus floating/keeping issues

28
 Mux Bus

Slave Salve
Master 1 Master 1
A A
Slave Slave
2 2
Master Master
B Slave B Slave
3 3

Bus Bus
Controller Controller

• Need additional routing area

29
 On-Chip Bus Suggestions

Multiplexer-based bus architecture.

A single-clock-edge, flip-flop based architecture.
Separate data and address buses.
Separate control buses.
Support multiple masters.

30
 Outline

Primary Concerns of SoC Design

IP Reuse
Definition, IP Integration, IP Reusability
Platform-Based SoC Design
Platform-based design concepts
Application Specific Platform & Platform Examples
Introduction to AMBA Bus Architecture

31
 Application Specific Platform
The specification of an ASIC (Application-Specific
Integrated Circuit) chip often includes application
adaptability due to the following factors:
Significant market shift,
Rapid evolved standards,
Product differentiation,
Hardware reuse.

An application specific platform contains:

Application specification and future roadmap.
A generic platform (bus system, processor, memory) + pre-
integrated IP for the specified application.
Complete verification methodology.
Trade off among performance, cost programmability and
configurability.

32
 Platform Design Objectives
Application Space
Platform Design Objectives:
Design the platform to
support multiple applications
Application
Space
Exploration

System
Platform

Platform
Specification

Architecture Space
33
 Platform Selection
Application Space
Platform Selection:
For a given application.
Application
select the best platform in
Specification
terms of performance, cost,
etc.

System
Platform

Platform
Space
Exploration

Architecture Space
34
 ARM PrimeXsys Platform

Sys Ctrl.
Timer Caches
VIC ARM MPMC
Watch dog TCMs

Multi-Layer AHB/APB

UART
GPIO CLCD DMAC SMC
SCI
RTC
SSP

35
 ARM PrimeXsys Wireless Platform
Trace Port SDRA SDRA SRAM ROM Flash
LCD Display
Analyzer M M
Bank0
SDRA Bank2
SDRA
M M
Bank1 Bank3
PC Cards

MOVE SDRAM Vectored

Static Memory Color DMA
Controller Interupt
ETM

Interface LCD
Control PCMCIA
ARM926
CPU Host

ARM I AHB
ARM D AHB
LCD AHB
SRAM
DMA1 AHB (Periph.)
Buffer
DMA2 AHB (Memory)
Expansion AHB

Core APB DMA APB

MPEG-4 Color
Engine Convert
Watch Dog Timers AHB/APB AHB/APB SSP
Camera
Interface

GPIOx4 RTC System UART SIM Card USB Camera

Control
Interface Control

Trans-
Clock/Reset ceiver
32kHz Generator
32 GPIO CLK
PLL
Lines
Xtal OSC Xtal OSC

36
Xpert-GPS 3000 Platform

37
 MIPS Platform

MIPS LV

BIU IC
SDRAM

MC Loop

Peripheral Bus
I/O IPIF1 back
SoC-it AMBA AHB
MC
101 IPIF2 AHB Loop
Kernel back
IPIF3 PBC PBUS
GI I/O

Arbiter
SOC-it 101 Deliverables
User
Connector
Additional
Clock
FPGA RTL
Generator LED
And User IP
FPGA Glue Logic Switches

System Clock

38
 PowerPC CoreConnect Platform

SRAM/ROM External
Peripheral Bus Master
Controller Controller IIC UART USB GPIO

FPU
OPB
Arbiter On-Chip Peripheral Bus (OPB) 32-bit

PPC 440 10/100

Interrupt OPB DMA Ethernet
CPU MAL
Inst. Data
Controller Bridge Controller
Device
Control
PLB Register
Arbiter Processor Local Bus (PLB) 128-bit Bus

SDRAM PCI-X SRAM Custom Reset

Controller Bridge Controller Logic Clock Control
Power Mgmt

39
 Outline

Primary Concerns of SoC Design

IP Reuse
Definition, IP Integration, IP Reusability
Platform-Based SoC Design
Platform-based design concepts
Application Specific Platform & Platform Examples
Introduction to AMBA Bus Architecture

40
 AMBA History
AMBA 1.0- ASB+APB in 1995
First generation, tri-state bus
AMBA 2.0- AHB+APB in 1999
Second generation, mux bus
AMBA 3.0-AXI+AHB+APB in 2003
Third generation, more than 30 participants
Agere Systems Fujitsu NEC Electronics (Europe)

Agilent Hewlett-Packard Company OKI Electric Industry

ARM Infineon Philips Semiconductors

Atmel LSI Logic QUALCOMM

Cadence Mentor Graphics Samsung

Conexant Systems Matsushita STMicroelectronics

CoWare Inc. Micronas Synopsys

Epson Motorola Toshiba Corporation

Ericsson Mobile Platforms NEC Electronics Corporation Verisity

41
 Basic AMBA(1.0,2.0)-Based Architecture

Processor RAM

UART Timer
External

Bridge
memory
interface
Keypad PIO
DMA
bus master AHB/ASB to APB

AMBA AHB AMBA ASB AMBA APB

„ High Performance „ High Performance „ Low power

„ Pipeline operation „ Pipeline operation „ Latched address and control
„ Multiple bus masters „ Multiple bus masters „ Simple interface
„ Burst transfers „ Burst transfers „ Suitable for many peripherals
„ Split transactions

42
 AMBA2.0 AHB
Features
burst transfers
split transaction
single-cycle bus master handover
single-clock edge operation
non-tristate implementation
wide data bus configuration s(8/16/32/64/128 bits)
Bus Components
AHB master: A bus master is able to initiate read and write operations.
AHB slave: A bus slave responds to a read or write operation within a given address
range.
AHB arbiter: The bus arbiter ensures that only one bus master at a time is allowed to
initiate data transfers.
AHB decoder: The AHB decoder is used to decode the address of each transfer and
provide a select signal for the involved slave.

43
 AHB2.0 Mux Bus Interconnection
Arbiter
Slave
Master #1
#1
Address/control

Slave
Master #2
#2
Write data

Slave
Master #3
#3
Read data

Slave
#4

Decoder

44
 Overview of AMBA AHB Operation
A bus master get granted access to the bus by the bus arbiter.
The granted bus master starts an AHB transfer by driving the address and
control signals.
Address
Direction
Data width
Burst Indication
Every transfer consists of:
An address and control cycle
One or more data cycles
During a transfer the slave shows the status using the response signals,
HRESP[1:0]:
OKAY
ERROR
RETRY
SPLIT

45
 AHB: Simple Transfer
Address phase Data phase

HCLK

HADDR[31:0] A

Control Control

HWDATA[31:0] Data
(A)

HREADY

HRDATA[31:0] Data
(A)

46
 AHB: Transfer with Wait States
Address phase Data phase

HCLK

HADDR[31:0] A

Control Control

Data
HWDATA[31:0]
(A)

HREADY

Data
HRDATA[31:0]
(A)

47
 AHB: Multiple Transfers

HCLK

HADDR[31:0] A B C

Control Control Control

Control (A) (B) (C)

Data Data Data

HWDATA[31:0]
(A) (B) (C)

HREADY

Data Data Data

HRDATA[31:0]
(A) (B) (C)

48
 AHB: Transfer Type

Four transfer types indicated by HTRANS[2:0]:

IDLE
No data transfer is required.
BUSY
The BUSY transfer type allows bus masters to insert IDLE cycles in
the middle of bursts of transfers.
NONSEQ
Indicates the first transfer of a burst or a single transfer.
SEQ
The remaining transfers in a burst are SEQUENTIAL and the address
is related to the previous transfer.

49
 AHB: Control Signals
Transfer direction:
HWRITE = high for write; HWRITE = low for read
Transfer Size:
HSIZE[2:0] Size Description
000 8bits Byte
001 16bits Halfword
010 32bits Word
011 64bits -
100 128bits 4-word line
101 256bits 8-world line
110 512bits
111 1024bits

50
 AHB: Control Signals
Protection control
HPROT[3:0] Description

- - - 0 Opcode fetch

- - - 1 Data access

- - 0 - User assess

- - 1 - Privileged access

- 0 - - Nit bufferable

- 1 - - Bufferable

0 - - - Not chaheable

1 - - - Cacheable

51
 AHB: Address Decoding
HADDR_M1[31:0]
Slave
Master #1
#1 HADDR

Slave
Master #2
#2 HADDR_M2[31:0]

Slave
Master #3
#3 HADDR_M3[31:0] HSEL_S1

Decoder HSEL_S2
Slave
HSEL_S3 #4
HSEL_S4

52
 Slave Response with Retry
T1 T2 T3 T4 T5

HCLK

HTRANS[1:0] NONSEQ SEQ IDLE NONSEQ

HADDR[31:0] A A+4 A

HWDATA[31:0] Data
(A)

HREADY

HRESP[1:0]
RETRY RETRY OKAY

53
 Slave Response with Error

HCLK

HADDR[31:0]
A

Control
Control

HWDATA[31:0] Data
(A)

HREADY

HRESP[31:0] OKAY
ERROR ERROR

HRDATA[31:0]

54
 AHB: Arbitration
HBUSREQx:
Bus request from a bus master.
HLOCKx:
Bus lock from a bus master.
HGRANTx:
Grant signal generated by the bus arbiter.
HMASTER[3:0]:
Current bus master indicator.
HMASTERLOCK:
Lock indicator for the current bus master.
HSPLIT[15:0]:
Indicator to show which bus master can complete a SPLIT transaction.

55
 AHB: Granting without Wait States
T1 T2 T3 T4 T5 T6

HCLK

HBUSREQx

HGRANTx

HMASTER[3:0]
#1

HADDR[31:0] A A+4

HWDATA[31:0] Data(A)

56
 AHB: Granting with Wait States
T1 T2 T3 T4 T5 T6 T7 T8 T9

Master asserts A number of cycles later Master drives address after both Address sampled and data
request Arbiter asserts grant HGRANT and HREADY are high starts when HREADY high

HCLK

HBUSREQx

HGRANTx

HMASTER[3:0] #1

HADDR[31:0] A A+4

HWDATA[31:0] Data(A)

HREADY

57
 AHB: Data Buses
HWDATA[31:0]: Write data bus; HRDATA[31:0]:
Read data bus.
Active byte lanes for a 32-bit little-endian data bus
Transfer Address DATA DATA DATA DATA
Size offset [31:24] [23:16] [15:8] [7:0]

Word 0
Halfword 0
Halfword 2
Byte 0
Byte 1
Byte 2
Byte 3

58
 AHB: Data Buses
Active byte lanes for a 32-bit big-endian data bus

Transfer Address DATA DATA DATA DATA

Size offset [31:24] [23:16] [15:8] [7:0]
Word 0
Halfword 0
Halfword 2
Byte 0
Byte 1
Byte 2
Byte 3

59
 AHB: a Narrow Slave on a Wide Bus

Address/control HREADY

HRESP[1:0]
HWDATA[63:32] AHB
WDATA[31:0] slave HRDATA[63:32]
RDATA[31:0]

HWDATA[31:0]

HRDATA[31:0]
HADDR[2]
D Q
HREADY
CE
HCLK

60
 AHB: a Wide Slave on a Narrow Bus
Address/control HREADY

HRESP[1:0]
HWDATA[63:32]
AHB HRDATA[63:32]
WDATA[31:0] slave RDATA[31:0]

HRDATA[31:0]
HWDATA[31:0]

HADDR[2]
D Q
HREADY
CE
HCLK

61
 AMBA APB

Processor RAM
UART Timer
External

Bridge
memory
interface
Keypad PIO
DMA
bus master AHB/ASB to APB

AMBA APB
•Low power
•Latched address and control
•Simple interface
•Suitable for many peripherals

62
 APB: State Diagram

No transfer
IDLE „ IDLE: The default state.
PSELx=0
PENABLE=0 „ SETUP: When a transfer is required
the bus moves into setup
Transfer
state, where the appropriate
select signal, PSELX, is
SETUP
asserted.
PSELx=1
PENABLE=0
„ ENABLE: The enable signal,
PENABLE is asserted.

ENABLE
PSELx=1
No transfer PENABLE=1
Transfer

63
 APB: Write Transfer
T1 T2 T3 T4 T5

PCLK

PADDR Addr 1

PWRITE

PSEL

PENABLE

PWDATA Data 1

64
 APB: Read Transfer
T1 T2 T3 T4 T5

PADDR Addr 1

PWRITE

PSEL

PENABLE

PRDATA Data1

65
 APB Bridge
The APB Bridge is the only Bus Master on the AMBA APB. It is
also a Bus Slave on the higher-level system bus.

Latches the address and holds it valid throughout the transfer.

Decodes the address and generates the peripheral select, PSELx.

Only one select signal can be active during a transfer.

Drives the data onto the APB for a write transfer.

Drives the APB data onto the system bus for a read transfer.

Generates a timing strobe, PENABLE, for the transfer.

66
 Interfacing APB to AHB: Read
T1 T2 T3 T4 T5

HADDR Addr 1

HWRITE

HRDATA Data 1

HREADY

PADDR Addr 1

PWRITE

PSEL

PENABLE

PRDATA Data 1

67
 Interfacing APB to AHB: Write
T1 T2 T3 T4 T5 T6

HADDR Addr 1

HWRITE

HWDATA Data 1

HREADY

PADDR Addr 1

PWRITE

PSEL

PENABLE

PWDATA Data 1

68
 Why AMBA 3.0 AXI Protocol

Develop for future SoC designs demand:

High-bandwidth and low-latency
High-frequency without complex bridge
Flexibility in interconnect architecture
Reduction of system power consumption

Retaining existing AMBA strengths:

Backward compatible with existing AHB and APB
Modular design, component re-use
Simple to understand interface

69
 AXI Protocol interface and interconnect

Single interface definition for describing interface

between:
A master and the interconnect
A slave and the interconnect
A master and a slave

Interconnect approaches
Shared address and data buses
Shared address buses and multiple data buses
Multilayer, with multiple address and data bus

70
 System connection for AXI Protocol

M1 M2 M3

Interconnect

Interface

S1 S1 S1 S1

71
 AMBA 3.0 AXI Protocol
Features
Channel architecture
Registers slices
Burst addressing
Multiple outstanding bursts
Out of order completion
Shared bus, multi-layer and mixed

More than just a bus protocol

RTL, Modelling and Verification environments

72
 AXI Read Channel Architecture

Read address channel

Address/
Control

Master Slave

Read data channel

Read Read Read Read

data data data data

73
 AXI Write Channel Architecture

Write address channel

Address/
Control

Write data channel

Master Read Read Read Read Slave

data data data data

Write response channel

Write
response

74
 Register Slices

Arbiter
Slave
Master #1
#1 Address/control

Slave
Master #2
#2
Write data

Slave
Master #3
#3
Read data

Slave
#4

Decoder

75
 Trade-off between Latency and Frequency

Register slices can be added at almost any point within

a given connection

Use a direct connection between a processor and high-

speed memory. Use simple register slices to isolate a
long path to less performance-critical peripherals.

Allow maximum frequency of operation by matching

channel latency to channel delay.

76
 AMBA 2.0 AHB Burst

ADDRESS A11 A12 A13 A14 A21 A22 A23 A31

DATA D11 D12 D13 D14 D21 D22 D23 D31

AHB Burst
Address and Data are locked together
Single pipeline stage
HREADY controls intervals of address and data

77
 AMBA 3.0 AXI Burst

ADDRESS A11 A21 A31

DATA D11 D12 D13 D14 D21 D22 D23 D31

AXI Burst
One Address for entire burst

78
 AXI - Outstanding Transactions

ADDRESS A11 A21 A31

DATA D11 D12 D13 D14 D21 D22 D23 D31

AXI Burst
One Address for entire burst
Allows multiple outstanding addresses

79
 Out of Order Interface

Each transaction has an ID attached

Channels have ID signals - AID, RID, etc.

Transactions with the same ID must be ordered

Requires bus-level monitoring to ensure correct

ordering on each ID
Masters can issue multiple ordered addresses

80
 AMBA 2.0 AHB Burst - Slow slave

ADDRESS A11 A12 A13 A14 A21 A22 A23 A31

DATA D11 D12

With AHB
If one slave is very slow, all data is held up.

81
 AXI - Out of Order Completion

ADDRESS A11 A21 A31

DATA D21 D22 D23 D31 D11 D12 D13 D14

Out of order completion allowed

Fast slaves may return data ahead of slow slaves
Complex slaves may return data out of order

82
 AXI - Data Interleaving

ADDRESS A11 A21 A31

DATA D21 D22 D11 D23 D12 D31 D13 D14

Returned data can even be interleaved

Gives maximum use of data bus
Note - Data within a burst is always in order

83
 AXI Multi-layer

Parallel paths between

masters and slaves Master Bus
Bus Slave
Slave
Master Matrix #1
#1 Matrix #1
Key Advantages #1

Increased bandwidth Slave

Slave
#2
Design flexibility Master
#2
Master
#2
Uses the same interface #2
Slave
Slave
protocol #3
#3

Master
Master
#3 Slave
Slave
#3 #4
#4

84
 AMBA Class Library

Defined method for modelling AXI components

Data structure used to fully describe a transaction
Standard method calls for generating and receiving
transactions
Modelling abstraction levels
Programmer view level
Programmer＇s view + timing
Cycle callable

85
 ARM AXI Support
RTL
Verification
Environment
Environment
AMBA AXI
Design Interconnect AMBA
Kit Generator Verification
Components

Modelling
Environment

RealView AMBA
Model Class
Library Library

86
 Summaries
Key factors for a successful system IC design: time to
market, cost reduction, application specification and IP
reuse.
A good IP must have the following properties-
configurability, standard interface, compliance to
defensive design practices and complete set of
deliverables.
Mux bus is recommended for on-chip bus, while tri-state
bus is recommended for on-board bus.
Platform-based architecture is regarded as the only way
for complex system chip design.
SoC platform bus example- from AMBA 2.0 to
AMBA3.0.

87