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Systolic-based 2D convolver for CNN in FPGA

Conference Paper · October 2017

DOI: 10.1109/ICETA.2017.8102485

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 Systolic-based 2D convolver for CNN in FPGA
J. Hrabovsky, P. Segec, M. Moravcik, J. Papan
Faculty of Management Science and Informatics, University of Zilina, Univerzitna 8215/1, 010 26 Zilina, Slovakia
{jakub.hrabovsky, pavel.segec, marek.moravcik, jozef.papan}@fri.uniza.sk
Abstract— Convolution is a primary mathematical operation
used in many signal processing and analysis algorithms. High
dependence of the complex systems on the correct operation
of the convolver demands its continual improvements mostly
related to the decrease of resource consumption. The paper
proposes a model of 2D convolution massively used in the
algorithms of image processing. The paper provides a
detailed description of the model structure with focus on the
implementation aspect. The model is particularly applied to
the convolutional layer of Convolutional Neural Network,
currently the most known image-based deep learning
method. The key difference of the proposed model compared
with other common implementations lies in the placement of
line buffers. The correctness of the model design is validated
through the simulation discussed at the end of paper.
Keywords- 2d convolution, FPGA, CNN, systolic array.
I. INTRODUCTION
Convolution is a primary mathematical operation used
in many signal processing and analysis algorithms, e.g.
FIR and IIR filters. Therefore, there will be always need
for an improvement of the convolution implementation in
order to meet increasing requirements on the consumed
resources of hardware platforms - memory, processing
units, and time.
An example of massive convolution application is the
Convolutional Neural Network (CNN), in particular its
convolutional layers. CNN is a type of deep neural
network applied to image processing and thus it processes
a huge amount of data. Furthermore, the method requires
the algorithm implementation to run in real-time and often
on embedded devices that achieve very restricted
resources. Therefore, the optimal algorithm
implementation for platforms like FPGA is crucial for the
overall performance of the system.
The paper presents a particular model of 2D convolution
with focus on the effectiveness of computation. The
second section introduces the mathematical expression of
2D convolution, a way of its decomposition into a group
of general one-dimensional convolutions and our selected
approach. The third and fourth sections provide a detailed
description of the proposed model structure composed of
two parts – data path and control path. The processing of
both parts and related timing control are described in the
fifth section. The last two sections contain the discussion
about the correctness of the proposed model, its
contribution, limits and future improvements.
II. 2D CONVOLUTION AND ITS DECOMPOSITION
The key operation of the convolutional layer in the CNN
model is the 2D convolution. This operation is a variant of
convolution that increases the dimension of data from a
vector to a matrix while it preserves the basic mathematical
way of output computation - the weighted sum. 2D
convolution is applied in areas that process multivariate
data, such as image processing. Because we selected the
pipelining as a primary processing approach related to
systolic arrays, we expect pixels to flow through the system
one-by-one in a stream. The streaming approach allows us
to avoid data preprocessing related to the data
rearrangement in memory, which would increase the
latency. However, the vector-based form does not fit data
structure required for the 2D convolution. Thus, the system
requires modifications in comparison with the traditional
1D convolution design.
There are various approaches presented in [1]–[5] that
deal with 2D convolution from the point of implementation
optimization regarding the consumed resources. The
common idea of streaming data through the system of
processing elements is same for all models described in
mentioned papers, but they differ in the structure and
interconnection of elementary processing units.
According to (1), which defines 2D convolution, we can
split the computation of the final output into several steps,
where each step returns only the partial result
corresponding to one line of the weights matrix - kernel
illustrated in Fig. 1 and presented as inner sum in (1). This
view enables us to decompose the operation into several 1D
vector-based convolutions and apply common practical
solutions. Before we describe the structure and behavior of
our proposed architecture, we state the assumptions about
the format of inputs and outputs of the system. These
assumptions specify the overall design of the 2D convolver.
𝐾−1 𝐾−1
𝑦(𝑖, 𝑗) = ∑ ∑ 𝑥(𝑖 + 𝑚, 𝑗 + 𝑙) × 𝑤(𝑚, 𝑙) (1)
𝑚=0 𝑙=0
A. Input conditions of the proposed model
We assume that the input feature map is a squared
image with the same width and height and this shape is a
constant known in advance. Therefore, we describe the
input image size only via one parameter N. The same
W W X X
W X
[1,1] [1,2] [1,3] [i,j] [i,j+1] [i,j+2] DP1
W W W X X X
[2,1] [2,2] [2,3] [i+1,j] [i+1,j+1] [i+1,j+2] DP2
W W W X X X
[3,1] [3,2] [3,3] [i+2,j] [i+2,j+1] [i+2,j+2] DP3
Figure 1. Visual form of 2D convolution
assumption is made about the shape of kernels defined via
the parameter K.
The other set of parameters defines the dimension of
inputs, weights and outputs. Because we use fixed-point
arithmetic, we set the integer and fraction width for all
these operands after consideration of their expected ranges
and the whole computational model. Thus, we perform
correct arithmetic computations and subsequent numeric
adjustments, such as rounding and truncation.
The changes of these parameters lead to the
modification of the original model and its components. On
the other side, these changes are straightforward due to the
chosen design of systolic arrays. Usually they require
only the insertion of additional elements while preserving
the model core. For that reason, all examples displayed in
figures assume K=3 as the elementary case. This
elementary case provides the simplicity and clear
understandability while it preserves the main principle.
B. Architectural approach – Systolic array
Systolic arrays represent an architectural approach that
enables a massive parallel computing and internal
pipelined processing. Both benefits lead to the increase of
the performance. This design form is applicable to the
problems that exhibit simplicity and regularity hidden in
repeated computational patterns. The modular design
consists of a set of basic cells - processing elements (PE)
- arranged in a systematic configuration, such as chain,
matrix, or tree. PE units are interconnected through a
simple regular network of links. The network controls the
correct flow of data through the system of PE units and so
it ensures the synchronization. Because the modular design
provides scalability and flexibility, the model created for
the solution of a particular problem is also usable for a set
of bigger problems. They require only minimal
modifications without the need to start from scratch. The
systolic array pays off when applied to the computation-
bound problems because its structure maximizes usage of
inputs required for many computational operations.
The principle of systolic array provides various models
that differ in the way of arrangement and interconnection
of PEs. The paper [6] explains the foundations of systolic
array with its benefits and presents several examples of
models appropriate for a particular task related to FIR filter
– the convolution. This digital signal processing task is an
example that deals with the combination of two input data
flows - the inputs and coefficients. Considering the
following implementation dependent on the structure and
possibilities of DSP blocks available in FPGA, we chose
the design W2 depicted in the mentioned paper. This model
makes the assets of permanent utilization of all
computation units, pipelining and continuous output flow
without the requirement for the adder tree to merge the
products.
However, not all systems can be effectively designed as
a systolic array. The suitable system has to meet particular
requirements - multiple usage of each input signal in
various operations, concurrent computation that allows
parallel and pipelined processing, the simple definition of
PE, and regular shape of interconnect network. The task of
convolution meets all of these requirements and therefore
is an exemplar candidate.
III. THE STRUCTURE OF DATA PATH
The data path of the proposed 2D convolver design
consists of two main parts depicted as abstract model in Fig.
2 and as implementation model in Fig. 3. The first part
computes all required partial sums of products. It performs
a classical digital signal processing (DSP) task based on the
multiplication and subsequent addition of signals
(Multiply-&-Accumulate - MAC). As an output we get the
partial inner products (DPi) that have to be properly
combined into the final result afterwards (P). Because the
inner products given in the particular moment belong to
different outputs, we need to provide the synchronization
accordingly.
The second part addresses the issue of timing. It
combines inner products and at the same time maintains the
synchronized state. In other words, it controls the speed of
data that flow through the system. The primary focus is on
timing because the related inner products have to be
combined into the same output.
A. Part 1 – Systolic Elements
The first computation part contains a chain of systolic
elements that are connected in the sequence. Each systolic
element (SEi) is represented by the N-tap FIR filter that
computes one line of the window - 1D convolution. That
fact allows us to apply all known and recommended
approaches to realize FIR filter in the FPGA. Considering
the implementation of the design into FPGA circuit, we
refer to the traditional and time-proven methods in [7], [8]
that describe various FPGA models of FIR filters using
DSP blocks. The abstract structure is straightforward and
represents a systolic array [6]. On the other hand, the
implementation design exhibits some distinctions in the
synchronization associated with the structure of DSP in
current FPGA (it uses 2K-1 registers instead of the original
K registers as shown for K=3 in upper side of Fig. 3
compared to Fig. 2).
Each DSP block executes the multiplication of the actual
input and the corresponding weight. The product is then
pushed to the adder and attached to the cumulative output.
The registers are inserted between the operators to enable
the pipelining and so they increase the maximal operating
frequency. The DSP blocks are introduced in the next
section.
1) The Structure and Application of DSP in SE
The DSP block provides features that lead to the optimal
implementation of FIR. Internal multiplier and post-adder
support symmetric rounding and quantization of the results
to address the bit growth caused by the arithmetic
X
z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1
W[1,1] W[1,2] W[1,3] W[2,1] W[2,2] W[2,3] W[3,1] W[3,2] W[3,3]
BIAS
+ + +
P
+
z-(N-3) +
z-(N-3)
Figure 2. Abstract model of 2D convolver
 PART 1
W1(3) W2(3) W3(3)
X
BIAS SE1 SE2 SE3
DP1 DP2 DP3
PART 2 N
SWITCHING BLOCK
ADD1 ADD2 ADD3
Z-|N-6+1|
P Z-|N-6+1|
Figure 3. Implementation model of 2D convolver
operations and thus eliminate the overflow effect. The
cascade internal signals enable fast interconnection of
adjacent DSP blocks within the same column and do not
consume any FPGA resources - adders, multipliers,
storage, and delay elements [8]. A registers placed in front
of each operator directly in the DSP enable multilevel
pipelining whereas the configurable multiplexers
contribute to the flexibility. A temporal storage for the
inputs during their use in the multipliers is realized through
the line of registers - data buffer - of the desired length.
Using these components, we can model a cascade of DSP
blocks to compute products and gradually combine them
through an adder chain into the final sum without external
logic.
Considering the requirements of very high sample rate
and small number of coefficients, we chose a specific type
of parallel FIR filter implementation - Systolic FIR -
because of its advantages stated in [8]. The systolic FIR is
generally considered as the optimal model for parallel
processing on FPGA. The additional latency compared
with the utilization of adder tree does not have any
noticeable impact on the performance. The cascade model
significantly improves power consumption and speed.
Furthermore, it is limited only by the total number of DSP
blocks in one column inside of FPGA [9]. This design
reflects the regularity of the arrangement and direct
connections between DSP, BRAM and CLB blocks. The
exemplar design of SE block is shown in Fig. 4.
The documents [7]–[9] provide lists of suggestions that
can highly improve the overall performance of the final
design when thoroughly met. They also address the
implementation including the DSP instantiation and
configuration in HDL.
B. Part 2 – Delay Buffers and Adders
The 2D convolution is executed on the matrix, which
does not correspond to the shape of incoming pixels
(lines). After the first design part computes inter-products,
the second part needs to rearrange the results to allow their
combination in the desired way according to the
mathematical formula of 2D convolution (1). The delay
buffers (in Fig. 3 the blocks between adders) are used to
regulate data flow so that the right sets of inner products
are combined together and the synchronized state is kept.
We see in the visual representation of 2D convolution
applied on the input image that the gap between partial
results corresponding to the same window is equal the
W(9)
W[i,1] W[i,2] W[i,3]
X(n) X(n-5)
DPi
Figure 4. Exemplar model of SE block
width of the image. It means, the distance between
adjacent partial results of the same output equals N time
units. After we subtract the delay caused by the SE chain,
we get the remaining required delay of N-2K+1 time units
that delay buffers are responsible for (Fig. 3 – Part 2).
The sequential arrangement of delay buffers in
combination with adders substitutes the adder tree - a
common choice used in current methods. The sequential
approach brings an advantage of simple implementation
and effective time utilization. The additions are executed
while we wait for the remaining inner products of the
computed output and so no additional delay is present
compared with the adder tree based alternatives.
IV. STRUCTURE OF CONTROL PATH
The data path is controlled via the control signals that
determine validity of output features considering the
validity of inputs. The control path is realized as a Finite
State Machine (FSM) tailored to our needs. The interface
of the FSM consists of one input and one output signal,
which represent validity of current input and output
features.
The current design of the FSM exploits the determined
width and height of the output feature map and the constant
length of the invalid intervals to periodically setup and
check binary counters in advance. The automaton counts
valid inputs and generated outputs and jumps between the
states according to the counter values. The states represent
distinct cases of the window placement in the input feature
map.
We differentiate three cases of window transition
through the input feature map:
 the transition inside of the feature map,
 the transition through the vertical borders - the
transition to the next line within the same feature
map,
 the transition through the horizontal borders - the
transition to the next feature map.
The results obtained during second and third enumerated
periods (illustrated in Fig. 6-9) are invalid and have to be
ignored in the further processing. Thus, only the results
obtained by the window inside of input feature map are
valid. The reason of invalidity is described in the next
section.
 pixel_counter_treshold <= STARTUP_DELAY;
pixel_counter_set <= ‘1’;
DEFAULT VALUES OF EACH STATE:
 ready <= ‘0’;
 valid_out <= ‘0’;
 all signals for TIMERS (PIXEL_COUNTER
and LINE_COUNTER) are set to 0.
VERTICAL
pixel_counter_alert=’0’;
_BORDER
pixel_counter_alert=’1’ & line_counter_alert=’0’;
pixel_counter_threshold <=
NO_INVALID_PIXELS_PER_LINE;
pixel_counter_set <= ‘1’;
valid_out <= ‘1’;
line_counter_alert=’1’;
pixel_counter_threshold <=
NO_INVALID_PIXELS_PER_TRANSITION;
pixel_counter_set <= ‘1’;
line_counter_clear <= ‘1’; HORIZONTAL
_BORDER
pixel_counter_alert=’0’;
Figure 5. State diagram of FSM representing the control path
The FSM is visually displayed in the Fig. 5. It consists
of five states that directly map beside the mentioned
window situations also the initialization and start-up
periods. The controller implements two counters with
dynamic upper limits - PIXEL_COUNTER and
LINE_COUNTER in the VHDL code. Each counter is
responsible for the particular transition between states. The
current form of the FSM operates only when the input is
valid, otherwise it waits in the last state without change of
any attribute, such as the current value of counters. This
chosen behavior simplifies its design and in the same way
influences the operation of the data path. In other words,
data path waits without action during the invalid inputs.
V. DESCRIPTION OF THE PROPOSED SYSTEM AND ITS
TIMING CONTROL
A. Data processing by the SE chain
To interpret data processing by the SE chain, we use a
simple visual model. Computation of 2D convolution
consists in scanning the input feature map by technique of
moving window that is gradually used for computation of
individual output features. Considering this process, the
SE cluster can be visually expressed as a pattern built of K
blocks shown in Fig. 6. Pattern blocks in the figure are
divided into K lines and each contains exactly one
highlighted line. The form of pattern depends on the
assignment of weights from the original kernel to
individual pattern blocks. Every pattern block represents
one SE that computes its highlighted line. In other words,
the particular pattern block colors always the specific line
DEFAULT STATE: INIT
INIT  this state is set on
active RESET (RST=’1’).
pixel_counter_alert=’1’;
pixel_counter_treshold <=
NO_VALID_PIXELS_PER_LINE;
pixel_counter_set <= ‘1’;
line_counter_ce <= ‘1’;
START_UP
pixel_counter_alert=’0’;
INSIDE_
IMAGE pixel_counter_alert=’1’;
pixel_counter_treshold <=
NO_VALID_PIXELS_PER_LINE;
pixel_counter_set <= ‘1’;
line_counter_treshold <=
NO_VALID_LINES_PER_IMAGE;
line_counter_set <= ‘1’;
pixel_counter_alert=’0’ & line_counter_alert=’0’;
pixel_counter_alert=’1’;
pixel_counter_threshold <=
NO_VALID_PIXELS_PER_LINE;
pixel_counter_set <= ‘1’;
of all windows in the input map. Therefore, we require a
window to be finally covered by each block in order to
compute all its lines - partial inner products (inner sum in
equation (1)). We can imagine the task of pattern blocks as
a coloring of the assigned line of windows. The processing
of the window is complete when all its lines are colored by
the corresponding pattern blocks. Because the visual shape
of pattern specifies different positions of blocks, inner
products returned from SE blocks in the particular time
point correspond to different windows in the original
feature map. Thus, they cannot be directly combined to the
final output, but they have to be reorganized at first. The
rearrangement of these products introduces the
synchronization performed by appropriately placed delay
buffers. The adders finish the computation and merge all
related inner products to the common output.
Regarding the form of the pattern (Fig. 6), blocks visit
a window sequentially in order from the left block first.
The gap between two adjacent blocks is exactly N-K time
units based on the line-by-line movement of the pattern.
Therefore, inner products of two adjacent blocks taken in
time points t and t+N-K belong to the same result. By
applying this principle to the chain of K blocks, the inner
products taken from blocks in t, t+N-K, ..., t+(N-K)×(K-1)
constitute one output feature. This time shift is a reason for
the deployment of delay buffers to adequately adjust time
points of all inner products. Thus, the length of each delay
buffer regarding the abstract model is equal N-K, as shown
in the Fig. 2.

Figure 6. SE blocks pattern
The pattern sequentially moves through the input
feature map as a consequence of the inputs continuously
streaming into the system data buffer. The regular
movement of the pattern line-by-line in the predefined
direction (depends on the direction of data streaming)
influences the validity of outputs based on various
situations that are described in the section related to the
design of the control path.
During the pattern transition through the vertical
border, the SE chain processes input features that form an
incoherent and thus invalid window (Fig. 7 - (b) and (c)).
Similar situation occurs during the pattern transition
through the horizontal border to the next image. In that
case, processed windows include data from both adjacent
images and therefore are incorrect (Fig. 8 - (b) and (c)). As
a consequence, all results obtained through the
combination of invalid inner products are also
considered as invalid.
Due to the specific values of parameters N and K, we
can derive valid and invalid areas of outputs. The
numerical expressions are used in the control path to
clearly identify validity of outputs in advance. The Fig. 9
depicts areas of valid and invalid outputs including their
size based on N and K parameters.
B. Data processing by the SE
The principle of the introduced SE block design as a
systolic FIR, which performs all numerical computations,
lies in a different speed of the top and bottom data flows
A)
B)
C)
D)
Figure 7. Transition through vertical border
A) B) C) D)
K-1
Figure 8. Transition through horizontal border
caused by the additional registers in the top path (Fig. 4).
Therefore, the top flow is slowed down to the half speed
of the bottom flow that represents the partial sum of the
products. Because the current input and its product are
actually the last element of the corresponding output
(currently on the left side of the cascade), this partial sum
has to reach products of several previous inputs (the
particular number equals the number of coefficients). The
increased speed of the sum flow compared with the input
flow provides always the correct results on the right side
of model but with a latency (the streaming of final sum to
the output takes K cycles measured from the arrival of its
last input).
C. Relationship between abstract and implementation
model
The model of the SE in FPGA implemented through
the systolic array requires additional registers in the input
data path that were not included in the abstract model. As
the Fig. 4 shows, the total delay (the number of registers)
in data path of the SE chain is equal 2K-1 instead of K.
Therefore, the overall length of delay buffers in the second
part has to be recalculated to meet the original timing
requirements set in the abstract model - we subtract the
additional delay of data path from the original length of
delay buffers, so each buffer delays inner products by N-
2K+1 time units.
D. The issue and solution of negative buffer length
When the buffer delay length is non-negative, i.e.
N>=2K-1, the original design exhibits the desired
behavior. But in the case of a small input feature map, i.e.
when the inequality N<2K-1 is valid, the delay buffer
should have a negative length considering the operation
requirements. The buffer of negative length cannot be
practically realized and so constitutes a complication. We
INVALID – VERTICAL BORDER
N-K+1
VALID – INSIDE IMAGE
K-1
INVALID – HORIZONTAL BORDER
K-1 N-K+1
Figure 9. Valid and invalid regions
need to change the perspective to overcome the stated
problem. If we add a delay buffer of the positive length to
the signal path, actually we slow the speed of the signal
that spreads inside the system. That means, the other
signals will be faster than the delayed one. On the contrary,
the delay buffer of negative length should have an inverse
effect, hence it should speed up the corresponding signal
in relation to the other signals of the system. We can
accomplish the same behavior corresponding to the
negative-long buffer through slowing down all signals but
the particular one. The synchronization state of the system
stays untouched. Switching block inserted between the
first and second part (Fig. 2) provides the desired
operation.
The particular structure of the second part enables us to
exploit its symmetry (all delay buffers have same length
and are connected in a raw) to design the switching block.
In the case of negative delay, we reverse the connections
of the inner products coming out of the SE blocks to the
individual adders, i.e. the last inner product will be
connected to the first adder; the first inner product will be
connected to the last adder. In practice, we reach it via a
set of multiplexers (shown in Fig. 10) that are
appropriately controlled via the selector - a signal defined
by the sign of the statement N-2K+1.
DP3
ADD3
DP1 SEL
DP2 ADD2
DP1
ADD1
DP3 SEL
N improvement from the implementation aspect. Therefore,
Sign(N-6+1)
Figure 10. Switching block model
VI. DISCUSSION
A. The desired operation of the proposed model
The correctness of the abstract design is grounded in
the mentioned documents [6], [7], [9]. The right behavior
of the proposed model including control path and data path
was practically validated through a behavioral simulation.
The simulator integrated into Vivado [10] was used as a
simulation tool. We carried out the controlled simulation
with stimulus and evaluated the results.
Fig. 11 shows the waveform diagram of the proposed
model simulation. Because of the length, the waveform is
split into two diagrams belonging to the same simulation
run. The important signals of data path and control path are
displayed with their values in different time points. The
first diagram displays the transition of window through the
vertical border with emphasis on the pixel_counter_alert
signal. This signal represents the activity of the
PIXEL_COUNTER, that counts the processed input
pixels. Its active state (value 1) indicates coming transition
to other state of control path. In similar way, the second
diagram displays the transition of window through the
horizontal border with emphasis on the line_counter_alert.
This signal represents the activity of the
LINE_COUNTER, that counts the processed lines of the
input image. It indicates the transition to other state of
control path in the same way as the previous alert signal.
The progress of signal valid_out corresponds to the areas
in Fig. 9.
The simulation run of the system captured in the
diagram matches the desired behavior of both parts of the
proposed model. Simulation outputs were also compared
with results of the experiments performed on the GPU
under same conditions - the kernel and input images. The
results are almost same considering the sufficiency of the
accuracy and so they serve as a proof of the desired
behavior of the proposed model.
B. Contribution of the proposed model
The proposed model introduces a novel structure
considering the delay buffers position. The other common
models insert the delay buffers before the computation
blocks to arrange the input pixels into matrix format at the
entrance to the multipliers. That approach requires the
adder tree placed after the sets of multipliers to merge the
inner products, which increases the latency. Our approach
inserts delay buffers after the computation blocks. The
buffers are interconnected with the adders in the scheme
that does not require the adder tree at all. By applying this
construction, we save time of signals spreading through the
adder tree and so we decrease the total latency of the
outputs.
VII. CONCLUSION AND FEATURE WORK
The paper emphasized the important role of the
convolution in various areas and the need for its continual
we proposed a model with increased effectivity compared
to other common models mentioned in second section. The
chosen approach - systolic array – suits well the
architectural structure of FPGA. The paper presented the
detailed structure of proposed model together with
description of its processing. Regarding the discussion
about functionality of the model we proved its correctness
in the computation of 2D convolution.
However, the proposed design exhibits drawbacks that
limit format of supported input data via the static N and K
parameters in the whole system. The potential
improvements of the model consist in providing the
additional flexibility through the dynamic setup of N and
K at run-time. If we assume the variability of these
parameters with the purpose to enable reuse of 2D
convolver blocks for inputs and kernels of distinct size, we
need to adjust the model architecture. All components, that
depend on these parameters, must be modified to preserve
their correct dynamic behavior. These components are SE
chain and delay buffers.
In case of the SE chain, we could use the neutral element
of summation - zero - and replace all extra inner products
considering the current value of K. This functionality could
be implemented as a part of the switching block.
The dynamic length of delay buffer could be realized by
application of the BRAM, as described in [11]. In that
implementation of FIFO as a delay buffer, the variable
 Figure 11. Waveform diagram of simulation
length represents an offset between address pointers to the
current write and read memory positions. If we change the
addresses and their offsets appropriately, the buffer length
will adapt accordingly.
VIII. ACKNOWLEDGMENT
This paper is supported by Faculty of management
science and informatics of University of Zilina, funded by
research grant number FVG/27/2017.
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