Aula prática UVM

TLM básico com UVM

Felipe Gonçalves Assis

Abril de 2013
 Visão Geral SystemVerilog
SystemC
top get port
analysis port
test
responder
env transaction flow
FIFO
interface

source sink
 Passos
● Escrever transação e seqüência básica
● Escrever componentes
 Transação
class my_transaction extends uvm_sequence_item;
rand bit cmd;
rand int data;

function new (string name = "");

super.new(name);
endfunction: new

endclass: my_transaction
 Transação
`uvm_object_utils_begin(my_transaction)
`uvm_field_int(cmd, UVM_ALL_ON)
`uvm_field_int(data, UVM_ALL_ON)
`uvm_object_utils_end

constraint c_data { data >= 0; data < 256; }

function string convert2string;

return $psprintf("cmd=%b, data=%0d",
cmd, data);
endfunction: convert2string
 Seqüência
class command_sequence
extends uvm_sequence #(my_transaction);
`uvm_object_utils(command_sequence)

function new (string name = "command_sequence");

super.new(name);
endfunction: new

...

endclass: command_sequence
 Seqüência
task body;
my_transaction tx;

forever begin
tx = my_transaction::type_id::create("tx");
start_item(tx);
assert( tx.randomize() );
finish_item(tx);
end
endtask: body
 Source

source

sequencer
 Source
class source extends uvm_component;
`uvm_component_utils(source)

typedef uvm_sequencer #(my_transaction)

sequencer_t;

uvm_seq_item_pull_port #(my_transaction)
seq_item_port;
uvm_put_port #(my_transaction) out;

sequencer_t sequencer_h;

...

endclass: source
 Source
function new(string name,
uvm_component parent);
super.new(name, parent);

seq_item_port = new(“seq_item_port”, this);

out = new(“out”, this);

endfunction: new
 Source
function void build_phase(uvm_phase phase);
super.build_phase(phase);

sequencer_h = sequencer_t::type_id::create(
“sequencer_h”, this);

endfunction: build_phase
 Source
function void connect_phase(uvm_phase phase);

seq_item_port.connect(
sequencer_h.seq_item_export);

endfunction: connect_phase
 Source
task run_phase(uvm_phase phase);
my_transaction tx;

forever begin
seq_item_port.get_next_item(tx);
out.put(tx);
seq_item_port.item_done();
end
endtask: run_phase
 Sink

sink
 Sink
class sink extends uvm_component;
`uvm_component_utils(sink)

uvm_get_port #(my_transaction) in;

...

endclass: sink
 Sink
function new(string name,
uvm_component parent);
super.new(name, parent);

in = new(“in”, this);

endfunction: new
 Sink
task run_phase(uvm_phase phase);
my_transaction tx;

phase.raise_objection(this);

repeat (10) begin

in.get(tx)
end

phase.drop_objection(this);
endtask: run_phase
 Environment
env

source sink
 Environment
class my_env extends uvm_env;
`uvm_component_utils(my_env)

source source_h;
sink sink_h;

uvm_tlm_fifo #(my_transaction)
source_sink;

...

endclass: my_env
 Environment
function new(string name,
uvm_component parent);
super.new(name, parent);

source_sink = new(“source_sink”, this);

endfunction: new
 Environment
function void build_phase(uvm_phase phase);
super.build_phase(phase);

source_h = source::type_id::create(
“source_h”, this);
sink_h = sink::type_id::create(
“sink_h”, this);

endfunction: build_phase
 Environment
function void connect_phase(uvm_phase phase);

source_h.out.connect(source_sink.put_export);
sink_h.in.connect(source_sink.get_export);

endfunction: connect_phase
 Teste
test
env
 Teste
class basic_test extends uvm_test;
`uvm_component_utils(basic_test)

my_env my_env_h;

...

endclass: basic_test
 Teste
function new(string name,
uvm_component parent);
super.new(name, parent);
endfunction: new
 Teste
virtual function void build_phase(
uvm_phase phase);
super.build_phase(phase);

my_env_h = my_env::type_id::create(
“my_env_h”, this);

endfunction: build_phase
 Teste
virtual task run_phase(uvm_phase phase);
command_sequence seq;

seq = command_sequence::type_id::create("seq");
seq.start(my_env_h.source_h.sequencer_h);
endtask: run_phase
 O Topo
module top;
initial
run_test();
endmodule: top
 Comando de simulação
irun -uvm -access +r \
+uvm_set_config_int="*",recording_detail,1 \
top.sv +UVM_VERBOSITY=LOW \
+UVM_TESTNAME=basic_test
 Gravando transações
task run_phase(uvm_phase phase);
my_transaction tx;

phase.raise_objection(this);

repeat (10)
begin_tr(sample, "sink");
in.get(tx);
#10;
end_tr(sample);
end

phase.drop_objection(this);
endtask: run_phase
 Inserindo atraso no source
task run_phase(uvm_phase phase);
my_transaction tx;

forever begin
seq_item_port.get_next_item(tx);
out.put(tx);
#10;
seq_item_port.item_done();
end
endtask: run_phase
 Visão Geral SystemVerilog
SystemC
top get port
analysis port
test
responder
env transaction flow
FIFO
interface

source refmod sink

 Refmod
class refmod extends uvm_component;
`uvm_component_utils(refmod)

uvm_put_port #(my_transaction) out;

uvm_get_port #(my_transaction) in;

...

endclass: source
 Refmod
function new(string name,
uvm_component parent);
super.new(name, parent);

out = new(“out”, this);

in = new(“in”, this);

endfunction: new
 Refmod
virtual task run_phase(uvm_phase phase);
my_transaction tx_in, tx_out;

forever begin
in.get(tx_in);
tx_out = transform(tx_in);
out.put(tx_out);
end
endtask: run_phase
 Refmod
virtual function my_transaction transform(
my_transaction x);

transform = new;
transform.data = x.data;
transform.cmd = ~x.cmd;

endfunction: transform