Boolean Algebra &

Logic Gates
 Digital Computers

➢Digital computers are capable of solving problems by processing information in discrete

form.

➢It operates on data including numbers, letters, and symbols; that are expressed in binary
code—i.e. using only the two bits 0 and 1.

➢The binary input is converted to binary output.

➢The input-to-output conversion depends on the CPU (ALU + CU).

 Logic Gates
➢The CPU work by reacting to an input of 0s and 1s in specific ways and then returning an
output based on the decision.

➢The decision itself happens in a circuit called a Logic Gate.

➢Simply, the manipulation of binary information is done by logic circuits called gates.

➢The logic gates work together to make decisions using Boolean algebra, which is based
on the algebraic system established by mathematician George Boole.
Boolean Algebra & Logic Gates
 Boolean Algebra
➢ Boolean algebra is a mathematical system for the manipulation of variables that can
have one of two values.

➢ In digital systems, these values are 1 and 0.

➢ Boolean functions/expressions are created by performing operations on Boolean

variables.

➢ Common boolean operators include AND, OR and NOT.

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 Boolean Operators (AND, OR)

➢ A Boolean operator can be completely described

using a truth table.

➢ The AND operator is also known as a Boolean

product. It is corresponding to AND logic gate.

➢ The OR operator is the Boolean sum. It is

corresponding to OR logic gate.

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 Boolean Operator
• The NOT operation is most often
designated by an over bar. It is sometimes
indicated by a prime mark ( „ ) or an
“elbow” ().

• It is corresponding to inverter/buffer logic

gate.

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 Boolean Function
• A Boolean function has
• At least one Boolean variable
• At least one Boolean operator
• At least one input from the set {0,1}.

• It produces an output that is also a member of the set {0,1}.

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 Boolean Function
➢ A Boolean functions can be
completely described using a truth
table.

➢ The truth table for the following

boolean function is shown at the
right.

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 Boolean Function
➢As with common arithmetic,
Boolean operations have rules of
precedence.

➢The NOT operator has highest

priority, followed by AND and then
OR.

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 Boolean Function
Find Truth Table for the following boolean functions

➢F(x, y) = xy + x‟y‟

➢F(a, b) = a‟b + ab‟

➢F(x, y, z) = xyz + x‟yz + xy‟z + xyz‟ + x‟y‟z‟

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Logic Gates

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 Logic Gates
• The Boolean functions are implemented as a logic circuits using Logic
Gates.

• A gate is an electronic device that produces a result based on two or

more input values.

– In reality, logic gates consist of one to six transistors, but digital

designers think of them as a single unit.

– Integrated circuits contain collections of gates to fulfill a particular

purpose.
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 Basic Logic Gates
➢ The three simplest gates are the AND, OR, and NOT gates.

➢ They correspond directly to their respective Boolean operations, as you

can see by their truth tables.
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 Logic Gates
➢NAND and NOR are two very important gates.

➢Their symbols and truth tables are shown at the right.

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 Logic Gates

➢Gates can have multiple inputs and more than one output.
➢A second output can be provided for the complement of the operation.

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 Logic Gates

➢Another very useful gate is the exclusive OR (XOR) gate.

➢The output of the XOR operation is true only when the values
of the inputs differ.

Note the special symbol for the XOR operation.

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 Logic Gates
➢Another very useful gate is the exclusive NOR (XOR) gate.

➢The output of the XOR operation is true only when the values
of the inputs do not differ.

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 Boolean Function & Logic Gates
➢Any boolean function can be represented using AND, OR and NOT
logic gates.

➢The circuit below implements the Boolean function using 1 AND-

gate, 1 OR-gate and 1 NOT-gate.

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 Boolean Function & Logic Gates

➢Implement Boolean functions using AND, OR or NOT

gates
➢F(x, y) = xy + x‟y‟
➢F(a, b) = a‟b + ab‟
➢F(x, y, z) = xyz + x‟yz + xy‟z + xyz‟ + x‟y‟z‟

➢F(x, y) = (x+y).(x‟+y‟)
➢F(a, b) = (a‟+b).(a+b‟)
➢F(x, y, z) = (x+y+z)(x‟+y+z)(x+y‟+z)(x+y+z‟)(x‟+y‟+z‟)

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Simplification

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 Digital Computers
➢The digital computers contain circuits that implement Boolean
functions.

➢The simpler that we can make a Boolean function, the smaller the
circuit.
➢Simpler circuits are cheaper to build, consume less power, and run faster
than complex circuits.

➢With this in mind, we always want to reduce our Boolean functions to

their simplest form.

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Implementation of a Boolean function

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Simplified Implementation of a Boolean function

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 Definitions
F(x, y) = x.y + x‟.y‟

➢Literal: A variable or its complement

➢x, x’

➢Product term: Literals connected by • (AND)

➢x.y’

➢Sum term: Literals connected by + (OR)

➢x + y’
 Minterm
➢Minterm
➢A product term in which all the variables appear exactly
once, either complemented or un-complemented.

➢Represents exactly one combination in the truth table.

➢Denoted by mj, where j is the decimal equivalent of the

minterm’s corresponding binary combination (bj).

➢A variable in mj is complemented if its value in bj is 0,

otherwise is un-complemented.
 Truth Table notation for Minterms

x y z Minterm
➢ Minterms are easy to denote using a truth
table. 0 0 0 0 x’y’z’ = m0

0 0 1 1 x’y’z = m1
➢ Example:
Assume 3 variables x, y, z 0 1 0 0 x’yz’ = m2
(order is fixed)
0 1 1 0 x’yz = m3

➢F(x, y, z) = xyz‟ + x‟y‟z 1 0 0 0 xy’z’ = m4

1 0 1 0 xy’z = m5

1 1 0 1 xyz’ = m6

1 1 1 0 xyz = m7
 Maxterm
➢Maxterm: A sum term in which all the variables appear exactly
once, either complemented or un-complemented.

➢Represents exactly one combination in the truth table.

➢Denoted by Mj, where j is the decimal equivalent of the

maxterm’s corresponding binary combination (bj).

➢A variable in Mj is complemented if its value in bj is 1,

otherwise is un-complemented.
 Truth Table notation for Maxterms
x y z Minterm Maxterm
➢ Minterms and Maxterms are easy to 0 0 0 1 x’y’z’ = m x+y+z = M0
0
denote using a truth table.
➢ Example: 0 0 1 0 x’y’z = m1 x+y+z’ = M1
Assume 3 variables x, y, z
(order is fixed) 0 1 0 1 x’yz’ = m2 x+y’+z = M2

0 1 1 1 x’yz = m3 x+y’+z’= M3
➢ F(x, y, z) = (x+y+z’).(x’+y’+z)
1 0 0 1 xy’z’ = m4 x’+y+z = M4

1 0 1 1 xy’z = m5 x’+y+z’ = M5

1 1 0 0 xyz’ = m6 x’+y’+z = M6

1 1 1 1 xyz = m7 x’+y’+z’ = M7
 Canonical Forms (Unique)
➢Any Boolean function F( ) can be expressed as a unique sum
of minterms OR a unique product of maxterms (under a
fixed variable ordering).

➢In other words, every Boolean function F() has two canonical
forms:
➢Canonical Sum-Of-Products (Sum of minterms)
➢Canonical Product-Of-Sums (Product of maxterms)
 Canonical Forms (cont.)
➢Canonical Sum-Of-Products
➢The minterms included are those mj such that F( ) = 1 in row
j of the truth table for F( ).

➢Canonical Product-Of-Sums
➢The maxterms included are those Mj such that F( ) = 0 in
row j of the truth table for F( ).
 Example
➢ Truth table for f1(a, b, c) at right a b c f1

0 0 0 0
➢ The canonical sum-of-products form for f1 is
0 0 1 1
f1(a, b, c) = m1 + m2 + m4 + m6 0 1 0 1
= a’b’c + a’bc’ + ab’c’ + abc’
0 1 1 0

f’1(a, b, c) = m0 + m3 + m5 + m7 1 0 0 1
= a’b’c’ + a’bc + ab’c + abc
1 0 1 0
1 1 0 1
1 1 1 0
 Example
➢ Truth table for f1(a, b, c) at right a b c f1

0 0 0 0
➢ The canonical product-of-sums form for f1 is 0 0 1 1
f1(a, b, c) = M0 • M3 • M5 • M7
= (a+b+c)•(a+b’+c’)• (a’+b+c’)•(a’+b’+c’) 0 1 0 1
➢ f’1(a, b, c) = M1 • M2 • M4 • M6 0 1 1 0
= (a+b+c’)•(a+b’+c)• (a’+b+c)•(a’+b’+c)
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
 Shorthand: ∑ and ∏
➢ f1(a, b, c) = m1 + m2 + m4 + m6 = ∑ m(1,2,4,6)

where ∑ indicates that this is a sum-of-products form, and m(1,2,4,6)

indicates that the minterms to be included are m1, m2, m4, and m6.

➢ f1(a, b, c) = M0 • M3 • M5 • M7 = ∏ M(0,3,5,7)

where ∏ indicates that this is a product-of-sums form, and M(0,3,5,7)

indicates that the maxterms to be included are M0, M3, M5, and M7.
 Conversion Between Canonical Forms

➢ Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in
the original form with those that do not.

➢ Example:
f1(a, b, c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
 Find Boolean functions & Logic circuit
a b c f1 a b c f1
0 0 0 1 0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 1 0 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 0
1 1 1 0 1 1 1 1
 Find Boolean functions & Logic circuit
a b c f1 a b c f1
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 1 0 1 1 0
1 0 0 1 1 0 0 0
1 0 1 1 1 0 1 0
1 1 0 0 1 1 0 0
1 1 1 0 1 1 1 1
 Standard Forms (NOT Unique)
➢ Standard forms are ―like” canonical forms, except that not all variables
necessarily appear in the individual product (SOP) or sum (POS) terms.

➢ Example:
f1(a, b, c) = a’b’c + bc’ + ac’
is a standard sum-of-products form

➢ f1(a,b, c) = (a+b+c)•(b’+c’)•(a’+c’)
is a standard product-of-sums form.
 Simplification Karnaugh Maps
➢Karnaugh maps (K-maps) are graphical representations
of boolean functions.

➢One cell corresponds to a row in the truth table.

➢Also, one cell corresponds to a minterm or a maxterm in

the boolean expression

➢Multiple-cell areas of the map correspond to standard

terms.
 Two Variable Map
x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1
OR 0 m0 m2
2 3 1 3
1 m2 m3 1 m1 m3

➢NOTE: ordering of variables is IMPORTANT for f(x1,x2), x1 is

the row, x2 is the column.
➢Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc.
➢If a minterm is present in the function, then a 1 is placed in the
corresponding cell.
 Two-Variable Map (cont.)
➢Any two adjacent cells in the map differ by ONLY
one variable, which appears complemented in one cell
and un-complemented in the other.
➢Example:
m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and m2 (=x1x2’)
but NOT m3 (=x1x2)
 2-Variable Map -- Example
f(x1,x2) = x1’x2’+ x1’x2 + x1x2’
= m0 + m1 + m2
= x 1 ’ + x 2’

➢ 1s placed in K-map for specified minterms m0,

m1, m2

➢ Grouping (ORing) of 1s allows simplification

➢Groups of 1, 2, 4 minterms are possible.

➢ What (simpler) function is represented by each

dashed rectangle?
x1’ = m0 + m1
x2’ = m0 + m2

➢ Note m0 covered twice

 Problems
f(x, y) = x’y + xy

f(x, y) = x’y’ + x’y

f(x, y) = x’y + xy’

f(x, y) = x’y + xy + x’y’

 Minimization as SOP using K-map
➢Enter 1s in the K-map for each minterm in the
function

➢Group adjacent K-map cells containing 1s to obtain a

product with fewer variables.

➢Group size must be in power of 2 (2, 4, 8, …)

➢Handle ―boundary wrap‖ for K-maps of 3 or more

variables.

➢Realize that answer may not be unique

 Three-Variable Map
yz
x 00 01 11 10
0 1 3 2
0 m0 m1 m3 m2
4 5 7 6
1 m4 m5 m7 m6

➢Note: variable ordering is (x, y, z); yz specifies column, x specifies row.

➢One cell represents the minterm of three variables.

➢Each cell is adjacent to three other cells (left or right or top or bottom or
edge wrap)
 Three-Variable Map (cont.)
➢Groups of 1, 2, 4, 8 terms are possible.

Group of 1 term

Group of 2 terms

Group of 4 terms
 Simplification
➢f1(x, y, z) = ∑ m(2, 3, 5, 7)

f1(x, y, z) = x’y + xz

➢f2(x, y, z) = ∑ m (0, 1, 2, 3, 6)

f2(x, y, z) = x’+yz’
 Simplification

• Example: f(a, b, c) = a’c + abc + bc’

• f(a, b, c) = a’c + b

a bc 00 01 11 10
bc 0 1 1 1
a 00 01 11 10
1 1
0 1 1 1 1
1 1
1
 Problems
➢f(x, y, z) = ∑ m(1, 2,4, 7)
➢f(x, y, z) = ∑ m (0,1,5,6,7)
➢f(x, y, z) = ∑ m (0,1,5,6,7)
➢f(x, y, z) = ∑ m (0,1,5,6,7)

➢f(x, y, z) = x’yz + xz
➢f(x, y, z) = x’y + xyz’ + xyz
➢f(x, y, z) = x’y’z + x’yz’ + xy’z’ + xyz
➢f(x, y, z) = x’yz + xy’z + xyz’ + xyz
 Minimization as SOP using K-map
➢Enter 1s in the K-map for each product term in the
function

➢Group adjacent K-map cells containing 1s to obtain a

product with fewer variables.

➢Group size must be in power of 2 (2, 4, 8, …)

➢Handle ―boundary wrap‖ for K-maps of 3 or more

variables.

➢Realize that answer may not be unique

 Four-Variable Maps
YZ
WX 00 01 11 10

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

➢ Top cells are adjacent to bottom cells. Left-edge cells are adjacent to
right-edge cells.
➢ Note variable ordering (WXYZ).
 Four-variable Map Simplification
➢One square represents a minterm of 4 literals.

➢A rectangle of 2 adjacent squares represents a product term of 3

literals.

➢A rectangle of 4 squares represents a product term of 2 literals.

➢A rectangle of 8 squares represents a product term of 1 literal.

➢A rectangle of 16 squares produces a function that is equal to logic 1.

 Example
➢ Simplify the following Boolean function
f(A,B,C,D) = ∑m(0,1, 2, 4, 5, 7, 8, 9, 10, 12, 13)
➢ First put the function f( ) into the map, and then group as many 1s as
possible.

cd
ab
1 1 1

1 1 1
1 1 1
1 1 1
1 1
1 1
1 1 1
1 1 1

f(A,B,C,D) = c’+b’d’+a’bd
 Problems
➢f(w, x, y, z) = ∑ m(1, 2, 4, 7, 9, 10)
➢f(w, x, y, z) = ∑ m (0, 2, 6, 7, 10, 14, 15 )

➢f(w, x, y, z) = wx’yz + w’xz

➢f(x, y, z) = wx’yz + w’x’y’z’ + w’xyz + w’x’yz + wxy’z'
 Combinational Circuits
➢We have designed a circuit that implements the Boolean function F(x, y,
z).

➢The following circuit is an example of a Combinational logic circuit.

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 Combinational Circuits
➢Combinational logic circuit produces a specified output at the instant
when input values are applied.

➢A circuit whose output is dependent only on its inputs.

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 Combinational v/s Sequential Circuits
➢Combinational logic circuit produces a specified output at the instant
when input values are applied.

➢A sequential circuit is a type of logic circuit whose output depends not

only on the present value of its input signals but on the sequence of
past inputs, the input history as well. This is in contrast to
combinational logic, whose output is a function of only the present
input.

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Sequential Circuit

58
Combinational v/s Sequential Circuits

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 Combinational Circuits
➢Combinational logic circuits give us many useful devices.

➢Half Adder: It performs the sum of two bits.

➢Full Adder: It performs the sum of three bits.

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 Half Adder
■ A combinational circuit that performs the addition of two bits is
known as half adder.
■ The truth table for the half adder is listed below:

S: Sum
C: Carry

S = m1+m2 = x’y + xy’

C = m3 = xy

The Boolean functions (S & C) are already simplified.

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 Implementation of Half-Adder

S = m1 + m2 = x’y + xy’

C = m3 = xy

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 Implementation of Half-Adder

S = m1 + m2 = x’y + xy’

C = m3 = xy

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 Full-Adder
■ A combinational circuit that performs the addition of three bits is known
as Full adder.
■ It adds two significant bits and a previous carry.

■ Example: X = X3X2X1X0 = 1011

Y = Y3Y2Y1Y0 = 0011

The Full adder adds Xi, Yi and previous Carry (Ci).

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 Full-Adder’s Truth Table
S = m1 + m2 + m4 + m7
= x’y’z + x’yz’ + xy’z’ + xyz

C = m3 + m5 + m6 + m7
= x’yz + xy’z + xyz’ + xyz

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Simplified Expressions using K-map

S = x’y’z + x’yz’ + xy’z’ + xyz

C = xy + xz + yz
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Full adder implemented in SOP

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 Another implementation
■ Full-adder can also be implemented with two half adders and one
OR gate.

S = xy’z’ + x’yz’ + xyz + x’y’z

= z’(xy’ + x’y) + z(xy’ + x’y)’ ; Using De Morgan’s Law
= z’(A) + z(A)’ ;Where A = xy’ + x’y = x ⊕ y
=z⊕A
= z ⊕ (x ⊕ y)

C = xy’z + x’yz + xy = z(xy’ + x’y) + xy

= (x ⊕ y).z + xy

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 Another implementation
■ Full-adder can also be implemented with two half adders and one
OR gate.

S = z ⊕ (x ⊕ y)

C = (x ⊕ y).z + xy

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 Another implementation
■ Full-adder can also implemented with two half adders and one
OR gate.

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Block diagram of FA

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 Ripple-Carry Adders
• Half Adder adds two binary bits (Two significant bits).
• Full Adder adds three binary bits (Two significant bits and one carry
bit).

• For addition two n-bits numbers,

– n Full-Adders can be connected in series.
– Use same approach as manual computation
• Apply the same basic binary addition rules at each bit position.
• Need to handle ―Carry In‖ for higher bit position additions.

• The carry bit ―ripples‖ from one adder to the next; hence, this
configuration is called a Ripple-Carry Adder.
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 Ripple-Carry adder
■ This is also called Ripple
Carry Adder ,because of
the construction with
full adders are
connected in cascade.

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4-Bit Ripple Carry Adder

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 4-Bit Ripple Carry Adder/Subtractor

■ M=0, It performs addition

■ M=1, It performs subtraction

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 Exercise

■ Design a 8-bit Ripple Carry Adder

■ Design a 8-bit Ripple Carry Adder/Subtractor

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 Carry Propagation

■ Whenever addition of two n-bit numbers (A & B) is performed.

■ A, B and C0 is available.
■ All bits of A and B are available initially.
■ The carry bit is not available for all adders.

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 Carry Propagation
■ The Ripple-Carry Adder causes a unstable factor on carry bit, and produces a
longest propagation delay.

■ The signal from Ci to the output carry Ci+1, propagates through an AND and OR
gates, so, for an n-bit RCA, there are 2n gate levels for the carry to propagate
from input to output.

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4-Bit Ripple adder

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 Carry Look-ahead Adder
■ Because the propagation delay will affect the output signals on
different time, so the signals are given enough time to get the
precise and stable outputs.

■ The most widely used technique employs the principle of Carry

Look-Ahead to improve the speed of the Adders.

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 Carry Look-ahead Adder (The Sum Bit)
Pi = Ai⊕Bi Steady state value
Gi = AiBi Steady state value

Gi : carry generate Pi : carry propagate

Output sum and carry

Si = Pi ⊕ Ci
Ci+1 = Gi + PiCi

S0 = P0⊕ C0

S1 = P1⊕C!

S2 = P2⊕C2

S3 = P3⊕C3 81
Carry Look-ahead Adder (The Carry Bit)
Pi = Ai⊕Bi Steady state value
Gi = AiBi Steady state value

C0 = input carry

C1 = G0 + P0C0 = A0B0 + (A0⊕B0).C0

C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0

C2 = A1B1 + (A1⊕B1)(A0B0) + (A1⊕B1)(A0⊕B0)C0

C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C3 = A2B2 + (A2⊕B2).(A1B1) + (A2⊕B2)(A1⊕B1)(A0B0) +
(A2⊕B2)(A1⊕B1)(A0⊕B0)C0

C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

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Carry Look-ahead Adder (The Carry Bit)
Pi = Ai⊕Bi Steady state value
Gi = AiBi Steady state value

C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

C4 = G3 + P3C3 = G3 + (A3⊕B3).G2 + (A3⊕B3).(A2⊕B2).G1

+ (A3⊕B3).(A2⊕B2).(A1⊕B1).G0 +
+ (A3⊕B3).(A2⊕B2).(A1⊕B1).(A0⊕B0).C0

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 Carry Look-ahead Adder (The Carry Bit)
Using the previous equations, All output carries for all
adders can be generated using A, B and C0 only.

Now, It is obvious that

■ C4 does not have to wait for C3 to propagate.

■ C3 does not have to wait for C2 to propagate.
■ C2 does not have to wait for C1 to propagate.
■ C1 does not have to wait for C0 to propagate.

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 Logic diagram of Carry look-ahead generator
■ C3 is propagated at the same time as C2 and C1.

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 4-bit Carry Lookahead Adder (CLA)
■ Delay time of n-bit CLAA = XOR + (AND + OR) + XOR

86
 Exercise

■ Design a 8-bit Carry Look-ahead Adder

87
Home-Assignment

88
 Find logical function & Truth Table
F2 = AB + AC + BC;
T1 = A + B + C; T2 = ABC; T3 = F2’T1;

F1 = T 3 + T 2

F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

Hint: De Morgan’s Law

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Circuit Implementation of Logic Expressions:- Examples

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Circuit Implementation of Logic Expressions:- Homework

91
Truth Tables: Find Output

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Find Truth Table of the logic circuit

93
Example: Find the logic expression and fill up the truth table for the circuit below.

94
Homework: Find the logic expression and fill up the truth table for the circuit below.

95
 Boolean Algebra (Examples)

Simplify the expressions given below. Use truth tables to verify your results.

96
 Boolean Algebra (Examples - Cont.)

Simplify the expressions given below. Use truth tables to verify your results.

97
 Boolean Algebra (Examples - Cont.)

Simplify the expression given below. Use truth tables to verify your results.

98
 Boolean Algebra (Examples - Cont.)

Simplify the expression given below. Use truth tables to verify your results.

99
Thank You

100