BALLARI INSTITUTE OF TECHNOLOGY & MANAGEMENT,

BALLARI.
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING

VLSI MINI-PROJECT – 2015-16

“IMPLEMENTATION OF LOGIC GATES USING TANNER TOOLS AND

XILINX ISE 14.7”

Project Associates
Name of student USN

1. JAGADEESH PRASAD H 3BR13EC036

2. HARSH G JAIN 3BR13EC041

3. HARICHARAN M S 3BR13EC039

Staff Handling Mini Projects

Mr. PRAMOD M

Mr.PREMCHAND

Mr. VIJAY PATEL Signature of H.O.D

Dr. U. Eranna
CONTENTS
 ABSTRACT
 INTRODUCTION
 SOFTWARES USED
 DESCRIPTION OF SOFTWARES
 BLOCK DIAGRAMS AND ITS
DESCRIPTION
 CIRCUIT,CODE AND
IMPLEMENTATION
 IMPLEMENTED WAVEFORMS
 APPLICATIONS
 CONLUSION
 REFERENCES
 Abstract
According to the density of chips, designers are trying
to put so many facilities of computational and storage
on single chips. Along with the complexity of
computational and storage circuits, the designing, the
testing and debugging become more and more
complex and expensive. So, hardware design will be
built by using hardware description language, which is
more efficient and cost effective. These projects will
focus on the implementation of LOGIC GATES based
on Switch level Verilog hardware description language
and Tanner Tools. The General strategy for designing
logic gates is to reduce time and to incorporate to
improve performance in various digital circuits.
 INTRODUCTION
This project has done in switch level manner. The
implementation of logic gates has done on ModelSim
XE 14.7IIIb. A logic gates is basic combinational circuit
performing logical operations. Logic gates are
primarily implemented using diodes and transistors
acting as electronic switches, but can also be
constructed using vacuum tubes, electromagnetic
relays, optics,molecules elements. With amplification,
logic gates can be cascaded in the same way that
Boolean functions can be composed, allowing the
construction of a physical model of all of Boolean
logic, and mathematics that can be described with
Boolean logic.
Logic circuits include such devices as multiplexers,
registers, arithmetic logic units(ALUs),and computer
memory, all the way up through the complete
microprocessors, which my contain more than
hundred million gates.
Compound logic gates AND-OR-INVERT(AOI) and OR-
AND-INVERT(OAI) are often employed in circuit
design because there construction using MOSFETs is
simpler and more efficient than the sum of individual
gates.
 SOFTWARES USED

 TANNER TOOLS (TANNER EDA)

S-EDIT
T-SPICE
W-EDIT

 XILINX ISE 14.7

MODELSIM SIMULATER
 DESCRIPTIONS OF SOFTWARES
TANNER EDA:

Tanner EDA offers a complete analog and digital IC design

environment supporting analog, mixed-signal, or MEMS
domains in one highly-integrated end-to-end flow.

Full Flow Solutions

Schematic Capture- S-Edit

Transform spice-T-Spice

Waveform Editor – W-Edit

Behavioral Modeling – Verilog-A

Layout Editor- L-Edit

XILINX ISE 14.7:

Xilinx ISE 14.7 (Integrated Synthesis Environment) is a

software tool produced by Xilinx for synthesis and analysis
of HDL designs, enabling the developer to synthesize
("compile") their designs, perform timing analysis, examine
RTL diagrams, simulate a design's reaction to different
stimuli, and configure the target device with the
programmer.
 BLOCK DIAGRAMS AND ITS
DESCRIPTION
1. NOT Gate:

The NOT gate is an electronic circuit that produces an

inverted version of the input at its output. It is also
known as an inverter. If the input variable is A, the
inverted output is known as NOT A. This is also shown as
A', or A with a bar over the top, as shown at the outputs.
The diagrams below show two ways that the NAND logic
gate can be configured to produce a NOT gate. It can also
be done using NOR logic gates in the same way.
2.NAND Gate:

This is a NOT-AND gate which is equal to an AND gate

followed by a NOT gate. The outputs of all NAND gates are
high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents
inversion.
3.NOR Gate:

This is a NOT-OR gate which is equal to an OR gate followed

by a NOT gate. The outputs of all NOR gates are low if any
of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.
 CIRCUIT,CODE AND IMPLIMENTATION
NAND GATE IMPLIMENTATIION USING TANNER TOOLS

S –EDIT WINDOW VIEW

T-SPICE

CODE FOR SIMULATION:

.tran 10ns 100ns

v1 A GND BIT ({00001111})

v2 B GND BIT ({00110011})

v3 VDD GND 5

.print tran v(y) v(A) v(B)

NAND GATE SIMULATED WAVEFORM IN T-SPICE WINDOW
IN XILINX:

NAND GATE CODE:

module nand2(in1,in2,out);
input in1,in2;
output out;
supply1 vdd;
supply0 gnd;
pmos (out,vdd,in1),(out,vdd,in2);
nmos (out,a,in1),(a,gnd,in2);
endmodule

TEST BENCH :

module nand2_tb;
// Inputs
reg in1;
reg in2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
nand2 uut (
.in1(in1),
.in2(in2),
.out(out)
);
initial begin
// Initialize Inputs
in1 = 0;
in2 = 0
// Wait 10 ns for global reset to finish
#10
in1 = 0;
in2 = 1;
// Wait 10 ns for global reset to finish
#10;
in1 = 1;
in2 = 0;
// Wait 10 ns for global reset to finish
#10;
in1 = 1;
in2 = 1;
// Wait 10 ns for global reset to finish
#10;
// Add stimulus here
end
endmodule

WAVEFORMS OF SIMULATED NAND GATE IN XILINX:

NOR GATE IMPLIMENTATIION USING TANNER TOOL

S –EDIT WINDOW VIEW

T-SPICE

CODE FOR SIMULATION:

.tran 10ns 100ns

v1 A GND BIT ({00001111})

V2 B GND BIT ({00110011})

V3 VDD GND 5

.print tran v(y) v(A) v(B)

NOR GATE SIMULATED WAVEFORM IN T-SPICE WINDOW
IN XILINXS

2-Input NOR Gate code:

module nor_2(in1,in2,out);
input in1,in2;
output out;
wire o;
supply1 a;
supply0 b;
pmos(out,o,in1),(o,a,in2);
nmos(out,b,in1),(out,b,in2);
endmodule

TEST BENCH :

module nor_2_tb;
// Inputs
reg in1;
reg in2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT
nor_2 uut (
.in1(in1),
.in2(in2),
.out(out));
initial begin
// Initialize Inputs
in1 = 0;
in2 = 0;
// Wait 10 ns for global reset to finish
#10;
in1 = 0;
in2 = 1;
#10;
in1 = 1;
in2 = 0;
#10;
in1 = 1;
in2 = 1;
#10;
// Add stimulus here
end
endmodule

WAVEFORMS OF SIMULATED NOR GATE IN XILINX

INVERTER IMPLIMENTATIION USING TANNER TOOL

S –EDIT WINDOW VIEW

T-SPICE

CODE FOR SIMULATION:

.tran 10ns 100ns

v1 A GND BIT ({00001111})

V3 VDD GND 5

.print tran v(y) v(A)

INVERTER SIMULATED WAVEFORM IN T-SPICE WINDOW
IN XILINX:
INVERTER CODE :

module inv( in,out);

input in;
output out;
supply1 a;
supply0 b;
pmos(out,a,in);
nmos(out,b,in);
endmodule

TEST BENCH:

module inv_tb;
reg in;
wire out;
// Instantiate the Unit Under Test (UUT)
inv uut (
.in(in),
.out(out) );
initial begin
// Initialize Inputs
in = 0;
// Wait 10 ns for global reset to finish
#10;
in = 1;
#10;
in = 0;
#10;
in = 1;
#10
// Add stimulus here

end

endmodule
WAVEFORMS OF SIMULATED INVERTER IN XILINX:
 APPLICATIONS
NAND Gate:

1.Burglar alarm:-

When the switch is closed one input of the NAND gate is

LOW. When the LDR is in the light the other input is LOW.
This means that if either of these things happen, i.e. the
switch is closed or the light is on one of the inputs is LOW,
the output is HIGH and the buzzer sounds.

2.Freezer warning buzzer:-

When the thermistor is COLD its resistance is LARGE and

the input to the NAND gate is high. Since the NAND gate is
connected as an INVERTER the output is LOW.As the
thermostat warms up its resistance decreases, the voltage
across it falls and the input to the NAND gate falls. When it
becomes low enough the output becomes HIGH and the
buzzer sounds.
NOR Gate:

1. Cell Phone
2. Computing
3. LCD TV
4. Industrial Controllers

INVERTER:

1. Pulsed Operation
2. To build the fastest full digital-Swing oscillator
3. As switch
 CONCLUTION

The implementation of the logic gate(NAND,NOR &

INVERTER) design based on Switch level verilog hardware
description language and tanner tools software has been
implemented correctly. The result obtained matches with
the truth table values.
 RESOURCES
Website:
 http://www.tannereda.com
 http://www.xilinx.com
 ^”foundation series ISE 3.1i user guide”.100728 xilinx.com
 ^circuit design with VHDL
HDL Programming(VHDL and Verilog)-Nazeih M.Botros-John
Weily India Pvt.Ltd.2008
 A Verilog HDL Primer-J.Bhaskar-BS Publications