Exp:02

Date:8-2-19

FULL ADDER:-

module FAbehav(

input a,

input b,

input cin,

output s,

output cout

);

reg s,cout;

always @(a or b or cin)

begin

if(a==0&&b==0&&cin==0)

begin

s=0;

cout=0;

end

else if(a==0&&b==0&&cin==1)

begin

s=1;

cout=0;

end

else if(a==0&&b==1&&cin==0)
Exp:02
Date:8-2-19

begin

s=1;

cout=0;

end

else if(a==0&&b==1&&cin==1)

begin

s=0;

cout=1;

end

else if(a==1&&b==0&&cin==0)

begin

s=1;

cout=0;

end

else if(a==1&&b==0&&cin==1)

begin

s=0;

cout=1;

end

else if(a==1&&b==1&&cin==0)

begin
Exp:02
Date:8-2-19

s=0;

cout=1;

end

else

begin

s=1;

cout=1;

end

end

endmodule

Test bench :-

module t3;

reg a;

reg b;

reg cin;

wire s;

wire cout;

FAbehav uut (

.a(a),
Exp:02
Date:8-2-19

.b(b),

.cin(cin),

.s(s),

.cout(cout)

);

initial begin

a = 0;

b = 0;

cin = 0;

#100;

a = 0;

b = 0;

cin = 1;

#100;

a = 0;

b = 1;

cin = 0;

#100;

a = 0;

b = 1;

cin = 1;
Exp:02
Date:8-2-19

#100;

a = 1;

b = 0;

cin = 0;l

#100;

a = 1;

b = 0;

cin = 1;

#100;

a = 1;

b = 1;

cin = 0;

#100;

a = 1;

b = 1;

cin = 1;

#100;

end

endmodule
Exp:02
Date:8-2-19

HALF ADDER:-

module hAdata(

input A,

input B,

output C,

output S

);

assign S=A^B;

assign C=A&B;

endmodule

Test bench:-

module t1;

reg A;

reg B;

wire C;

wire S;

hAdata uut (
Exp:02
Date:8-2-19

.A(A),

.B(B),

.C(C),

.S(S)

);

initial begin

A = 0;

B = 0;

#100;

A = 0;

B = 1;

#100;

A = 1;

B = 0;

#100;

A = 1;

B = 1;

#100;

end

endmodule