ECEN 468

Advanced Digital System Design

Lecture 8: Bus Architecture

ECEN 468 Lecture 8

 A Brief Picture

Processor Memory

DMA UART
Controller

ECEN 468 Lecture 8 2

 Terminology

v  Bus master: that initiates data transfer

v  Bus slave: addressed by the master
o  Some components are always masters, some are always slaves and some
can do each at different time

v  Bus arbitration: decide the next bus master

v  Decoder: decode address
v  Bridge: interface between two different buses

ECEN 468 Lecture 8 3

 Bus Signal Types

v  Address
v  Data
o  Typical data width 8-1024 bits
v  Control
o  Request
o  Acknowledge
o  Grant
o  … …

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Implementation of Bus Signals: Tri-state

Memory
Processor

Control

v  Less devices, wires and area

v  High power, high delay, hard to debug
v  Common for off-chip/backplane buses

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Implementation of Bus Signals: Mux

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 Bus Arbitration Schemes

v  Fixed priority (static priority)

o  Preemptive
o  Non-preemptive
o  Starvation of low-priority masters
v  Rotating priority (round-robin)
o  Critical data may wait for long time
v  TDMA (time division multiple access)
o  Each master is allocated certain time slots for data communication
v  Dynamic priority
v  Hybrid

ECEN 468 Lecture 8 7

 Centralized Bus Arbitration

BBUSY
BRQST Wired AND
Arbiter
BGRNT1 BGRNT2 Daisy
Comp1 Comp2
chain

BRQST

BGRNT1
BGRNT2

BBUSY

ECEN 468 Lecture 8

8
 Distributed Bus Arbitration

v  No arbiter, less arbitration hardware

v  Each component has an ID
v  Based on wired logic among bus requests, if it matches with ID
v  Often requires significant circuit change when additional
components are added
o  Easier for centralized arbitration

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 Data Transfer: Asynchronous
Request, Grant

Address

Master ready

Slave ready

Data

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 Data Transfer: Synchronous

Clock

Request, Grant

Address

Data

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 Data Transfer: Pipelined

Clock

Request1

Request2

Grant1

Grant2

Address A1 A2

Data D1 D2
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 Other Data Transfer Modes

v  Burst transfer

o  For one arbitration, do multiple data transfers
v  Split transfer
o  If slave operation will take multiple cycles, it issues “split” to arbiter
o  Its master is idle waiting for the slave
o  The arbiter start process next requests, masking of THE master
v  Out-of-order transfer
o  Interleave data transfers from multiple masters
v  Broadcast transfer
o  1 source, multiple receivers of the data

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 AMBA Bus

v  Advanced Microcontroller Bus Architecture

v  On-chip bus for SoC designs, like smart phone chips
v  Introduced by ARM in 1996
v  AMBA 1
o  ASB: Advanced System Bus
o  APB: Advanced Peripheral Bus
v  AMBA 2, AHB (Advanced High-performance Bus), extension
to ASB
v  AMBA 3, AXI (Advanced eXtensible Interface)
v  de facto standard for 32-bit embedded processors

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 AMBA Bus
AHB APB
v High performance v Low power
v Pipelined transfers v Simple interface
v Burst transfers v Accommodate many peripherals
v Split transfers
v Multiple masters

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 AHB Lite Architecture

v Supports burst transfers

v Mux-based implementation
v Configurable bus width

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 Bus Matrix (Crossbar)

Master1 Master2 Master3

Switched
link

Slave1 Slave2 Slave3

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 Partial Crossbar

Master1 Master2 Master3

Slave1 Slave2 Slave3

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 Multi-Master AHB Lite

v AHB-Lite allows only 1

master
v If multi-master needed
o  Isolate masters by additional
interconnect layer
o  The interconnect ~ partial
crossbar

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 PCI Bus

v  Peripheral Component Interconnect

v  Off-chip bus
v  Based on IBM PCs
v  Designed by Intel in 1992
v  Plug-and-play capability for connecting I/O components

ECEN 468 Lecture 8 20

 USB

v Universal Serial Bus Host computer

v Message from host broadcast to Root
all I/O components hub
v An I/O talks with host, not
other I/O Hub Hub
v Serial links
v Host poll each I/O Hub
v An I/O sends only if it is polled
v Data packet includes ID and
CRC (cyclic redundancy check)

ECEN 468 Lecture 8 21

Networks-On-Chip

Core

Router

Link

Data are transported

in packets like in
macro world network

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