A 70-nA 13-ppm/℃ All-MOSFET Voltage Reference

for Low-Power IoT Systems

Jianping Guo, Weimin Li, Yicheng Li, Siji Huang, Zhao Wang, Bing Mo*, and Dihu Chen
School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China
E-mail: mobing3@mail.sysu.edu.cn

Abstract—This paper presents a low-power All-MOSFET source without resistor is used to provide the bias current for
voltage reference implemented on a 0.18-μm standard CMOS the whole voltage reference [7]. A PTAT voltage generated by
technology. In order to improve the temperature coefficient (TC) the difference between gate-source voltages of NMOS
of voltage reference, a TC compensation technique based on transistors and a CTAT voltage generated by source-gate
controlling bulk voltage is proposed. The proposed voltage voltage of a diode-connected transistor are added to generate
reference achieves a TC of 13 ppm/℃ from -40 ℃ to 125 ℃ an output voltage with a near-zero temperature coefficient. In
while dissipating a supply current of 70 nA in normal temperature. order to further reduce the temperature coefficient (TC), a TC
The line regulation is 0.02%/V when the supply voltage varies comprehension method based on controlling bulk voltage is
from 1.3 V to 2.1 V, and the power supply rejection ratio (PSRR) adopted to improve the TC performance in the high
at 100Hz is 74 dB due to the cascode current mirror. Moreover, temperature and it doesn’t consume much power.
the current mirror can be reconfigured easily so that the output This paper is organized as follows: Section II introduces the
voltage can be trimmed in this design. principle of the proposed voltage reference, Section III presents
the simulation results and discussions, and Section IV
Keywords—Voltage reference; All-MOSFET; Low power; TC concludes this paper.
compensation; Trimming; High PSRR
Ⅱ. PRINCIPLE OF OPERATION
Ⅰ. INTRODUCTION
The schematic of the proposed voltage reference except
The demand for low-power and low-cost designs is startup circuit is shown in Fig. 1(a). It consists of current source
becoming increasingly dominant due to popularity and circuit [7], reference voltage generator and TC compensation
expansion of application in the area of Internet of Things (IoT), circuit. The detail analysis is given in the following.
where a longer lifetime and lower cost are required for the
system. A. Current Source Circuit
Voltage reference is one of the fundamental building blocks The drain current of a MOSFET operating in the sub-
used in IoT systems. Bandgap reference (BGR) circuits with threshold region can be formulated as:
CMOS-based vertical bipolar transistors are the conventional
type of voltage reference [1-4]. The BGR circuits produce a −
VGS −VTH
 V
− DS 
voltage about 1.2V which is composed by a weighted sum of I D = (η − 1) μCoxVT 2 Se ηVT
 1 − e VT  (1)
 
VBE and the thermal voltage. To achieve low temperature  
coefficient and low power consumption, the BGR circuit where S is the aspect ratio, is the sub-threshold slope, is
should adopt curvature compensation approaches and high the thermal voltage. For | | ≥ 4 , the effect of the in
ohmic resistors, which means complex circuit implementation (1) can be ignored. Hence
and large area cost. Therefore, traditional BGR circuits are not
welcome in IoT systems. In order to solve these problems, the ID
VGS = VTH + ηVT ln (2)
proportional to absolute temperature (PTAT) voltage or IS S
complementary to absolute temperature (CTAT) voltage can be Applying KVL in the loop formed by MP1, MP2 and MR,
served by CMOS threshold voltage and the resistor can be then
replaced by MOSFET that operates in the deep-triode region
[5-6]. As a result, the CMOS voltage references have been Vsg1 = Vsg 2 + VsdR (3)
suggested as an alternative to the BGR circuit.
This paper presents a simple low-power all-MOSFET Since MP1 and MP2 work in the sub-threshold region,
voltage reference implemented on a 0.18-μm standard CMOS using (2), can be expressed as
technology. A modified beta multiplier self-biased current S
VsdR =η pVT ln 2 (4)
S1
This work was partly supported by the Pearl River S&T Nova Program
of Guangzhou (Grant No. 201610010086), and the Fundamental Research
where and are the aspect ratios of MP1 and MP2,
Funds for the Central Universities (Grant No. 20177612031620006).
respectively.

978-1-5386-4881-0/18/$31.00 ©2018 IEEE

 (b)

(a) (c)
Fig. 1. Schematics of (a) the proposed voltage reference, (b) current source trimming block, and (c) TC trimming block.

The transistor MR operates in the deep-triode region and (MP14) and NMOS couple (MN9 and MN10). It’s shown that
MP3 is in the saturation region, hence the drain current of MR the drain current of MP14, which operates in the saturation
and MP3 are given by: region, is equal to 2 . Hence, is given as

I R = μ pCox S R (VsgR − VthR )Vsd (5) 4 I ref

Vsg14 = Vth14 + (10)
μ p Cox S14
1
I 3 = μ p Cox S3 (Vsg 3 − Vth 3 )
2
(6)
2 According to : = 4: 1 and (7), we can derive that
For =2 =2 and −| |= −| |,
substituting (4) and (6) in (5), is given as SR2 S
Vsg 14 = Vth14 + 2 η pVT ln 2 (11)
S 2 S S3 S14 S1
I bias = 4 μ p Cox R η p 2VT 2 ln 2 2 (7)
S3 S1
The depends on temperature as
The mobility that depends on temperature is given by
Vth ( T ) = Vth 0 − α ( T − T0 ) (12)
m
T 
μ ( T ) = μ0   (8) where is the threshold voltage at temperature , and
 T0  is the TC of threshold voltage, which is a positive constant.
Note that is the mobility at temperature T0, and m, Note that Vsg14 is a CTAT voltage, because is usually larger
which depends on the process used, is the mobility temperature than the temperature coefficient of .
exponent. What’s more, both MN9 and MN10 operate in the sub-
Given = /q and (8), the will result as threshold region. Using (2) and ignoring the difference of ,
the between MN9 and MN10 is shown as follow
m
1 S 2 K S S10
I bias = 4 μ0   R (η p ln 2 ) 2 T 2 − m (9) ΔVgs = η nVT ln (13)
T
 0 S 3 q S1 S9
Combining with (11) and (13), the output voltage of the
It is apparent that the proposed current source can generate proposed voltage reference can be given as
nano-ampere current which has positive correlation with
temperature by adjusting / and / .  SR 2 S S 
Vref = Vth14 + VT  2 η p ln 2 + ηn ln 10  (14)
B. Reference Voltage Generator  S3S14 S1 S9 

The cascode current mirrors, which consist of transistors
(MN1~MN8, MP6~MP13) operating in the sub-threshold Therefore, a near-zero TC reference voltage can be
region, copy to and , in a ratio of 4:1. It can achieved by adjusting the aspect ratio of MR, MP1, MP2, MP3,
lower power consumption of reference voltage generator. MP14, MN9 and MN10.
From Fig. 1(a), flows into diode-connected PMOS

978-1-5386-4881-0/18/$31.00 ©2018 IEEE

 C. TC compensation circuit 575.8m 0.6
-20

Since the substrate of MP14 connects to the source of MP15 0.4

PSRR (dB)
rather than that of itself, there exists the body effect in MP14. 575.8m 0.2
-40

V RE F (V)
The expression of of PMOS is given by [8] 0.0
0.0 0.7 1.4 2.1 2.8

575.8m

( )
-60

VTH = VTH 0 + γ 2φF + VBS − 2φF

(15) 575.8m
-80
≈ VTH 0 + (η − 1)VBS 575.7m 0 2 4 6 8
1.2 1.5 1.8 2.1 10 10 10 10 10
where is the threshold voltage with zero body bias, is VDD (V) Frequency (Hz)
the body effect constant, is the Fermi potential and is (a) (b)
the bulk- source voltage.
Fig. 4 (a) simulated supply dependence of . (b) simulated PSRR
According to = and (11), we can derive that

 1 1   SR 2 S 
Vbs = Vsg15 − Vsg14 =  −   2 η pVT ln 2  (16) 400 250
 S15 S14   S3 S1  n=1000
200
n=1000
300 μ=577mV μ=16 ppm/℃
Since < , is less than zero and is the CTAT σ=20mV 150 σ=2 ppm/℃
200
voltage at the same time. 100
Substituting (16) into (15), becomes 100 50
Vth14* = Vth14 + (η p − 1) ξVT (17) 0 0
515 545 575 605 635 665 10 12 14 16 18 20 22 24
(V) TC (ppm/℃)
where = − 2 ln . It is noted that
( a) (b )
| ∗ | is smaller than | | , especially at high Fig. 5. MC simulation for process variations. (a) . (b) TC
temperature. The temperature characteristic curve of voltage
reference without TC compensation is shown in Fig. 2 (a), and
Fig. 2 (b) shows the voltage reference with TC compensation. 640.0m
22.5ppm/ C
o
tt 17.4ppm/oC
640.0m
It is apparent that the body effect, which generates leakage 12.3ppm/ C
o ff
fs
12.3ppm/oC

current from parasitic diode, can compensate TC of reference 600.0m 600.0m

VREF (V)

13.1ppm/ C
o
sf 13.1ppm/oC
ss
voltage at high temperature. The TC of reference voltage can 560.0m 560.0m

be decreased from 21 ppm/℃ to 13 ppm/℃. 520.0m 16.5ppm/ C

o
16.5ppm/oC 520.0m

23.8ppm/ C
o
13.2ppm/oC
480.0m 480.0m
-60 -30 0 30 60 90 120 -60 -30 0 30 60 90 120
577.2m
Temperature ( C)
o
Temperature (oC)
570.5m
576.9m
o (a) (b)
570.0m 21.3ppm/ C
o 13.1ppm/ C
576.6m Fig. 6. Simulated temperature dependence of for different
V REF (V)
VREF (V)

569.5m
576.3m corners. (a) before trimming. (b) after trimming
569.0m
576.0m

568.5m 575.7m
-60 -30 0 30 60 90 120 -60 -30 0 30 60 90 120 III．SIMULATION RESULTS AND DISCUSSIONS
Temperature (oC) Temperature (oC)
The proposed voltage reference is implemented on a 0.18-
(a) (b) μm standard CMOS technology. The circuit totally consumes
Fig. 2. Simulated temperature dependence of for = 1.5 . 70 nA in 1.5 V supply voltage at room temperature. The ratio
(a) without TC compensation circuit, and (b) with proposed TC of current consumption in each branch is shown in Fig. 1(a).
compensation circuit. A. Simulation Results
The output voltage as a function of temperature with
0.5776 supply voltage as a parameter in typical condition is
0.5772
105.00n
shown in Fig. 3(a). The average of is 576 mV. The
90.00n voltage variation is about 1.2 mV in a temperature range from
VREF (V)

−40 ℃ to 125 ℃, so the TC is about 13 ppm/℃. The total

IDD (A)

0.5768
75.00n 1.3
1.5
0.5764 1.3 60.00n 1.7
current as a function of temperature with as a
0.5760
1.5
1.7
45.00n
1.9 parameter is shown in Fig. 3(b). is about 70 nA at room
1.9
2.1
2.1
temperature and reaches the maximum of 125 nA at 125℃.
0.5756
-60 -30 0 30 60 90 120
30.00n
-60 -30 0 30 60
o
90 120 Fig. 4(a) shows as a function of at room
Temperature (oC) Temperature ( C) temperature. The minimal supply voltage requirement is 1.3 V.
(a) (b) The line regulation is 0.02%/V for in the range of 1.3 V
Fig. 3. Simulated temperature dependence for various . (a) . (b) to 2.1 V. In addition, Fig. 4(b) shows the PSRR for = 1.5
at room temperature, the PSRR of at 100Hz and 10MHz
correspond to 74 dB and 37 dB, respectively.

978-1-5386-4881-0/18/$31.00 ©2018 IEEE

 The sensitivity of to process variations is shown in TABLE I
Fig. 5. The mean is 577 mV, the standard deviation is
20 mV, and the reference voltage of variation σ/μ is about 3.5%. This Work [10] [11] [12] [13] [14]
What’s more, the average TC of is 16 ppm/℃ , the
Process 0.18μm 0.18μm 0.35μm 0.18μm 0.18μm 90nm
standard deviation is 2 ppm/℃, and the reference voltage of
variation σ/μ is about 12.5%. It is noted that the value of Year 2017 2013 2013 2017 2017 2015
is sensitive to process variations because depends on
which is about 150 mV deviation in the statistics of process. Supply
1.3 0.7 0.75 0.8 1.1 1.15
According to [6], the measured value will be far smaller than voltage(V)
expected from the Monte Carlo simulations. Since the sample
chips are fabricated from the same wafer, it is an overestimation Supply current
70 None 2500 None 500 500
on the Die-to-Die variation simulations and the variation of the (nA)
reference voltage become smaller.
Power (nW) 91 52 2000 79 550 580
B. Trimming Technique
VREF (mV) 576 548 259 328 893 720
According to [9], threshold voltage differences (ΔV ) and
current factor differences ( Δ / ) are the dominant Temperature
-40 - 125 -40 - 120 -45 - 145 10 - 100 -30 - 80 0 - 100
sources underlying either the gate-source voltage or the drain- (℃)
source current mismatch for a matched pair of MOS transistors.
In order to reduce the impact of mismatch on current source, TC (ppm/℃) 13.1 114 2 33.8 19 43.5
another trimming block, which is shown in Fig. 1(b), is adopted
LS (%/V) 0.02 None None 0.21 0.09 0.3
by trimming the aspect ratio M3 and M6. It is believed that the
trimming block of current mirrors can optimize the PSRR (dB)
performance of current source in practical application. -74 -56 None -55 -75 -51
@100Hz
Fig. 6(a) shows the temperature characteristic of in
different process corners. The best case is 13 ppm/℃ and the Resistors None None Yes None None Yes
worst case is 24 ppm/℃. In order to improve TC performance
Measure or
in all corners, the trimming block is used on output stage to trim Simulation Measure Simulation Measure Measure Measure
the aspect ratio of M10 as shown in Fig. 1(c). The TC of Simulation
in all corners after trimming are shown in Fig. 6 (b). With the
trimming circuit, the worst TC can be down to 17 ppm/℃. [4] Y. Jiang and E. K. F. Lee, “Design of low-voltage bandgap reference
Table I summarizes the performance of the proposed using transimpedance amplifier,” IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing, vol. 47, no. 6, pp. 552-
voltage reference in comparison with other voltage references 555, Jun 2000.
reported in [10–14]. The proposed voltage reference can [5] S. S. Chouhan and K. Halonen, “Design and implementation of a micro-
achieve lower power than [11], [13] and [14]. The TC is better power CMOS voltage reference circuit based on thermal compensation
than [10] and [12-14], and the PSRR is better than [10-12] and of V-gs,” Microelectronics Journal, vol. 46, pp. 36-42, 2015.
[6] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 15 ppm/℃,
[14]. Therefore, the features of low-power, high precision, and 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold
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time, most of the transistors operate in the sub-threshold region, Design, Curitiba, 2013, pp. 1-4.
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