A 70nA 13ppm/℃ AllMOSFET Voltage Reference for LowPower IoT Systems
Jianping Guo, Weimin Li, Yicheng Li, Siji Huang, Zhao Wang, Bing Mo ^{*} , and Dihu Chen School of Electronics and Information Technology, Sun Yatsen University, Guangzhou, China Email: mobing3@mail.sysu.edu.cn
Abstract—This paper presents a lowpower AllMOSFET voltage reference implemented on a 0.18μm standard CMOS technology. In order to improve the temperature coefficient (TC) of voltage reference, a TC compensation technique based on controlling bulk voltage is proposed. The proposed voltage reference achieves a TC of 13 ppm/ ℃ from 40 ℃ to 125 ℃ while dissipating a supply current of 70 nA in normal temperature. The line regulation is 0.02%/V when the supply voltage varies from 1.3 V to 2.1 V, and the power supply rejection ratio (PSRR) at 100Hz is 74 dB due to the cascode current mirror. Moreover, the current mirror can be reconfigured easily so that the output voltage can be trimmed in this design.
Keywords—Voltage reference; AllMOSFET; Low power; TC compensation; Trimming; High PSRR
Ⅰ. INTRODUCTION
The demand for lowpower and lowcost designs is becoming increasingly dominant due to popularity and expansion of application in the area of Internet of Things (IoT), where a longer lifetime and lower cost are required for the system. Voltage reference is one of the fundamental building blocks used in IoT systems. Bandgap reference (BGR) circuits with CMOSbased vertical bipolar transistors are the conventional type of voltage reference [14]. The BGR circuits produce a voltage about 1.2V which is composed by a weighted sum of V _{B}_{E} and the thermal voltage. To achieve low temperature coefficient and low power consumption, the BGR circuit should adopt curvature compensation approaches and high ohmic resistors, which means complex circuit implementation and large area cost. Therefore, traditional BGR circuits are not welcome in IoT systems. In order to solve these problems, the proportional to absolute temperature (PTAT) voltage or complementary to absolute temperature (CTAT) voltage can be served by CMOS threshold voltage and the resistor can be replaced by MOSFET that operates in the deeptriode region [56]. As a result, the CMOS voltage references have been suggested as an alternative to the BGR circuit. This paper presents a simple lowpower allMOSFET voltage reference implemented on a 0.18μm standard CMOS technology. A modified beta multiplier selfbiased current
This work was partly supported by the Pearl River S&T Nova Program of Guangzhou (Grant No. 201610010086), and the Fundamental Research Funds for the Central Universities (Grant No. 20177612031620006).
9781538648810/18/$31.00 ©2018 IEEE
source without resistor is used to provide the bias current for the whole voltage reference [7]. A PTAT voltage generated by the difference between gatesource voltages of NMOS transistors and a CTAT voltage generated by sourcegate voltage of a diodeconnected transistor are added to generate an output voltage with a nearzero temperature coefficient. In order to further reduce the temperature coefficient (TC), a TC comprehension method based on controlling bulk voltage is adopted to improve the TC performance in the high temperature and it doesn’t consume much power. This paper is organized as follows: Section II introduces the principle of the proposed voltage reference, Section III presents the simulation results and discussions, and Section IV concludes this paper.
Ⅱ. PRINCIPLE OF OPERATION
The schematic of the proposed voltage reference except startup circuit is shown in Fig. 1(a). It consists of current source circuit [7], reference voltage generator and TC compensation circuit. The detail analysis is given in the following.
A. Current Source Circuit
The drain current _{} of a MOSFET operating in the sub threshold region can be formulated as:
I
D
(
=− 1
η
)
C
μ
ox
V
2
T
Se
e
(1)
where S is the aspect ratio, is the subthreshold slope, _{} is the thermal voltage. For  _{}_{} ≥4 _{} , the effect of the _{}_{} in (1) can be ignored. Hence
VV
GS
=
TH
V
+ η
T
ln
I
D
I
S
_{S}
(2)
Applying KVL in the loop formed by MP1, MP2 and MR, then
V
sg1
=
V
sg
2
+
V
sdR
(3)
Since MP1 and MP2 work in the subthreshold region, using (2), _{}_{}_{} can be expressed as
where _{}
respectively.
and _{}
V
sd
R
=η
p
V
T
ln
S
2
S
1
(4)
are the aspect ratios of MP1 and MP2,
Fig. 1.
Schematics of (a) the proposed voltage reference, (b) current source trimming block, and (c) TC trimming block.
The transistor MR operates in the deeptriode region and MP3 is in the saturation region, hence the drain current of MR and MP3 are given by:
I
R
= μ
p
CS
ox
R
( V
sgR
−
I
1
=
3 2
μ
p
CS
ox
3
( V
sg
3
V thR
)
−
V th 3
V sd
) ^{2}
(5)
(6)
For =2 =2 and − = − , substituting (4) and (6) in (5), _{}_{}_{}_{} is given as
S
R
2
ICV
bias
=
4
μ
p
ox
S
3
η
p
T
22
ln
2
S
2
S
1
(7)
The mobility that depends on temperature is given by
μ
(
T
)
=
μ
0
T
T
0
m
(8)
Note that _{} is the mobility at temperature T _{0} , and m, which depends on the process used, is the mobility temperature exponent. Given _{} = /q and (8), the _{}_{}_{}_{} will result as
I
bias
= 4
μ
0
1
m
S
2
R
T
S
03
K
S
2
(ln
η
p
qS
1
)
2
T
2 − m
(9)
It is apparent that the proposed current source can generate nanoampere current which has positive correlation with temperature by adjusting _{} ^{} / _{} and _{} / _{} .
B. Reference Voltage Generator
The cascode current mirrors, which consist of transistors (MN1~MN8, MP6~MP13) operating in the subthreshold region, copy _{}_{}_{}_{} to _{}_{}_{} and _{}_{}_{} , in a ratio of 4:1. It can lower power consumption of reference voltage generator. From Fig. 1(a), _{}_{}_{} flows into diodeconnected PMOS
(MP14) and NMOS couple (MN9 and MN10). It’s shown that the drain current of MP14, which operates in the saturation region, is equal to 2 _{}_{}_{} . Hence, _{}_{}_{}_{} is given as
V sg 14
=
V th 14
+
(10)
According to _{}_{}_{}_{} : _{}_{}_{} = 4: 1 and (7), we can derive that
VV
sg 14
=
th 14
+
2
η
p
V
T
ln
S
2
S
1
(11)
The _{}_{} depends on temperature as
(
VT
th
)
=−−α
th 0
0
V
(
TT
)
(12)
where _{}_{}_{} is the threshold voltage at temperature _{} , and
is the TC of threshold voltage, which is a positive constant. Note that Vsg14 is a CTAT voltage, because is usually larger than the temperature coefficient of _{} . What’s more, both MN9 and MN10 operate in the sub threshold region. Using (2) and ignoring the difference of _{}_{} , the _{}_{} between MN9 and MN10 is shown as follow
ΔV
gs
= η
n
V
T
ln
S
10
S
9
(13)
Combining with (11) and (13), the output voltage of the proposed voltage reference can be given as
VV =
ref
th
14
+
V
T
(14)
Therefore, a nearzero TC reference voltage can be achieved by adjusting the aspect ratio of MR, MP1, MP2, MP3, MP14, MN9 and MN10.
9781538648810/18/$31.00 ©2018 IEEE
C. TC compensation circuit
Since the substrate of MP14 connects to the source of MP15 rather than that of itself, there exists the body effect in MP14. The expression of _{}_{} of PMOS is given by [8]
VV
TH 0
V TH 0
) (15)
where _{}_{}_{} is the threshold voltage with zero body bias, is
the body effect constant, _{} is the Fermi potential and _{}_{} the bulk source voltage. According to _{}_{}_{} = _{}_{}_{} and (11), we can derive that
is
VV
sg
bs
=−=
15
14
V
sg
2
(16)
Since _{}_{} < _{}_{} , _{}_{} is less than zero and voltage at the same time. Substituting (16) into (15), _{}_{}_{}_{} becomes
VV
th
14*
=
th
14
(
+−
η
p
1
)
ξV
T
is the CTAT
(17)
where = ^{−} ^{}
_{} _{}_{} 2 ^{} ^{} ^{} _{} ln ^{} _{} ^{} . It is noted that
 _{}_{}_{}_{} _{∗}  is smaller than  _{}_{}_{}_{}  , especially at high temperature. The temperature characteristic curve of voltage reference without TC compensation is shown in Fig. 2 (a), and Fig. 2 (b) shows the voltage reference with TC compensation. It is apparent that the body effect, which generates leakage current from parasitic diode, can compensate TC of reference voltage at high temperature. The TC of reference voltage can be decreased from 21 ppm/℃ to 13 ppm/℃.
Temperature ( ^{o} C)
(a)
Temperature ( ^{o} C)
(b)
Fig. 2. Simulated temperature dependence of _{}_{}_{} for _{}_{} = 1.5 .
Fig. 3.
Simulated temperature dependence for various _{}_{} . (a) _{}_{}_{} . (b) _{}_{}
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Fig. 4 (a) simulated supply dependence of _{}_{}_{} . (b) simulated PSRR
400
300
200
100
0
_{}_{}_{} (V)
(a)
250
200
150
100
50
0
TC (ppm/℃)
(b)
Fig. 5.
MC simulation for process variations. (a) _{}_{}_{} . (b) TC
640.0m
600.0m
560.0m
520.0m
480.0m
Fig. 6. Simulated temperature dependence of _{}_{}_{} for different
corners. (a) before trimming. (b) after trimming
III．SIMULATION RESULTS AND DISCUSSIONS The proposed voltage reference is implemented on a 0.18 μm standard CMOS technology. The circuit totally consumes 70 nA in 1.5 V supply voltage at room temperature. The ratio of current consumption in each branch is shown in Fig. 1(a).
A. Simulation Results
The output voltage _{}_{}_{} as a function of temperature with supply voltage _{}_{} as a parameter in typical condition is
shown in Fig. 3(a). The average of _{}_{}_{} is 576 mV. The
voltage variation is about 1.2 mV in a temperature range from
−40 ℃ to 125 ℃, so the TC is about 13 ppm/℃. The total
current _{}_{} as a function of temperature with _{}_{} as a
parameter is shown in Fig. 3(b). _{}_{} is about 70 nA at room
temperature and reaches the maximum of 125 nA at 125℃.
Fig. 4(a) shows _{}_{}_{} as a function of _{}_{} at room temperature. The minimal supply voltage requirement is 1.3 V. The line regulation is 0.02%/V for _{}_{} in the range of 1.3 V to 2.1 V. In addition, Fig. 4(b) shows the PSRR for _{}_{} = 1.5 at room temperature, the PSRR of _{}_{}_{} at 100Hz and 10MHz correspond to 74 dB and 37 dB, respectively.
The sensitivity of _{}_{}_{} to process variations is shown in Fig. 5. The mean _{}_{}_{} is 577 mV, the standard deviation is 20 mV, and the reference voltage of variation σ/μ is about 3.5%. What’s more, the average TC of _{}_{}_{} is 16 ppm/℃, the standard deviation is 2 ppm/℃, and the reference voltage of variation σ/μ is about 12.5%. It is noted that the value of _{}_{}_{} is sensitive to process variations because _{}_{}_{} depends on _{}_{} which is about 150 mV deviation in the statistics of process. According to [6], the measured value will be far smaller than expected from the Monte Carlo simulations. Since the sample chips are fabricated from the same wafer, it is an overestimation on the DietoDie variation simulations and the variation of the reference voltage become smaller.
B. Trimming Technique
According to [9], threshold voltage differences (ΔV _{}_{} ) and current factor differences ( Δ _{}_{} / ) are the dominant sources underlying either the gatesource voltage or the drain source current mismatch for a matched pair of MOS transistors. In order to reduce the impact of mismatch on current source, another trimming block, which is shown in Fig. 1(b), is adopted by trimming the aspect ratio M3 and M6. It is believed that the trimming block of current mirrors can optimize the performance of current source in practical application. Fig. 6(a) shows the temperature characteristic of _{}_{}_{} in different process corners. The best case is 13 ppm/℃ and the worst case is 24 ppm/℃. In order to improve TC performance in all corners, the trimming block is used on output stage to trim the aspect ratio of M10 as shown in Fig. 1(c). The TC of _{}_{}_{} in all corners after trimming are shown in Fig. 6 (b). With the trimming circuit, the worst TC can be down to 17 ppm/℃. Table I summarizes the performance of the proposed voltage reference in comparison with other voltage references reported in [10–14]. The proposed voltage reference can achieve lower power than [11], [13] and [14]. The TC is better than [10] and [1214], and the PSRR is better than [1012] and [14]. Therefore, the features of lowpower, high precision, and simple structure make it suitable for lowpower IoT systems.
IV．
CONCLUSION
This paper presents an allMOSFET lowpower voltage reference implemented on 0.18μm CMOS technology, which has no requirement of resistors, BJTs, or special MOSFETs. A TC compensation method based on controlling bulk voltage is adopted to achieve optimized TC performance. At the same time, most of the transistors operate in the subthreshold region, which allows low power consumption. The trimming block of current mirrors and output stage can either optimize the performance of current source or improve TC in other process corners.
REFERENCES
[1] 
R. J. Widlar, “New developments in IC voltage regulators,” IEEE 
[2] 
International SolidState Circuits Conference, pp. 158159, 1970. A. P. Brokaw, “A simple threeterminal IC bandgap reference,” IEEE 
[3] 
Journal of SolidState Circuits, vol. SC9, pp. 388393, 1974. B. S. Song and P. R. Gray, “A precision curvaturecompensated CMOS bandgap reference,” IEEE International SolidState Circuits Conference. Digest of Technical Papers, pp. 240241, 1983. 
9781538648810/18/$31.00 ©2018 IEEE
TABLE I
This Work 
[10] 
[11] 
[12] 
[13] 
[14] 

Process 
0.18μm 
0.18μm 
0.35μm 
0.18μm 
0.18μm 
90nm 
Year 
2017 
2013 
2013 
2017 
2017 
2015 
Supply 

voltage(V) 
1.3 
0.7 
0.75 
0.8 
1.1 
1.15 
Supply current 

(nA) 
70 
None 
2500 
None 
500 
500 
Power (nW) 
91 
52 
2000 
79 
550 
580 
V _{R}_{E}_{F} (mV) 
576 
548 
259 
328 
893 
720 
Temperature 

(℃) 
40  125 
40  120 
45  145 
10  100 
30  80 
0  100 
TC (ppm/℃) 
13.1 
114 
2 
33.8 
19 
43.5 
LS (%/V) 
0.02 
None 
None 
0.21 
0.09 
0.3 
PSRR (dB) 

@100Hz 
74 
56 
None 
55 
75 
51 
Resistors 
None 
None 
Yes 
None 
None 
Yes 
Measure or 

Simulation 
Simulation 
Measure 
Simulation 
Measure 
Measure 
Measure 
[4] 
Y. Jiang and E. K. F. Lee, “Design of lowvoltage bandgap reference 
[5] 
using transimpedance amplifier,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 6, pp. 552 555, Jun 2000. S. S. Chouhan and K. Halonen, “Design and implementation of a micro 
[6] 
power CMOS voltage reference circuit based on thermal compensation of Vgs,” Microelectronics Journal, vol. 46, pp. 3642, 2015. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 15 ppm/℃, 
[7] 
20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs,” IEEE Journal of SolidState Circuits, vol. 44, pp. 2047 2054, 2009. H. J. Oguey and D. Aebischer, “CMOS current reference without 
[8] 
resistance,” IEEE Journal of SolidState Circuits, vol. 32, no. 7, pp. 11321135, Jul 1997. Y. Wang, Z. Zhu, J. Yao, and Y. Yang, “A 0.45V, 14.6nW CMOS 
[9] 
Subthreshold Voltage Reference With No Resistors and No BJTs,” IEEE Transactions on Circuits and Systems II Express Brifes, vol. 62, pp. 621625, 2015. A. L. Aita and C. R. Rodrigues, “PTAT CMOS current sources mismatch 
over temperature,” 26th Symposium on Integrated Circuits and Systems Design, Curitiba, 2013, pp. 14. [10] Y. Osaki, T. Hirose, N. Kuroki and M. Numa, “1.2V Supply, 100nW, 1.09V Bandgap and 0.7V Supply, 52.5nW, 0.55V Subbandgap Reference Circuits for Nanowatt CMOS LSIs,” IEEE Journal of Solid State Circuits, vol. 48, no. 6, pp. 15301538, June 2013. [11] C. M. Andreou and J. Georgiou, “An allsubthreshold, 0.75V supply, 2 ppm/℃, CMOS voltage reference,” IEEE International Symposium on Circuits and Systems, May 2013, pp. 1476–1479. [12] J. Duan, Z. Zhu, J. Deng, W. Xu and B. Wei, “A Novel 0.8 V 79 nW CMOSonly Voltage Reference With –55 dB PSRR @ 100 Hz,” in IEEE Transactions on Circuits and Systems II: Express Briefs, accepted for publication. [13] N. Alhassan, Z. Zhou and E. SánchezSinencio, “An AllMOSFET Voltage Reference With −50dB PSR at 80 MHz for LowPower SoC Design,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 8, pp. 892896, Aug. 2017. [14] K. Lee, T. S. Lande and P. Häfliger, “A SubμW Bandgap Reference Circuit With an Inherent CurvatureCompensation Property,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 62, no. 1, pp. 19, Jan.2015.
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