Sei sulla pagina 1di 109

11/3/2015

ECED3204: Microprocessor
Part V--Communication and Interface

Jason J. Gu
Department of Electrical and Computer Engineering
Dalhousie University

Electrical and Computer Engineering


Dalhousie University 1

Outline

i. Part V.1 Universal Synchronous


Asynchronous Receiver Transmitter (USART)
ii. Part V.2 The SPI Function
iii. Part V.3 Two-Wire Interface (TWI)
iv. Part V.4 Analog-to-Digital Converter

Electrical and Computer Engineering


Dalhousie University 2

1
11/3/2015

Part V.1 Universal Synchronous Asynchronous


Receiver Transmitter (USART)

Electrical and Computer Engineering


Dalhousie University 3

Outline

i. Fundamental Concepts of Serial


Communication
ii. The TIA-232 Standard
iii. The AVR USART
iv. USART Baud Rate Generation
v. The USART Operation
vi. Data Exchange with USART via the TIA-232
Interface
vii. Terminal and Terminal Emulation

Electrical and Computer Engineering


Dalhousie University 4

2
11/3/2015

Fundamental Concepts of Serial


Communication

 USART interface
 Primarily designed to transfer data in an asynchronous
mode that utilizes the industrial standard TIA-232
protocol, established in 1960 (originally called RS-232,
established 1960)
 Uses two (asynchronous mode) or three (synchronous
mode) wires

Electrical and Computer Engineering


Dalhousie University 5

The TIA-232 Standard

 First version of the standard: RS-232


(RS stands for recommended standard)
 Established in 1960 by Electronic Industry Association
(EIA) for interfacing between a computer and a
modem
 Current standard: TIA-232-F (TIA is the acronym
for Telecommunication Industry Association)
 Issued July 1997

Electrical and Computer Engineering


Dalhousie University 6

3
11/3/2015

The TIA-232 Standard (cont’d.)

 Data communication terms


 Data terminal equipment (DTE): computers and
terminals
 Data circuit–terminating equipment (DCE): modems,
bridges, routers, etc.

Electrical and Computer Engineering


Dalhousie University 7

The TIA-232 Standard (cont’d.)

 There are four aspects to the TIA-232 standard


 Electrical specification
 voltage level, rise and fall time, distance of communication
 Functional specification
 function of each signal
 Mechanical Specification
 number of pins, shapes and dimensions of the connectors
 Procedure specification
 sequence of events for data transmission and reception

Electrical and Computer Engineering


Dalhousie University 8

4
11/3/2015

The TIA-232 Standard (cont’d.)


 TIA-232 electrical specification
 Data rates: standard is applicable to data rates of
up to 20,000 bits per second
 Signal state voltage assignments
 Logic 1: voltages of -3 V to -25 V
 Logic 0: voltages of +3 V to +25 V
 No signal state: -3 V to +3 V
 Signal transfer distance: within 15 m

Electrical and Computer Engineering


Dalhousie University 9

The TIA-232 Standard (cont’d.)


 TIA-232 functional specification
 Categories
1. Signal ground and shield
2. Primary communications channel
3. Secondary communications channel
4. Modem status and control signals
5. Transmitter and receiver timing signals
6. Channel test signals

Electrical and Computer Engineering


Dalhousie University 10

5
11/3/2015

The TIA-232 Standard (cont’d.)

Electrical and Computer Engineering


Dalhousie University 11

The TIA-232 Standard (cont’d.)


 TIA-232 mechanical specification
 25-pin D-type connector recommended
 9-pin connector (DB9) is used in most computers

Electrical and Computer Engineering


Dalhousie University 12

6
11/3/2015

The TIA-232 Standard (cont’d.)


 TIA-232 procedural specification
 Example: Two DTEs are connected with a point-to-
point link using a modem
 Circuits required for modem operation: signal ground
(AB), transmitted data (BA), received data (BB), request to
send (CA), clear to sent (CB), data set ready (CC), and
carrier detect (CF)

Electrical and Computer Engineering


Dalhousie University 13

The TIA-232 Standard (cont’d.)


 Example1: Two DTEs are connected with a point-
to-point link using a modem
 DSR asserted, RTS asserted, CD asserted,

Electrical and Computer Engineering


Dalhousie University 14

7
11/3/2015

The TIA-232 Standard (cont’d.)


 Example2: Two DTEs are connected through a
public telephone line
 phase1 for connection, phase2 for transmission, 3 for
disconnect.

Electrical and Computer Engineering


Dalhousie University 15

The TIA-232 Standard (cont’d.)

 TIA-232 procedural specification (cont’d.)


 Example: Data transmission phases: establishing the
connection, data transmission, and disconnection
 Data format

Figure 13.4 The format of a character

Electrical and Computer Engineering


Dalhousie University 16

8
11/3/2015

The TIA-232 Standard (cont’d.)

 Detection of start bit

Electrical and Computer Engineering


Dalhousie University 17

The TIA-232 Standard (cont’d.)

 Data transmission errors


 Framing error: received character is improperly framed
by the start and stop bits
 Receiver overrun: All of the receive buffer register(s)
and receive shift registers filled with data but not read
by the CPU
 Parity error: an odd number of bits change value

Electrical and Computer Engineering


Dalhousie University 18

9
11/3/2015

The TIA-232 Standard (cont’d.)


 Null modem connection
 TIA-232 standard does not allow the direct connection
of two DTEs
 Null modem interconnects leads in such a way as to fool both
DTEs into thinking that they are connected to modems

Electrical and Computer Engineering


Dalhousie University 19

The AVR USART


 Number of USART modules allowed
 Mega device: up to four
 XMega device: up to eight
 USART signal pin assignment
 Asynchronous mode
 Transmit data (TXD) and receive data (RXD): 2 pins
 Synchronous or SPI mode
 Third pin needed for clock signal (XCK)

Electrical and Computer Engineering


Dalhousie University 20

10
11/3/2015

The AVR USART

 MEGA 644A
 RXD0/PD0,TXD0/PD1

Electrical and Computer Engineering


Dalhousie University 21

The AVR USART (cont’d.)

 Features of the USART module


 Full duplex operation (reception and transmission
can be proceeded simultaneously)
 Asynchronous or synchronous operation
 Master or slave clocked synchronous operation
 Supports serial frames with 5, 6, 7, 8, or 9 data bits
and 1 or 2 stop bits
 Odd and even parity generation and parity check
supported by hardware

Electrical and Computer Engineering


Dalhousie University 22

11
11/3/2015

The AVR USART (cont’d.)

 Features of the USART module (cont’d.)


 Data overrun and framing error detection
 Noise filtering, including false start bit detection and
digital low pass filter
 Three separate interrupts on TX complete, TX data
register empty, and RX complete
 Multiprocessor communication mode

Electrical and Computer Engineering


Dalhousie University 23

The AVR USART (cont’d.)

USART module consists of


a clock generator, a
transmitter, a receiver, and
three control registers

Electrical and Computer Engineering


Dalhousie University 24

12
11/3/2015

USART Baud Rate Generation


 Clock signals needed to control data
transmission and reception
 Clock operation modes supported: normal
asynchronous, double speed asynchronous, master
synchronous, and slave synchronous mode

Electrical and Computer Engineering


Dalhousie University 25

USART Baud Rate Generation (cont’d.)

 The Mega USART baud rate generator

Figure 13.8 Baud rate generator of Mega device’s USART module

Electrical and Computer Engineering


Dalhousie University 26

13
11/3/2015

The USART Operation

 Controlled by registers
 UCSRnA, UCSRnB, and UCSRnC: Mega device
 CTRLA, CTRLB, and CTRLC: Xmega device (skip)

Electrical and Computer Engineering


Dalhousie University 27

The USART Operation

Electrical and Computer Engineering


Dalhousie University 28

14
11/3/2015

The USART Operation

Electrical and Computer Engineering


Dalhousie University 29

The USART Operation

Electrical and Computer Engineering


Dalhousie University 30

15
11/3/2015

The USART Operation

 USART initialization
 Load appropriate values into the baud rate registers
and three control registers
 Set the directions of USART-related pins

Electrical and Computer Engineering


Dalhousie University 31

The USART Operation


 USART initialization example
 Write a subroutine and a C function to configure the USART3 on Port J of the MEGA640 to operate
with the following setting assuming that fPER = 32 MHz:
 one start bit, eight data bits, one stop bit, no parity 38,400 baud rate, Enable transmission and
reception; Disable multiprocessor mode; Normal asynchronous mode operation; Disable interrupts
 Solution:
 void initUSARTJ3 (void)
 {
 DDRJ = 0x02; // configure RDX3, TDX3 as input and output
 UBRR3L = 51; // set up baud rate to 38400
 UBRR3H = 0; // 32*106/52/16
 UCSR3A = 0; // disable parity using 16 as divider of transmitter clock
 UCSR3B = (1<<RXEN3)|(1<<TXEN3) // enable both transmission and reception
 UCSR3C = (1<<UCSZ31) | (1<<UCSZ30); // select asynchronous USART mode, disable
parity, 1 stop bit

Electrical and Computer Engineering


Dalhousie University 32

16
11/3/2015

The USART Operation (cont’d.)

 USART data transmission


 USART transmitter: must be enabled before it can
transmit data
 Enabled by setting the transmit enable (TXEN) bit in the
UCSRnB (Mega device) or CTRLB (XMega device) register
 load data to UDRn
 transmit complete flag TXCn
 data register empty flag UDREn is set
 If 9th bit is used, the 9th bit must be written to the TXB8 bit

Electrical and Computer Engineering


Dalhousie University 33

The USART Operation (cont’d.)


 Write a subroutine to output a 9 bit character passes in r17: r16 to
module, ASM
Putch9bit: lds r20, UCSR1A ; wait for buffer to be empty
sbrs r20, UDRE1
rjmp putch9bit
lds r20, UCSR1B ; clear TXB8 in UCSR1B
cbr r20, 1<<TXB81
sts UCSR1B, r20
sbrc r17, 0 ; skip if TXB8 is 0
rjmp setbit
rjmp done
setbit lds r20, UCSR1B
sbr r20,1<<TXB81
sts UCSR1B,r20
done sts UDR1,r16
ret

Electrical and Computer Engineering


Dalhousie University 34

17
11/3/2015

The USART Operation (cont’d.)


 Write a subroutine to output a 9 bit character passes in r17: r16 to
module C

Void putch9bit(Char c1, char c2)


{
while(!(UCSR1A & (1<<UDRE1)));
UCSR1B &= ~(1<<TXB81);
if(c1 & 0x01)
UCSR1B |= (1<<TXB81);
UDR1 =c2;
}

Electrical and Computer Engineering


Dalhousie University 35

The USART Operation (cont’d.)

 USART data reception


 USART receiver: must be enabled before it can
receive data; takes control of the RxDn pin of the
appropriate I/O PORT
 receive complete flag (RXC) is set
 reading UDRn
 Three error flags in UCSRnA

Electrical and Computer Engineering


Dalhousie University 36

18
11/3/2015

The USART Operation (cont’d.)

 read character from USART2 using polling


method
getch2: lds r20, UCSR2A ; wait for data
sbrs r20, RXC2
rjmp getch2
lds r22, UDR2 ; character copied to r22
ret

char getch2 (void)


{
while(!(UCSR2A & (1<<RXC2)));
return UDR2;
}

Electrical and Computer Engineering


Dalhousie University 37

The USART Operation (cont’d.)


 read 9-bit character from USART3 using polling method
Getch9bit: lds r20, UCSR3A ; wait for buffer to be empty
sbrs r20, RXC3
rjmp Getch9bit
lds r23, UCSR3B ; get 9th bit
lds r22, UDR3
lsr r23
andi r23, 0x01 ;keep RxB8 bit, results in r23:r22
ret
unsigned int getch9 (void)
{
unsigned char hiByte, loByte
while(!(UCSR3A & (1<<RXC3)));
hiByte=UCSR3B;
loByte=UDR3;
hiByte =(hiByte>>1) & 0x01;
return ((( unsigned int) hiByte <<8) +(unsigned)loByte);
}

Electrical and Computer Engineering


38
Dalhousie University

19
11/3/2015

The USART Operation (cont’d.)

 Write an interrupt-driven version of the getsUSART0 function in


assembly and C language.

Electrical and Computer Engineering


Dalhousie University 39

Data Exchange with USART via the TIA-


232 Interface

 TIA-232 (or RS-232) interface: one method of


exchanging data between two MCUs or between
an MCU and the PC
 Requires TIA-232 (or RS-232) transceiver to translate
the voltage levels of the USART signals (RXD and
TXD) to and from those of the corresponding TIA-232
signals

Electrical and Computer Engineering


Dalhousie University 40

20
11/3/2015

Data Exchange with USART via the TIA-


232 Interface

Electrical and Computer Engineering


Dalhousie University 41

Terminal and Terminal Emulation

 Terminal: CRT display and a keyboard


 Dumb terminal: lacks computation or editing
capabilities
 Before early 1990s: terminals connected to the host
computer via the TIA-232 interface
 Microprocessor development software: installed on the host
computer
 User entered and assembled/compiled his/her program using
the host computer; downloaded on demo board for execution

Electrical and Computer Engineering


Dalhousie University 42

21
11/3/2015

Terminal and Terminal Emulation


(cont’d.)

 PC platform: allows microprocessor software


development
 Roles served by PC
 Host computer: user enters and assembles/compiles the
program; user corrects syntax and semantics errors
 Terminal (terminal emulator program): user downloads the
assembled/compiled program onto the demo board; user
enters debug commands to communicate with monitor
program on demo board

Electrical and Computer Engineering


Dalhousie University 43

Terminal and Terminal Emulation


(cont’d.)

 PC first used as microprocessor application


development platform: connected to the demo
board via the TIA-232 interface
 Mid-1990s: background debug module added to
microcontroller hardware

Electrical and Computer Engineering


Dalhousie University 44

22
11/3/2015

Part V.2 The SPI Function

Electrical and Computer Engineering


Dalhousie University 45

Outline

i. Introduction to the SPI Function


ii. SPI Signal Pins
iii. SPI-Related Registers
iv. The SPI Operation
v. SPI-Compatible Chips
vi. The TC72 Digital Temperature Sensor
vii. The 12-Bit D/A Converter
viii. Using the USART in the SPI Mode
ix. Interfacing the MC14489 to the USART

Electrical and Computer Engineering


Dalhousie University 46
46

23
11/3/2015

Introduction to the SPI Function


 The serial peripheral interface (SPI): initially
proposed by freescale to simplify interfacing of
peripheral devices (ICs) to the microcontroller
 Low software overhead
 Simple hardware connection
 Good performance
 Used mainly in interfacing with peripheral devices
 operate as a master or as slave in both the three wire
or four wire models and support multiple masters and
slaves

Electrical and Computer Engineering


Dalhousie University 47

SPI Signal Pins

 SPI module communication signals


1. Serial clock (SCK): output from the master device
and input to the slave device
2. Master in, slave out (MISO): output from the slave
device and input to the master device
3. Master out, slave in (MOSI): output from the master
device and input to slave devices
4. Slave select (SS): can be configured as a slave or
as a master.

Electrical and Computer Engineering


Dalhousie University 48

24
11/3/2015

SPI-Related Registers

 SPI registers of Mega devices


 SPI control register (SPCR): see Figure 14.1
 SPI status register (SPSR): see Figure 14.2
 SPI data register (SPDR): frequency settings listed in
Table 14.1

Electrical and Computer Engineering


Dalhousie University 49

SPI-Related Registers

Electrical and Computer Engineering


Dalhousie University 50

25
11/3/2015

SPI-Related Registers

Electrical and Computer Engineering


Dalhousie University 51

SPI-Related Registers

Electrical and Computer Engineering


Dalhousie University 52

26
11/3/2015

The SPI Operation


 To send data to an SPI slave
 SPI write the byte to SPDR, this takes 8 clock pulses
 To received a byte from the SPI slave, the SPI master
also write a byte into the SPDR. The content doesn’t
matter, the write action trigger 8 clock pulses to shift
in a byte from slave
 To send a byte to an SPI master
 SPI write a byte to SPDR and wait for master to
generate SCK to shift out data.
 To receive a byte from the SPI master, the SPI slave
can check SPIF until it is set.
Electrical and Computer Engineering
Dalhousie University 53

The SPI Operation


 Data modes

Notes: 1. Mega device uses CPOL and CPHA bits to select SPI transfer mode
whereas the XMega device uses MODE[1:0] bits to set SPI transfer
mode.
2. Group configuration applies to XMega device only.

Table 14.3 SPI transfer modes

Electrical and Computer Engineering


Dalhousie University 54

27
11/3/2015

The SPI Operation (cont’d.)


 SPI circuit connection: Example illustrating only one
SPI master connecting to an SPI slave

Figure 14.6 Master/slave transfer block diagram

Electrical and Computer Engineering


Dalhousie University 55

The SPI Operation (cont’d.)


 SPI circuit connection: Single Master Multiple slave

Electrical and Computer Engineering


Dalhousie University 56

28
11/3/2015

The SPI Operation (cont’d.)


 SPI circuit connection: Single Master Multiple slave

Electrical and Computer Engineering


Dalhousie University 57

The SPI Operation (cont’d.)

 Configuring the SPI for data transfer


 Proper SPI module configuration required for data
transfer; SPI signal pins must be set correctly
 example:
 configure the Mega SPI module to operate with the following
setting
 Master mode with all interrupt disabled
 SCK signal idle high and sample data on the falling edge
 Data shift most significant bit first
 baud rate set to 2MHz assuming Fsys=16MHz

Electrical and Computer Engineering


Dalhousie University 58

29
11/3/2015

The SPI Operation (cont’d.)


ldi r20, 1<<SPE | 1<< MSTR | 1<< CPOL | 1<< SPR0
; master mode, SCK idle low, shift data on falling edge
out SPCR,r20 ; disable SPI interrupts, shift data msb first, baud rate = 2 MHz
ldi r20, 1<<SP12X
out SPSR,r20 ; 
in r20,SPDR ; clear all SPI flags
ldi r20, 1<<PB0 | 1<<PB1 | 1<<PB2 ;  SS/PB0, SCK/PB1,MOSI/PB2, MISO/PB3
out DDRB,r20 ; pin direction

Void initSPI (void)
{
char tmp;
SPCR =1<<SPE | 1<< MSTR | 1<< CPOL | 1<< SPR0;
SPSR =1<<SP12X;
tmp =SPDR;
DDRB =1<<PB0 | 1<<PB1 | 1<<PB2;
}

Electrical and Computer Engineering


59
Dalhousie University

The SPI Operation (cont’d.)

 Writing common SPI data transfer functions


1. putcSPI: sends out a character through the SPI module
2. getcSPI: reads a character from the SPI module
3. multiple byte transfer can be achieved by calling one of
these two functions repeatedly.

Electrical and Computer Engineering


Dalhousie University 60

30
11/3/2015

The SPI Operation (cont’d.)

; SPI master calls this subroutine to send a byte to the SPI slave
putcSPI_master:
out SPDR,r16
waitTX: in r20,SPSR
sbrs r20,SPIF ;wait until SPIF is set
rjmp wairTX
in r20,SPDR ;clear the SPIF by reading SPDR
ret

Electrical and Computer Engineering


Dalhousie University 61

The SPI Operation (cont’d.)

; SPI master calls this subroutine to get a byte from the SPI slave
getcSPI_master:
out SPDR,r16
waitRX: in r20,SPSR
sbrs r20,SPIF ;wait until SPIF is set
rjmp waitRX
in r22,SPDR ;fetch data and clear the SPIF 
ret

Electrical and Computer Engineering


Dalhousie University 62

31
11/3/2015

The SPI Operation (cont’d.)

; SPI slave calls this subroutine to send a byte to the SPI master
putcSPI_slave:
out SPDR,r16
waitTX: in r20,SPSR
sbrs r20,SPIF ;wait until SPIF is set
rjmp wairTX
in r22,SPDR ;clear the SPIF by reading SPDR
ret

Electrical and Computer Engineering


Dalhousie University 63

The SPI Operation (cont’d.)

; SPI slave calls this subroutine to receive a byte from the SPI master
getcSPI_slave:
waitRX: in r20,SPSR
sbrs r20,SPIF ;wait until SPIF is set
rjmp wairRX
in r22,SPDR ;clear the SPIF by reading SPDR
ret

Electrical and Computer Engineering


Dalhousie University 64

32
11/3/2015

The SPI Operation (cont’d.)


; C language SPI master calls this subroutine to send a byte from the master
void putcSPI_master(unsigned char cx)
{
char tmp;
SPDR = cx;
while(!(SPSR & (1<<SPIF))); //wait for data to be shifted out
tmp = SPDR; //clear SPIF flag
}
; C language SPI master calls this subroutine to get byte from the slave
void getcSPI_master(void)
{
SPDR = 0; //trigger clocks from SCK pin
while(!(SPSR & (1<<SPIF))); //wait for data to be shifted in
return SPDR; //clear SPIF flag
}

Electrical and Computer Engineering


Dalhousie University 65

The SPI Operation (cont’d.)


; C language SPI slave calls this subroutine to send a byte to the master
void putcSPI_slave (unsigned char cx)
{
char tmp;
SPDR = cx;
while(!(SPSR & (1<<SPIF))); //wait for data to be shifted out
tmp = SPDR; //clear SPIF flag
}
; C language SPI slave calls this subroutine to get byte from the master
void getcSPI_slave (void)
{
while(!(SPSR & (1<<SPIF))); //wait for data to be shifted in
return SPDR; //clear SPIF flag
}

Electrical and Computer Engineering


Dalhousie University 66

33
11/3/2015

SPI-Compatible Chips

 SPI protocol used to interface peripheral devices


with a microcontroller
 Introduced by Freescale
 Peripheral device that supports the SPI protocol
 Can be used with any microcontroller that implements
the SPI subsystem

Electrical and Computer Engineering


Dalhousie University 67

The 74HC595 Shift Register


 Main application: convert data from parallel to
serial and vice versa

Figure 14.9 The 74HC595 block diagram and pin assignment

Electrical and Computer Engineering


Dalhousie University 68

34
11/3/2015

The 74HC595 Shift Register


 74HC595 Pin assignment
 DS: Serial Data Input
 SC: Shift Clock
 RESET’: Active low reset (low on pin clear register)
 LC: latch clock
 OE’: Output Enable (active low)
 QA-QH: output
 SQH

Electrical and Computer Engineering


Dalhousie University 69

The 74HC595 Shift Register


 Use two 74HC595s to interface with Mega to drive eight common-
cathode, 7-segment display

Electrical and Computer Engineering


Dalhousie University 70

35
11/3/2015

The 74HC595 Shift Register


 C code to display 12345678 on display #7 to #0
#include <avr\io.h> while(1)
#include “delays_Mega.h” for (ix=0;ix<8;ix++){
#include “spiUtil_mMega.h” putchSPI_master(dispTab[ix][0];
Define SS PB0 putchSPI_master(dispTab[ix][1];
void initSPI(void) PORTB &= ~(1<<SS);// LC rising edge
void putcSPI_master(unsigned char cx); PORTB |= (1<<SS);   // LC rising edge
void delayby1ms(unsigned char cx); delayby1ms(1);
void main(void) }
{ }
unsigned char  }
dispTab[8][2]={{0x7F,0x30},{0xBF,0x6D},  void initSPI(void)
{0xDF,0x79},  {
{0xEF,0x33},{0xF7,0x58},{0xFB,0x5F},{0xFD,0x70},  char tmp;
{0xFE,0x7F}}; SPCR = 1<<SPE | 1<< MSTR ;
unsigned char ix; tmp = SPSR;
initSPI(); tmp = SPDR;
DDRB = 1<<PB0 | 1<<PB1 | 1<<PB2; SPSR = 0;
}

Electrical and Computer Engineering


Dalhousie University 71

The TC72 Digital Temperature Sensor


 Operation of the TC72
 Operation modes: continuous temperature conversion mode
(every 150ms) or the one-shot conversion mode

Electrical and Computer Engineering


Dalhousie University 72

36
11/3/2015

The TC72 Digital Temperature Sensor


 The temperature data format: represented by a 10-bit two’s complement
word with a resolution of 0.25°C per least significant bit

Electrical and Computer Engineering


Dalhousie University 73

The TC72 Digital Temperature Sensor


(cont’d.)

 The serial bus interface: consists of chip enable


(CE), serial clock (SCK), serial data input (SDI),
and serial data output (SDO)
 TC72 can be operated as a SPI slave only
 Internal register structure
 Four internal registers: control register, LSB
temperature, MSB temperature, and manufacturer ID

Electrical and Computer Engineering


Dalhousie University 74

37
11/3/2015

The TC72 Digital Temperature Sensor


(cont’d.)

 Procedure for reading


 1) pull the CE high to enable SPI transfer
 2) send the temperature result high byte address 0x02
to TC72, wait until SPI transfer complete
 3) read the temperature high byte, write a dummy byte
to SSPBUF to trigger eight pulses
 4) read the temperature low byte, write a dummy byte
to SSPBUF to trigger eight pulses
 5) pull the CE pin to low

Electrical and Computer Engineering


Dalhousie University 75

The TC72 Digital Temperature Sensor


(cont’d.)

Electrical and Computer Engineering


Dalhousie University 76

38
11/3/2015

The TC72 Digital Temperature Sensor


(cont’d.)

 Example:
 Set up the circuit connection between AVR Mega and
TC72 for digital temperature reading, write a c function
to read the temperature every 100 ms.
 f_PER is assumed as 16 MHz.

Electrical and Computer Engineering


Dalhousie University 77

The TC72 Digital Temperature Sensor


(cont’d.)

MEGA644 PIN
assignment

PB4:SS
PB5:MOSI
PB6:MISO
PB7:SCK

Electrical and Computer Engineering


Dalhousie University 78

39
11/3/2015

The TC72 Digital Temperature Sensor


(cont’d.)

 Example: c code here: eg14_07.pdf

Electrical and Computer Engineering


Dalhousie University 79

The 12-Bit D/A Converter MCP4922

 MCP4922: 12-bit voltage output digital-to-analog


converter (DAC) with a flexible
four-wire serial interface
 Signal pins: refer to Figure 14.14

Electrical and Computer Engineering


Dalhousie University 80

40
11/3/2015

The 12-Bit D/A Converter MCP4922

Electrical and Computer Engineering


Dalhousie University 81

The 12-Bit D/A Converter MCP4922


 AVss: Analog ground
 VDD: Power Supply
 VREFA,VREFB: reference voltage for A,B
 CS’: Chip Set, active low
 SDI: Serial data input
 LDAC’: Latch input, active low
 SHDN’: Shutdown
 VOUTA, VOUTB: output A and output B
 SCK: Clock
Electrical and Computer Engineering
Dalhousie University 82

41
11/3/2015

The 12-Bit D/A Converter MCP4922


 Data format: microprocessor or microcontroller
sends in a 16-bit frame (4 bits of command and
12 bits of data) to the MCP4922 to start a D/A
conversion

Electrical and Computer Engineering


Dalhousie University 83

The 12-Bit D/A Converter MCP4922


(cont’d.)

Electrical and Computer Engineering


Dalhousie University 84

42
11/3/2015

The 12-Bit D/A Converter MCP4922


(cont’d.)
 Interfacing the MCP4922 with the AVR

Figure 14.16 Circuit connection between the AVR and MCP4922

Electrical and Computer Engineering


Dalhousie University 85

The 12-Bit D/A Converter MCP4922(cont’d.)

 Example: For figure 14.16, write a


program to generate a sawtooth
waveform from V_OUTA. Divide a
period of the waveform into 60 equal
sections. F_clk=16MHz

Electrical and Computer Engineering


Dalhousie University 86

43
11/3/2015

Using the USART in the SPI Mode

 Comparison of USART in the MSPI mode and


regular SPI module
 setting UCSRnC (UMSELn[1:0]=11)
 USART in the MSPI mode: includes (double) buffering
of the transmitter; the SPI has no buffer
 USART receiver in the MSPI mode: includes an
additional buffer level
 SPI WCOL (Write Collision) bit: not included in the
USART in the MSPI mode
Electrical and Computer Engineering
Dalhousie University 87

Using the USART in the SPI Mode(cont’d.)

 Comparison of USART in the MSPI mode and


regular SPI module (cont’d.)
 SPI double speed mode (SPI2X) bit: not included;
same effect achieved by setting the UBRRn field
properly
 Interrupt timing is not compatible
 Pin control differs due to the master only operation of
the USART in MSPI mode
(refer to Table 14.7)

Electrical and Computer Engineering


Dalhousie University 88

44
11/3/2015

Using the USART in the SPI Mode(cont’d.)

Electrical and Computer Engineering


Dalhousie University 89

Using the USART in the SPI Mode (cont’d.)

 Clock generation in the MSPI mode


 Generated internally
 XCKn pin must be configured for output
 BAUD = f_OSC/(2*(UBRRn+1))
 UBRRn = f_OSC/(2*BAUD)-1
 USART registers of Mega devices in MSPI
mode: refer to Figure 14.18 and Figure 14.19

Electrical and Computer Engineering


Dalhousie University 90

45
11/3/2015

Using the USART in the SPI Mode (cont’d.)

Electrical and Computer Engineering


Dalhousie University 91

Using the USART in the SPI Mode (cont’d.)

Electrical and Computer Engineering


Dalhousie University 92

46
11/3/2015

Using the USART in the SPI Mode(cont’d.)

Electrical and Computer Engineering


Dalhousie University 93

Using the USART in the SPI Mode(cont’d.)

 USART module operation in MSPI mode


 Configuration includes: setting the baud rate, the
master mode of operation, and the frame format, and
enabling the transmitter and receiver

Electrical and Computer Engineering


Dalhousie University 94

47
11/3/2015

Using the USART in the SPI Mode(cont’d.)

 example to initialize the USART module 0 of the


Mega device
 Enable the transmitter and receiver
 XCK idle low, shift data on the rising edge
 Baud rate specified by the caller using r17:r16

Electrical and Computer Engineering


Dalhousie University 95

Using the USART in the SPI Mode(cont’d.)


 example eg14_09.asm

 Void initMegaMSPI( unsigned in baud)


 {

 UBRR0 =0;
 DDRE =0x06;
 UCSR0B =1<<RXEN0|1<<TXEN0;
 UCSR0C =1<<UMSEL01 |UMSEL00 |
0<<UCPHA0 | 0<<UCPOL0;
 UBRR0 =baud;
 }

Electrical and Computer Engineering


Dalhousie University 96

48
11/3/2015

Using the USART in the SPI Mode(cont’d.)


 example to write a subroutine to transmit a character
and a subroutine to receive a character via USART in
the MSPI mode. The character to be sent is in r16 and
received character is in r22. Asm code
Unsigned char putch (unsigned char cx) Unsigned char getch (unsigned char cx)
{ {
//wait until the UDR is empty //wait until the UDR is empty
while(!(UCSROA & (1<<UDER0))); while(!(UCSROA & (1<<UDER0)));
// sends the ch // trigger clock signals from XCK0 pin
UDR0=cx; UDR0=0;
//wait until the ch is shifted out //wait until the ch is shifted in
while(!(UCSROA & (1<<RXC0))); while(!(UCSROA & (1<<RXC0)));
//clear the RXC0 return UDR0;
return UDR0;

Electrical and Computer Engineering


Dalhousie University 97

Interfacing the MC14489 to the USART

 MC14489 from Freescale is a 7segment display


drive chip
 5-digit display plus decimals
 4 1/2 –digit display plus decimals and sign
 25 lamps

Electrical and Computer Engineering


Dalhousie University 98

49
11/3/2015

Interfacing the MC14489 to the USART

Electrical and Computer Engineering


Dalhousie University 99

Interfacing the MC14489 to the USART


 Operation of MC14489

Electrical and Computer Engineering


Dalhousie University 100

50
11/3/2015

Interfacing the MC14489 to the USART

 Operation of
MC14489

Electrical and Computer Engineering


Dalhousie University 101

Interfacing the MC14489 to the USART


 Design example eg14_11c, display 997.04

Electrical and Computer Engineering


Dalhousie University 102

51
11/3/2015

Interfacing the MC14489 to the USART


 Design example
 For the circuit, write a program to display the following

patterns repeatedly with each row lasting for 200ms


 12345

 23456

 34567

 45678

 56789

 67890

 78901

 89012

 90123

 01234

Electrical and Computer Engineering


Dalhousie University 103

Interfacing the MC14489 to the USART


 Cascading Design example

Electrical and Computer Engineering


Dalhousie University 104

52
11/3/2015

Interfacing the MC14489 to the USART


 Cascading Design example

Example: 0x01,0x00,0x00,0x01,0x00,0x00,0x45

Electrical and Computer Engineering


Dalhousie University 105

Interfacing the MC14489 to the USART


 Cascading Design example

 Display: 26.7oC 1200 08 0212

Electrical and Computer Engineering


Dalhousie University 106

53
11/3/2015

Interfacing the MC14489 to the USART

 Operation of
MC14489

Electrical and Computer Engineering


Dalhousie University 107

Interfacing the MC14489 to the USART


 Cascading Design example

 Asm code  C code

Electrical and Computer Engineering


Dalhousie University 108

54
11/3/2015

Part V.3 Two-Wire Interface (TWI)

Electrical and Computer Engineering


Dalhousie University 109

Outline

i. Introduction to the Two-Wire Interface


ii. The TWI of the Mega MCU
iii. Mega TWI Programming using the Polling
Approach
iv. Interfacing with Serial EEPROM AT24C08B
v. Interrupt-Driven Mega TWI Programming
vi. Using the Digital Thermostat DS1631A
vii. Using the Real-Time Clock DS1337

Electrical and Computer Engineering


Dalhousie University 110
110

55
11/3/2015

Outline

Semiconductors developed a simple bidirectional two-


wire bus, called I2C-Introduction to the Two-Wire
Interface
Only two bus line are required: serial data line (SDA) and
serial clock line (SCL).
Standard mode: 100kbit/s
fast mode: 400kbit/s
fast + mode 1M bit/s
high speed mode 3.4 Mbit/s
A device connected to the bus can be a master or a
slave
TWI doesn’t support high speed mode of I2C

Electrical and Computer Engineering


Dalhousie University 111
111

Introduction to the Two-Wire Interface


(TWI)

Figure 15.1 A typical Two-Wire Interface circuit connection

Electrical and Computer Engineering


Dalhousie University 112

56
11/3/2015

Introduction to the TWI (cont’d.)


 TWI addressing
 Master initiates a data transfer by addressing

a slave on the bus and indicating whether it


wants to transmit or receive data. TWI support
7 bit and 10 bit addressing.
 TWI supports the general call. The general call

address is seven 0’s and is used to address all


slaves on the bus.

Electrical and Computer Engineering


Dalhousie University 113

Introduction to the TWI (cont’d.)


 The TWI signal components
 Start (S): indicates that a device would like to transfer
data on the TWI bus
 Stop (P): indicates that a device wants to release the
TWI bus
 Repeated start (R)
 Data
 Acknowledge (ACK and NACK)

Electrical and Computer Engineering


Dalhousie University 114

57
11/3/2015

Introduction to the TWI (cont’d.)


 Start (S): indicates that a device would like to transfer
data on the TWI bus A
 A start condition is represented by the SDA line going
low when the SCL signal is high

Electrical and Computer Engineering


Dalhousie University 115

Introduction to the TWI (cont’d.)


 Stop (P): indicates that a device wants to release the
TWI bus
 SDA signal going high when the SCL is high

Electrical and Computer Engineering


Dalhousie University 116

58
11/3/2015

Introduction to the TWI (cont’d.)


 Repeated start (R)
 There is no stop condition between start and restart

Electrical and Computer Engineering


Dalhousie University 117

Introduction to the TWI (cont’d.)


 Data
 Data on the SDA line are valid only when the SCL is
high. 8 bit data may be a control code data

Electrical and Computer Engineering


Dalhousie University 118

59
11/3/2015

Introduction to the TWI (cont’d.)


 Acknowledge (ACK and NACK)
 A device can acknowledge the transfer of each byte bring the SDA line
low during the ninth clock pulse of the SCL. (ACK). If the device does not
pull the SDA line low and instead allows the SDA line to float high, it is
transmitting a negative acknowledge (NACK)

Electrical and Computer Engineering


Dalhousie University 119

Introduction to the TWI (cont’d.)


 Bus arbitration in TWI
 If two or more master devices attempt a simultaneous
transfer, one or more masters forced to give up the
bus. One device always wins, and no data are lost.

Electrical and Computer Engineering


Dalhousie University 120

60
11/3/2015

Introduction to the TWI (cont’d.)


 Clock and clock stretching
 Slow down the overall clock frequency or insert wait
states while processing data
 Clock stretching types: wake-up clock stretching,
periodic clock stretching, and random clock stretching

Electrical and Computer Engineering


Dalhousie University 121

Introduction to the TWI (cont’d.)


 Clock synchronization
 Two masters can begin transmitting on an idle bus at the same time, and
there must be a method for deciding which will take control. This is done by
clock synchronization and arbitration.

Figure 15.9 TWI clock synchronization

Electrical and Computer Engineering


Dalhousie University 122

61
11/3/2015

Introduction to the TWI (cont’d.)

 Handshaking
 Clock synchronization: can be used as a handshaking
in data transfer
 Data transfer format
 Related to the slave addressing method
 Seven-bit addressing: directly implemented in AVR’s
hardware
 10-bit addressing: requires the software intervention in
addition to hardware support

Electrical and Computer Engineering


Dalhousie University 123

Introduction to the TWI (cont’d.)

Electrical and Computer Engineering


Dalhousie University 124

62
11/3/2015

Introduction to the TWI (cont’d.)


 Master transmitter to slave receiver

Electrical and Computer Engineering


Dalhousie University 125

Introduction to the TWI (cont’d.)


 Master reads slave immediately after the
address byte

Electrical and Computer Engineering


Dalhousie University 126

63
11/3/2015

Introduction to the TWI (cont’d.)


 Combined format
 The master reads data from slave 1 and reads from slave 2
 The master write data to slave 1 and write to slave 2
 The master reads data from slave and write to same slave
 The master write data to slave and reads from same slave
 The master reads data from slave 1 and write to slave 2
 The master write to slave 1 and reads from slave 2

Electrical and Computer Engineering


Dalhousie University 127

The TWI of the Mega MCU


 Implemented with SCL and SDA pins sharing the use of the PD0
and PD1 pin, respectively

Electrical and Computer Engineering


Dalhousie University 128

64
11/3/2015

The TWI of the Mega MCU

 Characteristics
 Master and slave operations supported
 Implements slew-rate limited output drivers
 Provides noise suppression circuitry
 Address recognition feature

Electrical and Computer Engineering


Dalhousie University 129

The TWI of the Mega MCU (cont’d.)


 The SCL and SDA pins: interface the AVR TWI
module with the bus lines
 The bit-rate generator unit: controls the period of
the SCL signal when the TWI is operating in the
master mode. SCL is controlled by TWI bit-rate
register (TWBR) and the prescaler bits in the
TWI status register (TWSR)

Electrical and Computer Engineering


Dalhousie University 130

65
11/3/2015

The TWI of the Mega MCU (cont’d.)

 The bus interface unit: generates the


START/RESTART and STOP conditions,
suppressing the signal spikes, detecting whether
bus arbitration is won or lost, and receiving and
transmitting slave address and data bytes (using
the TWDR register)

Electrical and Computer Engineering


Dalhousie University 131

The TWI of the Mega MCU (cont’d.)


 The address match unit: checks if the received address byte
matches the 7-bit address in the TWI address register (TWAR)

Electrical and Computer Engineering


Dalhousie University 132

66
11/3/2015

The TWI of the Mega MCU (cont’d.)


 To allow the TWI module in slave mode to match with multiple
addresses.

Electrical and Computer Engineering


Dalhousie University 133

The TWI of the Mega MCU (cont’d.)


 The control unit: monitors the TWI bus and generates responses
corresponding to settings in the TWI control register (TWCR)
 TWINT flag is set in following situations:
 The TWI has transmitted a START/RESTARTED condition
 The TWI has transmitted the control byte
 The TWI has lost arbitration
 The TWI has transmitted a data byte
 The TWI has been addressed by its own address or general call address
 The TWI has received a data byte
 A STOP or RESTART has been received while still addressed as a slave
 A bus error has occurred due to an illegal START or STOP condition

Electrical and Computer Engineering


Dalhousie University 134

67
11/3/2015

The TWI of the Mega MCU (cont’d.)

Electrical and Computer Engineering


Dalhousie University 135

The TWI of the Mega MCU (cont’d.)


 TWSR register (typo on text)

Electrical and Computer Engineering


Dalhousie University 136

68
11/3/2015

The TWI of the Mega MCU (cont’d.)


 Example: write a function to configure the TW module to operate with
following parameters, assuming that the Mega device is running with
a 16-MHz crystal oscillator:
 100KHZ shift rate
 Enable TWI
 Enable TWI interrupt
 C language
 void initTWI (void)
 {
 TWBR = 72;
 TWSR &=0xFC;
 TWCR = 0x05;
 DDRD = 0;
 }

Electrical and Computer Engineering


Dalhousie University 137

Using the Mega TWI Module

 Embedded product with multiple MCUs operating


in the multi-master mode: allows same peripheral
chip (with TWI interface) to be shared by multiple
MCUs
 Note: MCU may also be configured to operate in the
slave mode
 Data transfer programs: may apply polling
approach or interrupt-driven method

Electrical and Computer Engineering


Dalhousie University 138

69
11/3/2015

Mega TWI Programming using the


Polling Approach

 Assembly and C subroutines


 Generating the START condition
 Generating the STOP condition
 Writing data to the TWI bus
 Read data byte from the TWI bus

Electrical and Computer Engineering


Dalhousie University 139

Mega TWI Programming using the


Polling Approach
 Generating the START condition

Electrical and Computer Engineering


Dalhousie University 140

70
11/3/2015

Mega TWI Programming using the


Polling Approach
 Generating the STOP condition

Electrical and Computer Engineering


Dalhousie University 141

Mega TWI Programming using the


Polling Approach
 Writing data to the TWI bus

Electrical and Computer Engineering


Dalhousie University 142

71
11/3/2015

Mega TWI Programming using the


Polling Approach
 Read data byte from the TWI bus

Electrical and Computer Engineering


Dalhousie University 143

Mega TWI Programming using the


Polling Approach
 Read data byte from the TWI bus

Electrical and Computer Engineering


Dalhousie University 144

72
11/3/2015

Interfacing with Serial EEPROM AT24C08B


 Pin assignment and block diagram of AT24C08B
2
 SCL and SDA pins: used for I C or TWI bus communications

 WP pin: used as the write-protection input

 A2, A1, and A0 pins: A2 is used for hardwire addressing; A1 and A0


are not used

Electrical and Computer Engineering


Dalhousie University 145

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

 Device addressing of AT24C08B, P1,P0 are


page number.

Figure 15.20 AT24C08B device address

Electrical and Computer Engineering


Dalhousie University 146

73
11/3/2015

Interfacing with Serial EEPROM


AT24C08B (cont’d.)
 The AT24C08B write operation
 supports byte-write and page-write operations
 The master (MCU) asserts the START condition
 The master sends the control byte to the AT24C08B
 The AT24C08B acknowledges the control byte transmission
 The master sends the byte address to the AT24C08B
 The AT24C08B acknowledges address byte
transmissionC08B
 The AT24C08B acknowledges the data byte transmission
 The master asserts the STOP condition
 page-write operations can write up to 16 bytes with one
address

Electrical and Computer Engineering


Dalhousie University 147

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

 The AT24C08B acknowledge polling


 Master sends a START condition followed by the
control byte for a write command (R/W = 0); if the
AT24C08B is still busy, then no ACK will be returned; if
the cycle is complete, the device will return the ACK,
and the master can proceed with the next read or write
command

Electrical and Computer Engineering


Dalhousie University 148

74
11/3/2015

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

 The AT24C08B read operation: three types


supported
 Current address read: read the byte immediately
following the location accessed by the previous read
or write operation
 Random read: access any memory location in a
random manner
 Sequential read: AT24C08B transmits the next
sequentially addressed byte

Electrical and Computer Engineering


Dalhousie University 149

Interfacing with Serial EEPROM


AT24C08B (cont’d.)
 example:
 Write a page-write subroutine in assembly and C language for the
circuit. Slave ID, Page number and R/W bit are in r16, the starting
address in r17, pointer to the data in r30-31

Electrical and Computer Engineering


Dalhousie University 150

75
11/3/2015

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

; ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
; This subroutine writes a block of bytes into the AT24C08B. The control byte with block 
; number, starting address to write, the number of bytes to write, and the pointer to the data
; block in data memory to write are passed in r16, r17, r18, and Z.
; ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
writeBlockEE:
call startTWI ; generate a START condition
call sendByteTWI ; send out control byte to EEPROM
mov r16,r17 ; send out address of the starting location to 
call sendByteTWI ; written
wloop: ld r16,Z+ ; fetch a byte to be written 
rcall sendByteTWI ; send to EEPROM
dec r18 ; decrement byte count
brne wloop
rcall stopTWI ; generate a STOP condition
call writePoll ; wait for internal write to complete
ret

Electrical and Computer Engineering


Dalhousie University 151

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
// This function performs write poll to make sure that EEPROM internal write operation is 
complete.
// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
WritePoll: call  startTWI ;generate start condition
call sendByteTWI ; send out control byte+page number + R/W bit
lds r21,TWSR ;check status register
andi r21,0xF8 ;mask out low three bit
cpi r21,0x18 ; has AVR received ACK? See table 15.1
breq wc
jmp Writepoll ;EEPROM returned NACK, continue to poll
Wc: ret

Electrical and Computer Engineering


Dalhousie University 152

76
11/3/2015

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
// This function writes a block of data into the EEPROM. The control byte, the starting
// address in EEPROM, number of bytes to write, and the pointer to the data memory
// that holds the data to be written are passed to this function.
// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
void writeByteEE(unsigned char SLA, unsigned char addr, unsigned char bytes, char *ptr)
{
startTWI();// generate START condition
sendByteTWI(SLA); // send out SLA + page number + /W
sendByteTWI(addr); // send out memory address to be written
while (bytes){
sendByteTWI(*ptr++); // send out data byte and move pointer
bytes‐‐;
}
stopTWI(); // generate STOP condition
writePoll(SLA); // wait until internal write operation is completed
}

Electrical and Computer Engineering


Dalhousie University 153

Interfacing with Serial EEPROM


AT24C08B (cont’d.)

// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
// This function uses ACK polling to make sure that EEPROM internal write operation is complete.
// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
void writePoll (unsigned  char SLA)
{
char busy = 1;
while(busy){ // wait while EEPROM returns ACK
startTWI();
sendByteTWI(SLA);
if ((TWSR & 0xF8) == 0x18)
busy = 0; 
}
}

Electrical and Computer Engineering


Dalhousie University 154

77
11/3/2015

Interrupt-Driven Mega TWI Programming

 TWI hardware provides timing and shifting


control for the serial transfers; byte-wise control
is user defined
 After TWI hardware finishes certain operation:
enters a new state (indicated in the upper 5 bits
of the TWSR register
 Sets TWINT flag in the TWCR register
 Interrupt generated if enabled

Electrical and Computer Engineering


Dalhousie University 155

Interrupt-Driven Mega TWI Programming

Electrical and Computer Engineering


Dalhousie University 156

78
11/3/2015

Interrupt-Driven Mega TWI Programming

Electrical and Computer Engineering


Dalhousie University 157

Interrupt-Driven Mega TWI Programming

Electrical and Computer Engineering


Dalhousie University 158

79
11/3/2015

Interrupt-Driven Mega TWI Programming

Electrical and Computer Engineering


Dalhousie University 159

Interrupt-Driven Mega TWI Programming

Electrical and Computer Engineering


Dalhousie University 160

80
11/3/2015

Interrupt-Driven Mega TWI Programming

Electrical and Computer Engineering


Dalhousie University 161

Using the Digital Thermostat DS1631A

 The DS1631A pin assignment


 The ambient temperature
exceeds the trip point
(stored in the TH register),
Tout will be asserted

Figure 15.23 Pin assignment of DS1631A

Electrical and Computer Engineering


Dalhousie University
162

81
11/3/2015

Using the Digital Thermostat DS1631A


(cont’d.)

 DS1631A functional description: refer to Figure


15.24
 convert temperature -55 to 125 degree into 9-12bit
 accuracy +-0.5 from 0 to 70 degree
 DS1631A registers: Config, TH, TL, and
Temperature
 The DS1631A operation
 Begins conversions automatically at power-up
 Continuous or single conversion modes supported
Electrical and Computer Engineering
Dalhousie University 163

Using the Digital Thermostat DS1631A


(cont’d.)

Electrical and Computer Engineering


Dalhousie University 164

82
11/3/2015

Using the Digital Thermostat DS1631A


(cont’d.)

Electrical and Computer Engineering


Dalhousie University 165

Using the Digital Thermostat DS1631A


(cont’d.)

Electrical and Computer Engineering


Dalhousie University 166

83
11/3/2015

Using the Digital Thermostat DS1631A


(cont’d.)

 Operation
 Positive conversion
 Truncate the lowest 4 bits.
 divide the upper 12 bit by 16
 Negative conversion
 compute the two’s complement of the conversion results
 Truncate the lowest 4 bits
 divide the upper 12 bit by 16

Electrical and Computer Engineering


Dalhousie University 167

Using the Digital Thermostat DS1631A


(cont’d.)

• DS1631A command set


 Start Convert T [0x51]  Access TL [0xA2]
 Stop Convert T [0x22]  Access Config [0xAC]
 Read Temperature [0xAA]  Software POR [0x54]
 Access TH [0xA1]

Electrical and Computer Engineering


Dalhousie University 168

84
11/3/2015

Using the Digital Thermostat DS1631A


(cont’d.)
 Interfacing the DS1631A with the AVR Mega MCU

Figure 15.26 Typical circuit connection between the Mega2560 and DS1631A

Electrical and Computer Engineering


Dalhousie University 169

Using the Digital Thermostat DS1631A


(cont’d.)

Electrical and Computer Engineering


Dalhousie University 170

85
11/3/2015

Using the Digital Thermostat DS1631A


(cont’d.)

 Write Data to DS1631A


 The master can write data to the DS1631A by issuing
an Access Config, Access TH, or Access TL command
following the control Byte
 Read Data from DS1631A
 The master can read data from the DS1631A by
issuing an Access Config, Access TH, or Access TL or
read Temperature command following the control Byte

Electrical and Computer Engineering


Dalhousie University 171

Using the Digital Thermostat DS1631A


(cont’d.)

Example: Use the interrupt‐driven approach 
and write a C function to set up the TH or the 
TL value, the prototype of this C function is 
void setupTHoTL(char val_hi, char val_lo char 
choice), where val_hi and val_lo are the high 
byte and low byte to be written into the 
DS1631A and choice specifies whether TH 
(choice == 1) or TL (choice == 0) should be set 
up. The circuit connection of the DS1631A is 
shown in Figure 15.26.
Electrical and Computer Engineering
Dalhousie University 172

86
11/3/2015

Using the Digital Thermostat DS1631A


(cont’d.)
// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
// This function sends a 16‐bit value to the TH or TL register.
// ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
void setupTHoTL(char val_hi, char val_lo, char choice)
{
while(TWIbusy); // wait until TWI bus is idle
TWIbusy = 1;  // occupies the TWI bus
RW = 0;  // perform write operation
WrAdr = DS1631A; // set up control byte
if(choice)
command = AccessTH;
else
command = AccessTL;
txbuf[0] = val_hi; // configuration value to be sent to DS1631A
txbuf[1]  = val_lo;
byte2Send  = 3; // number of bytes to be transferred
byte2Read  = 0; // number of bytes to be read
TWCR = 0xA5; // generate a START condition and enable TWI interrupts
}

Electrical and Computer Engineering


Dalhousie University 173

Using the Digital Thermostat DS1631A


(cont’d.)

 Complete Asm code

 Complete C code

Electrical and Computer Engineering


Dalhousie University 174

87
11/3/2015

Part V.4 Analog-to-Digital Converter

Electrical and Computer Engineering


Dalhousie University 175

Outline

i. Basics of A/D Conversion


ii. The Mega ADC Module
iii. Interfacing with Analog Temperature Sensor
TC1047A
iv. Measuring Barometric Pressure
v. Measuring Relative Humidity

Electrical and Computer Engineering


Dalhousie University 176
176

88
11/3/2015

Basics of A/D Conversion

 A data acquisition system


 Transducer: device that converts nonelectric quantity
to a voltage
 Amplifier (voltage scaler): used to amplify transducer
output voltage
 Signal-conditioning circuit: performs scaling and
shifting

Electrical and Computer Engineering


Dalhousie University 177

Basics of A/D Conversion

Electrical and Computer Engineering


Dalhousie University 178

89
11/3/2015

Basics of A/D Conversion (cont’d.)

Electrical and Computer Engineering


Dalhousie University 179

Basics of A/D Conversion (cont’d.)

 Analog voltage and digital code characteristic


 n-bit A/D converter has 2n possible output code values
 More bits used in representing the A/D conversion result, the
smaller the conversion error
 A/D conversion algorithms: categories
1. Parallel (flash) ADC: used in applications that require
high speed but low resolution

Electrical and Computer Engineering


Dalhousie University 180

90
11/3/2015

Basics of A/D Conversion (cont’d.)

 A/D conversion algorithms: categories (cont’d.)


2. Slope and double-slope ADC: high resolution (10-bit
to 16-bit) can be achieved
3. Sigma-Delta ADC: uses the oversampling technique
to perform A/D conversion
4. Successive-approximation ADC: may be used for
low-frequency applications with large DC noise

Electrical and Computer Engineering


Dalhousie University 181

Basics of A/D Conversion (cont’d.)

Electrical and Computer Engineering


Dalhousie University 182

91
11/3/2015

Basics of A/D Conversion (cont’d.)

Electrical and Computer Engineering


Dalhousie University 183

Basics of A/D Conversion (cont’d.)

 Optimal voltage range for A/D conversion


 An ADC needs a low reference voltage (VRL) and a
high reference voltage (VRH) to perform the conversion

Electrical and Computer Engineering


Dalhousie University 184

92
11/3/2015

Basics of A/D Conversion (cont’d.)


Example: Suppose that there is a 10‐bit A/D converter with
VRL and VRH set to 0 V and 5 V, respectively. Find the
corresponding voltage values for the A/D conversion results
of 40, 150, 250, 500, 768, and 100, respectively.
Solution: 
V(40)  = 0.2 V
V(150) = 0.73 V
V(250) = 1.22 V
V(500) = 2.44 V
V(768) = 3.75 V
V(100) = 0.49 V
Electrical and Computer Engineering
Dalhousie University 185

Basics of A/D Conversion (cont’d.)

 Scaling circuit: can be used to improve the


accuracy because it allows the ADC to utilize its
full dynamic range

Electrical and Computer Engineering


Dalhousie University 186

93
11/3/2015

Basics of A/D Conversion (cont’d.)


 Voltage translation circuit: improves accuracy of
A/D conversion shifting and scaling the
transducer output so that it falls in the full range
of 0 V~VDD

Electrical and Computer Engineering


Dalhousie University 187

Basics of A/D Conversion (cont’d.)


 Conversion ranges
 Single-ended mode: used to measure input voltages
on a single input channel
 Differential mode: used to measure the difference
between two channels

Electrical and Computer Engineering


Dalhousie University 188

94
11/3/2015

The Mega ADC Module


 Signal pins of Mega ADC
 A Mega device has a 10-bit ADC that uses the
successive approximation method to perform
conversion
 Single-ended mode: 8-channel external ADC analog
input pins are multiplexed with PORTF pins; 16-
channel ADC analog inputs are multiplexed with
PORTF and PORTK pins
 Differential mode: 16/32 differential voltage input
pairs derived from the combinations of PORTF and
PORTK inputs

Electrical and Computer Engineering


Dalhousie University 189

The Mega ADC Module


 The Mega device can only select one of the
analog channel to perform A/D conversion at a
time.
 Channel reference voltage selection are
controlled by ADC multiplexer selection register
(ADMUX) and bit 5 of ADC control and status
register B (ADCSRB)

Electrical and Computer Engineering


Dalhousie University 190

95
11/3/2015

The Mega ADC Module

Electrical and Computer Engineering


Dalhousie University 191

The Mega ADC Module

Electrical and Computer Engineering


Dalhousie University 192

96
11/3/2015

The Mega ADC Module

 Mega AVR ADC input channel selection

Electrical and Computer Engineering


Dalhousie University 193

The Mega ADC Module

Electrical and Computer Engineering


Dalhousie University 194

97
11/3/2015

The Mega ADC Module

Electrical and Computer Engineering


Dalhousie University 195

The Mega ADC Module (cont’d.)

 Prescaling and conversion timing of Mega ADC


 An acceptable ADC clock: generated by dividing the
CPU clock with a prescaler
 CPU frequency must be above 100 kHz
 If a resolution lower than 10 bit is selected, the input
clock frequency to the ADC can be as high as 1MHz

Electrical and Computer Engineering


Dalhousie University 196

98
11/3/2015

The Mega ADC Module (cont’d.)

Electrical and Computer Engineering


Dalhousie University 197

The Mega ADC Module (cont’d.)

Electrical and Computer Engineering


Dalhousie University 198

99
11/3/2015

The Mega ADC Module (cont’d.)

 Differential channels of Mega ADC


 Differential conversions: synchronized to the internal
clock CKADC2 half of the ADC clock.
 Conversion takes 14 clock cycle

Electrical and Computer Engineering


Dalhousie University 199

The Mega ADC Module (cont’d.)

 Changing channel or reference selection for


Mega ADC
 Changing ADC input channels
 Single conversion mode: always select the channel before
starting the conversion
 Free running mode: always select the channel before starting
the first conversion
 Changing ADC reference voltage
 User can select the AVCC, internal 1.1 V reference, internal
2.56 V reference, or the external AREF pin voltage as the
VREF for A/D conversion

Electrical and Computer Engineering


Dalhousie University 200

100
11/3/2015

The Mega ADC Module (cont’d.)


 Mega ADC noise canceller: enables conversion
during sleep mode, to reduce noise that is
induced from the CPU core and other I/O
peripherals
 Analog input circuitry
 Analog noise canceling techniques
 Disable digital input

Electrical and Computer Engineering


Dalhousie University 201

The Mega ADC Module (cont’d.)

Electrical and Computer Engineering


Dalhousie University 202

101
11/3/2015

The Mega ADC Module (cont’d.)


 Mega ADC conversion result: stored in the ADC
result registers (ADCH:ADCL)

 For single ended ADC=Vin*1024/Vref

 For differential ADC=(VPOS-VNEG)*512/Vref

Electrical and Computer Engineering


Dalhousie University 203

The Mega ADC Module (cont’d.)


 Example:
 Write a sequence of AVR instructions and C statements to
configure the AVR MEGA2560 to operate with the following
settings:
 Select single-ended mode

 Select ADC1 as input

 Enable auto trigger mode and use Timer/Counter 1 overflow

as the trigger source


 Set the ADC clock prescaler to 128

 Select AREF pin as reference voltage

 ADC result left-justified

 Disable digital input buffers of the unused analog inputs

 Disable ADC interrupt

Electrical and Computer Engineering


Dalhousie University 204

102
11/3/2015

The Mega ADC Module (cont’d.)

Solution: The assembly subroutine that performs the specified setting is as follows:
initADC:  ldi r20,0x21 ; select ADC1 as input, result left‐justified
sts ADMUX,r20 ;  "
lds r20,DDRF ; configure ADC1/PF1 pin for input
andi r20,0xFD ;  “
sts DDRF,r20 ;  “
ldi r20,0x06 ; use Timer1 overflow as trigger source 
sts ADCSRB,r20 ;  "
ldi r20,0xA7 ; enable ADC, enable auto triggering, set ADC clock
sts ADCSRA,r20; prescaler to 128
ret

Electrical and Computer Engineering


Dalhousie University 205

The Mega ADC Module (cont’d.)

The C language version of the function is as follows:
void initADC(void)
{
ADMUX = 0x21;  // select ADC as input, result left‐justified
DDRF &= 0xFD; // configure PF1/ADC1 pin for input
ADCSRB = 0x06;  // select Timer1 overflow as trigger source
ADCSRA = 0xA7; // enable ADC, auto‐triggering, set prescaler to 128

Electrical and Computer Engineering


Dalhousie University 206

103
11/3/2015

Interfacing with Analog Temperature


Sensor TC1047A

 TC1047A: three-pin temperature sensor whose


voltage output is proportional directly to the
measured temperature
 Voltage range: 0.1 to 1.75 V for temperature from -
40oC to 125oC
 using xMega MCU (skipped)

Electrical and Computer Engineering


Dalhousie University 207

Interfacing with Analog Temperature


Sensor TC1047A

Electrical and Computer Engineering


Dalhousie University 208

104
11/3/2015

Measuring Barometric Pressure

 Forms of pressure transducers


 Gauge (psig): measures pressure against ambient air
 Differential (psid): measures against a reference
pressure
 Absolute (psia): measures the pressure against a
vacuum (0 psia), i.e., measures barometric pressure

Electrical and Computer Engineering


Dalhousie University 209

Measuring Barometric Pressure

Electrical and Computer Engineering


Dalhousie University 210

105
11/3/2015

Measuring Barometric Pressure

Electrical and Computer Engineering


Dalhousie University 211

Measuring Barometric Pressure

Barometric pressure = (ADC result/75.2)+94.8kPa

Electrical and Computer Engineering


Dalhousie University 212

106
11/3/2015

Measuring Barometric Pressure

 Example

Electrical and Computer Engineering


Dalhousie University 213

Measuring Relative Humidity

 IH-3610: humidity sensor made by Honeywell


 Linear output from 0.8 to 3.9 V in the full range of 0-
100% relative humidity (RH) when powered by a 5 V
supply in the temperature range from -40oC to 85oC
 Refer to Table 16.13 Specifications of the
IH-3610

Electrical and Computer Engineering


Dalhousie University 214

107
11/3/2015

Measuring Relative Humidity

Relative Humidity= (ADC result-164)*100/634

Electrical and Computer Engineering


Dalhousie University 215

Measuring Relative Humidity

Electrical and Computer Engineering


Dalhousie University 216

108
11/3/2015

Measuring Relative Humidity

 Example

Electrical and Computer Engineering


Dalhousie University 217

109

Potrebbero piacerti anche