DDR3 SI Analisys Report

By: Alexander Karas Date : 27 December 2012
Ref : Signal Integrity DDR3.doc
Subject: Signal Integrity DDR3 Classification: Edality / internal
Index
1 Signal Integrity DDR3 ................................................................................................... 2

1.1 Introduction .................................................................................................................... 2
1.2 Project activities and deliverables ................................................................................... 2
1.3 Analysis software information ....................................................................................... 2
2 DDR3 PCB Layout ......................................................................................................... 3

2.1 Introduction .................................................................................................................... 3
2.2 Board stackup info ......................................................................................................... 4
2.3 Critical Net List .............................................................................................................. 5
3 Routing DDR3 board 22-12-2012 .................................................................................. 6

3.1 DDR3 clock ..................................................................................................................... 6
3.2 DDR3 address lines ........................................................................................................ 13
4 Routing DDR3 IF .......................................................................................................... 15

4.1 Address signals ............................................................................................................. 15
4.2 Bytelane 0 ...................................................................................................................... 18
4.3 Bytelane 1 ...................................................................................................................... 19
4.4 Bytelane 2 ...................................................................................................................... 20
4.5 Bytelane 3 ...................................................................................................................... 21
4.6 All address, clock and control ...................................................................................... 22
5 Timing analyses ............................................................................................................ 23

5.1 Address & clock ........................................................................................................... 23
5.2 Timing analyses result .................................................................................................. 26
6 Conclusion ..................................................................................................................... 27
7.1 Signal integrity .............................................................................................................. 27
7.2 Timing analyses ............................................................................................................. 27
Appendix A: Layer overview: .......................................................................................... 28
Appendix B: Selecting best models for simulation (due the driver impedance, signal
strength and ODT parameters) …………………………………………………………
1. Data lines, write cycle ……………………………………… .. ………………………
2. Data lines, write cycle …………………………………………… .. ………………
-1-
1 Signal Integrity DDR3

1.1 Introduction
A design review is done for the DDR3 design. This document describes the results of this
simulation.
1.2 Project activities and deliverables
For the SI analyses of the DDR3 design (IMX53_module_v6_fdb_221212_1800), the

following tasks and activities had to be done:
1. Creation/validation of missing IBIS models
2. Convert the DDR3 board databases to the analysis database
3. Collect board stack-up information
4. Post Layout SI Simulation DDR3 IF
5. Analysis document
1.3 Analysis software information
Simulator:
- Hyperlynx : 8.2.1
-2-
2 DDR3 PCB Layout
2.1 Introduction
-3-
2.2 Board stackup info
Received stackup for the iMX53 board:
-4-
Stackup from Mentor Graphics HyperLynx database:
Layer Stackup
Design: pcb.hyp, Designer: Sasha.
HyperLynx BoardSim v8.2.1
30 um, E r = 2.1
38 um
12 um, 1, Z0 = 50.6 ohms, w idth = 144 um
92 um, E r = 4
30 um, 2
105 um, Er = 3.8
16 um, 3, Z0 = 51.9 ohms, w idth = 115 um

100 um, Er = 3.8
16 um, 4, Z0 = 51.9 ohms, w idth = 115 um
105 um, Er = 3.8
16 um, 5
1220 um 100 um, Er = 3.8
16 um, 6
105 um, Er = 3.8
16 um, 7, Z0 = 51.9 ohms, w idth = 115 um
100 um, Er = 3.8
16 um, 8, Z0 = 51.9 ohms, w idth = 115 um
105 um, Er = 3.8

30 um, 9
92 um, E r = 4
12 um, 10, Z0 = 50.6 ohms, w idth = 144 um

38 um
30 um, E r = 2.1
2.3 Critical Net List
GROUP NAME SPEED RATE DESCRIPTION

DDR* DRAM_* 800 Mbps DDR3 interface without write
leveling
-5-
3 Routing DDR3 board 22-12-2012
3.1 DDR3 clock
DRAM_SDCLK_0 DRAM_SDCLK_1
Signal DRAM_SDCLK_0
Waveform, typical case, die, 48 Ohm driver Rload =40 OSCILLOSCOPE

Design file: PCB.HYP Designer: Sasha
HyperLynx v 8.2.1
DRAM_SDCLK_0.Probe V [U603.K7 (at die) / U603.J7 (at die)]

DRAM_SDCLK_0.Probe V [U603.K7 (at die)]
DRAM_SDCLK_0.Probe V [U603.J7 (at die)]
2000.0 DRAM_SDCLK_0.Probe V [U602.J7 (at die)]
1500.0
1000.0
500.0
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0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0 4500.0
Time (ps)
Date: Tuesday Jan. 22, 2013 Time: 18:43:34

Net name:
Show Latest Wav eform = YES, Show Prev ious Waveform = YES, Show Saved Waveform = YES
Termination resistor placed incorrectly. It should be placed as possible closer to receiver,

because all signal flowing down the trace is absorbed in the resistor at the end of trace and
there is no reflection. In this case ideal place for termination resistor is T-split, but it is
impossible because BGA chips placed from both sides of the board. So, best place is
between U1 and T-split, as possible closer to T-split.
-6-
Eye diagram, no jitter OSCILLOSCOPE

HyperLynx v 8.2.1
V [U603.K7 (at die) / U603.J7 (at die)]

2000.0
1500.0
1000.0
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-500.0 0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0
Time (ps)
Date: Thursday Jan. 10, 2013 Time: 15:43:45

Net name: DRAM_SDCLK_0
Eye diagram, 1% UI Gaussian jitter

OSCILLOSCOPE
HyperLynx v 8.2.1

2000.0
1500.0
1000.0
500.0
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-1000.0
-1500.0
-2000.0
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-500.0 0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0
Time (ps)

Net name: DRAM_SDCLK_0
-7-
Signal DRAM_SDCLK_1

HyperLynx v 8.2.1

V [U605.K7 (at die)]
V [U605.J7 (at die)]
2000.0 V [U604.J7 (at die)]
1500.0
1000.0
500.0
V
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-1500.0
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0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0 4500.0
Time (ps)
Date: Friday Jan. 11, 2013 Time: 18:25:04

Net name: DRAM_SDCLK_1_B
Show Latest Wav eform = YES
See comments for signal DRAM_SDCLK_0
Eye diagram, no jitter

OSCILLOSCOPE
HyperLynx v 8.2.1

2000.0
1500.0
1000.0
500.0
V
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-500.0
-1000.0
-1500.0
-2000.0
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-500.0 0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0
Time (ps)

-8-
Eye diagram, 1% UI Gaussian jitter

OSCILLOSCOPE
HyperLynx v 8.2.1

2000.0
1500.0
1000.0
500.0
V
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-500.0
-1000.0
-1500.0
-2000.0
-2500.0
-500.0 0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0
Time (ps)

Combine both Clock signals

HyperLynx v 8.2.1

V [U605.J7 (at die)]
2000.0 DRAM_SDCLK_0_for combine both clock together_31.Probe V [U603.K7 (at die) / U603.J7 (at die)]
DRAM_SDCLK_0_for combine both clock together_31.Probe V [U603.K7 (at die)]
DRAM_SDCLK_0_for combine both clock together_31.Probe V [U603.J7 (at die)]
DRAM_SDCLK_0_for combine both clock together_31.Probe V [U602.K7 (at die) / U602.J7 (at die)]
DRAM_SDCLK_0_for combine both clock together_31.Probe V [U602.K7 (at die)]
1500.0 DRAM_SDCLK_0_for combine both clock together_31.Probe V [U602.J7 (at die)]
1000.0
500.0
V
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g 0.00
e
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V-
-500.0
-1000.0
-1500.0
-2000.0
-2500.0
0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 3500.0 4000.0 4500.0
Time (ps)

Show Latest Waveform = YES, Show Saved Wav eform = YES
-9-
Zoom in to the rising edge OSCILLOSCOPE

HyperLynx v 8.2.1

500.0
400.0
300.0 DRAM_SDCLK_1.Probe V [U604.K7 (at die)]
200.0
100.0
V
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m
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-100.0
-200.0
-300.0
-400.0
860.00 870.00 880.00 890.00 900.00 910.00 920.00 930.00 940.00 950.00
Time (ps)
Date: Tuesday Jan. 22, 2013 Time: 18:51:28

Net name:
Cursor 1, Voltage = -1.4mV, Time = 896.06ps
Cursor 2, Voltage = 1.4mV, Time = 906.40ps
Delta Voltage = 2.8mV, Delta Time = 10.34ps
Show Latest Wav eform = YES, Show Prev ious Waveform = YES, Show Saved Waveform = YES
Delta skew is about 10ps, no problem.
Conclusion: fix termination resistors placement.
- 10 -
3.2 Address lines
Address signals routed on different layers. No problem.
Topology.
Net DRAM_A0
Note: impedances of latest stubs are incorrect. It should be 50.6 Ohms (trace 144um) instead
of 59.2 Ohms or 55.9 Ohms (100um and 115um corresponding).
- 11 -
Waveform, typical case, die

(DRIVER model is ddr3_sel00_ds101_mio – DDR, 1.5V, ddr3 mode, 48 Ohm driver impedance;
RECEIVER model is INPUT2_1600 – Add/Cmd/Ctrl Input Model, 1333/1600Mbps)
OSCILLOSCOPE
HyperLynx v 8.2.1
net-DRAM_A0_drv-U1.M19_rcv-U602.N3_W1.U602.N3
1600.0 net-DRAM_A0_drv-U1.M19_rcv-U605.N3_W1.U605.N3
1400.0
1200.0
1000.0
V
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t
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600.0
400.0
200.0
-0.00
-200.0
51.000 52.000 53.000 54.000 55.000 56.000 57.000 58.000 59.000

Time (ns)
Date: Wednesday Jan. 23, 2013 Time: 17:12:46

Show Sav ed Waveform = YES
All Address signals

Waveforms, typical case
- 12 -

OSCILLOSCOPE
HyperLynx v 8.2.1
net-DRAM_A1_drv-U1.L21_rcv-U602.P7_W1.U602.P7
1400.0 net-DRAM_A2_drv-U1.M20_rcv-U602.P3_W1.U602.P3
net-DRAM_A2_drv-U1.M20_rcv-U603.P3_W1.U603.P3
net-DRAM_A3_drv-U1.N20_rcv-U602.N2_W1.U602.N2
1200.0
net-DRAM_A4_drv-U1.K20_rcv-U602.P8_W1.U602.P8
1000.0 net-DRAM_A4_drv-U1.K20_rcv-U605.P8_W1.U605.P8
net-DRAM_A5_drv-U1.N21_rcv-U602.P2_W1.U602.P2
V net-DRAM_A5_drv-U1.N21_rcv-U605.P2_W1.U605.P2
o
l 800.0 net-DRAM_A6_drv-U1.M22_rcv-U602.R8_W1.U602.R8
t net-DRAM_A6_drv-U1.M22_rcv-U603.R8_W1.U603.R8
a
g net-DRAM_A6_drv-U1.M22_rcv-U604.R8_W1.U604.R8
e net-DRAM_A6_drv-U1.M22_rcv-U605.R8_W1.U605.R8
-
m net-DRAM_A7_drv-U1.N22_rcv-U602.R2_W1.U602.R2
V
- net-DRAM_A7_drv-U1.N22_rcv-U603.R2_W1.U603.R2
600.0
net-DRAM_A7_drv-U1.N22_rcv-U604.R2_W1.U604.R2
net-DRAM_A8_drv-U1.N23_rcv-U602.T8_W1.U602.T8
400.0 net-DRAM_A8_drv-U1.N23_rcv-U605.T8_W1.U605.T8
net-DRAM_A9_drv-U1.M21_rcv-U602.R3_W1.U602.R3
200.0 net-DRAM_A10_drv-U1.K19_rcv-U602.L7_W1.U602.L7
net-DRAM_A10_drv-U1.K19_rcv-U603.L7_W1.U603.L7
net-DRAM_A11_drv-U1.L22_rcv-U602.R7_W1.U602.R7
-0.00
net-DRAM_A12_drv-U1.L20_rcv-U602.N7_W1.U602.N7
-200.0 net-DRAM_A12_drv-U1.L20_rcv-U605.N7_W1.U605.N7
net-DRAM_A13_drv-U1.L23_rcv-U602.T3_W1.U602.T3
51.000 52.000 53.000 54.000 55.000 56.000 57.000 58.000 59.000 net-DRAM_A13_drv-U1.L23_rcv-U603.T3_W1.U603.T3
Time (ns) net-DRAM_A13_drv-U1.L23_rcv-U604.T3_W1.U604.T3
Zooming in to the rising edge OSCILLOSCOPE

HyperLynx v 8.2.1
1600.0
1400.0
1200.0
1000.0
V
o net-DRAM_A5_drv-U1.N21_rcv-U604.P2_W1.U604.P2
l 800.0
t
a net-DRAM_A6_drv-U1.M22_rcv-U602.R8_W1.U602.R8
g
e net-DRAM_A6_drv-U1.M22_rcv-U603.R8_W1.U603.R8
m- net-DRAM_A6_drv-U1.M22_rcv-U604.R8_W1.U604.R8
V net-DRAM_A6_drv-U1.M22_rcv-U605.R8_W1.U605.R8
- 600.0
400.0
200.0
-0.00
-200.0 net-DRAM_A11_drv-U1.L22_rcv-U605.R7_W1.U605.R7
50600.0 50800.0 51000.0 51200.0 51400.0 51600.0 51800.0 52000.0 52200.0 net-DRAM_A12_drv-U1.L20_rcv-U604.N7_W1.U604.N7
Time (ps) net-DRAM_A12_drv-U1.L20_rcv-U605.N7_W1.U605.N7
Cursor 1, Voltage = 902.6mV, Time = 51.2529ns
Delta Voltage = 0.000V, Delta Time = 156.1ps
Delta skew at VIH is about 150ps. It ’ s too much, should be max 50ps.
Conclusion:
1. Arrange address lines length to decrease skew
2. Arrange trace widths to improve signal quality.
- 13 -
4 Bytelanes
4.2 Byteline 0
All signals routed on same layer, some stubs on other. No problem.
Waveforms, Typical case, die

(DRIVER model is ddr3_sel00_ds101_mio – DDR, 1.5V, ddr3 mode, 48 Ohm driver impedance;
RECEIVER model is DQ_40_1600 – 40 Ohm Data I/O with no ODT, 1333/1600Mbps)
OSCILLOSCOPE
HyperLynx v 8.2.1
net-DRAM_D0_drv-U1.H20_rcv-U602.E3_W1.U602.E3
net-DRAM_D0_drv-U1.H20_rcv-U603.F7_W2.U603.F7
net-DRAM_D1_drv-U1.G21_rcv-U602.F7_W1.U602.F7
net-DRAM_D1_drv-U1.G21_rcv-U603.E3_W2.U603.E3
net-DRAM_D2_drv-U1.J21_rcv-U602.G2_W1.U602.G2
2000.0
net-DRAM_D2_drv-U1.J21_rcv-U603.H8_W2.U603.H8
net-DRAM_D4_drv-U1.J23_rcv-U602.F2_W1.U602.F2
net-DRAM_D4_drv-U1.J23_rcv-U603.F8_W2.U603.F8
1500.0
net-DRAM_D5_drv-U1.G23_rcv-U602.H8_W1.U602.H8
net-DRAM_D5_drv-U1.G23_rcv-U603.G2_W2.U603.G2
net-DRAM_D7_drv-U1.G22_rcv-U602.H7_W1.U602.H7
1000.0 net-DRAM_D7_drv-U1.G22_rcv-U603.H3_W2.U603.H3
net-DRAM_DQM0_drv-U1.H21_rcv-U602.E7_W1.U602.E7
net-DRAM_DQM0_drv-U1.H21_rcv-U603.E7_W2.U603.E7
net-DRAM_SDQS0_drv-U1.H23&H22_rcv-U602.F3&G3_W1.U602.F3&G3
net-DRAM_SDQS0_drv-U1.H23&H22_rcv-U603.F3&G3_W2.U603.F3&G3
500.0
V
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-500.0
-1000.0
-1500.0
-2000.0
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26000.0 26500.0 27000.0 27500.0 28000.0 28500.0 29000.0 29500.0 30000.0 30500.0
Time (ps)

Signal looks OK
- 14 -
4.3 Byteline 1
Waveforms, typical case, die OSCILLOSCOPE

HyperLynx v 8.2.1
net-DRAM_D8_drv-U1.E21_rcv-U602.A3_W1.U602.A3
net-DRAM_D8_drv-U1.E21_rcv-U603.A7_W2.U603.A7
net-DRAM_D9_drv-U1.D21_rcv-U602.C8_W1.U602.C8
net-DRAM_D9_drv-U1.D21_rcv-U603.C2_W2.U603.C2
net-DRAM_D10_drv-U1.E22_rcv-U602.C2_W1.U602.C2
2000.0 net-DRAM_D10_drv-U1.E22_rcv-U603.C8_W2.U603.C8
net-DRAM_D11_drv-U1.D20_rcv-U602.B8_W1.U602.B8
net-DRAM_D11_drv-U1.D20_rcv-U603.A2_W2.U603.A2
net-DRAM_D12_drv-U1.E23_rcv-U602.C3_W1.U602.C3
net-DRAM_D12_drv-U1.E23_rcv-U603.D7_W2.U603.D7
1500.0 net-DRAM_D13_drv-U1.C23_rcv-U602.D7_W1.U602.D7
net-DRAM_D13_drv-U1.C23_rcv-U603.C3_W2.U603.C3
net-DRAM_D14_drv-U1.F23_rcv-U602.A2_W1.U602.A2
net-DRAM_D14_drv-U1.F23_rcv-U603.B8_W2.U603.B8
net-DRAM_D15_drv-U1.C22_rcv-U602.A7_W1.U602.A7
net-DRAM_D15_drv-U1.C22_rcv-U603.A3_W2.U603.A3
1000.0
net-DRAM_DQM1_drv-U1.E20_rcv-U602.D3_W1.U602.D3
net-DRAM_DQM1_drv-U1.E20_rcv-U603.D3_W2.U603.D3
net-DRAM_SDQS1_drv-U1.D23&D22_rcv-U602.C7&B7_W1.U602.C7&B7
net-DRAM_SDQS1_drv-U1.D23&D22_rcv-U603.C7&B7_W2.U603.C7&B7
500.0
V
o
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a
g 0.00
e
-
m
V
-
-500.0
-1000.0
-1500.0
-2000.0
-2500.0
26000.0 26500.0 27000.0 27500.0 28000.0 28500.0 29000.0 29500.0 30000.0 30500.0
Time (ps)

Signal looks OK
- 15 -
4.4 Byteline 2

HyperLynx v 8.2.1
net-DRAM_D16_drv-U1.U20_rcv-U604.E3_W1.U604.E3
net-DRAM_D16_drv-U1.U20_rcv-U605.F7_W2.U605.F7
net-DRAM_D17_drv-U1.T21_rcv-U604.F7_W1.U604.F7
net-DRAM_D17_drv-U1.T21_rcv-U605.E3_W2.U605.E3
net-DRAM_D18_drv-U1.U21_rcv-U604.F2_W1.U604.F2
2000.0 net-DRAM_D18_drv-U1.U21_rcv-U605.F8_W2.U605.F8
net-DRAM_D19_drv-U1.R21_rcv-U604.F8_W1.U604.F8
net-DRAM_D19_drv-U1.R21_rcv-U605.F2_W2.U605.F2
net-DRAM_D20_drv-U1.U23_rcv-U604.H3_W1.U604.H3
1500.0 net-DRAM_D21_drv-U1.R22_rcv-U604.H8_W1.U604.H8
net-DRAM_D21_drv-U1.R22_rcv-U605.G2_W2.U605.G2
net-DRAM_D22_drv-U1.U22_rcv-U604.G2_W1.U604.G2
net-DRAM_D23_drv-U1.R23_rcv-U604.H7_W1.U604.H7
1000.0 net-DRAM_D23_drv-U1.R23_rcv-U605.H3_W2.U605.H3
net-DRAM_DQM2_drv-U1.T20_rcv-U604.E7_W1.U604.E7
net-DRAM_DQM2_drv-U1.T20_rcv-U605.E7_W2.U605.E7
net-DRAM_SDQS2_drv-U1.T22&T23_rcv-U604.F3&G3_W1.U604.F3&G3
net-DRAM_SDQS2_drv-U1.T22&T23_rcv-U605.F3&G3_W2.U605.F3&G3
500.0
V
o
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a
g 0.00
e
-
m
V
-
-500.0
-1000.0
-1500.0
-2000.0
-2500.0
26000.0 26500.0 27000.0 27500.0 28000.0 28500.0 29000.0 29500.0 30000.0 30500.0
Time (ps)

Signal looks OK.
- 16 -
4.5 Byteline 3

HyperLynx v 8.2.1
net-DRAM_D24_drv-U1.Y20_rcv-U604.A2_W1.U604.A2
net-DRAM_D24_drv-U1.Y20_rcv-U605.B8_W2.U605.B8
net-DRAM_D25_drv-U1.W21_rcv-U604.B8_W1.U604.B8
net-DRAM_D25_drv-U1.W21_rcv-U605.A2_W2.U605.A2
net-DRAM_D26_drv-U1.Y21_rcv-U604.A3_W1.U604.A3
2000.0 net-DRAM_D26_drv-U1.Y21_rcv-U605.A7_W2.U605.A7
net-DRAM_D28_drv-U1.AA23_rcv-U604.C3_W1.U604.C3
net-DRAM_D28_drv-U1.AA23_rcv-U605.D7_W2.U605.D7
1500.0 net-DRAM_D29_drv-U1.V23_rcv-U604.C8_W1.U604.C8
net-DRAM_D29_drv-U1.V23_rcv-U605.C2_W2.U605.C2
net-DRAM_D31_drv-U1.W23_rcv-U604.D7_W1.U604.D7
net-DRAM_D31_drv-U1.W23_rcv-U605.C3_W2.U605.C3
1000.0
net-DRAM_DQM3_drv-U1.W20_rcv-U604.D3_W1.U604.D3
net-DRAM_DQM3_drv-U1.W20_rcv-U605.D3_W2.U605.D3
net-DRAM_SDQS3_drv-U1.Y22&Y23_rcv-U604.C7&B7_W1.U604.C7&B7
net-DRAM_SDQS3_drv-U1.Y22&Y23_rcv-U605.C7&B7_W2.U605.C7&B7
500.0
V
o
l
t
a 0.00
g
e
-
m
V
-
-500.0
-1000.0
-1500.0
-2000.0
-2500.0
26000.0 26500.0 27000.0 27500.0 28000.0 28500.0 29000.0 29500.0 30000.0 30500.0
Time (ps)

Signal looks OK.
- 17 -
4.6 All Address, Clock and Control

HyperLynx v 8.2.1
2500.0 _net-DRAM_SDCLK_0_drv-U1.K23&K22_rcv-U602.J7&K7_W1.U602.J7&K7
_net-DRAM_SDCLK_0_drv-U1.K23&K22_rcv-U603.J7&K7_W1.U603.J7&K7
_net-DRAM_SDCLK_1_drv-U1.P22&P23_rcv-U604.J7&K7_W1.U604.J7&K7
_net-DRAM_SDCLK_1_drv-U1.P22&P23_rcv-U605.J7&K7_W1.U605.J7&K7
1500.0 net-DRAM_A1_drv-U1.L21_rcv-U604.P7_W1.U604.P7
1000.0 net-DRAM_A2_drv-U1.M20_rcv-U605.P3_W1.U605.P3
500.0 net-DRAM_A4_drv-U1.K20_rcv-U602.P8_W1.U602.P8
V
o net-DRAM_A4_drv-U1.K20_rcv-U604.P8_W1.U604.P8
l net-DRAM_A4_drv-U1.K20_rcv-U605.P8_W1.U605.P8
t
a net-DRAM_A5_drv-U1.N21_rcv-U602.P2_W1.U602.P2
g
e 0.00 net-DRAM_A5_drv-U1.N21_rcv-U603.P2_W1.U603.P2
- net-DRAM_A5_drv-U1.N21_rcv-U604.P2_W1.U604.P2
m
V- net-DRAM_A5_drv-U1.N21_rcv-U605.P2_W1.U605.P2
-500.0 net-DRAM_A6_drv-U1.M22_rcv-U604.R8_W1.U604.R8
-1000.0 net-DRAM_A7_drv-U1.N22_rcv-U605.R2_W1.U605.R2
-1500.0 net-DRAM_A9_drv-U1.M21_rcv-U602.R3_W1.U602.R3
-2000.0 net-DRAM_A10_drv-U1.K19_rcv-U603.L7_W1.U603.L7
51.000 52.000 53.000 54.000 55.000 56.000 57.000 58.000 59.000 60.000 net-DRAM_A11_drv-U1.L22_rcv-U604.R7_W1.U604.R7
Time (ns) net-DRAM_A11_drv-U1.L22_rcv-U605.R7_W1.U605.R7
Delta Voltage = 7.0mV, Delta Time = 207ps
Delta skew at VIH is about 150ps. It ’ s too much, should be max 50ps.
Conclusion: arrange address/command/control lines length to decrease skew; arrange trace

widths on the latest stubs.
- 18 -
5. TIMING ANALYSES
6 Conclusion
- 19 -
Appendix A: Layer overview:
Top layer. Clock signals, 1V5 and GND planes Layer 2. GND Plane
Layer 3. Databus-0, databus-2 Layer 4. Address, control stubs
- 20 -
Layer 5. 1V5 and GND planes Layer 6. 1V5 plane
Layer 7. Control signals Layer 8. Databus-1, databus-3; LVDS diff. pairs
- 21 -
Layer 9. GND plane Layer 10. Data and Control signal stubs, 1V5, GND.
- 22 -
Appendix B: Selecting best models for simulation (due the driver impedance, signal
strength and ODT parameters)
1. Data lines, Read from Controller cycle
Available models for controller: Available models for memory:
Equivalent schematic
Case 1, just one receiver (U602-DQ1) connected:

OSCILLOSCOPE
HyperLynx v 8.2.1
V [U602.F7 (at die)] Sweep

IC operating parameters Proce
3000.0
2500.0 V [U602.F7 (at die)] Sweep
2000.0 IC operating parameters Proce
1500.0 V [U602.F7 (at die)] Sweep
V IC operating parameters Proce
o 1000.0
l V [U602.F7 (at die)] Sweep
t IC operating parameters Proce
a
g V [U602.F7 (at die)] Sweep
e IC operating parameters Proce
-
m V [U602.F7 (at die)] Sweep
V 500.0
- IC operating parameters Proce
0.00 V [U602.F7 (at die)] Sweep
-500.0
-1000.0 IC operating parameters Proce
-1500.0 V [U602.F7 (at die)] Sweep
0.00 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 IC operating parameters Proce
Time (ns) V [U602.F7 (at die)] Sweep
Net name: DRAM_D1
- 23 -
Best case is: Typical, U1 DDR mode = “ ddr3_sel00_ds101_mio ” ; U602 DQ mode = “ DQ_4
OSCILLOSCOPE
HyperLynx v 8.2.1

3000.0
2500.0
2000.0
1500.0
V
o 1000.0
l
t
a
g
e
-
m
V 500.0
-
0.00
-500.0
-1000.0
-1500.0
0.00 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000
Time (ns)

Net name: DRAM_D1
Case 2, both receivers (U602-DQ1 and U603-DQ0) are connected:

OSCILLOSCOPE
HyperLynx v 8.2.1
V [U603.E3 (at die)]

V [U602.F7 (at die)]
3000.0
2500.0
2000.0
1500.0
V
o 1000.0
l
t
a
g
e
-
m
V 500.0
-
0.00
-500.0
-1000.0
-1500.0
0.00 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000
Time (ns)

Net name: DRAM_D1
Signal behavior is same when both receivers are connected.
- 24 -
2. Data lines, Write to Controller cycle
Available models for memory: Available models for controller:
Equivalent schematic
Sweep analysis result

OSCILLOSCOPE
HyperLynx v 8.2.1
V [U1.G21 (at die)] Sweep

IC operating parameters Proc
3000.0 V [U1.G21 (at die)] Sweep
2500.0
2000.0 IC operating parameters Proc
V IC operating parameters Proc
o 1000.0
l V [U1.G21 (at die)] Sweep
t IC operating parameters Proc
a
g V [U1.G21 (at die)] Sweep
e IC operating parameters Proc
m-
V 500.0
- IC operating parameters Proc
-500.0 IC operating parameters Proc

-1000.0
-1500.0 V [U1.G21 (at die)] Sweep
0.00 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 IC operating parameters Proc
Time (ns) V [U1.G21 (at die)] Sweep
Net name: DRAM_D1
All signals looks OK, any model can be selected for read cycle analysis.
- 25 -

DDR3 SI Analisys Report

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DDR3 SI Analisys Report

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By: Alexander Karas Date : 27 December 2012

Ref : Signal Integrity DDR3.doc

Subject: Signal Integrity DDR3 Classification: Edality / internal

1 Signal Integrity DDR3 ................................................................................................... 2

2 DDR3 PCB Layout ......................................................................................................... 3

3 Routing DDR3 board 22-12-2012 .................................................................................. 6

4 Routing DDR3 IF .......................................................................................................... 15

5 Timing analyses ............................................................................................................ 23

Appendix A: Layer overview: .......................................................................................... 28

Subject: Signal Integrity DDR3 Classification: Edality / internal

1 Signal Integrity DDR3

1.2 Project activities and deliverables

For the SI analyses of the DDR3 design (IMX53_module_v6_fdb_221212_1800), the

1. Creation/validation of missing IBIS models

2. Convert the DDR3 board databases to the analysis database

3. Collect board stack-up information

4. Post Layout SI Simulation DDR3 IF

1.3 Analysis software information

Subject: Signal Integrity DDR3 Classification: Edality / internal

2 DDR3 PCB Layout

Subject: Signal Integrity DDR3 Classification: Edality / internal

2.2 Board stackup info

Received stackup for the iMX53 board:

Subject: Signal Integrity DDR3 Classification: Edality / internal

Stackup from Mentor Graphics HyperLynx database:

Design: pcb.hyp, Designer: Sasha.

HyperLynx BoardSim v8.2.1

16 um, 3, Z0 = 51.9 ohms, w idth = 115 um

105 um, Er = 3.8

12 um, 10, Z0 = 50.6 ohms, w idth = 144 um

2.3 Critical Net List

GROUP NAME SPEED RATE DESCRIPTION

Subject: Signal Integrity DDR3 Classification: Edality / internal

3 Routing DDR3 board 22-12-2012

3.1 DDR3 clock

Waveform, typical case, die, 48 Ohm driver Rload =40 OSCILLOSCOPE

DRAM_SDCLK_0.Probe V [U603.K7 (at die) / U603.J7 (at die)]

Date: Tuesday Jan. 22, 2013 Time: 18:43:34

Termination resistor placed incorrectly. It should be placed as possible closer to receiver,

Subject: Signal Integrity DDR3 Classification: Edality / internal

Eye diagram, no jitter OSCILLOSCOPE

V [U603.K7 (at die) / U603.J7 (at die)]

Date: Thursday Jan. 10, 2013 Time: 15:43:45

Eye diagram, 1% UI Gaussian jitter

V [U603.K7 (at die) / U603.J7 (at die)]

Date: Thursday Jan. 10, 2013 Time: 15:56:06

Subject: Signal Integrity DDR3 Classification: Edality / internal

Waveform, typical case, die, 48 Ohm driver Rload =40 OSCILLOSCOPE

V [U605.K7 (at die) / U605.J7 (at die)]

Date: Friday Jan. 11, 2013 Time: 18:25:04

See comments for signal DRAM_SDCLK_0

Eye diagram, no jitter

V [U605.K7 (at die) / U605.J7 (at die)]

Date: Friday Jan. 11, 2013 Time: 18:40:34

Subject: Signal Integrity DDR3 Classification: Edality / internal

Eye diagram, 1% UI Gaussian jitter

V [U605.K7 (at die) / U605.J7 (at die)]

Date: Friday Jan. 11, 2013 Time: 18:55:15

Combine both Clock signals

Waveform, typical case, die, 48 Ohm driver Rload =40 OSCILLOSCOPE

V [U605.K7 (at die) / U605.J7 (at die)]

Date: Thursday Jan. 10, 2013 Time: 16:14:40