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1 1

Compal Confidential
2

Hasswell M/B Schematics Document 2

Intel ULV Processor with DDRIIIL


Date : 2014/02/08
3 3

Version 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 1 of 54
A B C D E
A B C D E

Compal Confidential
Model Name : Haswell
VRAM*4 Nvidia PCI-Ex4
Lane 7-Lane10
File Name : Single Rank N15V-GM
PCIe 2.0:5Gb/s
1 LA-A992PR10 17W PCIe 3.0:8Gb/s 1
P37~P40 P32~P36 DDR3-SO-DIMM X 2
Dual Channel
P15,16
eDPx2 DDR3L 1600MHz 1.35V
LVDS panel RTD2132R
P20 P18 2.7Gb/s
Haswell SATA 3.0 Port 0
2.5" SATA HDD P22
DDI Ultra Light & Thin GEN1 1.5Gb/s
CRT Conn IT6513 GEN2 3Gb/s Port 1
P29 P29 GEN3 6Gb/s ODD P22
1168P BGA
HDMI USB3.0
HDMI Conn 5Gb/s
DDPB port P19 222.75MHz (USW ULT) USB2.0 Port 0 Port 0
480Mb/s USB3.0 port P26
2 2

PCI-E Card reader Lane 4 PCI-E Port 1


USB2.0 port P26
RTS5239 P25 PCIe 1.0:2.5Gb/s
PCIe 2.0:5Gb/s
Port 2
10/100 1G LAN Lane 5 USB2.0 Port P27
8151/8166 Option P24
Port 3
Lane 11 PCIe 1.0:2.5Gb/s WLAN P20
PCIe 2.0:5Gb/s
WLAN(MiniPCIe slot) PCI-E
P23 Port 4
Camera P19

Port 5
Touch Screen P19
Port 3 Port 3 (Reserved) USB2.0
3 480Mb/s 3

SMBUS
1MHz

Int.KBD ENE KB9012 LPC


PS2 33MHz HDA Aduio codec
Touch Pad P30 HDA 24MHz
ALC3227 Internal SPK
FAN P25
TPM 1.2 @
Lid switch SLB 9656 P28 Combo Jack

SPI
4 50MHz 4

SPI ROM
8M P7
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 2 of 54
A B C D E
A B C D E

DAX
Power rail Control (EC) Source (CPU) 45@
ZZZ1
+RTCVCC X X
@ is NO SMT part (empty) <USB2.0 port>
VIN X X
PCB <BOM Structure>
BATT+ X X Part Number = DAZ14Z00100
DESTINATION
B+ X X
short@ : short pad , don't pop. PCB 14Z LA-A992P REV0 M/B 3 ROYALTY HDMI W/LOGO+HDCP
Part Number = RO0000003HM
ROYALTY HDMI W/LOGO+HDCP
+VL X X USB2.0 port UMA Dis
+3VL X X
@EMI@,@ESD@,@RF@ : Reserve , don't pop.
+5VALW EC_ON X 0 USB 2.0/3.0(left side) USB 2.0/3.0(left side)
1 1
+3VALW EC_ON X
+3VALW_EC EC_ON X
RF@ : RF team request, must add. 1 USB 2.0(right side) USB 2.0(right side)
+3V_PCH PCH_PWR_EN X
ZSO40@,ZSO50@ : Board ID config.
+1.35V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4#
EMI@ : EMI team request, must add. DIS@ : GPU BOM config. 2 USB 2.0(right side) USB 2.0(right side)
+5VS SUSP# PM_SLP_S3#
+3VS SUSP# PM_SLP_S3#
ESD@ : ESD team request, must add. 3 WLAN/BT WLAN/BT
+1.5VS SUSP# PM_SLP_S3#
+1.05VS SUSP# PM_SLP_S3#
LVDS@ : Support LVDS panel. 4 Camera Camera
+0.6V_0.675VS SUSP#
+VCC_CORE X VR12.5_VR_ON
GCLK@ : Support GCLK 5 Touch screen(Options) Touch screen(Options)
CRT@,CRTEMI@ : Support CRT port
6 X X
eDP@,eDPEMI@ : Support eTP panel
7 X X

<PCI-E,SATA,USB3.0>
2 UCPU1 2
+3V_PCH +3VS DESTINATION
Lane# PCI-E SATA USB3.0
R=2.2K R=10K
UMA Dis
AP2 SMBCLK PCH_SMBCLK 1 1 USB3.0 USB3.0
AH1 SMBDATA 2N7002 PCH_SMBDATA
SO‐DIMM A 2 2 X X
3 1 3 X X
CPU +3V_PCH
SO‐DIMM B
4
5
2
3
4 Card reader(PCI-E)
10/100/1000 LAN 10/100/1000 LAN
Card reader(PCI-E)

R=1K 6 4
SML0CLK
AN1 SML0DATA 7 GPU(DIS only)
AK1
8 GPU(DIS only)
5
9 GPU(DIS only)
+3V_PCH +3VS
10 GPU(DIS only)
11 L3 3 WLAN WLAN
R=2.2K R=2.2K
AU3 SML1CLK 12 L2 2 X X
AH3 SML1DATA 6
2N7002 13 L1 1 ODD ODD
EC_SMB_CK2
EC_SMB_DA2 14 L0 0 2.5"HDD 2.5"HDD
+3VS
3 3

Thermal Sensor @
UK1:+3VALW_EC

+3VS
79 EC_SMB_CK2
80 EC_SMB_DA2
eDP to LVDS bridge RTD2132R
EC +3VL

R=2.2K
77 EC_SMB_CK1
78 EC_SMB_DA1 R=100 BAT

Charger

G‐Sensor @
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A992P
Date: Thursday, March 20, 2014 Sheet 3 of 54
A B C D E
5 4 3 2 1

UCPU1A HASWELL_MCP_E L CC97~CC102 must closed to connector not CPU

<20> PCH_DPB_N2 C54 C45


DDI1_TXN0 EDP_TXN0 EDP_CPU_LANE_N0_C <18>
<20> PCH_DPB_P2 C55 B46 <eDP>
DDI1_TXP0 EDP_TXP0 EDP_CPU_LANE_P0_C <18>
<20> PCH_DPB_N1 B58 A47
C58 DDI1_TXN1 EDP_TXN1 B47
<20> PCH_DPB_P1 DDI1_TXP1 EDP_TXP1
D <20> PCH_DPB_N0 B55 D
A55 DDI1_TXN2 C47
<20> PCH_DPB_P0 DDI1_TXP2 EDP_TXN2
<HDMI> <20> PCH_DPB_N3 A57 C46
B57 DDI1_TXN3 EDP_TXP2 A49
<20> PCH_DPB_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
<29> PCH_DPC_N0 DDI2_TXN0
<29> PCH_DPC_P0 C50 A45 <eDP>
DDI2_TXP0 EDP_AUXN EDP_CPU_AUX#_C <18>
<DP TO CRT> <29> PCH_DPC_N1 C53 B45
DDI2_TXN1 EDP_AUXP EDP_CPU_AUX_C <18>
<29> PCH_DPC_P1 B54
C49 DDI2_TXP1 D20 EDP_COMP
B50 DDI2_TXN2 EDP_RCOMP A43 RC1 1 @ 2 0_0201_5%
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3 RC2 1 @ 2 0_0201_5%
DDI2_TXP3 BKL_PWM_CPU <18,8>

RC11 2 1 10K_0402_5% H_CPUPWRGD_R


+3V_PCH COMPENSATION PU FOR eDP DG V0.9 PEG_COMP
1 OF 19 +VCCIOA_OUT L Trace width=20mil and spacing=25mil

1
RC234 EDP_COMP 2 1
Max length=100mil
+VCCIO_OUT 10K_0402_5% 24.9_0402_1% RC3
HASWELL_MCP_E
UCPU1B

2
1

C RC4 PROC_DETECT# D61 C


62_0402_5% PAD T51 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY# T58 @ PAD
<30> H_PECI PECI PRDY K62 XDP_PREQ#
2

PREQ E60 XDP_TCK


PROC_TCK XDP_TCK <6>
E61 XDP_TMS_CPU
JTAG PROC_TMS XDP_TMS_CPU <6>
<30,44> PROCHOT# PROCHOT# RC6 1 2 56_0402_5% H_PROCHOT#_R K63 E59 XDP_TRST#_CPU
PROCHOT THERMAL
PROC_TRST F63 XDP_TDI_CPU
PROC_TDI XDP_TDI_CPU <6> +1.05VS_VCCST
1 F62 XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU <6>
@ESD@ @
C295 <11,6> +1.05VS_PG RC7 1 2 H_CPUPWRGD_R C61
10P_0402_50V8J 1K_0402_1% PROCPWRGD PWR
2 J60 XDP_OBS0_R T80 @ PAD XDP_TDI_CPU @ RC12 2 1 51_0402_1%
BPM#0 H60 XDP_OBS1_R T79 @ PAD
L DG V0.5 Trace width=12~15 mil BPM#1 H61 XDP_OBS2_R T52 @ PAD XDP_PREQ# @ RC13 2 1 51_0402_1%
Max length=500mil BPM#2 H62 XDP_OBS3_R T53 @ PAD
SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R T54 @ PAD
DDR3 COMPENSATION SIGNALS SM_RCOMP1 AV60 SM_RCOMP0 DDR3
BPM#4 H63 XDP_OBS5_R T55 @ PAD XDP_TRST#_CPU
SM_RCOMP1 BPM#5 XDP_TRST#_CPU <6>
SM_RCOMP2 AU61 K60 XDP_OBS6_R T56 @ PAD
200_0402_1% 2 1 RC18 SM_RCOMP0 DDR3_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R T57 @ PAD
SM_DRAMRST BPM#7 1
DDR_PG_CNTL AV61 @ESD@
120_0402_1% 2 1 RC19 SM_RCOMP1 SM_PG_CNTL1 CC99
0.1U_0402_16V7K
100_0402_1% 2 1 RC20 SM_RCOMP2 2 OF 19 2

B B

+1.35V_VDDQ
+1.35V_VDDQ
1

RC308
470_0402_5%
UC10
5 1
2

DDR3_DRAMRST# VCC NC
DDR3_DRAMRST# <15,16>
1 2 DDR_PG_CNTL
4 A
<15> SM_PG_CTRL Y
@ESD@ CC88 3
GND
0.1U_0402_16V7K
2 74AUP1G07GW_TSSOP5

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDI,MSIC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-A992P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 4 of 54
5 4 3 2 1

Compal Electronics, Inc.


5 4 3 2 1

<15> DDR_A_D[0..63] <16> DDR_B_D[0..63]

HASWELL_MCP_E
UCPU1D

UCPU1C HASWELL_MCP_E <DDR3L>


<DDR3L>
DDR_B_D0 AY31 AM38
SB_DQ0 SB_CK#0 M_CLK_DDR#2 <16>
DDR_A_D0 AH63 AU37 DDR_B_D1 AW31 AN38
D SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <15> SB_DQ1 SB_CK0 M_CLK_DDR2 <16> D
DDR_A_D1 AH62 AV37 DDR_B_D2 AY29 AK38
SA_DQ1 SA_CLK0 M_CLK_DDR0 <15> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <16>
DDR_A_D2 AK63 AW36 DDR_B_D3 AW29 AL38
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <15> SB_DQ3 SB_CK1 M_CLK_DDR3 <16>
DDR_A_D3 AK62 AY36 DDR_B_D4 AV31
SA_DQ3 SA_CLK1 M_CLK_DDR1 <15> SB_DQ4
DDR_A_D4 AH61 DDR_B_D5 AU31 AY49
SA_DQ4 SB_DQ5 SB_CKE0 DDR_CKE0_DIMMB <16>
DDR_A_D5 AH60 AU43 DDR_B_D6 AV29 AU50
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <15> SB_DQ6 SB_CKE1 DDR_CKE1_DIMMB <16>
DDR_A_D6 AK61 AW43 DDR_B_D7 AU29 AW49
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <15> SB_DQ7 SB_CKE2
DDR_A_D7 AK60 AY42 DDR_B_D8 AY27 AV50
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_B_D9 AW27 SB_DQ8 SB_CKE3
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D10 AY25 SB_DQ9 AM32
SA_DQ9 SB_DQ10 SB_CS#0 DDR_CS0_DIMMB# <16>
DDR_A_D10 AP63 AP33 DDR_B_D11 AW25 AK32
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <15> SB_DQ11 SB_CS#1 DDR_CS1_DIMMB# <16>
DDR_A_D11 AP62 AR32 DDR_B_D12 AV27
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <15> SB_DQ12
DDR_A_D12 AM61 DDR_B_D13 AU27 AL32
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_B_D14 AV25 SB_DQ13 SB_ODT0
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D15 AU25 SB_DQ14 AM35
SA_DQ14 SB_DQ15 SB_RAS DDR_B_RAS# <16>
DDR_A_D15 AP60 AY34 DDR_B_D16 AM29 AK35
SA_DQ15 SA_RAS DDR_A_RAS# <15> SB_DQ16 SB_WE DDR_B_WE# <16>
DDR_A_D16 AP58 AW34 DDR_B_D17 AK29 AM33
SA_DQ16 SA_WE DDR_A_WE# <15> SB_DQ17 SB_CAS DDR_B_CAS# <16>
DDR_A_D17 AR58 AU34 DDR_B_D18 AL28
SA_DQ17 SA_CAS DDR_A_CAS# <15> SB_DQ18
DDR_A_D18 AM57 DDR_B_D19 AK28 AL35
SA_DQ18 SB_DQ19 SB_BA0 DDR_B_BS0 <16>
DDR_A_D19 AK57 AU35 DDR_B_D20 AR29 AM36
SA_DQ19 SA_BA0 DDR_A_BS0 <15> SB_DQ20 SB_BA1 DDR_B_BS1 <16>
DDR_A_D20 AL58 AV35 DDR_B_D21 AN29 AU49
SA_DQ20 SA_BA1 DDR_A_BS1 <15> SB_DQ21 SB_BA2 DDR_B_BS2 <16>
DDR_A_D21 AK58 AY41 DDR_B_D22 AR28
SA_DQ21 SA_BA2 DDR_A_BS2 <15> SB_DQ22 DDR_B_MA[0..15] <16>
DDR_A_D22 AR57 DDR_B_D23 AP28 AP40 DDR_B_MA0
SA_DQ22 DDR_A_MA[0..15] <15> SB_DQ23 SB_MA0
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D24 AN26 AR40 DDR_B_MA1
DDR_A_D24 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
C C
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D32 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D34 AY21 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D35 AW56 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D36 AV58 SA_DQ35 DDR CHANNEL A SA_MA12 AR35 DDR_A_MA13 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D39 AU21 SB_DQ38 SB_MA15
SA_DQ38 SA_MA15 SB_DQ39 DDR_B_DQS#[0..7] <16>
DDR_A_D39 AU56 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
SA_DQ39 DDR_A_DQS#[0..7] <15> SB_DQ40 SB_DQSN0
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D41 AW19 AV26 DDR_B_DQS#1
DDR_A_D41 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
SA_DQ47 SA_DQSN7 SB_DQ48 DDR_B_DQS[0..7] <16>
DDR_A_D48 AK40 DDR_B_D49 AR22 AV30 DDR_B_DQS0
SA_DQ48 DDR_A_DQS[0..7] <15> SB_DQ49 SB_DQSP0
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D50 AL21 AW26 DDR_B_DQS1
DDR_A_D50 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
B
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7 B
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D58 AK18 SB_DQ57
DDR_A_D58 AM49 SA_DQ57 AP49 +V_SM_VREF_CNT DDR_B_D59 AL18 SB_DQ58
SA_DQ58 SM_VREF_CA +V_SM_VREF_CNT SB_DQ59
DDR_A_D59 AK49 AR51 +V_DDR_REFA_R +V_DDR_REFA_R DDR_B_D60 AK20
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 +V_DDR_REFB_R DDR_B_D61 AM20 SB_DQ60
SA_DQ60 SM_VREF_DQ1 +V_DDR_REFB_R SB_DQ61
DDR_A_D61 AK48 DDR_B_D62 AR18
DDR_A_D62 AM51 SA_DQ61 DDR_B_D63 AP18 SB_DQ62
DDR_A_D63 AK51 SA_DQ62 SB_DQ63
SA_DQ63

4 OF 19

3 OF 19

A A

Security Classification Compal Secret Data


2011/06/29 2011/06/29 Title
Issued Date Deciphered Date DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 5 of 54
5 4 3 2 1

Compal Electronics, Inc.


5 4 3 2 1

+RTCBATT
+RTCVCC PCH_RTCX1
XTAL@
1 2 PCH_RTCX2 RTC BAT conn
330K_0402_5% 1 2 RC236 PCH_INTVRMEN RC31 10M_0402_5% 15mils
1 2 1
- +

1
+RTCVCC XTAL@ +RTCBATT_R +RTCBATT
CC2 JCMOS1 CMOS YC1 +RTCVCC
1U_0402_6.3V6K SHORT PADS 1 2 1K_0402_5%

2
2
1 2 RC33
INTVRMEN PCH_RTCRST# XTAL@ 1 32.768KHZ Q13FC1350000500
1 DC1 15mils 15mils
* H:Integrated
L:Integrated
VRM enable
VRM disable
RC32
1
20K_0402_5%
2 PCH_SRTCRST#
CC3 CC4 XTAL@
18P_0402_50V8J
15mils 1
2 2 1 JRTC1
LOTES_AAA-BAT-054-K01 +3VS
RC34 20K_0402_5% 1 18P_0402_50V8J 1 3 +3VL CONN@

1
2 2 CC6
CC5 JME1 ME CMOS 1U_0402_6.3V6K BAV70W 3P C/C_SOT-323
1U_0402_6.3V6K SHORT PADS

2
2 2

D MPHY_PWREN RC217 1 2 10K_0402_5% D


<9> MPHY_PWREN
PCH_RTCX1
PCH_RTCX1 <31>
ODD_PLUG# RC218 1 2 100K_0402_5%
HASWELL_MCP_E
UCPU1E

PCH_RTCX1 AW5
PCH_RTCX2 AY5 RTCX1
RC353 short@ RC35 1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
+RTCVCC INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <22>
HDA_SYNC_R 1 2 HDA_SYNC PCH_INTVRMEN AV7 H5 SATA_PRX_DTX_P0 <22>
PCH_SRTCRST# AV6 INTVRMEN SATA_RP0/PERP6_L3 B15
0_0402_5% PCH_RTCRST# AU7 SRTCRST
RTC
SATA_TN0/PETN6_L3 A15
SATA_PTX_DRX_N0 <22> 2.5" HDD
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <22>
J8
SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1 <22>
H8 SATA_PRX_DTX_P1 <22> ODD
SATA_RP1/PERP6_L2 A17
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 <22>
Intel ME update B17
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <22>
short@ HDA_BIT_CLK AW8 J6
RC356 1 20_0201_5% HDA_SDOUT HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
<30> HDA_SDO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
HDA_RST# AU8 B14
HDA_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
<25> HDA_SDIN0 HDA_SDI0/I2S0_RXD AUDIO SATA_TP2/PETP6_L1
AU12
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 PCIE_PRX_DTX_N6 <21>
EMI@ RC367 AW10 E5 PCIE_PRX_DTX_P6 <21>
HDA_BITCLK_AUDIO 2 1 HDA_BIT_CLK AV10 DOCKEN/I2S1_TXD SATA SATA_RP3/PERP6_L0 C17 PCIE_PTX_DRX_N6 CC71 2 0.1U_0402_16V7K
<25> HDA_BITCLK_AUDIO
33_0402_5% AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 PCIE_PTX_DRX_P6 CC81 2 0.1U_0402_16V7K
PCIE_PTX_C_DRX_N6 <21> WLAN
RP1
SI# 2012.11.1 Add RC367 EMI@ to isolate  I2S1_SCLK SATA_TP3/PETP6_L0 PCIE_PTX_C_DRX_P6 <21>
1 8 Audio Clock by EMI request
<25> HDA_RST_AUDIO# HDA_RST_AUDIO# 2 7 HDA_RST# V1
3 6 HDA_SYNC_R SATA0GP/GPIO34 U1 ODD_PLUG#
<25> HDA_SYNC_AUDIO SATA1GP/GPIO35 ODD_PLUG# <22>
<25> HDA_SDOUT_AUDIO 4 5 HDA_SDOUT V6 PCH_GPIO36 T159 PAD
33_0804_8P4R_5% SATA2GP/GPIO36 AC1 mSATA_DET#
SATA3GP/GPIO37 mSATA_DET# <7>
PCH_JTAG_RST# AU62
PCH_JTAG_TCK AE62 PCH_TRST A12
PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 RC39
+1.05VS_VCCSATA3PLL <Page 12>
+3V_PCH PCH_JTAG_TDO AE61 PCH_TDI TP7 K10 3K_0402_1%
C
9/17 add RF solution PCH_JTAG_TMS AD62 PCH_TDO TP8 C12 SATA_COMP 1 2 C
PAD T156 AL11 PCH_TMS
JTAG
SATA_RCOMP U3 SATA_LED# L DG V0.9 SATA_COMP
TP5 SATALED SATA_LED# <27,9>
1

AC4 Width=12mil
RC283 @ XDP_TCK_JTAGX AE63 TP6
210_0402_5% @
CM28
PAD T157 AV2 JTAGX Max length=500mil
1 2 HDA_BITCLK_AUDIO RSVD

R3d
2

PCH_JTAG_TDO
22P_0402_50V8J
1

5 OF 19
CM29
RC304 @ @
100_0402_1% 1 2 HDA_RST_AUDIO#
2

22P_0402_50V8J
+3VS
RC240
@ @ CC86
+3V_PCH EC_+1.05VS_PG 2 1 1 2

+3V_PCH +3V_PCH
10K_0402_5% .1U_0402_16V7K
1

@ UC5
RC45 @ 2 16
1OE VCC
1

210_0402_5%
RC41 @ RC46 XDP_TDO_CPU 3 4 XDP_TDO
1A 1B
210_0402_5% 210_0402_5%
R5
2

PCH_JTAG_TMS 5
@ 2OE
R8 <CPU site>
2

PCH_JTAG_TDI XDP_TCK_JTAGX XDP_TDI_CPU 6 7 XDP_TDI_SWITCH


R4 RC303 @ 2A 2B
1

100_0402_1% 12
RC301 @ RC302 3OE
100_0402_1% 100_0402_1% 11 10 XDP_TMS
<4> XDP_TMS_CPU
2

@ 3A 3B
15
2

4OE
XDP_TRST#_CPU 14 13 XDP_TRST#
S1 <4> XDP_TRST#_CPU 4A 4B
1
XDP_TRST# RC37 1 @ 2 0_0201_5% XDP_TRST#_CPU NC
<CPU site> 8 9
B
<XDP> PCH_JTAG_RST#
Contact ok GND NC B
<PCH site>
74CBTLV3126DS_SSOP16
S2 R6
<PCH site> PCH_JTAG_TMS RC196 1 @ 2 0_0201_5% XDP_TMS_CPU <CPU site>
Contact ok PCH_JTAG_TCK 51_0402_5% 1 @ 2 RC38
XDP_TMS +1.05VS_VCCST
<XDP>

1
S3 +3V_PCH
XDP_TDI_SWITCH RC199 1 @ 2 0_0201_5% XDP_TDI_CPU
XDP_TDI_CPU <4> <CPU> R9 R511
U16 10K_0402_5%
XDP_TRST#_CPU RC16 2 @ 1 51_0402_1% <EC output> 1 5
J3S

2
NC VCC
<PCH site> PCH_JTAG_TDO RC307 1 @ 2 0_0201_5% XDP_TDI_SWITCH <XDP> EC_+1.05VS_PG 2
<30> EC_+1.05VS_PG A 4
3 Y +1.05VS_PG <11,4> <CPU,XDP,XDP Switch>
J4d GND
<XDP> XDP_TDI RC200 1 2 0_0201_5% XDP_TDI_SWITCH 74AUP1G07GW_TSSOP5
short@

PCH_JTAG_TDI RC195 1 2 0_0201_5% XDP_TDI +1.05VS_VCCST Resistors Resistors


<PCH site> short@
Topolog Description Be st Use for Stuffed ufStuffed
R1d
S4 XDP_TDO_CPU RC10 2 1 51_0402_1%
Default Setting: Dual In this topology, the - Run control oper. R1d,R2,R3d, J1s, J2s,
XDP_TDO RC198 1 @ 2 0_0201_5% XDP_TDO_CPU
XDP_TDO_CPU <4>
<XDP> TCK S can Chains CPU JTAG chain will be - ME/Sx debug R4,R5,J1d J3s
+1.05VS_VCCST (also known as controlled by TCK0 and J2d,J3d* R6,R7,R8,R9
J3D <PCH site> "Shared JTAG" in TCK1 will control J4d and Rs5*
RC194
short@
1 2 0_0201_5% PCH_JTAG_TDO R7 other docum ent) the PCH JTAG chain.
@
XDP_TDO RC14 2 1 51_0402_1%
XDP_TCK:XDP contact with CPU No 0ohm(RS5) R1d,r3d,J1d,J2d
In th is topolog y, PCH -B oundary Scan/ J1s,J2s,J3s**
A Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est R2,R4,R5,R5s** J3d**,J4d, A

<PCH site>
R2 (also known as "Com m on will be chained to form
R6,R7,R8,R9
PCH_JTAG_TCK XDP_TCK RC15 2 1 51_0402_1% JTAG" in other docum one JTAG scan chain
ent) controlled by TCK0
J1S
RC197 1 @ 2 0_0201_5% XDP_TCK XDP_TCK <4> <CPU and XDP>

<PCH site> J2D


XDP_TCK_JTAGX RC193 1 2 0_0201_5%
short@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

J2S <XDP> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTC,SATA,HDA,JTAG
<PCH site> XDP_TCK_JTAGX RC306 1 @ 2 0_0201_5% XDP_TDO Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 6 of 54
5 4 3 2 1
5 4 3 2 1

CPU_XTAL24_IN CPU_XTAL24_IN <31> CPU_XTAL24_IN

CPU_XTAL24_OUT
XTAL@
HASWELL_MCP_E 2 1
UCPU1F
1M_0402_5% RC48

3 1
CLK_PCIE_LAN# C43 A25 CPU_XTAL24_IN 3 1
<23> CLK_PCIE_LAN# CLKOUT_PCIE_N0 XTAL24_IN GND GND
PCIE LAN CLK_PCIE_LAN C42 B25 CPU_XTAL24_OUT XTAL@ 1 1 XTAL@
<23> CLK_PCIE_LAN CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKREQ0# U2 CC9 CC10
PCIECLKRQ0/GPIO18 K21 RC52 4 XTAL@ 2 18P_0402_50V8J
CLK_PCIE_CR# B41 TP15 M21 3K_0402_1% 18P_0402_50V8J YC2
D <23> CLK_PCIE_CR# CLKOUT_PCIE_N1 TP16 2 2 D
PCIE Card reader CLK_PCIE_CR A41 C26 PCH_CLK_BIASREF 1 2 +1.05VS_AXCK_LCPLL <Page12> 24MHZ 12PF 5YEA24000122IF40Q3
<23> CLK_PCIE_CR CLKOUT_PCIE_P1 DIFFCLK_BIASREF
<23,9> CR_CLKREQ# CR_CLKREQ# Y5
PCIECLKRQ1/GPIO19 C35 TESTLOW1 4 5 RPH22
CLK_PCIE_MINI1# C41 CLOCK TP19 C34 TESTLOW2 3 6
<21> CLK_PCIE_MINI1#
CLK_PCIE_MINI1 B42 CLKOUT_PCIE_N2 SIGNALS TP20 AK8 TESTLOW3 2 7
<PV>PRH13 change to RPH22.
WLAN <21> CLK_PCIE_MINI1
LAN_CLKREQ# AD1 CLKOUT_PCIE_P2 TP21 AL8 TESTLOW4 1 8
<23> LAN_CLKREQ# PCIECLKRQ2/GPIO20 TP22 10K_0804_8P4R_5%
CLK_PCIE_GPU# B38 AN15 CLK_PCI0 EMI@ RC61 1 2 22_0402_5% CLK_PCI_LPC <EC>
<32> CLK_PCIE_GPU# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC <30>
GPU CLK_PCIE_GPU C37 AP15 CLK_PCI1 EMI@ RC62 1 2 22_0402_5% CLK_PCI_TPM
<32> CLK_PCIE_GPU CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM <28>
<32,8> GPU_CLKREQ# GPU_CLKREQ# N1
PCIECLKRQ3/GPIO21 B35 CLK_CPU_ITP# T82 @ PAD
A39 CLKOUT_ITPXDP A35 CLK_CPU_ITP T81 @ PAD
B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P <XDP CLK reserve TP>
PCIECLKREQ4# U5 CLKOUT_PCIE_P4
+3VS <9> PCIECLKREQ4# PCIECLKRQ4/GPIO22
RPH11 9/17 add RF solution
B37
4 5 LAN_CLKREQ# A37 CLKOUT_PCIE_N5
3 6 SYS_RESET# MINI1_CLKREQ# T2 CLKOUT_PCIE_P5 +3V_PCH
SYS_RESET# <8> <21> MINI1_CLKREQ# PCIECLKRQ5/GPIO23
2 7 EC_KBRST# @RF@
EC_KBRST# <30,9> CM30
1 8 MSATA_DET# MSATA_DET# <6>
6 OF 19 1 2 CLK_PCI_LPC
10K_0804_8P4R_5%

+3VS RPH12 22P_0402_50V8J SML0CLK 1K_0402_5% 1 2 RC72


HASWELL_MCP_E
UCPU1G @RF@
CM31
4 5 PCIECLKREQ0# SML0DATA 1K_0402_5% 1 2 RC73
3 6 MINI1_CLKREQ# LPC_AD0 AU14 AN2 SMBALERT# 1 2 CLK_PCI_TPM
<28,30> LPC_AD0 LAD0 SMBALERT/GPIO11 SMBALERT# <9>
2 7 PCI_PIRQB# PCI_PIRQB# <8> LPC_AD1 AW12 AP2 SMBCLK
<28,30> LPC_AD1 LAD1 LPC SMBCLK
1 8 PCH_GPIO33 PCH_GPIO33 <9> LPC_AD2 AY12 AH1 SMBDATA SMBCLK RP2 1 8 2.2K_0804_8P4R_5%
<28,30> LPC_AD2 LAD2 SMBUS SMBDATA 22P_0402_50V8J
C LPC_AD3 AW11 AL2 USB_CR_PWREN USB_CR_PWREN <8> SMBDATA 2 7 C
<28,30> LPC_AD3 LAD3 SML0ALERT/GPIO60
10K_0804_8P4R_5% LPC_FRAME# AV12 AN1 SML0CLK @RF@ SML1CLK 3 6
<28,30> LPC_FRAME# LFRAME SML0CLK CM33
RPH19 AK1 SML0DATA SML1DATA 4 5
PCH_SPI_CS0# 8 1 PCH_SPI_CS0#_R SML0DATA AU4 SML1ALERT# 1 2 PCH_SPI_CLK_R
SML1ALERT/PCHHOT/GPIO73 SML1ALERT# <9>
PCH_SPI_SO 7 2 PCH_SPI_SO_R AU3 SML1CLK
PCH_SPI_SI 6 3 PCH_SPI_SI_R SML1CLK/GPIO75 AH3 SML1DATA
PCH_SPI_HOLD# 5 4 PCH_SPI_SIO3 PCH_SPI_CLK AA3 SML1DATA/GPIO74 22P_0402_50V8J
PCH_SPI_CS0# Y7 SPI_CLK AF2
DB# 2013.08.27 RC368 place near CPU 15_0804_8P4R_5% Y4 SPI_CS0 CL_CLK AD2
AC2 SPI_CS1 SPI C-LINK CL_DATA AF4
PCH_SPI_CLK RC368 1 2 PCH_SPI_CLK_R PCH_SPI_SI AA2 SPI_CS2 CL_RST
EMI@ 15_0402_5% PCH_SPI_SO AA4 SPI_MOSI +3VS +3VS
RPH20 PCH_SPI_SIO2 Y6 SPI_MISO
8 1 PCH_SPI_SI_R PCH_SPI_SIO3 AF1 SPI_IO2
<30> EC_SPI_SI SPI_IO3
7 2 PCH_SPI_SO_R
<30> EC_SPI_SO
6 3 PCH_SPI_CS0#_R SI# 2012.11.1 Add RC368 ,RC369 to 
<30> EC_SPI_CS0#

2
PCH_SPI_SIO2 5 4 PCH_SPI_WP#
Isolate SPI Clock by EMI request RC78 RC79
15_0804_8P4R_5% 7 OF 19 10K_0402_5% 10K_0402_5%

2
EMI@ RC369 1 2 short@ RC56 1 2 0_0402_5% PCH_SPI_CLK_R QC2A 2N7002DWH_SOT363-6
<30> EC_SPI_CLK

1
15_0402_5%
DB# 2013.08.27 RC369 place near SPI ROM SMBCLK 6 1
PCH_SMBCLK <15,16>

+3V_PCH

5
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P 2N7002DWH_SOT363-6
MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P QC2B
2

WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM SMBDATA 3 4


B
@ RC80
3.3K_0402_5%
SPI ROM 8M Micron SA00005L100 S IC FL 64M +3V_PCH
N25Q064A13ESEC0F SO8W 8P PCH_SMBDATA <15,16>
B

+3VS
1

UC2
PCH_SPI_CS0#_R 1 8
PCH_SPI_SO_R 2 CS# VCC 7 PCH_SPI_HOLD# 2 1 RC84 3.3K_0402_5%
SO/SIO1 HOLD# 1
+3V_PCH 1 2 PCH_SPI_WP# 3 6 PCH_SPI_CLK_R
RC85 3.3K_0402_5% 4 WP# SCLK 5 PCH_SPI_SI_R CC11
GND SI/SIO0
0.1U_0402_16V7K

2
EN25Q64-104HIP 2 @ 2N7002DWH_SOT363-6

SML1CLK 6 1
EC_SMB_CK2 <18,30,32>

5
QC6A

SML1DATA 3 4
EC_SMB_DA2 <18,30,32>
2N7002DWH_SOT363-6
QC6B

remove thernal sensor 10/14


A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLK,SPI,SMB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 7 of 54
5 4 3 2 1
5 4 3 2 1

+RTCVCC

T83 short@ RC268 1 20_0201_5% PM_SLP_S0#_R


DSWODVREN - On Die DSW VR Enable
PAD H:Enable DSWODVREN RC254 2 1 330K_0402_5%
RC269 1 2 0_0201_5% PM_SLP_S3# *
@ L:Disable DSWODVREN RC255 2 1 330K_0402_5%
Non Deep S3 RC91-->SMT @
Deep S3 RC93-->SMT
UCPU1H HASWELL_MCP_E
@
SUSWARN#_R RC91 1 2 0_0201_5% SYSTEM POWER MANAGEMENT
<9> SUSWARN#_R

<30> SUSACK# short@ RC93 1 20_0201_5% SUSACK#_R AK2 AW7 DSWODVREN RC371 1 2 0_0402_5% AOAC_PME#
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_DPWROK_R short@
D <7> SYS_RESET# SYS_RESET DPWROK D
<30> SYS_PWROK SYS_PWROK AG2 AJ5 WAKE#
SYS_PWROK WAKE WAKE# <41> +3V_DSW_P
short@ RC99 1 2 0_0402_5% PM_PWROK_R AY7
PCH_PWROK short@ RC1001 2 0_0402_5% APWROK_R AB5 PCH_PWROK
<30> PCH_PWROK APWROK T147
PLT_RST#_PCH AG7 V5 PM_CLKRUN# PM_CLKRUN# <30>
PLTRST CLKRUN/GPIO32 AG4 SUS_STAT# WAKE# RC98 1 2 1K_0402_5%
SUS_STAT/GPIO61 AE6
SUSCLK/GPIO62 AP5
SLP_S5/GPIO63 PAD PM_SLP_S5# <30>
<30> PCH_RSMRST# PCH_RSMRST# AW6
short@ RC1041 2 0_0402_5% SUSWARN#_R AV4 RSMRST @
Deep S3 <30> PCH_SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
<30> PBTN_OUT# short@ RC1031 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4# <30>
1 2 DC2 ACIN_R AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S3#
<30,44,45,46> ACIN ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <30>
CH751H-40PT_SOD323-2 PM_BATLOW# AN4 AL5 T145PAD @
PM_SLP_S0#_R AF3 BATLOW/GPIO72 SLP_A AP4 1 2 0_0201_5%
SLP_S0 SLP_SUS PM_SLP_SUS# <30>
PCH_SLP_WLAN# AM5 AJ7
SLP_WLAN/GPIO29 SLP_LAN short@ RC286 PCH_RSMRST# RC106 2 1 10K_0402_5%

C70 ESD@
1 2 PCH_PWROK Non Deep S3 RC286-->@
8 OF 19 T142 T143DeepS3 RC286-->SMT T144
PAD PAD PAD
0.047U_0402_16V7K @ @ @

CH751H-40PT_SOD323-2
Deep S3:DSW power choose on page12
PCH_RSMRST# 1 2 DC3 PCH_PWROK

CH751H-40PT_SOD323-2 +3V_DSW_P
RC112 2 1 100K_0402_5% SYS_PWROK DC4 2 1 SPOK <47>
C C
PCH_DPWROK_R RC316 1 20_0201_5% PCH_DPWROK <30>
short@

RPH15
HASWELL_MCP_E 1 8
UCPU1I PM_BATLOW#
<7> USB_CR_PWREN USB_CR_PWREN 2 7
PANEL_BKEN_CPU PD 100K on Page20 3 6
PCH_SLP_WLAN# 4 5

short@ RC114 1 2 0_0402_5% BKL_PWM_CPU_R B8 B9 PCH_DDPB_CLK 10K_0804_8P4R_5%


<18,4> BKL_PWM_CPU EDP_BKLCTL DDPB_CTRLCLK PCH_DDPB_CLK <20>
short@ RC115 1 2 0_0402_5% ENBKL_CPU A9 C9 PCH_DDPB_DAT <HDMI> ACIN_R RC101 1 2 10K_0402_5%
<30> ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA PCH_DDPB_DAT <20>
ENVDD_CPU RC116 1 2 0_0402_5% ENVDD_CPU_R C6 D9 @ 1RC107 2 2.2K_0402_5%
<19> ENVDD_CPU EDP_VDDEN DDPC_CTRLCLK
short@ D11 1 2 +3VS
DDPC_CTRLDATA RC102 2.2K_0402_5%

EC_SMI# U6 <SI>Displayport Port C Enable pin RC102 pull high +3VS


<9> EC_SMI# PIRQA/GPIO77
PCI_PIRQB# P4 C5
<7> PCI_PIRQB# PIRQB/GPIO78 DISPLAY DDPB_AUXN +3VS
PCI_PIRQC# N4 B6 DDI1_AUX_DN
<9> PCI_PIRQC# PIRQC/GPIO79 DDPC_AUXN DDI1_AUX_DN <29>
@ PCH_GPIO80 N2 B5
<30> AOAC_PME# AOAC_PME# 1 2 AOAC_PME#_R AD4 PIRQD/GPIO80 DDPB_AUXP A6 DDI1_AUX_DP <DP TO CRT HPD>
PME GPIO DDPC_AUXP DDI1_AUX_DP <29>
RC305 0_0402_5%
U7
TS_RST# L1 GPIO55
PAD T146 @ GPIO52
PCH_MC_WAKE# L3 C8 <HDMI> PM_CLKRUN# RC110 2 1 8.2K_0402_5%
GPIO54 DDPB_HPD PCH_DDPB_HPD <20>
PCH_MIC_DET R5 A8
PAD T154 @ GPIO51 DDPC_HPD DDI1_HPD <29> <DP TO CRT HPD>
PCH_HP_DET L4 D6
GPIO53 EDP_HPD EDP_HPD <18>
RC120 1 2 100K_0402_5% ENVDD_CPU
<eDP HPD>
B B

9 OF 19

+3VS

@
1 2
RC300 0_0402_5%
RC125 2 1 10K_0402_5% PCH_MC_WAKE#
+3VS

RPH27 4 5 GPU_CLKREQ#
GPU_CLKREQ# <32,7>
3 6 PCH_GPIO80
5

2 7 PCH_HP_DET UC9
1 8 DEVSLP1 1 PLT_RST#_PCH <CPU>
P

DEVSLP1 <22,9> IN1


10K_0804_8P4R_5% <21,23,28,30,32> PLT_RST# PLT_RST# 4
O 2
IN2
G

<PV>PRH18 change to RPH27. SN74AHC1G08DCKR_SC70-5


3

PD on KBC page
A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PM,GPIO,DDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 8 of 54
5 4 3 2 1
5 4 3 2 1

+1.05VS_VCCST

1
HASWELL_MCP_E
UCPU1J RC242
1K_0402_5%

short@ RC129

2
0_0402_5%
PCH_AUDIO_PWREN P1 D60 H_THERMTRIP#_C 1 2 H_THEMTRIP#
AU2 BMBUSY/GPIO76 THRMTRIP V4 EC_KBRST#
GPIO8 RCIN/GPIO82 EC_KBRST# <30,7>
<23> LAN_PWR_EN LAN_PWR_EN AM7 T4 SERIRQ SERIRQ <28,30> DG V0.9 PCH_OPIRCOMP
EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15PCH_OPIRCOMP 2 1
<30> EC_LID_OUT# GPIO15 OPI_COMP2
RC122 1@ 2 0_0201_5% PCH_GPIO16 Y1 MISC AF20 RC131 Width=12mil,spacing=12mil
D
<30> EC_FB_CLAMP_TGL_REQ#
<34> DGPU_GC6_EN RC123 1@ 2 0_0201_5% PCH_GPIO17
UART_WAKE#
T3
AD5
GPIO16
GPIO17
RSVD
RSVD
AB21 49.9_0402_1% L Max length=500mil D

EC_PME# AN5 GPIO24


<23,30> EC_PME# GPIO27
PAD T148 AD7
PAD T149 AN3 GPIO28
GPIO26 R6 NGFF_WIFI_3.3_PWREN Boot BIOS Strap
BT_ON AG6 GSPI0_CS/GPIO83 L6 WWAN_PWREN
GPIO56 GSPI0_CLK/GPIO84 PCH_GPIO86 Boot BIOS Location
AP1 N6 PCH_GPIO85 RC108 1@ 2 0_0201_5%
GPIO57 GSPI0_MISO/GPIO85 DGPU_PWR_EN <30,35,53>
RC119 1@ 2 PCH_GPIO58 AL4 L8 MSATA_SSD_PWREN 0 SPI
<30,32> DGPU_HOLD_RST#
<10,21> WL_OFF# 0_0201_5% WL_OFF# AT5 GPIO58
GPIO59 GPIO
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
R7 *
<30> NMI_DBG#_CPU NMI_DBG#_CPU AK4 L5
LPDDR3_ID1 AB6 GPIO44 GSPI1_CLK/GPIO88 N7 TOUCH_PANEL_PWREN
LPDDR3_ID2 U4 GPIO47 GSPI1_MISO/GPIO89 K2 SATA1_PWREN
LPDDR3_ID3 Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PCH_LAN_RST#
PAD T150 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_LAN_WAKE#
9/12 reserve DGPU_PWR_EN on GPIO85
MPHY_PWREN Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_CR_RST#
<6> MPHY_PWREN HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93
USB32_P0_PWREN_R# AT3 G1 PCH_CR_WAKE#
AH4 GPIO13 UART0_CTS/GPIO94 K4
USB_CAM_PWREN AM4 GPIO14 UART1_RXD/GPIO0 G2
TS_GPIO_CPU AG5 GPIO25 UART1_TXD/GPIO1 J3
<19> TS_GPIO_CPU GPIO45 UART1_RST/GPIO2
<28> ACCEL_INT# ACCEL_INT# AG3 J4 ODD_DA# ODD_DA# <22>
GPIO46 UART1_CTS/GPIO3 F2 I2C_0_SDA
PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C_0_SCL
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C_1_SDA
<30> EC_SCI# GPIO10 I2C1_SDA/GPIO6
PCH_GPIO33 P2 F1 I2C_1_SCL
<7> PCH_GPIO33 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
PAD T158 Dummy C4 E3
DEVSLP1 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4
<22,8> DEVSLP1 DEVSLP1/GPIO38 SDIO_CMD/GPIO65
N5 D3
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4
<25> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
C C3 ODD_PWR NGFF_WIFI_3.3_PWREN 4 5 RPH21 C
SDIO_D2/GPIO68 ODD_PWR <22>
E2 WWAN_PWREN 3 6
+3VS SDIO_D3/GPIO69 MSATA_SSD_PWREN 2 7
+3V_PCH 10 OF 19 TOUCH_PANEL_PWREN 1 8
10K_0804_8P4R_5%
<SI> PRH14.4 change from +3V_PCH to +3VS for S3 leakage 
RPH23 4 5 ODD_DA# <PV>PRH12 change to RPH21.
3 6 EC_LID_OUT# +3V_PCH +3VS +3VS
2 7 UART_WAKE# +3VS
1 8 BT_ON
1

1
10K_0804_8P4R_5%
RC135 RC261 RC262
RPH24 4 5 USB_OC2#
USB_OC2# <10>
3 6 10K_0402_5% 10K_0402_5% 10K_0402_5%
2 7 ACCEL_INT# @ @ @
<PV>PRH19 change to RPH28.
2

2
1 8 PCH_GPIO58 LPDDR3_ID1
10K_0804_8P4R_5% LPDDR3_ID2 PCH_CR_WAKE# 4 5 RPH28
LPDDR3_ID3 PCH_CR_RST# 3 6
RPH25 4 5 USB_OC0# PCH_LAN_WAKE# 2 7
USB_OC0# <10,24>
3 6 USB32_P0_PWREN_R# PCH_LAN_RST# 1 8
1

2 7 PCH_GPIO9 10K_0804_8P4R_5%
1 8 NMI_DBG#_CPU @RC263 @RC264 @RC265 @
10K_0804_8P4R_5%
<PV>PRH14 change to RPH23. 10K_0402_5% 10K_0402_5% 10K_0402_5%
I2C_1_SDA 8 1 RPH18
2

          PRH15 change to RPH24. I2C_0_SCL 7 2
I2C_0_SDA 6 3
+3VS           PRH16 change to RPH25. I2C_1_SCL 5 4
B RPH13 B
4 5 1K_0804_8P4R_5%
3 6 CR_CLKREQ# @
CR_CLKREQ# <23,7>
2 7 SERIRQ
1 8 SATA_LED# +3V_PCH
SATA_LED# <27,6>
10K_0804_8P4R_5%
RPH26 4 5 PCH_GPIO17
3 6 EC_SMI# RPH14 4 5 SUSWARN#_R
EC_SMI# <8> SUSWARN#_R <8>
2 7 PCIECLKREQ4# 3 6 SML1ALERT#
PCIECLKREQ4# <7> SML1ALERT# <7>
1 8 PCI_PIRQC# 2 7 SMBALERT#
PCI_PIRQC# <8> SMBALERT# <7>
10K_0804_8P4R_5% 1 8 EC_SCI#
10K_0804_8P4R_5%
RPH10 4 5 SATA1_PWREN
3 6 PCH_AUDIO_PWREN
2 7 USB_CAM_PWREN
1 8 LAN_PWR_EN
10K_0804_8P4R_5% <PV>PRH10 change to RPH10.
           PRH17 change to RPH26.
+3V_DSW_P
DSW power choose on page12
* GPIO27 RC277 1 2 10K_0402_5% EC_PME#

A A
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPIO,UART,I2C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 9 of 54
5 4 3 2 1
5 4 3 2 1

HASWELL_MCP_E
UCPU1K
<DB>change AC cap to 0.22uF review by Nvidia 
PEG_GTX_C_HRX_N7 F10 AN8
D <32> PEG_GTX_C_HRX_N7 PERN5_L0 USB2N0 USB20_N0 <24> D
PEG_GTX_C_HRX_P7 E10 AM8 USB2.0/USB3.0
<32> PEG_GTX_C_HRX_P7 PERP5_L0 USB2P0 USB20_P0 <24>
0.22U_0402_6.3V6K DIS@ 1 2 CC90 C23
PEG_HTX_GRX_N7 AR7
<32> PEG_HTX_C_GRX_N7 PETN5_L0 USB2N1 USB20_N1 <24>
0.22U_0402_6.3V6K DIS@ 1 2 CC91 C22
PEG_HTX_GRX_P7 AT7 USB2.0
<32> PEG_HTX_C_GRX_P7 PETP5_L0 USB2P1 USB20_P1 <24>
PEG_GTX_C_HRX_N8 F8 AR8
<32> PEG_GTX_C_HRX_N8 PERN5_L1 USB2N2 USB20_N2 <24>
PEG_GTX_C_HRX_P8 E8 AP8 USB2.0
<32> PEG_GTX_C_HRX_P8 PERP5_L1 USB2P2 USB20_P2 <24>
0.22U_0402_6.3V6K DIS@ 1 2 CC89 B23
PEG_HTX_GRX_N8 AR10
<32> PEG_HTX_C_GRX_N8 PETN5_L1 USB2N3 USB20_N3 <21>
0.22U_0402_6.3V6K DIS@ 1 2 CC92 A23
PEG_HTX_GRX_P8 AT10 WLAN/BT
<32> PEG_HTX_C_GRX_P8 PETP5_L1 USB2P3 USB20_P3 <21>
PEG_GTX_C_HRX_N9 H10 AM15
<32> PEG_GTX_C_HRX_N9 PERN5_L2 USB2N4 USB20_N4 <19>
PEG_GTX_C_HRX_P9 G10 AL15 Camera
<32> PEG_GTX_C_HRX_P9 PERP5_L2 USB2P4 USB20_P4 <19>
0.22U_0402_6.3V6K DIS@ 1 2 CC93 PEG_HTX_GRX_N9 B21 AM13
<32> PEG_HTX_C_GRX_N9 PETN5_L2 USB2N5 USB20_N5 <19>
0.22U_0402_6.3V6K DIS@ 1 2 CC94 PEG_HTX_GRX_P9 C21 AN13 Touch screen
<32> PEG_HTX_C_GRX_P9 PETP5_L2 USB2P5 USB20_P5 <19>
PEG_GTX_C_HRX_N10 E6 AP11
<32> PEG_GTX_C_HRX_N10 PERN5_L3 USB2N6
PEG_GTX_C_HRX_P10 F6 AN11
<32> PEG_GTX_C_HRX_P10 PERP5_L3 USB2P6
0.22U_0402_6.3V6K DIS@ 1 2 CC95 PEG_HTX_GRX_N10 B22 AR13
<32> PEG_HTX_C_GRX_N10 PETN5_L3 USB2N7
0.22U_0402_6.3V6K DIS@ 1 2 CC96 PEG_HTX_GRX_P10 A21 AP13
<32> PEG_HTX_C_GRX_P10 PETP5_L3 USB2P7
<23> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11
C PERN3 C
<23> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 F11 G20 USB3_RX0_N <24>
PERP3 USB3RN0 H20
10/100/1G LAN CC12 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3RP0 USB3_RX0_P <24>
<23> PCIE_PTX_C_DRX_N3
CC13 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3 PCIe USB C33
USB2.0/USB3.0
<23> PCIE_PTX_C_DRX_P3 PETP3 USB3TN0 USB3_TX0_N <24>
B34
USB3TP0 USB3_TX0_P <24>
F13
G13 PERN4 E18
PERP4 USB3RN1 F18
B29 USB3RP1
A29 PETN4 B33
PETP4 USB3TN1 A33
G17 USB3TP1
F17 PERN1/USB3RN2 L DG V0.9 USBRBIAS
PERP1/USB3RP2 Trace width=50ohm and spacing=15mil
C30
C31 PETN1/USB3TN2 AJ10 USBRBIAS RC148 1 2
Max length=500mil
22.6_0402_1%
PETP1/USB3TP2 USBRBIAS AJ11
PCIE_PRX_DTX_N2 F15 USBRBIAS AN10
<23> PCIE_PRX_DTX_N2 PERN2/USB3RN3 TP13
<23> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 G15 AM10
PERP2/USB3RP3 TP14
PCI-E Card reader CC16 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N2 B31
<23> PCIE_PTX_C_DRX_N2 PETN2/USB3TN3
<23> PCIE_PTX_C_DRX_P2 CC17 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P2 A31
PETP2/USB3TP3 AL3 USB_OC0#
OC0/GPIO40 USB_OC0# <24,9>
B AT1 USB_OC1# B
OC1/GPIO41 USB_OC1# <24>
AH2 USB_OC2#
OC2/GPIO42 USB_OC2# <9>
RC151 E15 AV3 USB1_PWR_EN
3K_0402_1% E13 TP3 OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 TP4 +3V_PCH
<Page12> +1.05VS_VCCUSB3PLL
B27 PCIE_RCOMP
PCIE_IREF RPH17
4 5
DG V0.9 PCIE_RCOMP USB_OC1# 3 6
L Width=12mil,spacing=12mil
11 OF 19 <21,9> WL_OFF# WL_OFF#
USB1_PWR_EN
2
1
7
8
Max length=500mil 10K_0804_8P4R_5%

<PV>PRH11 change to RPH17.

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE,USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-A992P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 10 of 54
5 4 3 2 1
5 4 3 2 1

+VCC_CORE@10000mA
+VCC_CORE
HASWELL_MCP_E
UCPU1L

+1.35V_VDDQ L59 C36


J58 RSVD VCC C40
RSVD VCC C44
+VCC_CORE 2500mA AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
D D
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
AY44 VDDQ VCC E35
AY50 VDDQ VCC E37
+1.05VS_VCCST VDDQ VCC E39
DG V0.5 H_CPU_SVIDALRT#
SVID ALERT L RC154 close to CPU<300mil VCC_SENSE
F59
N58 VCCIN
RSVD
VCC
VCC
VCC
E41
E43
PH on power page AC58 E45
Max length=1000~2000mil RSVD VCC

1
E47
RC154 VCCSENSE E63 VCC E49
<PWR VR12.6> <50> VCCSENSE
AB23 VCC_SENSE VCC E51
75_0402_5% A59 RSVD VCC E53
+VCCIO_OUT VCCIO_OUT VCC
<VR IV and CPU> +VCCIOA_OUT E20 E55

2
AD23 VCCIOA_OUT VCC E57
<EDP_COMP power rail> RSVD VCC
RC155 1 2 H_CPU_SVIDALRT# AA23 F24
<50> VR_SVID_ALRT# RSVD VCC
<PWR VR12.6> 43_0402_1% AE59 F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
VR_SVID_CLK N63 VIDALERT VCC F40
+1.05VS_VCCST <50> VR_SVID_CLK VIDSCLK VCC
VR_SVID_DAT L63 F44
B59 VIDSOUT VCC F48
SVID DATA <4,6> +1.05VS_PG
<50> VR12.5_VR_ON F60 VCCST_PWRGD
VR_EN
VCC
VCC
F52
1

VR12.6PG_MCP C59 F56


RC156 VR_READY HSW ULT POWER VCC G23
D63 VCC G25
110_0402_1% VSS VCC
CPU_PWR_DEBUG H59 G27
P62 PWR_DEBUG VCC G29
<PWR VR12.6>
2

P60 VSS VCC G31


P61 RSVD_TP VCC G33
C
VR_SVID_DAT N59 RSVD_TP VCC G35 C
<50> VR_SVID_DAT RSVD_TP VCC
N61 G37
T59 RSVD_TP VCC G39
AD60 VSS VCC G41
AD59 VSS VCC G43
AA59 VSS VCC G45
AE60 VSS VCC G47
AC59 VSS VCC G49
AG58 VSS VCC G51
+VCCIO_OUT +1.05VS_VCCST U59 VSS VCC G53
@ V59 VSS VCC G55
<CPU> RC294 1 2 0_0402_5% +VCC_CORE VSS VCC G57
+1.05VS 600mA AC22 VCC H23
AE22 VCCST VCC J23
AE23 VCCST VCC K23
VCCST VCC K57
AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
L DG V0.5 VIDSOUT VCC VCC
RC156 close to CPU<500mil 12 OF 19
Max length=1000~2000mil

+1.05VS_VCCST
+1.05VS_VCCST

1
B +3V_PCH B
150_0402_5%

RC288
1

+1.05VS +1.05VS_VCCST UC8 10K_0402_5%


RC166

1 5
NC VCC

2
short@ 2
<50> VGATE A
RC223 1 2 4 VR12.6PG_MCP
2

3 Y
1U_0402_6.3V6K

CPU_PWR_DEBUG 0_0805_5% GND


22U_0805_6.3V6M
CC71

1 1 74AUP1G07GW_TSSOP5
10K_0402_5%

CC72
1

@
@

2 2
RC167
2

+1.35V_VDDQ +1.35V_VDDQ
2.2U_0402_6.3V6M
CC20

2.2U_0402_6.3V6M
CC21

2.2U_0402_6.3V6M
CC22

2.2U_0402_6.3V6M
CC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1
1 1 1 1 1 1 @ 1 1 @ 1 1 @
CC24 + CC25 +

CC26

CC27

CC28

CC29

CC30

CC31
@
330U_2.5V_M 330U_2.5V_M
2 2 2 2 2 2 2 2 2 2 2 2

@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 11 of 54
5 4 3 2 1
5 4 3 2 1

+1.05VS_VCCUSB3PLL short@
RC168 1 2
1.838A +1.05VS_VCCHSIO short@

1U_0402_6.3V6K
RC170
+1.05VS_MODPHY 65mA +3V_DSW_PRTCSUS RC169 2 1 0_0402_5%
1 +3V_PCH
1 2 +1.05VS_VCCUSB3PLL 0_0805_5%

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.05VS_MODPHY 1 1

CC32
47U_0805_6.3V6M
41mA

CC33

CC34
2.2UH_LQM2MPN2R2NG0L_30%

1U_0402_6.3V6K
2
1 1 2 2

CC35

CC36
+RTCVCC +RTCVCC
HASWELL_MCP_E
UCPU1M
D 2 2 D

0.1U_0402_16V7K
CC37
K9

1U_0402_6.3V6K
VCCHSIO 1 1
L10
VCCHSIO

CC39
M9
N8 VCCHSIO mPHY RTC AH11 @
+1.05VS_VCCSATA3PLL +1.05VS VCCIO VCCSUS3 2 2
P9 AG10

1U_0402_6.3V6K
1 VCCIO VCCRTC
+1.05VS_VCCUSB3PLL B18 AE7 CC40 1 2 0.1U_0402_16V7K
VCCUSB3PLL DCPRTC

CC41
RC171 +1.05VS_VCCSATA3PLL B11
1 2 +1.05VS_VCCSATA3PLL VCCSATA3PLL
+1.05VS_MODPHY 2

47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
42mA RC173 Y20 SPI Y8
18mA

1U_0402_6.3V6K
0_0402_5% 1 @ 2 +1.05VS_APPLOPI AA21 VCCAPLL OPI VCCSPI +3V_PCH SPI ROM power rail
1 CC42 1 Use +1.05V +1.05V
W21 VCCAPLL 1
VCCAPLL

CC43
AG14 +1.05VS CC44 @
2 1 VCCASW AG13
USB3 VCCASW 0.1U_0402_16V7K
2 2 10U_0603_6.3V6M CC45 2
2 1 J13

10U_0603_6.3V6M
+1.05V_DCPSUS

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K CC46 DCPSUS3 J11
1.6A
VCC1P05 +1.05VS
H11 1 1 1
AXALIA/HDA CORE VCC1P05

CC48

CC49

CC50
+VCCSUSHDA AH14 H15
VCCSUSHDA VCC1P05 AE8 RC174 CC52

1U_0402_6.3V6K
1 VCC1P05
short@ AF22 5.11_0402_1% 1U_0402_6.3V6K
VRM/USB2/AZALIA VCC1P05 2 2 2

CC51
<DB>Aduio code power rail +1.5VS RC172 1 2 0_0402_5% AH13 AG19 2 1 1 2
DCPSUS2 DCPSUSBYP AG20 short@
C 2 DCPSUSBYP AE9 +1.05VS_VCCASW
0.658A RC175 1 2
C

1U_0402_6.3V6K
VCCASW +1.05VS
RC176 AF9
VCCASW

CC54
1 2 AC9 AG8

22U_0805_6.3V6M
+1.05VS +1.05VS_APPLOPI +3V_PCH 1 1 0_0805_5%
VCCSUS3_3 VCCASW

CC53
22U_0805_6.3V6M

57mA AA9 AD10 +1.05V_DCPSUS


VCCSUS3_3 DCPSUS1

CC55
22U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% +3V_DSW_P AH10 AD8
1U_0402_6.3V6K

1 VCCDSW3_3 DCPSUS1
V8 GPIO/LCC
1 1 VCC3_3 2 2
CC57

+3VS W9
VCC3_3
CC58

CC59
22U_0805_6.3V6M
1 J15 +1.5VS
2 THERMAL SENSOR VCCTS1_5 K14
2 2 VCC3_3 +3VS
K16
VCC3_3
2 ICC 1 2
+1.05VS_AXCKDCB J18 SDIO/PLSS CC76 0.1U_0402_16V7K
K19 VCC1P05 U8 +3V_1V8_SDIO
+1.05VS_AXCK_LCPLL A20 VCC1P05 VCCSDIO T9 RC178 short@

1U_0402_6.3V6K
1 RC280 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCACLKPLL VCCSDIO 1 2 0_0603_5%
+1.05VS VCCCLK 1 +3VS
62mA +V1.05S_SSCFF R21
VCCCLK LPT LP POWER

CC60
0_0603_5% T21
1U_0402_6.3V6K

K18 VCCCLK SUS OSCILLATOR AB8 +1.05V_AOSCSUS


1 VCCCLK DCPSUS4 2
M20
VCCCLK
CC61

V21
RC281 AE20 VCCCLK AC20
2 +3V_PCH VCCSUS3_3 VCCAPLL
+1.05VS 1 2 +V1.05S_SSCFF AE21 AG16
VCCSUS3_3 USB2 VCCIO AG17 @
1U_0402_6.3V6K

B
short@
124mA VCCIO +1.05VS
RC180
B

1U_0402_6.3V6K
1
0_0603_5% 1 +1.05V_AOSCSUS 1 2 +1.05V
CC62

CC65
13 OF 19 2.2UH_LQM2MPN2R2NG0L_30%

1U_0402_6.3V6K
2

100U_1206_6.3V6K
2 1 1

CC67
+3V_DSW_P

CC66
@
RC179
1 2 Deep S3 and Non Deep S3 2 2
47U_0805_6.3V6M

+1.05VS +1.05VS_AXCKDCB @
short@
2.2UH_LQM2MPN2R2NG0L_30% 1 RC285 1 2 0_0402_5%
1U_0402_6.3V6K

1 +3VALW Deep S3 RC285-->SMT Total 1.05VS=1838+2274=4111mA


CC63

CC64

+3V_PCH RC182 1 2 0_0402_5% +3V_DSW_P Non Deep S3 RC182-->SMT Total 1.5VS=3mA


2 2 1

1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
@ Total 1.8VS=7mA

CC70
RC181 2 Total 3VS=0mA
+1.05VS 1 2 +1.05VS_AXCK_LCPLL Total 3VALW=200+62=262mA
47U_0805_6.3V6M

2.2UH_LQM2MPN2R2NG0L_30%
31mA
1U_0402_6.3V6K

Total 3V_PCH=99mA
1 1
CC68

Total 1.05V=540+109=649mA
CC69

A A

2 2

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-A992P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 12 of 54
5 4 3 2 1
5 4 3 2 1

UCPU1NHASWELL_MCP_E

A11 AJ35 HASWELL_MCP_E


UCPU1O
A14 VSS VSS AJ39
A18 VSS VSS AJ41 AP22 AV59
A24 VSS VSS AJ43 AP23 VSS VSS AV8
A28 VSS VSS AJ45 AP26 VSS VSS AW16
A32 VSS VSS AJ47 AP29 VSS VSS AW24
A36 VSS VSS AJ50 AP3 VSS VSS AW33 UCPU1P HASWELL_MCP_E
D A40 VSS VSS AJ52 AP31 VSS VSS AW35 H17 D
A44 VSS VSS AJ54 AP38 VSS VSS AW37 D33 VSS H57
A48 VSS VSS AJ56 AP39 VSS VSS AW4 D34 VSS VSS J10
A52 VSS VSS AJ58 AP48 VSS VSS AW40 D35 VSS VSS J22
A56 VSS VSS AJ60 AP52 VSS VSS AW42 D37 VSS VSS J59
AA1 VSS VSS AJ63 AP54 VSS VSS AW44 D38 VSS VSS J63
AA58 VSS VSS AK23 AP57 VSS VSS AW47 D39 VSS VSS K1
AB10 VSS VSS AK3 AR11 VSS VSS AW50 D41 VSS VSS K12
AB20 VSS VSS AK52 AR15 VSS VSS AW51 D42 VSS VSS L13
AB22 VSS VSS AL10 AR17 VSS VSS AW59 D43 VSS VSS L15
AB7 VSS VSS AL13 AR23 VSS VSS AW60 D45 VSS VSS L17
AC61 VSS VSS AL17 AR31 VSS VSS AY11 D46 VSS VSS L18
AD21 VSS VSS AL20 AR33 VSS VSS AY16 D47 VSS VSS L20
AD3 VSS VSS AL22 AR39 VSS VSS AY18 D49 VSS VSS L58
AD63 VSS VSS AL23 AR43 VSS VSS AY22 D5 VSS VSS L61
AE10 VSS VSS AL26 AR49 VSS VSS AY24 D50 VSS VSS L7
AE5 VSS VSS AL29 AR5 VSS VSS AY26 D51 VSS VSS M22
AE58 VSS VSS AL31 AR52 VSS VSS AY30 D53 VSS VSS N10
AF11 VSS VSS AL33 AT13 VSS VSS AY33 D54 VSS VSS N3
AF12 VSS VSS AL36 AT35 VSS VSS AY4 D55 VSS VSS P59
AF14 VSS VSS AL39 AT37 VSS VSS AY51 D57 VSS VSS P63
AF15 VSS VSS AL40 AT40 VSS VSS AY53 D59 VSS VSS R10
AF17 VSS VSS AL45 AT42 VSS VSS AY57 D62 VSS VSS R22
AF18 VSS VSS AL46 AT43 VSS VSS AY59 D8 VSS VSS R8
C VSS VSS VSS VSS VSS VSS C
AG1 AL51 AT46 AY6 E11 T1
AG11 VSS VSS AL52 AT49 VSS VSS B20 E17 VSS VSS T58
AG21 VSS VSS AL54 AT61 VSS VSS B24 F20 VSS VSS U20
AG23 VSS VSS AL57 AT62 VSS VSS B26 F26 VSS VSS U22
AG60 VSS VSS AL60 AT63 VSS VSS B28 F30 VSS VSS U61
AG61 VSS VSS AL61 AU1 VSS VSS B32 F34 VSS VSS U9
AG62 VSS VSS AM1 AU16 VSS VSS B36 F38 VSS VSS V10
AG63 VSS VSS AM17 AU18 VSS VSS B4 F42 VSS VSS V3
AH17 VSS VSS AM23 AU20 VSS VSS B40 F46 VSS VSS V7
AH19 VSS VSS AM31 AU22 VSS VSS B44 F50 VSS VSS W20
AH20 VSS VSS AM52 AU24 VSS VSS B48 F54 VSS VSS W22
AH22 VSS VSS AN17 AU26 VSS VSS B52 F58 VSS VSS Y10
AH24 VSS VSS AN23 AU28 VSS VSS B56 F61 VSS VSS Y59
AH28 VSS VSS AN31 AU30 VSS VSS B60 G18 VSS VSS Y63
AH30 VSS VSS AN32 AU33 VSS VSS C11 G22 VSS VSS
AH32 VSS VSS AN35 AU51 VSS VSS C14 G3 VSS
AH34 VSS VSS AN36 AU53 VSS VSS C18 G5 VSS V58
AH36 VSS VSS AN39 AU55 VSS VSS C20 G6 VSS VSS AH46
AH38 VSS VSS AN40 AU57 VSS VSS C25 G8 VSS VSS V23
AH40 VSS VSS AN42 AU59 VSS VSS C27 H13 VSS VSS E62
AH42 VSS VSS AN43 AV14 VSS VSS C38 VSS VSS_SENSE AH16
VSSSENSE <50> <PWR VR12.6>
AH44 VSS VSS AN45 AV16 VSS VSS C39 16 OF 19 VSS
AH49 VSS VSS AN46 AV20 VSS VSS C57
AH51 VSS VSS AN48 AV24 VSS VSS D12
B B
AH53 VSS VSS AN49 AV28 VSS VSS D14
AH55 VSS VSS AN51 AV33 VSS VSS D18
AH57 VSS VSS AN52 AV34 VSS VSS D2
AJ13 VSS VSS AN60 AV36 VSS VSS D21
AJ14 VSS VSS AN63 AV39 VSS VSS D23
AJ23 VSS VSS AN7 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV43 VSS VSS D26
AJ27 VSS VSS AP17 AV46 VSS VSS D27
AJ29 VSS VSS AP20 AV49 VSS VSS D29
VSS VSS AV51 VSS VSS D30
AV55 VSS VSS D31
VSS 15 OF 19 VSS
14 OF 19

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/27 Deciphered Date 2011/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GND/VSSSEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 13 of 54
5 4 3 2 1
5 4 3 2 1

HASWELL_MCP_E
UCPU1Q CFG4

1
DC_TEST_AY2_AW2 AY2 A3 TP_DC_TEST_A3_B3
DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 RC185
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 1K_0402_1%
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60

2
DC_TEST_AY61_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62
TP_DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1
D DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 D
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 Display Port Presence Strap
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY61_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63
17 OF 19 DAISY_CHAIN_NCTF_AW63 1 : Disabled; No Physical Display Port        
CFG4 attached to  Embedded Display Port
0 : Enabled; An external Display Port device is          
UCPU1R HASWELL_MCP_E
* connected to the Embedded Display Port  
N23
RSVD R23
RSVD T23
AT2 RSVD U10
AU44 RSVD RSVD
AV44 RSVD
D15 RSVD AL1
RSVD RSVD AM11
RSVD AP7
F22 RSVD AU10
H22 RSVD RSVD AU15
J21 RSVD RSVD AW14
C RSVD TP2 C
AY14
TP1

18 OF 19

UCPU1S HASWELL_MCP_E

PAD @ T59 CFG0 AC60 AV63


PAD @ T60 CFG1 AC62 CFG0 RSVD_TP AU63
PAD @ T61 CFG2 AC63 CFG1 RSVD_TP
PAD @ T63 CFG3 AA63 CFG2
CFG4 AA60 CFG3 C63
PAD @ T64 CFG5 Y62 CFG4 RSVD_TP C62
PAD @ T65 CFG6 Y61 CFG5 RSVD_TP B43
PAD @ T66 CFG7 Y60 CFG6 EDP_SPARE
PAD @ T67 CFG8 V62 CFG7 A51
PAD @ T68 CFG9 V61 CFG8 RSVD_TP B51
PAD @ T69 CFG10 V60 CFG9 RSVD_TP
PAD @ T70 CFG11 U60 CFG10 L60
B B
PAD @ T71 CFG12 T63 CFG11 RSVD_TP
PAD @ T72 CFG13 T62 CFG12 N60
PAD @ T73 CFG14 T61 CFG13 RESERVED RSVD
PAD @ T74 CFG15 T60 CFG14 W23
CFG15 RSVD Y22 MCP_RSVD_29 RC296 2 @ 1 49.9_0402_1%
PAD @ T75 CFG16 AA62 RSVD AY15 PROC_OPI_COMP RC186 2 1 49.9_0402_1%
PAD @ T76 CFG18 U63 CFG16 OPI_COMP1 L DG V0.9 PROC_OPI_COMP
PAD @ T77 CFG17 AA61 CFG18 AV62 Width=12mil,spacing=12mil
PAD @ T78 CFG19 U62 CFG17 RSVD D58
CFG19 RSVD Max length=500mil
2 1 CFG_RCOMP V63 P22
RC188 49.9_0402_1% CFG_RCOMP VSS N21
A5 VSS
RSVD P20
E1 HVM_CLK R20
D1 TP9 HVM_CLK_P
J20 TP10
H18 TP11
1 2 TD_IREF B12 TP12
RC191 8.2K_0402_5% TD_IREF
19 OF 19

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSVD/CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 14 of 54
5 4 3 2 1
5 4 3 2 1

+V_VDDR_REFA_DQ +1.35V_VDDQ +1.35V_VDDQ

JDIMM1
+V_VDDR_REFA_DQ 1 2
D
3 VREF_DQ VSS1 4 DDR_A_D9 D
VSS2 DQ4

0.1U_0402_16V7K
DDR_A_D13 5 6 DDR_A_D12
<5> DDR_A_D[0..63] DQ0 DQ5

CD1
1 DDR_A_D8 7 8
9 DQ1 VSS3 10 DDR_A_DQS#1
<5> DDR_A_DQS[0..7] VSS4 DQS#0
11 12 DDR_A_DQS1
13 DM0 DQS0 14
<5> DDR_A_DQS#[0..7] 2 VSS5 VSS6
DDR_A_D14 15 16 DDR_A_D15
DDR_A_D10 17 DQ2 DQ6 18 DDR_A_D11
<5> DDR_A_MA[0..15] DQ3 DQ7
19 20
DDR_A_D29 21 VSS7 VSS8 22 DDR_A_D25
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
25 DQ9 DQ13 26
DDR_A_DQS#3 27 VSS9 VSS10 28
DDR_A_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <16,4>
31 32 1
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 @ESD@
DDR_A_D31 35 DQ10 DQ14 36 DDR_A_D26 CD99 +1.35V_VDDQ
37 DQ11 DQ15 38
VSS13 VSS14 0.1U_0402_16V7K
DDR_A_D44 39 40 DDR_A_D45 2
DDR_A_D41 41 DQ16 DQ20 42 DDR_A_D40
43 DQ17 DQ21 44 +5VALW QD1
DDR_A_DQS#5 45 VSS15 VSS16 46 BSS138_NL_SOT23-3
DDR_A_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D42 1 3 RD20 1 2 66.5_0402_1% M_ODT0

S
VSS18 DQ22

1
DDR_A_D43 51 52 DDR_A_D46
DDR_A_D47 53 DQ18 DQ23 54 RD21 RD22 1 2 66.5_0402_1% M_ODT1
55 DQ19 VSS19 56 DDR_A_D52

G
2
DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53 220K_0402_5% RD23 1 2 66.5_0402_1% M_ODT2
DQ24 DQ29 M_ODT2 <16>
DDR_A_D50 59 60

2
61 DQ25 VSS21 62 DDR_A_DQS#6 RD24 1 2 66.5_0402_1% M_ODT3
VSS22 DQS#3 M_ODT3 <16>
63 64 DDR_A_DQS6
65 DM3 DQS3 66
VSS23 VSS24

1
DDR_A_D49 67 68 DDR_A_D54 @
DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55 RD25 SM_PG_CTRL
DQ27 DQ31 SM_PG_CTRL <4>
71 72
VSS25 VSS26 2M_0402_5%

2
C C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<5> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <5>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<5> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<5> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <5>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<5> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <5>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <5>
<5> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# <5>
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
<5> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +V_VDDR_REFA_CA
DDR_CS1_DIMMA# 121 A13 ODT1 122
<5> DDR_CS1_DIMMA# S1# NC2
123 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 NCTEST VREF_CA 128
VSS27 VSS28

0.1U_0402_16V7K
DDR_A_D0 129 130 DDR_A_D5
DDR_A_D1 131 DQ32 DQ36 132 DDR_A_D4
DQ33 DQ37

CD3
133 134 1
DDR_A_DQS#0 135 VSS29 VSS30 136
DDR_A_DQS0 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_A_D3
DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 2
DDR_A_D6 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D18
B
DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19 B
DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
153 VSS36 DQS#5 154 DDR_A_DQS2
155 DM5 DQS5 156
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
161 DQ43 DQ47 162
+1.35V_VDDQ DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
DDR_A_DQS#4 169 VSS41 VSS42 170
DQS#6 DM6
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_A_DQS4 171 172


DQS6 VSS43
CD6

CD7

CD8

CD9

CD10

CD11

CD12

CD13

1 1 1 1 1 1 1 1 173 174 DDR_A_D35


DDR_A_D34 175 VSS44 DQ54 176 DDR_A_D39
@ @ DDR_A_D38 177 DQ50 DQ55 178
@ @ 179 DQ51 VSS45 180 DDR_A_D63
2 2 2 2 2 2 2 2 DDR_A_D62 181 VSS46 DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56 +0.6V_0.675VS
+1.35V_VDDQ DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
195 DQ59 DQ63 196
197 VSS51 VSS52 198
SA0 EVENT#
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

199 200 PCH_SMBDATA


+3VS VDDSPD SDA PCH_SMBDATA <16,7>
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CD24

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 201 202 PCH_SMBCLK
SA1 SCL PCH_SMBCLK <16,7>
CD17

CD19

CD21
1 203 204 1 1 1
VTT1 VTT2 +0.6V_0.675VS
CD55

CD56

CD57

CD58

CD63

CD64

CD65

CD66

205 206
2 2 @ 2 @ 2 @ 2 2 2 2 G1 G2
2 FOX_AS0A626-U4R6-7H 2 2 2

CONN@

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 15 of 54
5 4 3 2 1
5 4 3 2 1

+V_VDDR_REFB_DQ +1.35V_VDDQ +1.35V_VDDQ

JDIMM2
+V_VDDR_REFB_DQ 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
VSS2 DQ4

0.1U_0402_16V7K
DDR_B_D8 5 6 DDR_B_D9
<5> DDR_B_D[0..63] DQ0 DQ5

CD27
1 DDR_B_D14 7 8
9 DQ1 VSS3 10 DDR_B_DQS#1
<5> DDR_B_DQS[0..7] VSS4 DQS#0
11 12 DDR_B_DQS1
D
13 DM0 DQS0 14 D
<5> DDR_B_DQS#[0..7] 2 VSS5 VSS6
DDR_B_D10 15 16 DDR_B_D13
DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D15
<5> DDR_B_MA[0..15] DQ3 DQ7
19 20
DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
DDR_B_D29 23 DQ8 DQ12 24 DDR_B_D24
25 DQ9 DQ13 26
DDR_B_DQS#3 27 VSS9 VSS10 28
DDR_B_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <15,4>
31 32
DDR_B_D26 33 VSS11 VSS12 34 DDR_B_D30
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DDR_B_D41 41 DQ16 DQ20 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS15 VSS16 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D61
DDR_B_D56 57 VSS20 DQ28 58 DDR_B_D60
DDR_B_D57 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#7
63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
71 DQ27 DQ31 72
VSS25 VSS26

DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<5> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <5>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<5> DDR_B_BS2 BA2 A14
C 81 82 C
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<5> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <5>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<5> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <5>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <5>
<5> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# <5>
111 BA0 RAS# 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMB#
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
<5> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <15>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +V_VDDR_REFA_CA
A13 ODT1 M_ODT3 <15>
DDR_CS1_DIMMB# 121 122
<5> DDR_CS1_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 NCTEST VREF_CA 128
VSS27 VSS28

0.1U_0402_16V7K
DDR_B_D4 129 130 DDR_B_D5
DDR_B_D1 131 DQ32 DQ36 132 DDR_B_D0
DQ33 DQ37

CD29
133 134 1
DDR_B_DQS#0 135 VSS29 VSS30 136
DDR_B_DQS0 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_B_D2
DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D16
DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
153 VSS36 DQS#5 154 DDR_B_DQS2
155 DM5 DQS5 156
B
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19 B
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
DDR_B_DQS#4 169 VSS41 VSS42 170
DDR_B_DQS4 171 DQS#6 DM6 172
+1.35V_VDDQ 173 DQS6 VSS43 174 DDR_B_D34
DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38
DDR_B_D39 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D51
VSS46 DQ60
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_D52 181 182 DDR_B_D55


DQ56 DQ61
CD33

CD34

CD35

CD36

CD37

CD38

CD39

CD40

1 1 1 1 1 1 1 1 DDR_B_D49 183 184


185 DQ57 VSS47 186 DDR_B_DQS#6
187 VSS48 DQS#7 188 DDR_B_DQS6
@ @ @ @ 189 DM7 DQS7 190
2 2 2 2 2 2 2 2 DDR_B_D48 191 VSS49 VSS50 192 DDR_B_D54
DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50 +0.6V_0.675VS
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <15,7>
0.1U_0402_16V7K

201 202 PCH_SMBCLK


SA1 SCL PCH_SMBCLK <15,7>
CD44

0.1U_0402_16V7K

0.1U_0402_16V7K

CD50

10U_0603_6.3V6M
1 203 204
VTT1 VTT2 +0.6V_0.675VS
1
10K_0402_5%
RD4

CD45

CD46
1 1 1
205 206
G1 G2
+1.35V_VDDQ 2 +3VS FOX_AS0A626-U4R6-7H
2 2 2
2

CONN@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1
CD59

CD60

CD61

CD62

CD67

CD68

CD69

CD70

2 2 2 2 2 @ 2 @ 2 2
@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/27 Deciphered Date 2011/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 16 of 54
5 4 3 2 1
5 4 3 2 1

+1.35V_VDDQ
DDR3L VREF +1.35V_VDDQ
D D

1
RD5 RD6
1.8K_0402_1% 1.8K_0402_1%
RD7 RD8

2
<CPU> +V_DDR_REFA_R 1 2 +V_VDDR_REFA_DQ <DDR3L_A> +V_SM_VREF_CNT 1 2 +V_VDDR_REFA_CA <DDR3L_A_CA>
1 <CPU> 1
CD52 2_0402_1% CD53 2_0402_1% <DDR3L_B_CA>

1
0.022U_0402_25V7K 0.022U_0402_25V7K
2 RD9 2 RD10

1
RD11 1.8K_0402_1% RD12 1.8K_0402_1%
@ @
24.9_0402_1% 24.9_0402_1%

2
2

2
@ @

+1.35V_VDDQ
C C

1
RD13
1.8K_0402_1%
RD15

<CPU> +V_DDR_REFB_R 1 2 2 +V_VDDR_REFB_DQ <DDR3L_B>


1
CD54 2_0402_1%
1

0.022U_0402_25V7K
2 RD17
1

RD19 1.8K_0402_1%
@
24.9_0402_1%
2
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L VREF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 17 of 54
5 4 3 2 1
5 4 3 2 1

+3VS
JPHW7 need to short +3VS_RT Layout note
Layout note Close to
80mil @ JPHW7 80mil
※ROM only  mode : PIN 30 4.7k pull low,  Pin 31 4.7k pull high.
1 2 Close to LT5 Close to Pin18 Close to Pin13 Close to Pin11  Pin27 Close to Pin7
1 2 EP mode               : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
JUMP_43X79 +SWR_VDD +SWR_V12
EEPROM               : PIN 30 4.7k pull high, Pin 31 4.7k pull high.

10U_0603_6.3V6M

0.1U_0402_16V4Z

22U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
Layout note 1 1 1 1 1 1 1 1 1
〈 ※Default mode 〉
Close to Pin3

CT7

CT8

CT9

CT10

CT11

CT12

CT13

CT14

CT15
+3VS_RT +3VS_RT
D +DP_V33 2 2 2 2 2 2 2 2 2 D
2132S@

2
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
@
1 1 1 LVDS@ RT2 RT3
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ 4.7K_0402_5% LVDS@ 4.7K_0402_5%
CT16

CT17

CT18

1
2 2 2 MIIC_SDA MIIC_SCL

+3VS_RT 2132S@

2
LVDS@ LVDS@ LVDS@ UT1 @
LVDS@ 19 LVDS_CLKP LVDS_CLKP <19> RT4 RT5
LT6 2 1 +DP_V33 TXEC+
40mil 3 DP_V33 TXEC-
20 LVDS_CLKN LVDS_CLKN <19> LVDS@ 4.7K_0402_5% 4.7K_0402_5%
FBMA-L11-201209-221LMA30T_0805
LVDS@ 100mil 13 21 LVDS_TXP2 PIN30 PIN31

1
SWR_VDD TXE2+

Power
80mil LT5 2 1 +SWR_VDD 40mil 18 22 LVDS_TXN2

LVDS
FBMA-L11-201209-221LMA30T_0805 PVCC TXE2-
+SWR_V12 2 1 +SWR_LX 40mil 12 23 LVDS_TXP1 <CONN>
SWR / LDO Mode select @ LT7 0_1206_5% 40mil 11
SWR_LX
SWR_VCCK
TXE1+
TXE1-
24 LVDS_TXN1
LVDS_TXP1 <19>
LVDS_TXN1 <19>
40mil 27 VCCK
40mil 7 DP_V12 TXE0+
25 LVDS_TXP0 LVDS_TXP0 <19>
LDO SWR 26 LVDS_TXN0 LVDS_TXN0 <19>
TXE0- +3VS_RT
<SI> LT7 change to 0 ohm short pad LVDS@
LCD_EDID_CLK RT6 1 2 4.7K_0402_5%
2132S Do not support mount LT7
        use LDO mode translator only RTD2132S LVDS@
EDP_CPU_AUX 2 LCD_EDID_DATA RT7 1 2 4.7K_0402_5%
AUX_P

DP-IN
EDP_CPU_AUX# 1 14 DP_INT_PWM
<CONN>

GPIO
AUX_N GPIO(PWM OUT) DP_INT_PWM <19>
15 +DP_ENVDD
GPIO(Panel_VCC) +DP_ENVDD <19>
2132R Use 0 ohm mount LT7 EDP_CPU_LANE_P0 5 16 BKL_PWM_CPU
EDP_CPU_LANE_N0 6 LANE0P GPIO(PWM IN) 17 TS_BKOFF#
BKL_PWM_CPU <4,8> <CPU> PIN15 PIN16 Accept voltage input (high level)
LANE0N GPIO(BL_EN)
C C

※ If use 2132R, please select LDO mode as default. <30,32,7> EC_SMB_CK2


9
CIICSCL1 LVDS MIICSCL1
29 LCD_EDID_CLK 2132S TL_ENVDD 2132S 3.3V
10 28 LCD_EDID_DATA
<CPU CTRL> <30,32,7> EC_SMB_DA2 CIICSDA1 EDID MIICDA1

Other
LVDS@ 2132R +LCD_VDD * 2132R 1.5~3.3V
EDP_HPD 1 2 RT192 32 ROM 31 MIIC_SCL
<8> EDP_HPD HPD MIICSCL0
1K_0402_1% 30 MIIC_SDA
MIICSDA0
1

8 * Version R internal Power Switch, can * Version R has internal level shifter, remove
RT11 4 DP_REXT 33
DP_GND GND output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform

2
100K_0402_5%

RT8 LVDS@ RTD2132R-CG QFN32


2

12K_0402_1% SA000069200
LVDS@
Different between 2132S and 2132R
1

2132S 2132R
Layout note
+LCDVDD 1. Support SWR mode 1. Support LDO mode and SWR mode
Close to Pin8 2. Internal ROM
+DP_ENVDD 1 2
80ml trace width RT9 0_0805_5% 3. Support LCD_VDD(internal Power switch)
LVDS@
4. Integrates Level shifter

1
2
Close to Pin15 RT10
CT23 100K_0402_5%
CC102 1 2 .1U_0402_16V7K EDP_CPU_AUX 4.7U_0603_6.3V6K
<CPU> <4> EDP_CPU_AUX_C
LVDS@ 1
LVDS@

2
CC101 1 2 .1U_0402_16V7K EDP_CPU_AUX#
<4> EDP_CPU_AUX#_C
B CC98 1 2 .1U_0402_16V7K EDP_CPU_LANE_P0 B
<4> EDP_CPU_LANE_P0_C
Close to Panel conn. <CPU by PASS eDP>
CC97 1 2 .1U_0402_16V7K EDP_CPU_LANE_N0 <eDP to connector>
<4> EDP_CPU_LANE_N0_C

0_0804_8P4R_5% RP9
eDP@ SD309000080
EDP_CPU_LANE_N0 1 8 EDP_LANE_N0 EDP_AUX 4 5 LCD_CLK
LCD_CLK <19>
EDP_CPU_LANE_P0 2 7 EDP_LANE_P0 EDP_AUX# 3 6 LCD_DATA
LCD_DATA <19>
EDP_CPU_AUX 3 6 EDP_AUX EDP_LANE_N0 2 7 LVDS_TXN2_LN0
LVDS_TXN2_LN0 <19>
EDP_CPU_AUX# 4 5 EDP_AUX# EDP_LANE_P0 1 8 LVDS_TXP2_LP0
10/9 colay eDP use close Connector LVDS_TXP2_LP0 <19>
eDP@ SD309000080
RP6 0_0804_8P4R_5%

2 4

EDP_HPD RT34 1 eDP@ 2 0_0201_5% EDP_HPD_PANEL


EDP_HPD_PANEL <19>
@ BKL_PWM_CPU RT35 1 eDP@ 2 0_0201_5% DP_INT_PWM
RT14 1 2 0_0402_5%
CT24
@ <LVDS to connector>
<PV>Change PR37 pin define , Add PR38.
1 2
+3VS <PV>PR36 Change to RP6.
<SI> Update UT3 footprint (As UV11) 0_0804_8P4R_5%
0.1U_0402_16V7K LCD_EDID_CLK 1 8           PR37 change to RP9.
LCD_CLK
5

UT3 LCD_EDID_DATA 2 7 LCD_DATA


<RTS2132> TS_BKOFF# 1 LVDS_TXN2 3 6           PR38 change to RP10.
LVDS_TXN2_LN0
P

B 4 LVDS_TXP2 4 5 LVDS_TXP2_LP0
EC_BKOFF# 2 Y EC_TS_BKOFF# <19> <LVDS Panel>
<EC CTRL> <30> EC_BKOFF# A
G

A LVDS@ SD309000080 A
RP10
TC7SH08FUF_SSOP5
3
1

LVDS@
RT12 PD 100K on LVDS page
100K_0402_5%
LVDS@
<PV> Add RT12
2

Security Classification Compal Secret Data Compal Electronics, Inc.


eDP@ 2013/3/1 2015/3/1 Title
RT15 1 2 0_0402_5%
Issued Date Deciphered Date
LVDS Translator-RTD2132R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 18 of 54
5 4 3 2 1
5 4 3 2 1

LVDS Power 2132S@ +3VALW


+3VS eDP@
W=60mils W=60mils
UG1 INVPWR_B+ B+
Touch Screen Power

1
5 1 +LCDVDD eDP@ @EMI@
IN OUT RTS2 0_0805_5% 2 1 L1
0_0201_5% 2 2132S@ 2132S@ 100K_0402_5%
GND

0.1U_0402_16V7K
@EMI@ 0_0805_5%

2
CG3
RG1 1 eDP@ 2 4 3 1 eDP@ 1 @ 2 1 L2
SS EN CG2
1

1
eDP@ 1 1

1
CG1 APL3512_SOT23-5 4.7U_0603_6.3V6K RTS1 eDP@ D @EMI@ C117 C118
D 2132S@ 2 2
SM010014520 3000ma D
eDP@ 1K_0402_5% QTS1 2 680P_0402_50V7K 68P_0402_50V8J
1500P_0402_50V7K 2 G
TOUCH_ON# <30> 220ohm@100mhz
2N7002K_SOT23
CTS2 S 2 2 DCR 0.04

3
1 2
+VCC_TOUCH eDP@

2
0.047U_0402_16V7K

G
RG3 1 @ 2 0_0402_5%
<18> +DP_ENVDD
1 3 +3VS

S
R172 1 2 0_0402_5%
<PV>Change Touch power to 3V
<8> ENVDD_CPU 1 eDP@
CTS1 eDP@
eDP@ 0.1U_0402_16V4Z QTS2
S TR LP2301ALT1G 1P SOT-23-3
2
<PV>Change BOM structure

Camera @
R170 1 2 0_0402_5%

L12 EMI@
D5
1 2 USB20_N4_R
<10> USB20_N4 1 2 USB20_P4_R 2 C121 2 1 220P_0402_50V7K INVTPWM
Part Number = SM070003Y00 1
4 3 USB20_P4_R USB20_N4_R 3 C122 2 1 220P_0402_50V7K DISPOFF#
<10> USB20_P4 4 3
C C
WCM-2012-900T_4P
PESD5V0U2BT_SOT23-3
1 R171 2 0_0402_5% @ESD@ SCA00000U10

R2591 @ 2 INVTPWM @
<30> EC_INVT_PWM
0_0402_5%
<PV>L12 change PN.
LCD/LED PANEL Conn.
+LCDVDD
1

<18> DP_INT_PWM R258 1 @ 2 0_0402_5% @


R163 CONN@
10K_0402_5% JLVDS1
1
2 1 41
D3
2

LCD_CLK 3 2 G1 42
<18> LCD_CLK 3 G2
D_MIC_L_CLK 2 LCD_DATA 4 43
<18> LCD_DATA 4 G3
1 5 44
D_MIC_L_DATA 3 6 5 G4 45
<18> LVDS_TXP0 6 G5
7 46
<18> LVDS_TXN0 7 G6
8
PESD5V0U2BT_SOT23-3 9 8
<18> LVDS_TXP1 9
@ESD@ SCA00000U10 10
<18> LVDS_TXN1 10
R166 33_0402_5% <DB>LA1/LA2 closed to Aduio codec 11
EC_TS_BKOFF# 1 2 DISPOFF# 12 11
<18> EC_TS_BKOFF# <18> LVDS_TXP2_LP0 12
EMI@ 13
<18> LVDS_TXN2_LN0 13
LA1 FBMA-L10-160808-301LMT_2P 14
14
1

B D_MIC_CLK 1 2 D_MIC_L_CLK 15 B
<25> D_MIC_CLK <18> LVDS_CLKP 15
R167 D_MIC_DATA 1 @ 2 D_MIC_L_DATA 16
<25> D_MIC_DATA <18> LVDS_CLKN 16
10K_0402_5% LA2 0_0603_5% 17
<PV>LA1,LA2 change PN, LA2 change to 0ohm. USB20_N4_R 18 17
<MV>LA2 change to short pad. USB20_P4_R 19 18
2

20 19
USB20_P5_R 21 20
USB20_N5_R 22 21
TS_GPIO_CPU R2601 @ 2 TS_GPIO DISPOFF# 23 22
<9> TS_GPIO_CPU 23
0_0402_5% INVTPWM 24
TS_GPIO_EC R2611 @ 2 TS_GPIO 25 24
<30> TS_GPIO_EC 25
0_0402_5% 26
27 26
INVPWR_B+ 27
28
29 28
30 29
+VCC_TOUCH 30
<PV>L13 change PN,BS. 31
32 31
<PV>Remove R168,R169. Touch Screen @
+3VS
33 32
33
R173 1 2 0_0402_5% 34
D_MIC_L_CLK 35 34
L13 eDPEMI@ D_MIC_L_DATA 36 35
D6 36
1 2 USB20_P5_R 37
<10> USB20_P5 1 2 37
USB20_P5_R 2 38
<18> EDP_HPD_PANEL 38
1 Part Number = SM070003Y00 39
USB20_N5_R 3 4 3 USB20_N5_R 40 39
<10> USB20_N5 4 3 40
A WCM-2012-900T_4P STARC_107K40-000001-G2 A
PESD5V0U2BT_SOT23-3
@ESD@ SCA00000U10 1 R174 2 0_0402_5% <PV>JLVDS1 pin40 change to NC.
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-A992P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 19 of 54
5 4 3 2 1
5 4 3 2 1

+3VS
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C
<4> PCH_DPB_P0
PCH_DPB_N0 0.1U_0402_16V7K 1 2 CG28 PCH_DPB_N0_C
<4> PCH_DPB_N0
PCH_DPB_P1 0.1U_0402_16V7K 1 2 CG29 PCH_DPB_P1_C
<4> PCH_DPB_P1
PCH_DPB_N1 0.1U_0402_16V7K 1 2 CG30 PCH_DPB_N1_C
<CPU> <4> PCH_DPB_N1

1
RG47
PCH_DPB_P2 0.1U_0402_16V7K 1 2 CG31 PCH_DPB_P2_C
<4> PCH_DPB_P2
PCH_DPB_N2 0.1U_0402_16V7K 1 2 CG32 PCH_DPB_N2_C 1M_0402_5%
<4> PCH_DPB_N2

2
PCH_DPB_P3 0.1U_0402_16V7K 1 2 CG33 PCH_DPB_P3_C
<4> PCH_DPB_P3

2
D PCH_DPB_N3 0.1U_0402_16V7K 1 2 CG34 PCH_DPB_N3_C D
<4> PCH_DPB_N3
1 6 HP_DETECT
<8> PCH_DDPB_HPD

20K_0402_5%
QG1A 1

5
6
7
8

5
6
7
8

1
2N7002KDW_SOT363-6 CM17 @
5V Level RG56 220P_0402_50V7K
2N7002KDW_SOT363-6 2
QG1B

4
3
2
1

4
3
2
1
3 4

2
RP3 RP4
470_0804_8P4R_5% 470_0804_8P4R_5%

5
+3VS

+3VS

@
PCH_DPB_P3_C RG59 1 2 0_0402_5% HDMI_R_CK+

4 3
C
4 3 C

5
EMI@ CMMI21T-900Y-N
SM070003K00 LM13 1 2 QG2B
1 2 PCH_DDPB_CLK 4 3 HDMI_SCLK
<8> PCH_DDPB_CLK
PCH_DPB_N3_C RG60 1 2 0_0402_5% HDMI_R_CK-
@ 2N7002DWH_SOT363-6
SB00000DH00
@ +3VS
PCH_DPB_N0_C RG61 1 2 0_0402_5% HDMI_R_D0-

1 2
EMI@ LM14 1 2

2
SM070003K00 CMMI21T-900Y-N
4 3
4 3 PCH_DDPB_DAT 1 6 HDMI_SDATA
<8> PCH_DDPB_DAT
PCH_DPB_P0_C RG63 1 2 0_0402_5% HDMI_R_D0+
@ 2N7002DWH_SOT363-6
+HDMI_5V_OUT SB00000DH00 QG2A
PCH_DPB_P1_C RG64 1 @ 2 0_0402_5% HDMI_R_D1+

4 3 +3VS
4 3 RG105
EMI@ CMMI21T-900Y-N 1 8 HDMI_SDATA
SM070003K00 LM15 1 2 2 7 HDMI_SCLK
1 2 3 6 PCH_DDPB_DAT
PCH_DPB_N1_C RG65 1 2 0_0402_5% HDMI_R_D1- 4 5 PCH_DDPB_CLK
@
2.2K_0804_8P4R_5%
PCH_DPB_P2_C RG66 1 @ 2 0_0402_5% HDMI_R_D2+
B B
4 3
4 3
EMI@ CMMI21T-900Y-N HDMI Conn.
SM070003K00 LM16 1 2
1 2
PCH_DPB_N2_C RG70 1 2 0_0402_5% HDMI_R_D2-
@ JHDMI1
HP_DETECT 19
SC300002800 18 HP_DET
+HDMI_5V_OUT +5V
@ESD@ DG1 17
HP_DETECT 1 1 109 HP_DETECT HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
HDMI_SDATA 2 2 98 HDMI_SDATA 14 SCL
W=40mils 13 Reserved
FG1 +HDMI_5V_OUT CEC
HDMI_SCLK 4 4 77 HDMI_SCLK HDMI_R_CK- 12 20
@ @ 11 CK- GND 21
CK_shield GND

10P_0402_50V8J

10P_0402_50V8J
3 5 5 66 1 1 HDMI_R_CK+ 10 22
OUT CM26 CM27 HDMI_R_D0- 9 CK+ GND 23
1 3 3 8 D0- GND
+5VS IN D0_shield
1 HDMI_R_D0+ 7
2 8 2 2 HDMI_R_D1- 6 D0+
GND 5 D1-
CG46 IP4292CZ10-TB HDMI_R_D1+ 4 D1_shield
0.1U_0402_16V7K 2 HDMI_R_D2- 3 D1+
AP2330W-7_SC59-3 2 D2-
HDMI_R_D2+ 1 D2_shield
D2+
CONCR_099AKAC19NBLCNF
A A
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn/Level shift
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 20 of 54
5 4 3 2 1
5 4 3 2 1

+3VS_WLAN

1
D +3VS_WLAN RN3 +1.5VS_WLAN +3VS_WLAN D
<41> MC_WAKE#
10K_0402_5%
short@ 0_0201_5% JMINI1

2
<30> EC_PCIE_WAKE# RN13 1 2 1 2
3 1 2 4
BT_ON_EC 5 3 4 6
7 5 6 8
<7> MINI1_CLKREQ# 7 8
9 10
11 9 10 12
<7> CLK_PCIE_MINI1# 11 12
13 14
<7> CLK_PCIE_MINI1 13 14
15 16
17 15 16 18
19 17 18 20 WL_OFF#
19 20 WL_OFF# <10,9>
21 22 PLT_RST# <23,28,30,32,8>
23 21 22 24
<6> PCIE_PRX_DTX_N6 23 24 +3VS_WLAN
25 26
<6> PCIE_PRX_DTX_P6 25 26
27 28
29 27 28 30
31 29 30 32
<6> PCIE_PTX_C_DRX_N6 31 32
<6> PCIE_PTX_C_DRX_P6 33 34
35 33 34 36
35 36 USB20_N3 <10>
37 38
37 38 USB20_P3 <10>
39 40
C 39 40 C
41 42
43 41 42 44
43 44 MINI1_LED# <30>
45 46
47 45 46 48
E51TXD_P80DATA 49 47 48 50
<30> E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52
<30> E51RXD_P80CLK 51 52
53 54
GND1 GND2

1
2
RN7
R216 BELLW_80053-1021 4.7K_0402_5%
100K_0402_5% CONN@
<30> BT_ON_EC BT_ON_EC 1 RC160 2 E51RXD_P80CLK

2
1K_0402_1%

1
+3VS_WLAN

+1.5VS +1.5VS_WLAN

B RN1 @ B
1 2 <PV>Change WLAN power to single load switch.
1
0_0603_5% CN1 +5VALW +3VALW
Q23
4.7U_0603_6.3V6K
2 1 7
VIN VOUT +3VS_WLAN_R
@ 2 8
VIN VOUT
1

10U_0603_6.3V6M
C571
WL_PWREN_EC 3 6
+3VS_WLAN_R +3VS_WLAN <30> WL_PWREN_EC ON CT
1
2

100P_0402_50V8J
C558
4
R271 @ VBIAS 5
1 2 GND 9 2
GND
0.1U_0402_16V7K
CN3

0_0805_5% 1@ 1
CN2 TPS22967DSGR_SON8_2X2
<PV>R271 change to 0805 4.7U_0603_6.3V6K
2 2
<PV>C558 change to 100pf for SVTP spec.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 21 of 54
5 4 3 2 1
5 4 3 2 1

JHDD1
2.5" SATA HDD connector +5VS_HDD1 1
GND GND
23
<6> SATA_PTX_DRX_P0 C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 24
C156 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 A+ GND
<6> SATA_PTX_DRX_N0 A-
4
C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
<6> SATA_PRX_DTX_N0 B-

10U_0603_6.3V6M

0.1U_0402_16V7K
+5VS C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6
<6> SATA_PRX_DTX_P0 B+

C150
1 1 7
GND

C149
@ 0_0603_5%
D R201 1 2 +5VS_HDD1
<SI>RS11 change to un pop D
@ 0_0603_5% +3VS RS11 1 @ 2 0_0402_5% 8
R212 1 2 2 2 9 VCC3.3
RS12 1 @ 2 0_0402_5% JHDD_P10 10 VCC3.3
<8,9> DEVSLP1 VCC3.3
11
12 GND
13 GND
14 GND
15 VCC5
+5VS_HDD1 VCC5
16
17 VCC5
18 GND
19 RESERVED
20 GND
21 VCC12
22 VCC12
VCC12
SANTA_193202-1
CONN@

Change to dual load switch for ODD and WLAN


<PV>Q22 change to single load switch.
C C

+5VALW +5VS
Q22
+5VS_ODD
1 7 +5VS_ODD
Pleace near ODD Connector
2 VIN VOUT 8
VIN VOUT

10U_0603_6.3V6M

1000P_0402_50V7K

0.1U_0402_25V6K

10U_0805_10V6K
ODD_PWR 3 6 C555 1 2
<9> ODD_PWR ON CT

22U_0805_6.3V6M
1 1 1 1 1

C576

CC73
100P_0402_50V8J

CS13
CS16

CS12
4 <MV>Add 22UF for RF suggestion ,4/10.
VBIAS 5
GND 9 2 2 @ 2 2 2
GND

TPS22967DSGR_SON8_2X2

JODD1
1
CS11 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2 GND
<6> SATA_PTX_DRX_P1 RX+
<6> SATA_PTX_DRX_N1 CS14 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3
4 RX-
B B
CS15 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND
<6> SATA_PRX_DTX_N1 CS18 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6 TX-
<6> SATA_PRX_DTX_P1 7 TX+
GND
8
<6> ODD_PLUG# 9 DP
10 +5V
ODD_DA# 11 +5V
<9> ODD_DA# 12 MD 14
13 GND GND1 15
GND GND2
<SI> Delete Q84, R954 OCTEK_SLS-13HCAB
1
CS17 CONN@
0.1U_0402_25V6K
ESD@
2

Place CS17 close to JODD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ODD/SATA Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 22 of 54
5 4 3 2 1
5 4 3 2 1

JHW1 need to short LDO mode Switcing mode


JHW1
@ LL1 SMT @
1 2 RTL8151G (LDO mode)
1 2
+LAN_VDD_3V3 Rising time CL21 SMT @
JUMP_43X79
+3VALW
@ UG5   need>0.5mS and <100mS LL2 @ SMT
CL8 @ SMT +LAN_VDD_1V0
5 1 +LAN_VDD_3V3
IN OUT LL1 1 20_0603_5%
2
CL14 & CL15 close UL1 Pin22
GND
1@ RL35 20_0201_5% 1 4 3 @ LL2
CL26 & CL27 close UL1 Pin30
SS EN +LAN_REGOUT 1 2

1U_0402_6.3V6K

1U_0402_6.3V6K
@ CL28 2.2UH +-5% NLC252018T-2R2J-N

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
APL3512_SOT23-5

0.1U_0402_16V7K
D 2 1 1 1 1 1 1 1 1 1 D

CL8

CL23
1500P_0402_50V7K 1 @ CL12 CL13
CL11 CL14 CL15 CL26 CL27
CL21 @ @ 8161@ @8161@ 8166@ @8166@
@ 2 2 2 2 2 2 2 2 2
RL29 2 1 10K_0402_5%
LAN_PWR_EN_R 2
<9> LAN_PWR_EN

Place CL11~CL13 close UL1 Pin 3, 8 , 22 EC_LAN_ISOLATEB# 2 1 +3VS


LL2, CL8, CL23 for 8161 1K_0402_5% RL5
1

2
+LAN_VDD_3V3 +VDDREG @ CL29
CL8 & CL18 close LL2 RL8
2
0.1U_0402_16V7K 8151/8166 Co‐Lay 15K_0402_5%
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
+LAN_VDD_3V3=40mil

1
1 1 1 1 1 1 8161@
CL10

CL16
@8161@ @ UL1 +LAN_VDD_1V0 +VDDREG=40mil
CL20 CL19 CL9 CL5 L
@ @ +LAN_REGOUT=60mil
2 2 2 @ 2 2 2 LAN_MDIP0 1 3 XTLO
MDIP0 AVDD10 XTLO <31>
LAN_MDIN0 2 8
LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3 XTLI
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIP2 6 MDIN1 DVDD10 2 1 XTLO
LAN_MDIN2 7 MDIP2 11 +LAN_VDD_3V3 1M_0402_5% RL7
MDIN2 AVDD33

1
LAN_MDIP3 9 32 @ XTAL@
LAN_MDIN3 10 MDIP3 AVDD33 RL15
MDIN3 23 +VDDREG RL10 1 2
CL9 & CL5 close to UL1: Pin 11,32 CL10& CL16 close to UL1: Pin 23 VDDREG(VDD33) 24 +LAN_REGOUT 0_0603_5%
10K_0402_5%
LAN_CLKREQ#2 @ RL6 1 0_0201_5% LAN_CLKREQ#_R 12 REGOUT
CL19 close to UL1: Pin 32 <7> LAN_CLKREQ# RTL8111G

2
PLT_RST# 19 CLKREQB 21 LANWAKEB XTAL@
<21,28,30,32,8> PLT_RST# PERSTB LANWAKEB EC_PME# <30,9>

3
CL20 close to UL1: Pin 11 20 EC_LAN_ISOLATEB# YL1
ISOLATEB

10P_0402_50V8J

10P_0402_50V8J
CLK_PCIE_LAN 15 XTAL@ 1 XTAL@ 1

OSC

OSC
<7> CLK_PCIE_LAN REFCLK_P
CLK_PCIE_LAN# 16 27 LED0 TH2 CL25 CL24
<7> CLK_PCIE_LAN# REFCLK_N LED0 26 LED1/GPO TH1
PCIE_PTX_C_DRX_P3 13 LED1/GPO 25 LED2 TH3

GND

GND
<10> PCIE_PTX_C_DRX_P3 HSIP LED2(LED1) 2 2
PCIE_PTX_C_DRX_N3 14
<10> PCIE_PTX_C_DRX_N3 HSIN
C PCIE_PRX_DTX_P3 CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17 28 XTLI C
<10> PCIE_PRX_DTX_P3 HSOP CKXTAL1
PCIE_PRX_DTX_N3 CR13 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18 29 XTLO
<10> PCIE_PRX_DTX_N3

4
HSON CKXTAL2
RSET 31 33
RSET GND 25MHZ 10PF 5YEA25000102IF50Q3

2
SP050005L00 Footprint RL11
TSL1 8161@ 2.49K_0402_1% SA00005YT00 <PV>CL24,CL25 change to 10pf.
UL1 8166@
+V_DAC 1 24

1
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_TX3- RP5 SA000063500
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_TX3+ 1 8 RTL8166EH-CG QFN 32P E-LAN CTRL
TD1- MX1- 2 7 SANTA_130456-291 JLAN1 CONN@
4 21 3 6 RJ45_TX3- 8
LAN_MDIN2 5 TCT2
TD2+
MCT2
MX2+
20 RJ45_TX2- 4 5 (SA000063500) 10/100 8166@ PR4-
GND
10
LAN_MDIP2 6 19 RJ45_TX2+ RJ45_TX3+ 7 9

7
TD2- MX2-
18
75_0804_8P4R_1%
SD300002E80
(SA00005YT00) Giga 8151@ RJ45_RX1- 6
PR4+ GND

TCT3 MCT3 2 PR2-


LAN_MDIN1 8 17 RJ45_RX1- CL2
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_RX1+ SE167100J80 RJ45_TX2- 5
TD3- MX3- 10P_1808_3KV PR3-
10 15 1 RJ45_TX2+ 4
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_TX0- PR3+ LANGND
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_TX0+ 1 EMI@ RJ45_RX1+ 3
TD4- MX4- PR2+
3

CL3
YSLC05CH_SOT23-3

ESD@ LANGND 120P_0402_50V8 RJ45_TX0- 2


2

DL1 PR1-
2 1 LANKO_LG-2446S-1 RJ45_TX0+ 1
@ @EMI@ SP050006800 PR1+
CL1 CL4 S X’FORM_ LG-2446S-1 100/1000BASE-TX LAN
0.01U_0402_16V7K 0.1U_0402_16V7K
1 2
TSL1 8166@
1

SCA00000U10
SP050003P00
S X'FORM_ NS892404 ETHERNET 10/100

B
(SP050003P00) 10/100 8166@ B

(SP050006800) Giga 8161@

RR1
+3VS 1 2 +3VS_CR +3VS_CR
0_0603_5%
short@
1 1 Card Reader Connector
4.7U_0402_6.3V6M
CR9
2
CR10
2 0.1U_0402_16V7K
RTS5239 RR4-RR9 close to chip CONN@
CR12-CR13 close to chip or socket JREAD1
UR1 SD_D3_R 1
PCIE_PTX_C_DRX_P2 1 12 SD_D1 @EMI@ 1 RR2 2 0_0402_5% SD_D1_R 208MHz DAT3
Close to Chip <10> PCIE_PTX_C_DRX_P2 HSIP SP1
PCIE_PTX_C_DRX_N2 2 13 SD_D0 @EMI@ 1 RR4 2 0_0402_5% SD_D0_R @ CR12 SD_CMD_R 2
<10> PCIE_PTX_C_DRX_N2 HSIN SP2 +CR_VDD_3V3 CMD
CLK_PCIE_CR 3 14 SD_CLK EMI@ 1 RR5 2 33_0402_5% SD_CLK_R 1 2
<7> CLK_PCIE_CR REFCLKP SP3
CLK_PCIE_CR# 4 16 SD_CMD @EMI@ 1 RR3 2 0_0402_5% SD_CMD_R Close to Conn 3
<7> CLK_PCIE_CR# REFCLKN SP4 VSS1
CL17 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P2 5 17 SD_D3 @EMI@ 1 RR6 2 0_0402_5% SD_D3_R 6.8P_0402_50V8C
<10> PCIE_PRX_DTX_P2 HSOP SP5
CL18 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N2 6 18 SD_D2 @EMI@ 1 RR7 2 0_0402_5% SD_D2_R +CR_VDD_3V3 4
<10> PCIE_PRX_DTX_N2 HSON SP6 VDD

0.1U_0402_16V7K
20 SD_WP
SP7

4.7U_0603_6.3V6M
1 SD_CLK_R 5
CLK

1
15 1 2 CR7 CR8
CR_CLKREQ# 24 DV33_18 11 +DVDD12 CR14 1U_0402_6.3V4Z 6
<7,9> CR_CLKREQ# CLKREQ# DV12_S
Close to Chip VSS2
PLT_RST# 23

2
22 PERST# 2 SD_D0_R 7
SD_CD# 21 MS_INS# 9 +3VS_CR DAT0
+3VS_CR 1 2 19 SD_CD# 3V3_IN 7 +AVDD12 SD_D1_R 8
10K_0402_5% RR8 GPIO AV12 10 DAT1
CARD_3V3 +CR_VDD_3V3
SD_D2_R 9
DAT2
6.2K_0402_1% 1 2 RR9 RREF 8 25 SD_CD# 10 12
RREF GND CD G1
RTS5239-GR_QFN24_4X4 SD_WP 11 13
RR9 close to chip WP G2
TAITW_PSDAT0-09GLBS1ZZ4H1
A A

+DVDD12 +DVDD12 +AVDD12 +AVDD12 Close to Chip


+3VS_CR
0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

1 1
1

0.1U_0402_16V7K

CR1 CR2 CR3 CR4 1 1


CR5 CR6
2

2 2 4.7U_0402_6.3V6M @
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN 8111G
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 23 of 54
5 4 3 2 1
A B C D E

RS1 @ 0_0402_5% USB3.0 need support 2.5A


<10> USB3_TX0_P USB3_TX0_P 2 1 CS1 USB3_TX0_C_P 1 2 USB3TXDP0_C_R change USB PWR SW SA00005VN00
0.1U_0402_16V7K
CMMI21T-900Y-N low active
4 3 +5VALW +USB_VCCA
4 3
EMI@ US1 W=100mils
1 2 W=100mils 1 8

1000P_0402_50V7K
1 2 2 GND VOUT 7

0.1U_0402_16V7K

47U_0805_6.3V6M
LM1 SM070003K00 3 VIN VOUT 6
1 USB3_TX0_N 2 1 CS2 USB3_TX0_C_N 1 2 USB3TXDN0_C_R 4 VIN VOUT 5 1
<10> USB3_TX0_N EN FLG 1 1 1
0.1U_0402_16V7K RS2 @ 0_0402_5% @

CS6
1 G547I2P81U_MSOP8 CS5
CS4
CS3
2 2 2
RS3 @ 0_0402_5% 0.1U_0402_16V7K
2
1 2 USB3RXDP0_C
<10> USB3_RX0_P
CMMI21T-900Y-N @
4 3 <30> USB_ON# USB_ON# 1 2 RS4
4 3 0_0402_5% RS5 1 @ 2 USB_OC0#
EMI@
<EC> 0_0402_5%
USB_OC0# <10,9>
1 2
1 2
LM2 SM070003K00
1 2 USB3RXDN0_C @ESD@
<10> USB3_RX0_N
RS6 @ 0_0402_5% DM1 SCA00000U10
2 USB20_N0_C
RS7 @ 0_0402_5% 1
1 2 USB20_P0_C 3 USB20_P0_C
<10> USB20_P0
LM3 YSLC05CH_SOT23-3
1 2
1 2
2 EMI@ Part Number = SM070003Y00 USB2.0/USB3.0 port 1 2

4 3
4 3 SC300002800 +USB_VCCA
WCM-2012-900T_4P ESD@ DM2 JUSB1
1 2 USB20_N0_C USB3RXDN0_C 1 1 109 USB3RXDN0_C USB3TXDP0_C_R 9
<10> USB20_N0 SSTX+
RS8 @ 0_0402_5% 1
USB3RXDP0_C 2 2 98 USB3RXDP0_C USB3TXDN0_C_R 8 VBUS
USB20_P0_C 3 SSTX-
<PV>LM3 change PN. USB3TXDN0_C_R 4 4 77 USB3TXDN0_C_R 7 D+
USB20_N0_C 2 GND 10
USB3TXDP0_C_R 5 5 66 USB3TXDP0_C_R USB3RXDP0_C 6 D- GND 11
4 SSRX+ GND 12
3 3 USB3RXDN0_C 5 GND GND 13
SSRX- GND
8 ACON_TARA4-9K1311
CONN@
IP4292CZ10-TB

@ RS13 0_0402_5%
<PV>LM4,LM5 change PN.
3 USB2.0 port x 2 <10> USB20_N2
1 2 USB20_N2_C 3

LM4
1 2 +USB_VCCB E-T_6916K-Q12N-00L
+USB_VCCB 1 2
+5VALW
EMI@ Part Number = SM070003Y00
US2 W=100mils 4 3 12 14
W=100mils 1 8 4 3 11 12 G2 13
2 GND VOUT 7 WCM-2012-900T_4P 10 11 G1
3 VIN VOUT 6 1 2 USB20_P2_C 9 10
VIN VOUT <10> USB20_P2 9
4 5 @ RS14 0_0402_5% 8
EN FLG 7 8
1 G547I2P81U_MSOP8 @ RS15 0_0402_5% USB20_P2_C 6 7
1 2 USB20_N1_C USB20_N2_C 5 6
CS10 <10> USB20_N1 5
4
0.1U_0402_16V7K LM5 USB20_P1_C 3 4
2
1 2 USB20_N1_C 2 3
1 2 1 2
EMI@ Part Number = SM070003Y00 1
USB_ON# RS101
@RS10
@ 2 4 3
0_0402_5% RS9 1 @ 2 USB_OC1# 4 3
USB_OC1# <10> JUSB2
0_0402_5% WCM-2012-900T_4P
1 2 USB20_P1_C
<10> USB20_P1
@ RS16 0_0402_5%
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB 3.0/2.0 conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 24 of 54
A B C D E
5 4 3 2 1

UA1
+3VS +DVDD +DVDD_IO +1.5VS
20 1 +DVDD
19 MIC1_R DVDD 9 1 @ 2 1 2
MIC1_L DVDD_IO +DVDD_IO
LA3

.1U_0402_16V7K
CA5

10U_0603_6.3V6M
CA6

.1U_0402_16V7K
CA7

10U_0603_6.3V6M
CA8
CA1 1 2 4.7U_0402_6.3V6M INT_MICR_C 18 26
+5VS_AVDD RA2 SUPPRE_ KC FBMA-10-100505-101T 0402
INT_MIC RA3 1 2 1K_0402_5% CA4 1 2 4.7U_0402_6.3V6M INT_MICL_C 17 MIC2_R AVDD1 40 0_0603_5% PCB Footprint = R_0402
MIC2_L AVDD2 +1.5VS_AVDD 1 1 1 1
31 41 +5VS_PVDD
MUTE_LED_CTR 30 MIC1_VREFO_L PVDD1 46
29 MIC1_VREFO_R PVDD2 2 2 2 2
+MIC2_VREFO MIC2_VREFO
23 45 SPK_R+
24 LINE2_R SPK_OUT_R+ 44 SPK_R-
LINE2_L SPK_OUT_R-
Internal Speaker Place near Pin1 Place near Pin9
16 42 SPK_L+
D MONO_OUT SPK_OUT_L+ 43 SPK_L- D
PC_BEEP 12 SPK_OUT_L- +5VS_AVDD +5VS
PCBEEP LA4 +1.5VS_AVDD +1.5VS
+3VS 10 33 HPOUT_R RA4 1 2 75_0402_1% HP_OUTR 1 2
<6> HDA_SYNC_AUDIO SYNC HPOUT_R 32 HPOUT_L RA5 1 2 75_0402_1% HP_OUTL
Headphone FBMA-L11160808601LMA10T_2P 1 2
HPOUT_L

.1U_0402_16V7K
CA9

4.7U_0603_6.3V6K
CA10
HDA_RST_AUDIO# 11 LA5
<6> HDA_RST_AUDIO# RESET#

.1U_0402_16V7K
CA12

4.7U_0603_6.3V6K
CA13
1 2 600ohms @100MHz 1A SUPPRE_ KC FBMA-10-100505-101T 0402
2 CPVDD +3VS 1 @ 2 5 1 2 PCB Footprint = R_0402
SDATA_OUT HDA_SDOUT_AUDIO <6> Main:SM010007Z00
RA6 8 SDATA_IN RA7 1 2 22_0402_5%
SDATA_IN HDA_SDIN0 <6>
CA17 4.7K_0402_5% CA11 1 2 10U_0603_6.3V6M ALDO_CAP 7 2nd:SM01000BU00
LDO3-CAP 6 2 1
4.7U_0603_6.3V6K BCLK HDA_BITCLK_AUDIO <6>
1 CA14 1 2 2.2U_0402_6.3V6M ACPVEE 34 2 1
CPVDD 36 CPVEE 22
CBN 35 CPVDD LINE1_L 21
CA15 1 2 2.2U_0402_6.3V6M CBP 37 CBN LINE1_R 48 MIC_JD
CBP SPDIFO/GPIO2 Place near Pin26
Place near Pin40
15 JDREF RA9 2 1 20K_0402_1% GNDA
2 JDREF 28 AVREF CA16 2 1 .1U_0402_16V7K GNDA
<19> D_MIC_DATA GPIO0/DMIC_DATA VREF
3 27 CA18 1 2 10U_0603_6.3V6M
<19> D_MIC_CLK GPIO1/DMIC_CLK LDO1_CAP +5VS_PVDD +5VS
39 CA19 1 2 10U_0603_6.3V6M MUTE_LED <26>
LDO2_CAP LA6 600ohms @100MHz 2A
PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 2 RA29 1 100K_0402_5% 1 2
14 SENSE_A AVSS1 38 @ FBMA-L11-201209601LMA20T_2P Main:SM01000NS00
SENSE_B AVSS2

.1U_0402_16V7K
CA20

.1U_0402_16V7K
CA21

10U_0603_6.3V6M
CA22
10U_0603_6.3V6M
CA23
2nd:SM01000EE00

3
4 GNDA 1 1 2 2
47 DVSS 49 DA8
PDB Thermal Pad

3
+1.5VS +DVDD YSLC05CH_SOT23-3
SCA00002900 Q4B
1

ALC3227-CG_MQFN48P_6X6 AVREFCA24 1 2 2.2U_0402_6.3V6M 2 2 1 1


2N7002KDW_SOT363-6

1
MUTE_LED_CTR 5
RA25
2.2K_0402_5% 1K_0402_5%
<SI> QA2 change from NMOS to BJT

4
1
RA26 GNDA
<PV> QA2 change to QA1.
2 2

1
GNDA
2

10K_0402_5%
B

RA12
E

HDA_RST_AUDIO# 3 1 PD#

2
C

C C
Part Number = SB000008E10 QA1

Internal SPK
1

MMBT3904WH_SOT323-3

10K_0402_5% Power down (PD#) power stage for save power <DB>Relace RA13/RA14/RA15/RA16 close to UA1
1 2 <PV>RA13~RA16 change to SM010008A00, 30-ohm.
<30> EC_MUTE# RA11 0V: Power down power stage
DA3
CH751H-40PT_SOD323-2 JSPK1
3.3V: Power up power stage
2

SPK_R- EMI@ RA13 1 2 PBY160808T-300Y-N_2P SPK_R-_CONN 1


SPK_R+ EMI@ RA14 1 2 PBY160808T-300Y-N_2P SPK_R+_CONN 2 1
SPK_L- EMI@ RA15 1 2 PBY160808T-300Y-N_2P SPK_L-_CONN 3 2 5
SPK_L+ EMI@ RA16 1 2 PBY160808T-300Y-N_2P SPK_L+_CONN 4 3 GND 6
4 GND
E-T_3703-Q04N-11R

wide 40 MIL

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
Delete ESD Diode CONN@

1 1 1 1

@EMI@ C123

@EMI@ C124

@EMI@ C125

@EMI@ C126
SPK_R-_CONN SPK_L-_CONN
2 2 2 2
SPK_R+_CONN SPK_L+_CONN

3
DA1 @ESD@ DA2 @ESD@
SCA00002900 SCA00002900
L03ESDL5V0CC3-2_SOT23-3 L03ESDL5V0CC3-2_SOT23-3
PC Beep

1
EC Beep 1 2 PC_BEEP_R
<30> EC_BEEP#
CA31 Reserve for ESD request.
.1U_0402_16V7K RA19 INT_MIC_R HP_OUTR_R HP_OUTL_R +MIC2_VREFO
B
47K_0402_5%
GNDA Jack detect B

3
SB Beep <9> HDA_SPKR 1 2 1 2 1 2 PC_BEEP Combo Mic = High

1
CA33 CA34 DA4
1

.1U_0402_16V7K .1U_0402_16V7K YSLC05CH_SOT23-3 DA6 Normal HP = Low


SCA00002900 YSLC05CH_SOT23-3 RA17
RA20 SCA00000U10 2.2K_0402_5%
10K_0402_5% ESD@

2
@ESD@ MIC_JD 1 2 INT_MIC
2

RA18
Close to Codec pin12

10U_0603_6.3V6M
CA32
22K_0402_5%

1
2

1
1

GNDA

COMBO AUDIO JACK


RA27 1 @ 2 0_0402_5% EMI@
HPR, HPL, 15mil Keep 30mil JHP1
INT_MIC RA21 1 2 BLM15AG601SN1D_2P INT_MIC_R 3

6
RA28 1 @ 2 0_0402_5% EMI@
HP_OUTL RA22 1 2 BLM15AG601SN1D_2P HP_OUTL_R 1

1 2 EMI@ 2
CA40 @EMI@ HP_OUTR RA23 1 2 BLM15AG601SN1D_2P HP_OUTR_R 4
.1U_0402_16V7K
<PV>RA21~23 change to PLUG_IN#
5
Main : SM01000II00
100P_0402_50V8J
CA35

10P_0402_50V8J
CA36

10P_0402_50V8J
CA37
1 2 1 1 1
1

CA38 @EMI@ 2nd : SM01000I000


A .1U_0402_16V7K RA24 @EMI@ SINGA_2SJ-E960-001F A

@EMI@

@EMI@
22K_0402_5%
2 2 2 GNDA CONN@
1 2 Delete ESD Diode
2

CA39 @EMI@ Pin6 and Pin5


.1U_0402_16V7K Normal OPEN
1 2 GNDA GNDA GNDA GNDA
CA29 EMI@
.1U_0402_16V7K

1 2 Security Classification Compal Secret Data Compal Electronics, Inc.


CA30 EMI@ 2013/01/04 2015/01/04 Title
.1U_0402_16V7K
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO ALC3227-CG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 25 of 54
5 4 3 2 1
<30> KSI[0..7]
KSI7 Keyboard conn
KSI6
KSI5
KSI4
Touch pad conn KSI3
KSI2 CONN@ JKB1
KSI1 KSI1 1
KSI0 KSI7 2 1
KSI6 3 2
KSO9 4 3
KSI4 5 4
<30> KSO[0..17] KSI5 6 5
KSO17 KSO0 7 6
KSO16 KSI2 8 7
KSO15 KSI3 9 8
KSO14 KSO5 10 9
ESD@ KSO13 KSO1 11 10
KSI0 C193 2 1 100P_0402_50V8J KSO12 KSI0 12 11
KSO11 KSO2 13 12
KSO10 KSO4 14 13
KSO9 KSO7 15 14
KSO8 KSO8 16 15
KSO7 KSO6 17 16
KSO6 KSO3 18 17
KSO5 KSO12 19 18
KSO4 KSO13 20 19
KSO3 KSO14 21 20
KSO2 KSO11 22 21
KSO1 KSO10 23 22
KSO0 KSO15 24 23
KSO16 25 24
KSO17 26 25
+5VS 27 26
CAP_LOCK# R203 1 2 3.3K_0402_5% 28 27
<30> CAP_LOCK#
<25> MUTE_LED MUTE_LED R207 1 2 3.3K_0402_5% 29 28
WL_WHIT 30 29
WL_AMBER 31 30 33
+5VS 32 31 G1 34
32 G2
ACES_50690-0320N-P01

+5VALW +5VALW
+3VALW

JTP1
1 1
TP_CLK 2 1 @EMI@
<30> TP_CLK 2
TP_DATA 3 5 C134
<30> TP_DATA 3 G1
4 6 470P_0402_50V8J CAP_LOCK#
4 G2 2 MUTE_LED
HB_A090420-SAHR21
CONN@

1 1

1
Amber White
2

CC122 CC123
DM5 R157 R158 100P_0402_50V8J 100P_0402_50V8J
3.3K_0402_5% 3.3K_0402_5% 2 2
YSLC05CH_SOT23-3 ESD@ ESD@
SCA00000U10

2
WL_AMBER WL_WHIT
@ESD@

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6
6

3
Q20A

Q20B
1

2 5
<30> WLAN_OFF_LED# WLAN_ON_LED# <30>

4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 26 of 54
A B C D E

Powert Button Connector


+3VL

1 1
@EMI@ 1 LID_SW#
White
remove at SI phase LED10 +3VALW
C166 0.1U_0402_16V7K 220_0402_5% R2744
1
PWR_LED# 2 1 1 2
2 CC124 <30> PWR_LED#
JPWR1 100P_0402_50V8J
1 2 @ESD@ LTW-110DC5-C_WHITE
ESD@ 1

3
LID_SW# 2 1
<30> LID_SW#
ON/OFF# 3 2 5
remove at SI phase CS20 0.1U_0402_16V7K
<30> ON/OFF# 3 G1
4 6
4 G2 +3VL 2
HB_A090420-SAHR21
White
CONN@ LED9 +3VS
R215
220_0402_5% R2743
ON/OFF# 2 1 SATA_LED# 2 1 1 2
<6,9> SATA_LED#

100K_0402_5% @ESD@ 1 LTW-110DC5-C_WHITE

3
remove at SI phase CS19 0.1U_0402_16V7K
2
2 2

<SI> Del New Lid SW conn

3 3

+FAN_POWER

40mil FAN conn +3VS


2.2U_0603_6.3V6K

1
+FAN_POWER
1
RE50
CE22 +5VS 10K_0402_5%
CE25
2 2.2U_0603_6.3V6K 40milCONN@ JFAN1

2
1 2 1
2 1
<30> FAN_SPEED1 2
3
UE3 3
1 8 1 4
2 VEN GND 7 5 GND
3 VIN GND 6 CE24 GND
4 VO GND 5 0.01U_0402_16V7K ACES_85204-0300N
<30> EN_DFAN1 VSET GND 2
APE8873M SOP 8P

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
PWRBTN/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 27 of 54
A B C D E
5 4 3 2 1

+3VS +3VS
ACCELEROMETER +3V_GSEN

+3VL RH411 1 @ 2 +3V_GSEN


TPM1.2

1
0_0402_5%
@ RH503
0_0402_5%
0.1U_0402_16V4Z
1@ 1@ 1@

2
C1060 C1059 C1058 @
DH8
1 SI# 2012.04.10 Change ACCEL_INT# to INT1
0.1U_0402_16V4Z @ 1 2
2 2 2 +3V_GSEN ACCEL_INT# <9>
C1061 * ACCEL_INT#_R
0.1U_0402_16V4Z @ 0.1U_0402_16V4Z

24
19
10
CH751H-40PT_SOD323-2

5
U70 2 @
U25

VDD
VDD
VDD

VSB
1 9 +3V_GSEN
Vdd_IO INT2 11
D LPC_AD0 26 28 EC_SMB_CK1 4 INT1 14 D
<30,7> LPC_AD0 LAD0 LPCPD# <30,45,46> EC_SMB_CK1 SCL/SPC VDD
LPC_AD1 23 9 BADD 1 2 PLT_RST# EC_SMB_DA1 6
<30,7> LPC_AD1 LAD1 TESTB1/BADD <30,45,46> EC_SMB_DA1 SDA/SDI/SDO
LPC_AD2 20 8 7 5
<30,7> LPC_AD2 LAD2 TEST1 SDO/SA0 GND
LPC_AD3 17 @ R1413 0_0402_5% +3V_GSEN 2 @ R208 1 8 12
<30,7> LPC_AD3 LAD3 CS GND
14 10K_0402_5% 10
XTALO RES

1
13 13 1 1
TPM XTALI @ R227 2 RES 15 C231
21 SLB 9656 TT 1.2 @ 0_0402_5% 3 NC RES 16 C232
<7> CLK_PCI_TPM LCLK NC RES
LPC_FRAME# 22 2 T48 PAD 0.1U_0402_16V7K 10U_0603_6.3V6M
<30,7> LPC_FRAME# LFRAME# GPIO2 2 2
PLT_RST# 16 6 HP3DC2TR
<21,23,30,32,8> PLT_RST# LRESET# GPIO

2
SERIRQ 27 T47 PAD
<30,9> SERIRQ SERIRQ @
15 @ @
1 @ 2 7 CLKRUN# 1
+3VS PP NC

1
R1383 3
4.7K_0402_5% NC 12 @R209

GND
GND
GND
GND
NC
0_0402_5%
1

@ SLB 9656 TT 1.2

4
11
18
25

2
R1414
0_0402_5%
2

Screw Hole
H3 H4 H5 H6 H7
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8

HOLEA HOLEA HOLEA HOLEA HOLEA

C @ @ @ @ @ C
1

H9 H10 H11 H13 H15 H16


H_5P0 H_5P0 H_5P0 H_5P0 H_5P0 H_5P0

H14 H1 H2 H12 H17 H18 H19 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA FD3 FD4 FD2 FD1
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P0 H_2P0X2P5

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA @ @ @ @ @ @ @ @ @ @


1

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @ @ @
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/Screw hole
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 28 of 54

B B

A A

5 4 3 2 1
5 4 3 2 1

Use 0 ohm for material shortage  Use 0 ohm for material shortage 
If Vp-p small than 50mV +IVDDO_1.8V +RXIVDD_1.8V +IVDDO_1.8V +DAC_1.8V
+3VS +3VS_OVDD L4107 L4108
change L4106 to 0 ohm
BLM15PD600SN1D_2P BLM15PD600SN1D_2P
+RXVCC_1.8V 1 2 1 2
R4110 2 1 0_0603_5% +IVDDO_1.8V L4106 CRT@ CRT@

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C4106 CRT@

C4109 CRT@

C4136 CRT@
Rated current 500mA, DC 0.1ohm Rated current 500mA, DC 0.1ohm

1U_0402_6.3V6K
BLM15PD600SN1D_2P

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C4107 CRT@
1U_0402_6.3V6K
short@ 1 2 1 1 1 1 1

10U_0603_6.3V6M
CRT@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 Note: Depend on Note: Depend on

CRT@ C4108

CRT@ C4101

CRT@ C4110

C4105
1U_0402_6.3V6K
Project, if Vp-p small Project, if Vp-p small

CRT@ C4115
1 1 1 1 1 the 50mV change to 0 2 2 the 50mV change to 0 2 2 2

CRT@ C4111

CRT@ C4103

CRT@ C4104

CRT@ C4112
2 2 2 ohm @ ohm
2 2 2 2 2

Note: Place close pin 24


Note: Place close pin 10
D D
+3VS_IVDD33 Note: Place close pin 38,39
LDO input Note: Place close pin 22,15,31,32

10U_0603_6.3V6M
R4109 2 1 0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C4113 CRT@

C4114 CRT@

C4125 CRT@
short@ 1

CRT@ C4100
1 1 1
ISPSCL_R
ISPSDA_R
2 +3VS_IVDD33 @ESD@
DT4

1
1
CRT@ CRT@ 2 2 2 SC300001G00

22_0402_5%
R4100

R4101
22_0402_5%
CRT_HSYNC_2 6 3 CRT_VSYNC_2
+3VS_OVDD +RXIVDD_1.8V I/O4 I/O2
+HDMI_5V_OUT
+3VS R4102

2
2
4.7K_0402_5% +IVDDO_1.8V Note: Place close pin 12,14,44,46 5 2
1 @ 2 VDD GND
1 @ 2
R4103 Pin38,39 LDO output +IVDDO_1.8V.
4.7K_0402_5% CRT_DATA 4 1 CRT_CLK
I/O3 I/O1

13
48

35
36

38
39

12
14
44
46
UT5

1
2
+HDMI_5V_OUT AZC099-04S.R7G_SOT23-6
1.52mA

DDCSCL
DDCSDA

IVDD33
IVDD33

IVDDO
IVDDO
OVDD
OVDD

IVDD
IVDD
IVDD
IVDD
VGA_HPD 40
HPD C4116 @ @ESD@
DT3
4.2mA 100.5mA 45 1 2 0.1U_0402_16V4Z SC300001G00
CRT@ C4123 2 1 0.1U_0402_16V7K PCH_DPC_C_P0 26 MCUVDDH +HDMI_5V_OUT CRT_R_2 6 3 CRT_G_2
<4> PCH_DPC_P0 RX0P I/O4 I/O2
<4> PCH_DPC_N0 CRT@ C4119 2 1 0.1U_0402_16V7K PCH_DPC_C_N0 27
RX0N +HDMI_5V_OUT
<4> PCH_DPC_P1 CRT@ C4120 2 1 0.1U_0402_16V7K PCH_DPC_C_P1 29 47 MCURSTN @ T4102
RX1P MCURSTN

1
2.2K_0402_5%

2.2K_0402_5%
<4> PCH_DPC_N1 CRT@ C4124 2 1 0.1U_0402_16V7K PCH_DPC_C_N1 30 5 2
RX1N VDD GND

R4124

CRT@

R4125

CRT@
CPU DDI1 28 @ T4101
R4108 2 CRT@ 1 1M_0402_5% URDBG
+3VS RP4102
(2-Lane only) R4104 2 @ 1 100K_0402_5% C4121 CRT@ 15 ISPSCL_R CRT@ 4 1 CRT_B_2

2
0.1U_0402_16V7K ISPSCL 16 ISPSDA_R 1 8 I/O3 I/O1
2 1 DDI1_AUX_C_DP 20 ISPSDA 2 7
<8> DDI1_AUX_DP RXAUXP AZC099-04S.R7G_SOT23-6
2 1 DDI1_AUX_C_DN 19 23 3 6 CRT_CLK CRT_CLK
<8> DDI1_AUX_DN RXAUXN VGADDCCLK
C4122 CRT@ 21 4 5 CRT_DATA CRT_DATA
0.1U_0402_16V7K VGADDCSDA

+3VS R4113 2 @ 1 100K_0402_5% DDI1_AUX_DP 18 3 VSYNC


R4114 2 1 1M_0402_5% DDI1_AUX_DN 17 DCAUXP VSYNC 4 HSYNC 22_0804_8P4R_5%
CRT@ DCAUXN HSYNC Note: ISPSCL/ISPSDA for F/W update

+RXIVDD_1.8V +RXVCC_1.8V RGB Trace must less than 2000mils.


+DAC_1.8V
C C
CRB1.0 use 33ohm@100Mhz Bead
25
31 AVCC
56.95mA 65.5mA VDDC 10 CRT Connector
AVCC
R_out & B_out can be swapped.
22
PVCC
41.6mA
IT6513FN L4103
PBY160808T-600Y-N @
T4103 6
11
JCRT1

11 CRT_R CRT_R 1 2 CRTEMI@ CRT_R_2 1


IORP L4104 7
PBY160808T-600Y-N CRT_DATA 12
9 CRT_G CRT_G 1 2 CRTEMI@ CRT_G_2 2
+HDMI_5V_OUT IOGP L4105 8
24 47.3mA PBY160808T-600Y-N CRT_HSYNC_2 13
DVDD18 8 CRT_B CRT_B 1 2 CRTEMI@ CRT_B_2 3
IOBP

6.8P_0402_50V8C

6.8P_0402_50V8C

6.8P_0402_50V8C

6.8P_0402_50V8C

6.8P_0402_50V8C

6.8P_0402_50V8C
1 1 1 1 1 1 +HDMI_5V_OUT +HDMI_5V_OUT 9
41 VGADETECT @ T4104 CRT_VSYNC_2 14
NC/VGADETECT
1

8
7
6
5

C4126

C4127

C4128

C4129

C4130

C4131
CRT@ CRT@ CRT@ SM010005N00 W=40mils 4

CRTEMI@

CRTEMI@

CRTEMI@

CRTEMI@

CRTEMI@

CRTEMI@
R4123 R4126 5 1 2 RP4100 1 10 G 16
4.7K_0402_5% 4.7K_0402_5% 32 RSET R4118 CRT@ 100_0402_1% 2 2 2 2 2 2 CRT_CLK 15 17
ASPVCC
6.158mA 75_0804_8P4R_1% G

C4132
0.1U_0402_16V4Z
5
0.293mA 7 @
2

1
2
3
4
VDDA +DAC_1.8V 2 C-H_13-12201560CP
CRT@ CONN@
PCSDA 6 1 2 C4133

0.1U_0402_16V4Z
COMP DC060006E00

C4137 CRT@
PCSDA 43 0.1U_0402_16V4Z
PCSCL PCSCL 42 PCSDA
PCSCL 1
Note: need external PU to 2K ~ 10K 34 XTALIN_6513 Pin41_VGADETECT is not use in IT6513. <MV> EMI fine tune Pi-filiter to 60-ohm and 6.8pf .
XTALIN 33 XTALOUT_6513
XTALOUT
PWDNB

2
PAD

IT6513FN_QFN48_6X6
37

49

+HDMI_5V_OUT CRT@
CRT@
R4120 1 2 0_0402_5%

1 2 +HDMI_5V_OUT
+5VS R4121 10K_0402_5% CRT@
CRT@ RT26 1 CRT@ 2 CRT_HSYNC_2
<PV>Add R4121 by vender recommand. 1 2 CRT@ 2 1 LT14 33_0402_5%
CT27 0.1U_0402_16V4Z
2
G

10K_0402_5% 1 CRT@ 2 CRT_VSYNC_2

1
UT2 CRT@ LT15 33_0402_5% 1 1
3 1 VGA_HPD 74AHCT1G125GW_SOT353-5

OE#
B <8> DDI1_HPD B
HSYNC 2 4 CRT_HSYNC_1 @ @
S

A Y
1

CT26 CT28

G
Q4100 R4122 10P_0402_50V8J 2 2 10P_0402_50V8J
L2N7002LT1G_SOT23-3 4.7K_0402_5%

3
@ CRT@
+HDMI_5V_OUT
2

CT25 1 2 0.1U_0402_16V4Z
CRT@

1
P

OE#
VSYNC 2 4 CRT_VSYNC_1
R4127 A Y

G
1M_0402_5% UT4 CRT@
XTALOUT_6513 @ XTALIN_6513 74AHCT1G125GW_SOT353-5

3
X4100 @
27MHZ_10PF_X3G027000BA1H-U
Crystal
3 4
OUT GND
2 1
GND IN
18P_0402_50V8J

1
18P_0402_50V8J

1
@
C4134 @
2 C4135
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP to CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 29 of 54
5 4 3 2 1
5 4 3 2 1

+3VL +3VALW_EC
LK1 +3VALW_EC
15" DB SI PV MV 14" DB SI PV MV
short@ RK57 FBMA-L11-160808-800LMT_0603 UMA UMA

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 +3VALW_EC 1 2 +EC_VCCA 12k ohm 20K ohm 0 ohm 15K ohm
33K ohm 56K ohm 27K ohm 43K ohm

2
RK13 RK13

CK2

CK3
1 1 1
0_0603_5% RK6 DIS DIS
CK7 100K_0402_5% 160k ohm 240k ohm 330k ohm 560k ohm 130k ohm 200k ohm 270k ohm 430k ohm
RK13 RK13

ECAGND
0.1U_0402_16V7K
2 2 2
PV# 2013.01.29 Add CK4 for ESD protection

1
BOARD_ID Board ID control
+3V_EC_VDD
<DB>RK13 change to 160K ==>for 15" DIS

2
ESD@ RK12 short@
CK4
D 2 1 +3VL DIS@ <DB>RK13 change to 12K ===>for 15" UMA D
2 1 PLT_RST# RK13
0_0402_5% 560K_0402_1% UMA@
SD034560380 RK13

1
0.1U_0402_16V7K

111
125
56K_0402_1% CH751H-40PT_SOD323-2

22
33
96

67
9
UK1 SD034560280 EC_ACIN 2 1 ACIN <44,45,46,8>
DK1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
CK8 2 1 100P_0402_50V8J
+3VALW_EC RK15 2 1 330K_0402_5% EC_RST#
1 21 GPU_HOT# <53>
<35,53,9> DGPU_PWR_EN GATEA20/GPIO00 GPIO0F
1 2 EC_KBRST# 2 23 EC_BEEP# <25>
<7,9> EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10
CK9 0.1U_0402_16V7K <28,9> SERIRQ SERIRQ 3 26 TS_GPIO_EC <19> short@ RK17
LPC_FRAME# 4 SERIRQ GPIO12 27 0_0402_5%
<28,7> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 AC_AND_CHAG <45>
LPC_AD3 5 VR_HOT# 1 2 PROCHOT# <4,44>
<28,7> LPC_AD3 LPC_AD3 <50> VR_HOT#
LPC_AD2 7 PWM Output
<28,7> LPC_AD2 LPC_AD2
LPC_AD1 8 63 B/I#
<28,7> LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38 B/I# <44,45>
LPC_AD0 10 LPC & MISC 64 BOARD_ID
<28,7> LPC_AD0 LPC_AD0 AD1/GPIO39 65 ADP_I
ADP_I/AD2/GPIO3A ADP_I <44,46>

1
CLK_PCI_LPC 12 66 D
<7> CLK_PCI_LPC CLK_PCI_EC AD Input AD3/GPIO3B
<21,23,28,32,8> PLT_RST# PLT_RST# 13 75 ADP_ID H_PROCHOT#_EC 2
PCIRST#/GPIO05 AD4/GPIO42 ADP_ID <44> <44> H_PROCHOT#_EC
EC_RST# 37 76 ENBKL G
EC_SCI# 20 EC_RST# IMON/AD5/GPIO43 ENBKL <8> QK1
<9> EC_SCI# S

3
1 @ 2 PM_CLKRUN#_R 38 EC_SCII#/GPIO0E 2N7002_SOT23-3
<8> PM_CLKRUN# GPIO1D
<21> EC_PCIE_WAKE# RK59 1 2 0_0402_5% short@ RK53 1 2 0_0201_5% <PWR>
+1.05V_VS_PG_PWR <49>
RK61 short@ 0_0402_5% 68 +1.05V_VS_PG_PWR
+3VALW_EC DAC_BRIG/GPIO3C 70
<26> KSI[0..7] DA Output EN_DFAN1/GPIO3D EN_DFAN1 <27>
KSI0 55 71
KSI0/GPIO30 IREF/GPIO3E DGPU_HOLD_RST# <32,9>
KSI1 56 72 SYS_PWROK <8>
+3VS KSI2 57 KSI1/GPIO31 CHGVADJ/GPIO3F
KSI3 58 KSI2/GPIO32 83
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <25> +3VALW_EC
RP7 1 8 EC_SMB_CK1 KSI4 59 84 PM_SLP_S4# PM_SLP_S4# <8>
C
2 7 EC_SMB_DA1 KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 WLAN_OFF_LED# C
KSI5/GPIO35 CAP_INT#/GPIO4C WLAN_OFF_LED# <26>
3 6 EC_SMB_CK2 KSI6 61 PS2 Interface 86
4 5 EC_SMB_DA2 KSI7 62 KSI6/GPIO36 EAPD/GPIO4D 87 TP_CLK
<26> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <26>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <26>
KSO1 40
2.2K_0804_8P4R_5% KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 EC_PME# EC_FB_CLAMP_TGL_REQ# RK60 1 @DIS@ 2 10K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_PME# <23,9>
KSO4 43 98
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 HDA_SDO
WL_PWREN_EC <21> <PV>N15V don,t support GC6,RK60 change to @DIS@.
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
HDA_SDO <6>
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <44>
KSO7 46 SPI Device Interface
KSO8 47 KSO7/GPIO27
KSO9 48 KSO8/GPIO28 119
EC_SPI_SO <7>
<SI> Update Pin119 and Pin120 net name
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 +3VALW
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SI <7>
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <7>
KSO12 51 128 TP_CLK RK2 1 2 4.7K_0402_5%
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <7>
KSO13 52
KSO14 53 KSO13/GPIO2D TP_DATA RK4 1 2 4.7K_0402_5%
KSO15 54 KSO14/GPIO2E 73 TOUCH_ON#
KSO15/GPIO2F ENBKL/AD6/GPIO40 TOUCH_ON# <19>
KSO16 81 74 EC_FB_CLAMP_TGL_REQ# EC_FB_CLAMP_TGL_REQ# <9>
@ KSO17 82 KSO16/GPIO48 PECI_KB930/AD7/GPIO41 89 AOAC_PME#
KSO17/GPIO49 FSTCHG/GPIO50 AOAC_PME# <8>
+3VS RK36 1 2 10K_0402_5% EC_SCI# 90
BATT_CHG_LED#/GPIO52 BAT_CHG_LED <44>
91 CAP_LOCK#
CAPS_LED#/GPIO53 CAP_LOCK# <26>
EC_SMB_CK1 77 GPIO 92 PWR_LED#
<28,45,46> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <27>
EC_SMB_DA1 78 93
<28,45,46> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 WLAN_ON_LED# <26>
EC_SMB_CK2 RK39 1 short@ 2 0_0402_5% EC_SMB_CK2_R 79 SM Bus 95 SYSON
<18,32,7> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <40,48> +3VL
EC_SMB_DA2 RK40 1 2 0_0402_5% EC_SMB_DA2_R 80 121 BT_ON_EC
<18,32,7> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 BT_ON_EC <21>
short@ 127 PCH_DPWROK
PM_SLP_S4#/GPIO59 PCH_DPWROK <8>
RP8
PCH_RSMRST# <8>
<8> PM_SLP_S3# PM_SLP_S3# 6 100 PCH_RSMRST# CK10 2 1 100P_0402_50V8J ECAGND PCH_PWR_EN 8 1
PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PLT_RST# 7 2
<8> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <9>
B <8> SUSACK# SUSACK# 15 102 VCIN1_PH VCIN1_PH <44> EC_ON 6 3 B
16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC EC_ACIN 5 4
<21> MINI1_LED# GPIO0A H_PROCHOT#_EC/GPXIOA06
PCH_SUSWARN# 17 104 MAINPWON
<8> PCH_SUSWARN# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <47>
18 GPO 105 EC_BKOFF# EC_BKOFF# <18> 100K_0804_8P4R_5%
19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT#
<6> EC_+1.05VS_PG GPIO0D GPIO PBTN_OUT#/GPXIOA09 PBTN_OUT# <8>
25 107 PCH_PWR_EN
<19> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <42>
FAN_SPEED1 28 108 USB_ON# USB_ON# <24>
<27> FAN_SPEED1 PM_SLP_SUS# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
<8> PM_SLP_SUS# EC_PME#/GPIO15
E51TXD_P80DATA 30
<21> E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN
<21> E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01
PCH_PWROK 32 112 EC_ON
<8> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <47>
AC_LED# 34 114 ON/OFF#
<44> AC_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF# <27>
36 GPI 115 LID_SW# LID_SW# <27>
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
SUSP#/GPXIOD05 SUSP# <40,48,49,52,55>
117 NMI_DBG#
GPXIOD06 118 EC_PECI RK34 1 2
PECI_KB9012/GPXIOD07 H_PECI <4>
AGND/AGND

<32> GPU_THERMAL_DET# GPU_THERMAL_DET# 122 43_0402_1%


123 XCLKI/GPIO5D 124 +V18R +3VALW_EC
GND/GND
GND/GND
GND/GND
GND/GND

XCLKO/GPIO5E V18R
1
GND0

CK17
LID_SW# RK44 2 1 47K_0402_5%
4.7U_0603_6.3V6K
KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113

69

Part Number = SA00004OB30 20mil

LK2
ECAGND 2 1
FBMA-L11-160808-800LMT_0603

@ RK49 100K_0402_5% +3VALW_EC


1 2 PCH_DPWROK ECAGND <44>
@ RK50 100K_0402_5%
1

A A
1 2 PCH_PWROK
RK18
10K_0402_5%
2

NMI_DBG# 1 2

DK2
NMI_DBG#_CPU <9> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
CH751H-40PT_SOD323-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9012
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 30 of 54
5 4 3 2 1
5 4 3 2 1

BOM control

Platform Silego P/N Compal PN 25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark


D
Intel ULT UMA SLG3NB3375V SA00006RE00 1 1 1 X X GCLKUMA@ D

Intel ULT Dis SLG3NB3374V SA00006RD00 1 1 1 1 X GCLKDIS@

Base on  A32 32.768KHz use 10ppm, G‐CLK 25MHz X'TAL use 10ppm.

+RTCBATT

+RTCVCC

1
RG106 GCLK@

1
330_0402_5%
+3VGS +1.05VS +LAN_VDD_3V3 +3VL +3VALW RG107 @
0_0402_5%

2
GCLKDIS@ 1 1 GCLK@ 1 GCLK@ 1 GCLK@ 1 GCLK@

2
Depop if GCLK

2.2U_0603_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

C with UMA CG47 CG48 CG49 CG50 0.1U_0402_10V7K CG51 1 C


CG52 1
2 2 2 2 2 22U_0805_6.3V6M

CG53
GCLK@
GCLK@ 2 GCLKDIS@
UG2 2

GCLK_VRTC 10 14 RTC_VOUT
VBAT VDD_RTC_OUT
Place close +3VL 15 CPU 32.768M(P.6)
+V3.3A
to UG2.8
+3VALW 2 @
Place RG114 close to YC1 <SI> Change RG109 to 33 ohm recommend by vender
VDD 9 PCH_RTCX1_R 1 2
32kHz PCH_RTCX1 <6> VGA 27M(P.32)
RG114 0_0402_5% Place RG110 close to YV1 <CPU RTC>
GCLKDIS@ GCLKDIS@
+3VGS 11 12 VGA_X1_R RG109 1 2 33_0402_5% XTALIN_R 1 2 <GPU>
VDDIO_27M 27MHz XTALIN <32>
RG110 0_0402_5%
Check Power Rail  +LAN_VDD_3V3 8 6 LAN_X1_R RG1111 2 33_0402_5% XTLI_R 1 2 <LAN>
VDDIO_25M_A 25MHz_A XTLO <23>
GCLK@ RG112 GCLK@ 0_0402_5%
+1.05VS 3 5 PCH_X1_R RG1131 2 0_0402_5% <CPU>
VDDIO_25M_B 25MHz_B CPU_XTAL24_IN <7>
GCLK@ LAN 25M(P.23)

1
CLK_X1 1 CPU_CLK 24M(P.7) Place RG112 close to YL1
CLK_X2 16 XTAL_IN CG54
XTAL_OUT Place RG113 close to YC2

GND1
GND2
GND3

GND4
5P_0402_50V8C

2
GCLK@
S CRYSTAL 25MHZ 12PF +-10PPM FL2500048
SJ10000G600 S IC SLG3NB3374VTR TQFN 16P CRYSTAL RG3, RG7,RG8, RG6 0ohm_0402

4
7
13

17
SA00006RD00 for isolated CLK tail
YG1 GCLK@
4 3 CLK_X2
GND OUT
2 2
GCLK@ 1 2 GCLK@
CG59 IN GND CG58 VGA_X1_R
18P_0402_50V8J 18P_0402_50V8J UG2 GCLKUMA@
1 1

1
SA00006RE00
CLK_X1 S IC SLG3NB3375VTR TQFN 16P CRYSTAL CG57
5P_0402_50V8C
B B

2
@
<SI> Change CG58, CG59 to 18pf recommend by vender

Reserve CG57 for vendor


Place close to RG109

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/06/10 Deciphered Date 2014/07/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GCLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 31 of 54
5 4 3 2 1
1 2 3 4 5

+3VGS

#9/2 , Add RV191 between.


UV1A GPU_PWR_LEVEL# RV62 1 DIS@ 2 100K_0402_5%

PEG_HTX_C_GRX_P7 AG6
Part 1 of 5 GPU_PWR_LEVEL# and GPU_THERMAL_DET# GPU_GPIO6 RV43 1 DIS@ 2 10K_0402_5%
<10> PEG_HTX_C_GRX_P7 PEX_RX0
PEG_HTX_C_GRX_N7 AG7 C6 GPU_GPIO0
<10> PEG_HTX_C_GRX_N7 PEX_RX0_N GPIO0
PEG_HTX_C_GRX_P8 AF7 B2 NVVDD_PSI RV44 1 DIS@ 2 10K_0402_5%
<10> PEG_HTX_C_GRX_P8 PEX_RX1 GPIO1
PEG_HTX_C_GRX_N8 AE7 D6
<CPU> <10>
<10>
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P9 AE9 PEX_RX1_N GPIO2 C7 GPU_GPIO8 RV46 1 DIS@ 2 10K_0402_5%
PEG_HTX_C_GRX_N9 AF9 PEX_RX2 GPIO3 F9
<10> PEG_HTX_C_GRX_N9 PEX_RX2_N GPIO4
PEG_HTX_C_GRX_P10 AG9 A3 GPU_GPIO9 RV48 1 DIS@ 2 10K_0402_5%
<10> PEG_HTX_C_GRX_P10 PEX_RX3 GPIO5
A PEG_HTX_C_GRX_N10 AG10 A4 GPU_GPIO6 A
<10> PEG_HTX_C_GRX_N10 PEX_RX3_N GPIO6
AF10 B6
PEX_RX4 GPIO7

GPIO
AE10 A6 GPU_GPIO8
AE12 PEX_RX4_N GPIO8 F8 GPU_GPIO9
AF12 PEX_RX5 GPIO9 C5
AG12 PEX_RX5_N GPIO10 E7 NVVDD_PWM_VID
PEX_RX6 GPIO11 NVVDD_PWM_VID <53>
AG13 D7 GPU_PWR_LEVEL# RV191 1 DIS@ 2 0_0402_5%
AF13 PEX_RX6_N GPIO12 B4 NVVDD_PSI
GPU_THERMAL_DET# <30> CHECK!! GPU_GPIO0 RV49 1 DIS@ 2 10K_0402_5%
PEX_RX7 GPIO13 NVVDD_PSI <53>
AE13 B3
AE15 PEX_RX7_N GPIO14 C3
AF15 NC GPIO15 D5
AG15 NC GPIO16 D4
AG16 NC GPIO17 C2
AF16 NC GPIO18 F7
AE16 NC GPIO19 E6
AE18 NC GPIO20 C4
AF18 NC GPIO21
AG18 NC
AG19 NC
AF19 NC AE3
AE19 NC
NC
DACA_HSYNC
DACA_VSYNC
AE4 #8/19 ,N15V-GM didn't support GC6,
AE21
AF21 NC AG3 unpop QV13 ,QV14.

DACA
AG21 NC DACA_RED AF3
AG22 NC DACA_BLUE AF4
NC DACA_GREEN
PEG_GTX_C_HRX_P7 CV1 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P7 AC9 AE2

PCI EXPRESS
<10> PEG_GTX_C_HRX_P7 PEX_TX0 DACA_VREF
PEG_GTX_C_HRX_N7 CV2 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N7 AB9 AF2
<10> PEG_GTX_C_HRX_N7 PEX_TX0_N DACA_RSET
PEG_GTX_C_HRX_P8 CV3 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P8 AB10
<10> PEG_GTX_C_HRX_P8 PEX_TX1
PEG_GTX_C_HRX_N8 CV4 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N8 AC10
<CPU> <10>
<10>
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P9 CV5 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P9 AD11 PEX_TX1_N
PEG_GTX_C_HRX_N9 CV6 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N9 AC11 PEX_TX2 AE5 GPU_JTAG_TCK
<10> PEG_GTX_C_HRX_N9 PEX_TX2_N JTAG_TCK
PEG_GTX_C_HRX_P10 CV7 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P10 AC12 AE6
<10> PEG_GTX_C_HRX_P10 PEX_TX3 JTAG_TDI T1402
PEG_GTX_C_HRX_N10 CV8 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N10 AB12 AF6
<10> PEG_GTX_C_HRX_N10 T1403

TEST
AB13 PEX_TX3_N JTAG_TDO AD6
B PEX_TX4 JTAG_TMS T1404 B
AC13 AG4 GPU_JTAG_TRST
AD14 PEX_TX4_N JTAG_TRST_N
AC14 PEX_TX5 AD9 TESTMODE
AC15 PEX_TX5_N TESTMODE
AB15 PEX_TX6
AB16 PEX_TX6_N
AC16 PEX_TX7 B7 I2CA_SCL RV14 1 DIS@ 2 2.2K_0402_5%
AD17 PEX_TX7_N I2CA_SCL A7 I2CA_SDA RV15 1 DIS@ 2 2.2K_0402_5%
AC17 NC I2CA_SDA #08/22,unused I2C change to pull‐down.
AC18 NC C9 I2CB_SCL +3VGS DIS@ RV16
AB18 NC I2CB_SCL C8 I2CB_SDA I2CB_SDA 1 8
AB19 NC I2CB_SDA I2CB_SCL 2 7

I2C
AC19 NC A9 I2CC_SCL I2CC_SDA 3 6
AD20 NC I2CC_SCL B9 I2CC_SDA +3VGS DIS@ RV36 I2CC_SCL 4 5
AC20 NC I2CC_SDA GPU_JTAG_TCK 1 8
AC21 NC D9 I2CS_SCL RV21 1 DIS@ 2 2.2K_0402_5% TESTMODE 2 7 2.2K_0804_8P4R_5%
AB21 NC I2CS_SCL D8 I2CS_SDA RV22 1 DIS@ 2 2.2K_0402_5% GPU_JTAG_TRST 3 6
AD23 NC I2CS_SDA GPU_CLKREQ#_R 4 5
#08/22,unused I2C change to pull‐down.
AE23 NC
NC Internal Thermal Sensor
AF24
AE24 NC A10 XTALSSIN RV23 1 DIS@ 2 10K_0402_5% 10K_0804_8P4R_5%
AG24 NC XTAL_SSIN
AG25 NC C10 XTALOUT RV25 1 DIS@ 2 10K_0402_5%
NC XTAL_OUTBUFF

CLK
AE8 B10 XTAL_OUT
<7> CLK_PCIE_GPU PEX_REFCLK XTAL_OUT
AD8
<CPU> <7> CLK_PCIE_GPU# PEX_REFCLK_N C11 XTALIN
1 DIS@ 2 PEX_TSTCLK_OUT AF22 XTAL_IN
RV26 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT
Differential signal PEX_TSTCLK_OUT_N +3VGS
1 2 PEX_TERMP AF25 AB6
RV27 DIS@ 2.49K_0402_1% PEX_TERMP NC
PLT_RST_VGA# AC7 D10 RV58 1 DIS@ 2 10K_0402_5%
PEX_RST_N NC
C GPU_CLKREQ#_R AC6 E9 C
PEX_CLKREQ_N NC

5
N15V-GM
DIS@ QV2B DIS@
I2CS_SCL 4 3
EC_SMB_CK2 <18,30,7>
2N7002KDWH_SOT363-6
+3VGS
10K_0402_5% RV13 1 @ 2 0_0402_5%
+3VGS +3VGS RV182
DIS@
1 2

2
CV12

0.01U_0402_16V7K
1 QV2A DIS@
SI 11/05 change RV182.1 I2CS_SDA 1 6
EC_SMB_DA2 <18,30,7>
1

RV183 1 2 change to +3VGS from GPU_PWR_EN

DIS@
@ 0_0402_5% RV184 2N7002KDWH_SOT363-6
10K_0402_5% 2
@ RV20 1 @ 2 0_0402_5%
5

2
UV11
2

PLT_RST# 1 PU AT EC SIDE, +3VS AND 4.7K

G
P

<21,23,28,30,8> PLT_RST# B 4 PLT_RST_VGA#


DGPU_HOLD_RST# 2 Y 1 3 GPU_CLKREQ#_R
<30,9> DGPU_HOLD_RST# A <7,8> GPU_CLKREQ#
G

S
1

TC7SH08FUF_SSOP5 1
3

1
DIS@ RV186 @ CV17 QV10 DIS@ XTALIN XTALDIS@
EC or CPU control 10K_0402_5% 2N7002K_SOT23-3 RV187
XTALIN <31>
RV24 1 2 10M_0402_5%
DIS@ 0.1U_0402_16V7K 10K_0402_5%
2 1 @ 2 @ XTALDIS@
2

YV1

2
RV188 0_0402_5%
XTALIN 1 3 XTAL_OUT
1 3
GND GND

10P_0402_50V8J

10P_0402_50V8J
1 1
CV9 CV10
D 2 4 D
XTALDIS@ XTALDIS@
2 27MHZ 10PF 5YEA27000102IF50Q3 2

<PV>CV9,CV10 change to 10pf.

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15V-GM
Size Document Number
PCIE/DAC/GPIO Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 32 of 54
1 2 3 4 5
1 2 3 4 5

UV1C
Part 3 of 5
AC3 D1 STRAP0
IFPA_TXC STRAP0 STRAP0 <39>
AC4 D2 STRAP1

STRAP
IFPA_TXC_N STRAP1 STRAP1 <39>
Y4 E4 STRAP2
IFPA_TXD0 STRAP2 STRAP2 <39>
Y3 E3 STRAP3
A IFPA_TXD0_N STRAP3 STRAP3 <39> A
AA3 D3 STRAP4
IFPA_TXD1 STRAP4 STRAP4 <39>
AA2 C1
AB1 IFPA_TXD1_N NC
AA1 IFPA_TXD2
AA4 IFPA_TXD2_N
AA5 IFPA_TXD3
IFPA_TXD3_N DIS@

GENERAL
D11 RV28 1 2 100K_0402_5%
AB5 BUFRST_N
AB4 IFPB_TXC E12
AB3 IFPB_TXC_N THERMDN F12
AB2 IFPB_TXD4 THERMDP
AD3 IFPB_TXD4_N

LVDS / TMDS
AD2 IFPB_TXD5
AE1 IFPB_TXD5_N DIS@
AD1 IFPB_TXD6 D12 ROM_CS RV29 1 2 10K_0402_5%
IFPB_TXD6_N ROM_CS_N +3VGS
AD4
AD5 IFPB_TXD7 C12 ROM_SCLK
ROM_SCLK <39>

SERIAL
IFPB_TXD7_N ROM_SCLK
B12 ROM_SI
ROM_SI ROM_SI <39>
N4
N5 IFPC_AUX_I2CW_SCL A12 ROM_SO
IFPC_AUX_I2CW_SDA_N ROM_SO ROM_SO <39>
T2
T3 IFPC_L0
B
T1 IFPC_L0_N B

R1 IFPC_L1 AA6
R2 IFPC_L1_N IFPAB_RSET
R3 IFPC_L2 T6
N2 IFPC_L2_N IFPC_RSET
N3 IFPC_L3 U6
IFPC_L3_N IFPD_RSET
K6
P3 NC
P4 IFPD_AUX_I2CX_SCL
V3 IFPD_AUX_I2CX_SDA_N
V4 IFPD_L0 AD10
U3 IFPD_L0_N NC AD7
U4 IFPD_L1 NC B19
T4 IFPD_L1_N NC
T5 IFPD_L2 G1
R4 IFPD_L2_N NC_G1 G2
R5 IFPD_L3 NC_G2 G3
IFPD_L3_N NC_G3 G4
NC_G4 G5
J2 NC_G5 G6
J3 IFPE_AUX_I2CY_SCL NC_G6 G7
N1 IFPE_AUX_I2CY_SDA_N NC_G7
M1 NC V1
C C
M2 NC NC_V1 V2
M3 NC NC_V2 V5
K2 NC NC_V5 V6
K3 NC NC_V6
K1 NC W1
J1 NC NC_W1 W2
NC NC_W2 W3
NC_W3 W4
H3 NC_W4
H4 IFPF_AUX_I2CZ_SCL
M4 IFPF_AUX_I2CZ_SDA_N
M5 NC
L3 NC E10
L4 NC NC F10
K4 NC NC
K5 NC
J4 NC
J5 NC
NC

N15V-GM

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N15V-GM LVDS/HDMI/DP/THM Rev
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 33 of 54
1 2 3 4 5
1 2 3 4 5

+1.5VGS
UV1D
Part 4 of 5
B26 K10 +VGA_CORE
C25 FBVDDQ VDD K12
FBVDDQ VDD

CV28

0.1U_0402_10V7K

CV20

0.1U_0402_10V7K

CV21

1U_0402_6.3V6K

CV22

1U_0402_6.3V6K

CV23

4.7U_0603_6.3V6K

CV24

4.7U_0603_6.3V6K

CV29

10U_0603_6.3V6M

CV26

22U_0805_6.3V6M
E23 K14
E26 FBVDDQ VDD K16
1 1 1 1 1 1 1 1 FBVDDQ VDD
F14 K18
F21 FBVDDQ VDD L11
FBVDDQ VDD

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
G13 L13
2 2 2 2 2 2 2 2 G14 FBVDDQ VDD L15
G15 FBVDDQ VDD L17
G16 FBVDDQ VDD M10
G18 FBVDDQ VDD M12
G19 FBVDDQ VDD M14
Reference circuit: FBVDDQ VDD
A G20 M16 A
0.1uF *2 G21 FBVDDQ VDD M18
H24 FBVDDQ VDD N11
1 uF*2 FBVDDQ VDD
H26 N13
4.7uF*2 J21 FBVDDQ VDD N15
K21 FBVDDQ VDD N17
10uF*1 FBVDDQ VDD
L22 P10
22uF*1 L24 FBVDDQ VDD P12
L26 FBVDDQ VDD P14
M21 FBVDDQ VDD P16
N21 FBVDDQ VDD P18
R21 FBVDDQ VDD R11
T21 FBVDDQ VDD R13
V21 FBVDDQ VDD R15
W21 FBVDDQ VDD R17
FBVDDQ VDD

POWER
T10
AA10 VDD T12
+1.05VGS PEX_IOVDDQ VDD
AA12 T14
PEX_IOVDDQ VDD

CV51

1U_0402_6.3V6K

CV52

1U_0402_6.3V6K

CV53

4.7U_0603_6.3V6K

CV54

10U_0805_6.3V6M

CV55

10U_0805_6.3V6M

CV56

22U_0805_6.3V6M

CV57

22U_0805_6.3V6M
AA13 T16
AA16 PEX_IOVDDQ VDD T18
Reference circuit: 1 1 1 1 1 1 1 PEX_IOVDDQ VDD
AA18 U11
1uF *2 AA19 PEX_IOVDDQ VDD U13
PEX_IOVDDQ VDD
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
4.7uF*1 AA20 U15
2 2 2 2 2 2 2 AA21 PEX_IOVDDQ VDD U17
10uF*2 AB22 PEX_IOVDDQ VDD V10
AC23 PEX_IOVDDQ VDD V12
22uF*2 PEX_IOVDDQ VDD
AD24 V14
AE25 PEX_IOVDDQ VDD V16
AF26 PEX_IOVDDQ VDD V18 Power :VDD_SENSE & GND_SENSE
AF27 PEX_IOVDDQ VDD Differential signal
PEX_IOVDDQ F2 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <53>
CV58

1U_0402_6.3V6K

CV59

1U_0402_6.3V6K

CV60

4.7U_0603_6.3V6K

CV61

10U_0805_6.3V6M

CV62

10U_0805_6.3V6M

CV63

22U_0805_6.3V6M

CV69

22U_0805_6.3V6M
Reference circuit: AA22
AB23 PEX_IOVDD G10 short@1 RV30 2
1 1 1 1 1 1 1 +3VGS
1uF *2 PEX_IOVDD VDD33

CV64

0.1U_0402_10V7K

CV65

0.1U_0402_10V7K

CV66

0.1U_0402_10V7K

CV67

1U_0402_6.3V6K

CV68

4.7U_0603_6.3V6K
AC24 G12 0_0603_5%
AD25 PEX_IOVDD VDD33 G8
B 4.7uF*1 PEX_IOVDD VDD33 1 1 1 1 1 B
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
AE26 G9
10uF*2 2 2 2 2 2 2 2 AE27 PEX_IOVDD VDD33
PEX_IOVDD

DIS@

DIS@

DIS@

DIS@

DIS@
22uF*2 F11
NC 2 2 2 2 2

+PEX_3V3_NV AA8 AB8 +PEX_3V3_NV


AA9 PEX_PLL_HVDD PEX_SVDD_3V3
PEX_PLL_HVDD W6
IFPA_IOVDD Y6
<SI> LV1 use R_0402 footprint +PEXPLL_VDD AA14 IFPB_IOVDD P6
RV34 1 2 0_0402_5% +PEX_3V3_NV DIS@ AA15 PEX_PLLVDD IFPC_IOVDD R6
+3VGS PEX_PLLVDD IFPD_IOVDD
short@ LV1 +GPU_SP_PLLVDD N6 H6
VID_PLLVDD NC
CV70

0.1U_0402_10V7K

CV71

4.7U_0603_6.3V6K

CV72

4.7U_0603_6.3V6K

BLM18PG121SN1D_0603 M6 J6
1 2 +GPU_PLLVDD L6 SP_PLLVDD NC
1 1 1 +1.05VGS CORE_PLLVDD
+FB_PLLAVDD F16 V7 Remove IFPC_PLLVDD,IFPD_PLLVDD,IFPC_IOVDD,IFPD_IOVDD,IFPAB_PLLVDD,+DACA_VDD,IFPA_IOVDD
FB_PLLAVDD IFPAB_PLLVDD

CV73

0.1U_0402_10V7K

CV74

22U_0805_6.3V6M
#8/19,LV1 change to P22 W7
FB_PLLAVDD IFPAB_PLLVDD
DIS@

DIS@

DIS@

1 1 H22
2 2 2 Z=30 ohm , RDC=0.05 FB_DLLAVDD M7
SM01000F100 IFPC_PLLVDD N7
IFPC_PLLVDD
DIS@

DIS@
W5
PCB Footprint = R_0402 2 2 DACA_VDD R7
+FB_CAL_PD_VDDQ D22 IFPD_PLLVDD T7
FB_CAL_PD_VDDQ IFPD_PLLVDD
F3 J7
RV45 1 2 0_0402_5% +PEXPLL_VDD FB_CLAMP NC K7
+1.05VGS FB_CLAMP NC
short@
CV75

0.1U_0402_10V7K

CV76

1U_0402_6.3V6K

CV77

4.7U_0603_6.3V6K

RV47 1 2 0_0402_5%
<9> DGPU_GC6_EN
1 1 1 short@
DIS@

DIS@

DIS@

2 2 2 N15V-GM
DIS@

C C

DIS@
LV3
BLM18PG121SN1D_0603
+1.05VGS 1 2 +GPU_SP_PLLVDD

DG : LV3 ‐>Z=180 ohm , RDC=0.2 ohm.0603
CV82

0.1U_0402_10V7K

CV83

0.1U_0402_10V7K

CV84

4.7U_0603_6.3V6K

CV85

22U_0805_6.3V6M

1 1 1 1 DIS@
1 2 +FB_CAL_PD_VDDQ
<PV>LV3,LV4 change PN. +1.5VGS
RV50 40.2_0402_1%
DIS@

DIS@

DIS@

DIS@

Main:SM01000BW00 2 2 2 2 #7/27 Follow DG to chenge


R1591 to 40.2 ohm
2nd:SM01000CC00

DG:LV4‐>Z=30 ohm , RDC=0.01 ohm.0603 +FB_PLLAVDD
LV4 DIS@
BLM18PG121SN1D_0603
+1.05VGS 1 2
CV91

0.1U_0402_10V7K

CV90

0.1U_0402_10V7K

CV88

0.1U_0402_10V7K

CV89

22U_0805_6.3V6M

1 1 1 1
DIS@

DIS@

DIS@

DIS@

2 2 2 2

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15V-GM
Size Document Number
POWER Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 34 of 54
1 2 3 4 5
1 2 3 4 5

UV1E
Part 5 of 5
AA7 L10
A2 GND GND L12
A26 GND GND L14
AB11 GND GND L16
AB14 GND GND L18
AB17 GND GND L2
AB20 GND GND L23
AB24 GND GND L25
AC2 GND GND L5
AC22 GND GND M11
AC26 GND GND M13
AC5 GND GND M15
A A
AC8 GND GND M17
AD12 GND GND N10
AD13 GND GND N12
AD15 GND GND N14
AD16 GND GND N16
AD18 GND GND N18
AD19 GND GND P11
GND
AD21 GND GND P13
AD22 GND GND P15
AE11 GND GND P17
AE14 GND GND P2 #8/20 : N15V‐GM don't support GC6 function. UV20 unpop.
AE17 GND GND P23
AE20 GND GND P26
AF1 GND GND P5
AF11 GND GND R10
AF14 GND GND R12
AF17 GND GND R14
AF20 GND GND R16
AF23 GND GND R18
AF5 GND GND T11
AF8 GND GND T13
AG2 GND GND T15
AG26 GND GND T17
B1 GND GND U10
B11 GND GND U12
B14 GND GND U14
B17 GND GND U16
B20 GND GND U18
B23 GND GND U2
B27 GND GND U23
B5 GND GND U26
B8 GND GND U5
E11 GND GND V11
E14 GND GND V13
B
E17 GND GND V15 B
E2 GND GND V17
E20 GND GND Y2
E22
E25
E5
GND
GND
GND
GND
GND
GND
Y23
Y26
Y5
+1.05VGS=1.6A,4vias. J2 @
E8 GND GND AB7 2 1
GND GND +1.05V_GPU 2 1 +1.05VGS
H2
H23 GND C24 1 DIS@ 2 JUMP_43X79
H25 GND FB_CAL_PU_GND RV67 42.2_0402_1%
H5 GND B25 1 DIS@ 2
K11 GND FB_CAL_TERM_GND RV68 51.1_0402_1%
K13 GND F6 1 2 40.2K_0402_1%
K15 GND MULTI_STRAP_REF0_GND F4 RV70 @ #8/19.RV70 unpop , N15V‐GM  use binary mode. +3VALW to +3VGS
K17 GND NC F5
GND NC Contrl by power
GND_SENSE
F1 VSSSENSE_VGA
VSSSENSE_VGA <53> +1.05V to +1.05VGS +1.05V_GPU

N15V-GM
DIS@ Power :VDD_SENSE & GND_SENSE
+3VALW +1.05V
Differential signal DIS@
QV12
1 14
Power on RV92
2 VIN1 VOUT1 13
VIN1 VOUT1
DGPU_PWROK DIS@ 3 12 CV181 1 2 680P_0402_50V7K
ON1 CT1
DGPU_PWR_EN +5VALW 20K_0402_5% 4 11 DIS@
VBIAS GND
<30,53,9> DGPU_PWR_EN DGPU_PWR_EN 5 10 CV182 1 2 100P_0402_50V8J
+3VGS
+1.5VGS=3.6A,8vias.
J3 @
6
7
ON2

VIN2 VOUT2
CT2
9
8
DIS@

C +VGA_CORE +1.5VGS_GPU 2 1 +1.5VGS


VIN2 VOUT2
C
2 1 15
JUMP_43X118 GPAD
DGPU_PWROK #8/19.QV15 change to TPS22967 TPS22966DPUR_SON14_2X3-D
+3VGS

+1.05VGS +1.5V to +1.5VGS +3VGS=0.5A,2vias.


+1.5VGS_GPU
+1.5VGS +1.5VS QV15

1 7 +1.05VGS
2 VIN VOUT 8
40us < Rt < 2ms 1
VIN VOUT +3VALW
DIS@ CV81 3 6
ON CT

2
1 1 1 DIS@
10U_0603_6.3V6M DIS@ CV80 CV79 RC370 DIS@
2 4 CV183 DIS@
+5VALW VBIAS 18_0402_5%

1
1U 6.3V K X5R 0402
5
GND 2 2 2

100P_0402_50V8J

10U_0603_6.3V6M
9 RV210 SD028180A80

1
GND DIS@
DIS@ 100K_0402_5%

3
<53> DGPU_PWROK DGPU_PWROK RV66 1 2 TPS22967DSGR_SON8_2X2

2
47K_0402_5% 1
#08/20 Don't support GC6,Add RV66. DIS@
CV78 @ 5 QV17B
Unpop QV16,RV41,RV42,CV78. 0.01U_0603_50V7K DMN66D0LDW-7_SOT363-6

6
2

4
DIS@
DGPU_PWROK 2 QV17A
DMN66D0LDW-7_SOT363-6

1
D D

PV# 2013.01.08 Add +1.05VGS discharge circuit

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15V-GM
Size Document Number
VGA CORE, GND Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 35 of 54
1 2 3 4 5
1 2 3 4 5

PU for X16 mode


UV1B
Part 2 of 5
MDA0 E18 C27 CMDA0
<37> MDA0 FBA_D0 FBA_CMD0 CMDA0 <37>
A MDA1 F18 C26 Dummy A
<37> MDA1 FBA_D1 FBA_CMD1
MDA2 E16 E24 CMDA2 Note: DG use 1%
<37> MDA2 FBA_D2 FBA_CMD2 CMDA2 <37>
MDA3 F17 F24 CMDA3
<37> MDA3 FBA_D3 FBA_CMD3 CMDA3 <37>
MDA4 D20 D27 CMDA4
<37> MDA4 FBA_D4 FBA_CMD4 CMDA4 <37,38>
MDA5 D21 D26 CMDA5 DIS@
<37> MDA5 FBA_D5 FBA_CMD5 CMDA5 <37,38>
MDA6 F20 F25 CMDA6 2 RV169 1 CMDA2
<37> MDA6 FBA_D6 FBA_CMD6 CMDA6 <37,38>
MDA7 E21 F26 CMDA7 10K_0402_1%
<37> MDA7 FBA_D7 FBA_CMD7 CMDA7 <37,38>
MDA8 E15 F23 CMDA8 DIS@
<37>
<37>
MDA8
MDA9
MDA9 D15 FBA_D8
FBA_D9
FBA_CMD8
FBA_CMD9
G22 CMDA9
CMDA8 <37,38>
CMDA9 <37,38>
2 RV170 1 CMDA18 Mode D Command Mapping
MDA10 F15 G23 CMDA10 10K_0402_1%
<37> MDA10 FBA_D10 FBA_CMD10 CMDA10 <37,38>
MDA11 F13 G24 CMDA11 DIS@ RANK 0
<37> MDA11 FBA_D11 FBA_CMD11 CMDA11 <37,38>
MDA12 C13 F27 CMDA12 2 RV185 1 CMDA3
<37> MDA12 FBA_D12 FBA_CMD12 CMDA12 <37,38>
MDA13 B13 G25 CMDA13 10K_0402_1% Address 0..31 32..63
<37> MDA13 FBA_D13 FBA_CMD13 CMDA13 <37,38>
MDA14 E13 G27 Dummy DIS@
<37> MDA14 FBA_D14 FBA_CMD14
MDA15 D13 G26 CMDA15 2 RV189 1 CMDA19 FBx_CMD0 CS0#
<37> MDA15 FBA_D15 FBA_CMD15 CMDA15 <37,38>
MDA16 B15 M24 CMDA16 10K_0402_1%
<37> MDA16 FBA_D16 FBA_CMD16 CMDA16 <38>
MDA17 C16 M23 Dummy DIS@ FBx_CMD1
<37> MDA17 FBA_D17 FBA_CMD17
MDA18 A13 K24 CMDA18 2 RV190 1 CMDA5
<37> MDA18 FBA_D18 FBA_CMD18 CMDA18 <38>
MDA19 A15 K23 CMDA19 10K_0402_1% FBx_CMD2 ODT
<37> MDA19 FBA_D19 FBA_CMD19 CMDA19 <38>
MDA20 B18 M27 CMDA20
<37> MDA20 FBA_D20 FBA_CMD20 CMDA20 <37,38>
MDA21 A18 M26 CMDA21 FBx_CMD3 CKE
<37> MDA21 FBA_D21 FBA_CMD21 CMDA21 <37,38>
MDA22 A19 M25 CMDA22
<37> MDA22 FBA_D22 FBA_CMD22 CMDA22 <37,38>
MDA23 C19 K26 CMDA23 FBx_CMD4 A14 A14
<37> MDA23 FBA_D23 FBA_CMD23 CMDA23 <37,38>
MDA24 B24 K22 CMDA24
<37> MDA24 FBA_D24 FBA_CMD24 CMDA24 <37,38>
MDA25 C23 J23 CMDA25 FBx_CMD5 RST RST

MEMORY INTERFACE
<37> MDA25 FBA_D25 FBA_CMD25 CMDA25 <37,38>
MDA26 A25 J25 CMDA26
<37> MDA26 FBA_D26 FBA_CMD26 CMDA26 <37,38>
MDA27 A24 J24 CMDA27 FBx_CMD6 A9 A9
<37> MDA27 FBA_D27 FBA_CMD27 CMDA27 <37,38>
MDA28 A21 K27 CMDA28
<37> MDA28 FBA_D28 FBA_CMD28 CMDA28 <37,38>
MDA29 B21 K25 CMDA29 FBx_CMD7 A7 A7
<37> MDA29 FBA_D29 FBA_CMD29 CMDA29 <37,38>
MDA30 C20 J27 CMDA30
<37> MDA30 FBA_D30 FBA_CMD30 CMDA30 <37,38>
MDA31 C21 J26 FBx_CMD8 A2 A2
<37> MDA31 FBA_D31 FBA_CMD31
MDA32 R22
<38> MDA32 FBA_D32
MDA33 R24 FBx_CMD9 A0 A0
<38> MDA33 FBA_D33
MDA34 T22 D19 DQMA0
<38> MDA34 FBA_D34 FBA_DQM0 DQMA0 <37>
MDA35 R23 D14 DQMA1 FBx_CMD10 A4 A4
B <38> MDA35 FBA_D35 FBA_DQM1 DQMA1 <37> B
MDA36 N25 C17 DQMA2
<38> MDA36 FBA_D36 FBA_DQM2 DQMA2 <37>
MDA37 N26 C22 DQMA3 FBx_CMD11 A1 A1
<38> MDA37 FBA_D37 FBA_DQM3 DQMA3 <37>
MDA38 N23 P24 DQMA4
<38> MDA38 FBA_D38 FBA_DQM4 DQMA4 <38>
MDA39 N24 W24 DQMA5 FBx_CMD12 BA0 BA0
<38> MDA39 FBA_D39 FBA_DQM5 DQMA5 <38>
MDA40 V23 AA25 DQMA6
<38> MDA40 FBA_D40 FBA_DQM6 DQMA6 <38>
MDA41 V22 U25 DQMA7 FBx_CMD13 WE# WE#
<38> MDA41 FBA_D41 FBA_DQM7 DQMA7 <38>
MDA42 T23
<38> MDA42 FBA_D42
MDA43 U22 F19 DQSA#0 FBx_CMD14
<38> MDA43 FBA_D43 FBA_DQS_RN0 DQSA#0 <37>
MDA44 Y24 C14 DQSA#1
<38> MDA44 FBA_D44 FBA_DQS_RN1 DQSA#1 <37>
MDA45 AA24 A16 DQSA#2 FBx_CMD15 CAS# CAS#
<38> MDA45 FBA_D45 FBA_DQS_RN2 DQSA#2 <37>
MDA46 Y22 A22 DQSA#3
<38> MDA46 FBA_D46 FBA_DQS_RN3 DQSA#3 <37>
MDA47 AA23 P25 DQSA#4 FBx_CMD16 CS0#
<38> MDA47 FBA_D47 FBA_DQS_RN4 DQSA#4 <38>
MDA48 AD27 W22 DQSA#5
<38> MDA48 FBA_D48 FBA_DQS_RN5 DQSA#5 <38>
MDA49 AB25 AB27 DQSA#6 FBx_CMD17
<38> MDA49 FBA_D49 FBA_DQS_RN6 DQSA#6 <38>
MDA50 AD26 T27 DQSA#7
<38> MDA50 FBA_D50 FBA_DQS_RN7 DQSA#7 <38>
MDA51 AC25 FBx_CMD18 ODT
<38> MDA51 FBA_D51
MDA52 AA27 E19 DQSA0
<38> MDA52 FBA_D52 FBA_DQS_WP0 DQSA0 <37>
MDA53 AA26 C15 DQSA1 FBx_CMD19 CKE
<38> MDA53 FBA_D53 FBA_DQS_WP1 DQSA1 <37>
MDA54 W26 B16 DQSA2
<38> MDA54 FBA_D54 FBA_DQS_WP2 DQSA2 <37>
MDA55 Y25 B22 DQSA3 FBx_CMD20 A13 A13
<38> MDA55 FBA_D55 FBA_DQS_WP3 DQSA3 <37>
MDA56 R26 R25 DQSA4
<38> MDA56 FBA_D56 FBA_DQS_WP4 DQSA4 <38>
MDA57 T25 W23 DQSA5 FBx_CMD21 A8 A8
<38> MDA57 FBA_D57 FBA_DQS_WP5 DQSA5 <38>
MDA58 N27 AB26 DQSA6
<38> MDA58 FBA_D58 FBA_DQS_WP6 DQSA6 <38>
MDA59 R27 T26 DQSA7 FBx_CMD22 A6 A6
<38> MDA59 FBA_D59 FBA_DQS_WP7 DQSA7 <38>
MDA60 V26
<38> MDA60 FBA_D60
MDA61 V27 D18 FBx_CMD23 A11 A11
<38> MDA61 FBA_D61 FBA_WCK01
MDA62 W27 C18
<38> MDA62 FBA_D62 FBA_WCK01_N
MDA63 W25 D17 FBx_CMD24 A5 A5
<38> MDA63 FBA_D63 FBA_WCK23 D16
D23 FBA_WCK23_N T24
T1405 FB_VREF_PROBE FBA_WCK45 FBx_CMD25 A3 A3
U24
CLKA0 D24 FBA_WCK45_N V24
<37> CLKA0 FBA_CLK0 FBA_WCK67 FBx_CMD26 BA2 BA2
CLKA0# D25 V25
<37> CLKA0# FBA_CLK0_N FBA_WCK67_N
FBx_CMD27 BA1 BA1
C CLKA1 N22 C
<38> CLKA1 FBA_CLK1
CLKA1# M22 F22 RV137 1 @ 2 60.4_0402_1% +1.5VGS FBx_CMD28 A12 A12
<38> CLKA1# FBA_CLK1_N FBA_DEBUG0 J22 RV138 1 @ 2 60.4_0402_1%
FBA_DEBUG1
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
N15V-GM

DIS@

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15V-GM
Size Document Number
MEM Interface Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 36 of 54
1 2 3 4 5
1 2 3 4 5

Memory Partition A RANK 0 MDA[0..63] <36,38>

CMDA[30..0] <36,38>
+1.5VGS
Data0~Data31
Rank 0 Rank 0
1
RV139
1.33K_0402_1%
DIS@ UV12 X76@ UV14 X76@
2
+FBA_VREF0 +FBA_VREF0 M8 E3 MDA19 +FBA_VREF0 M8 E3 MDA4
A
H1 VREFCA DQL0 F7 MDA21 H1 VREFCA DQL0 F7 MDA0 A
VREFDQ DQL1 VREFDQ DQL1
CV96

0.01U_0402_16V7K
F2 MDA16 F2 MDA5
DQL2 DQL2
1

CMDA9 N3 F8 MDA22 CMDA9 N3 F8 MDA2


RV140
1
CMDA11 P7 A0 DQL3 H3 MDA18 Group 2 CMDA11 P7 A0 DQL3 H3 MDA7
1.33K_0402_1% CMDA8 P3 A1 DQL4 H8 MDA23 CMDA8 P3 A1 DQL4 H8 MDA1 Group 0
A2 DQL5 A2 DQL5
DIS@

DIS@ CMDA25 N2 G2 MDA17 CMDA25 N2 G2 MDA6


2 CMDA10 P8 A3 DQL6 H7 MDA20 CMDA10 P8 A3 DQL6 H7 MDA3 Mode D Command Mapping
2

CMDA24 P2 A4 DQL7 CMDA24 P2 A4 DQL7


CMDA22 R8 A5 CMDA22 R8 A5
A6 A6 RANK 0
CMDA7 R2 D7 MDA10 CMDA7 R2 D7 MDA31
CMDA21 T8 A7 DQU0 C3 MDA13 CMDA21 T8 A7 DQU0 C3 MDA27
A8 DQU1 A8 DQU1
Address 0..31 32..63
CMDA6 R3 C8 MDA11 CMDA6 R3 C8 MDA30
CMDA29 L7 A9 DQU2 C2 MDA14 CMDA29 L7 A9 DQU2 C2 MDA25
A10/AP DQU3 Group 1 A10/AP DQU3 Group 3 FBx_CMD0 CS0#
CMDA23 R7 A7 MDA8 CMDA23 R7 A7 MDA28
CLKA0 CMDA28 N7 A11 DQU4 A2 MDA15 CMDA28 N7 A11 DQU4 A2 MDA26
A12 DQU5 A12 DQU5 FBx_CMD1
CMDA20 T3 B8 MDA9 CMDA20 T3 B8 MDA29
CMDA4 T7 A13 DQU6 A3 MDA12 CMDA4 T7 A13 DQU6 A3 MDA24
A14 DQU7 A14 DQU7 FBx_CMD2 ODT
1

M7 M7
RV141 A15/BA3 +1.5VGS A15/BA3 +1.5VGS FBx_CMD3 CKE
162_0402_1%
DIS@ CMDA12 M2 B2 CMDA12 M2 B2 FBx_CMD4 A14 A14
CMDA27 N8 BA0 VDD D9 CMDA27 N8 BA0 VDD D9
2

CMDA26 M3 BA1 VDD G7 CMDA26 M3 BA1 VDD G7


BA2 VDD BA2 VDD FBx_CMD5 RST RST
CLKA0# K2 K2
VDD K8 VDD K8
VDD VDD FBx_CMD6 A9 A9
#8/19 , change CLK N1 N1
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9
termination to 162 ohm. <36> CLKA0 CK VDD CK VDD FBx_CMD7 A7 A7
CLKA0# K7 R1 CLKA0# K7 R1
<36> CLKA0# CK VDD CK VDD
CMDA3 K9 R9 CMDA3 K9 R9 FBx_CMD8 A2 A2
CKE/CKE0 VDD CKE/CKE0 VDD
B B
160 ohm:SD00000XP00 FBx_CMD9 A0 A0
CMDA2 K1 A1 CMDA2 K1 A1
CMDA0 L2 ODT/ODT0 VDDQ A8 CMDA0 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ FBx_CMD10 A4 A4
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ FBx_CMD11 A1 A1
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ E9 WE VDDQ E9
VDDQ VDDQ FBx_CMD12 BA0 BA0
F1 F1
DQSA2 F3 VDDQ H2 DQSA0 F3 VDDQ H2
<36> DQSA2 DQSL VDDQ <36> DQSA0 DQSL VDDQ FBx_CMD13 WE# WE#
DQSA1 C7 H9 DQSA3 C7 H9
<36> DQSA1 DQSU VDDQ <36> DQSA3 DQSU VDDQ
FBx_CMD14
DQMA2 E7 A9 DQMA0 E7 A9 FBx_CMD15 CAS# CAS#
H:Group 1 <36> DQMA2
<36> DQMA1
DQMA1 D3 DML VSS B3 L:Group 0 <36> DQMA0
<36> DQMA3
DQMA3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
L:Group 2 VSS H:Group 3 VSS FBx_CMD16 CS0#
G8 G8
DQSA#2 G3 VSS J2 DQSA#0 G3 VSS J2
<36> DQSA#2 DQSL VSS <36> DQSA#0 DQSL VSS FBx_CMD17
DQSA#1 B7 J8 DQSA#3 B7 J8
<36> DQSA#1 DQSU VSS <36> DQSA#3 DQSU VSS
M1 M1 FBx_CMD18 ODT
VSS M9 VSS M9
VSS P1 VSS P1
VSS VSS FBx_CMD19 CKE
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS FBx_CMD20 A13 A13
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
FBx_CMD21 A8 A8
1

1
J1 B1 J1 B1 FBx_CMD22 A6 A6
RV145 L1 NC/ODT1 VSSQ B9 RV150 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
C NC/CE1 VSSQ NC/CE1 VSSQ FBx_CMD23 A11 A11 C
DIS@ L9 D8 DIS@ L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 FBx_CMD24 A5 A5
2

2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ VSSQ FBx_CMD25 A3 A3
G1 G1
VSSQ G9 VSSQ G9
VSSQ VSSQ FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VGS Closed to UV12
L
+1.5VGS Closed to UV14
L
CV97

0.1U_0402_16V7K

CV98

0.1U_0402_16V7K

CV99

0.1U_0402_16V7K

CV100

0.1U_0402_16V7K

CV101

0.1U_0402_16V7K

CV102

1U_0402_6.3V6K

CV103

1U_0402_6.3V6K

CV104

1U_0402_6.3V6K

CV105

1U_0402_6.3V6K

CV106

1U_0402_6.3V6K

2 2 2 2 2 1 1 1 1 1
CV118

0.1U_0402_16V7K

CV119

0.1U_0402_16V7K

CV120

0.1U_0402_16V7K

CV121

0.1U_0402_16V7K

CV122

0.1U_0402_16V7K

CV123

1U_0402_6.3V6K

CV124

1U_0402_6.3V6K

CV125

1U_0402_6.3V6K

CV126

1U_0402_6.3V6K

CV127

1U_0402_6.3V6K
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
1 1 1 1 1 2 2 2 2 2

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N15V-GM VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 37 of 54
1 2 3 4 5
1 2 3 4 5

Memory Partition A RANK 0 32 bits MDA[0..63] <36,37>


+1.5VGS
CMDA[30..0] <36,37>

Rank 0
1
RV152
1.33K_0402_1%
DIS@ 2
Data32~Data63 Rank 0
A A
+FBA_VREF1 UV16 X76@ UV18 X76@
CV138

0.01U_0402_16V7K
+FBA_VREF1 M8 E3 MDA35 +FBA_VREF1 M8 E3 MDA52
VREFCA DQL0 VREFCA DQL0
1

1 H1 F7 MDA37 H1 F7 MDA49
RV153 VREFDQ DQL1 F2 MDA34 VREFDQ DQL1 F2 MDA53
1.33K_0402_1% CMDA9 N3 DQL2 F8 MDA39 CMDA9 N3 DQL2 F8 MDA50
A0 DQL3 A0 DQL3 Group 6
DIS@

DIS@ CMDA11 P7 H3 MDA32 CMDA11 P7 H3 MDA54


2 CMDA8 P3 A1 DQL4 H8 MDA38 Group 4 CMDA8 P3 A1 DQL4 H8 MDA48 Mode D Command Mapping
2

CMDA25 N2 A2 DQL5 G2 MDA33 CMDA25 N2 A2 DQL5 G2 MDA55


CMDA10 P8 A3 DQL6 H7 MDA36 CMDA10 P8 A3 DQL6 H7 MDA51
A4 DQL7 A4 DQL7 RANK 0
CMDA24 P2 CMDA24 P2
CMDA22 R8 A5 CMDA22 R8 A5 Address
A6 A6 0..31 32..63
CMDA7 R2 D7 MDA56 CMDA7 R2 D7 MDA44
CMDA21 T8 A7 DQU0 C3 MDA60 CMDA21 T8 A7 DQU0 C3 MDA40
A8 DQU1 A8 DQU1 FBx_CMD0 CS0#
CMDA6 R3 C8 MDA58 CMDA6 R3 C8 MDA46
CMDA29 L7 A9 DQU2 C2 MDA61 CMDA29 L7 A9 DQU2 C2 MDA41
A10/AP DQU3 Group 7 A10/AP DQU3 Group 5 FBx_CMD1
CMDA23 R7 A7 MDA57 CMDA23 R7 A7 MDA45
CMDA28 N7 A11 DQU4 A2 MDA63 CMDA28 N7 A11 DQU4 A2 MDA43
A12 DQU5 A12 DQU5 FBx_CMD2 ODT
CMDA20 T3 B8 MDA59 CMDA20 T3 B8 MDA47
CMDA4 T7 A13 DQU6 A3 MDA62 CMDA4 T7 A13 DQU6 A3 MDA42
A14 DQU7 A14 DQU7 FBx_CMD3 CKE
CLKA1 M7 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS FBx_CMD4 A14 A14
1

CMDA12 M2 B2 CMDA12 M2 B2 FBx_CMD5 RST RST


RV154 CMDA27 N8 BA0 VDD D9 CMDA27 N8 BA0 VDD D9
162_0402_1% CMDA26 M3 BA1 VDD G7 CMDA26 M3 BA1 VDD G7
BA2 VDD BA2 VDD FBx_CMD6 A9 A9
DIS@ K2 K2
VDD K8 VDD K8 FBx_CMD7 A7 A7
2

VDD N1 VDD N1
CLKA1# CLKA1 J7
310mA VDD N9 CLKA1 J7 VDD N9
B
<36> CLKA1 CK VDD CK VDD FBx_CMD8 A2 A2 B
CLKA1# K7 R1 CLKA1# K7 R1
<36> CLKA1# CK VDD CK VDD
#8/19 , change CLK CMDA19 K9 R9 CMDA19 K9 R9 FBx_CMD9 A0 A0
CKE/CKE0 VDD CKE/CKE0 VDD
termination to 162 ohm. FBx_CMD10 A4 A4
CMDA18 K1 A1 CMDA18 K1 A1
CMDA16 L2 ODT/ODT0 VDDQ A8 CMDA16 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ FBx_CMD11 A1 A1
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ FBx_CMD12 BA0 BA0
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ E9 WE VDDQ E9
VDDQ VDDQ FBx_CMD13 WE# WE#
F1 F1
DQSA4 F3 VDDQ H2 DQSA6 F3 VDDQ H2
<36> DQSA4 DQSL VDDQ <36> DQSA6 DQSL VDDQ FBx_CMD14
DQSA7 C7 H9 DQSA5 C7 H9
<36> DQSA7 DQSU VDDQ <36> DQSA5 DQSU VDDQ
FBx_CMD15 CAS# CAS#
DQMA4 E7 A9 DQMA6 E7 A9 FBx_CMD16 CS0#
L:Group 4 <36> DQMA4
<36> DQMA7
DQMA7 D3 DML VSS B3 L:Group 6 <36> DQMA6
<36> DQMA5
DQMA5 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
H:Group 7 VSS H:Group 5 VSS FBx_CMD17
G8 G8
DQSA#4 G3 VSS J2 DQSA#6 G3 VSS J2
<36> DQSA#4 DQSL VSS <36> DQSA#6 DQSL VSS FBx_CMD18 ODT
DQSA#7 B7 J8 DQSA#5 B7 J8
<36> DQSA#7 DQSU VSS <36> DQSA#5 DQSU VSS
M1 M1 FBx_CMD19 CKE
VSS M9 VSS M9
VSS P1 VSS P1
VSS VSS FBx_CMD20 A13 A13
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS FBx_CMD21 A8 A8
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
FBx_CMD22 A6 A6
1

1
C C
J1 B1 J1 B1 FBx_CMD23 A11 A11
RV155 L1 NC/ODT1 VSSQ B9 RV162 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
NC/CE1 VSSQ NC/CE1 VSSQ FBx_CMD24 A5 A5
DIS@ L9 D8 DIS@ L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 FBx_CMD25 A3 A3
2

2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ VSSQ FBx_CMD26 BA2 BA2
G1 G1
VSSQ G9 VSSQ G9
VSSQ VSSQ FBx_CMD27 BA1 BA1
96-BALL 96-BALL FBx_CMD28 A12 A12
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#

+1.5VGS Closed to UV16


L +1.5VGS
L Closed to UV18
CV139

0.1U_0402_16V7K

CV140

0.1U_0402_16V7K

CV141

0.1U_0402_16V7K

CV142

0.1U_0402_16V7K

CV143

0.1U_0402_16V7K

CV144

1U_0402_6.3V6K

CV145

1U_0402_6.3V6K

CV146

1U_0402_6.3V6K

CV147

1U_0402_6.3V6K

CV148

1U_0402_6.3V6K

CV160

0.1U_0402_16V7K

CV161

0.1U_0402_16V7K

CV162

0.1U_0402_16V7K

CV163

0.1U_0402_16V7K

CV164

0.1U_0402_16V7K

CV165

1U_0402_6.3V6K

CV166

1U_0402_6.3V6K

CV167

1U_0402_6.3V6K

CV168

1U_0402_6.3V6K

CV169

1U_0402_6.3V6K
2 2 2 2 2 1 1 1 1 1
2 2 2 2 2 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

1 1 1 1 1 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
1 1 1 1 1 2 2 2 2 2
D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15V-GM VRAM C Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 38 of 54
1 2 3 4 5
1 2 3 4 5

+3VGS Table 123


Strap pin Strap Mapping Resistance Polarity Logical
Name Strapping Bit0
Check Strap pin status ROM_SCLK SMB_ALT_ADDR 10K Pull-down to GND.

1
RV164 RV165 RV166 RV167 RV168 ROM_SI SUB_VENDOR 10K Pull-down to GND if no VBIOS ROM.
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@ X76@ @ ROM_SO VGA_DEVICE 10K Pull-down to GND(no diaplay).

2
STRAP0 RAM_CFG[0] 10K
STRAP0
<33> STRAP0
STRAP1 STRAP1 RAM_CFG[1] 10K
<33> STRAP1
STRAP2
<33> STRAP2
STRAP3 STRAP2 RAM_CFG[2] 10K
<33> STRAP3
A STRAP4 A
<33> STRAP4
STRAP3 RAM_CFG[3] 10K
STRAP4 PCIE_MAX_SPEED 10K Pull-down to GND(PCIE Gen1).

1
RV171 RV172 RV173 RV174 RV175
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@ X76@ DIS@ SMBUS_ALT_ADDR SUB_VENDOR

2
0 0x9E (Default) 0 Disable (Default)

1 0x9C (Multi-GPU usage) 1


+3VGS

VGA_DEVICE
Check SPI pin status 1 0 Non-Primary 3D Acceleration Device(Class Code 302h)(Default)

1
RV176 RV177 RV178
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 Primary Display or VGA Device .
@ @ @
2

2
PCIE_MAX_SPEED
ROM_SI
<33> ROM_SI
ROM_SO 0 Limit to PCIE Gen1
<33> ROM_SO
ROM_SCLK
<33> ROM_SCLK
1 PCIE Gen 2/3 Capable
1

1
B B
ZZZ001 ZZZ001 ZZZ001
RV179 RV180 RV181
10K_0402_5% 10K_0402_5% 10K_0402_5%
DIS@ DIS@ DIS@
2

SAM@ MIC@ HY@


1G SAMSUNG 1G MICRON 1G HYNIX
X7654132L21 X7654132L23 X7654132L22

ROM CFG setup


GPU Project VRAM size CH Description Compal VRAM P/N VRAM description [3...0] RAM_CFG R P/N
128M(X16) CHA DDR3 Hynix 128Mx16 1.5V SA00006H400 H5TC2G63FFR-11C 1000MHz 1100 RV171+RV172+RV167+RV166
ZSO40
ZSO50 128M(X16) CHA DDR3 Micron 128Mx16 1.5V SA000067500 MT41J128M16JT-093G:K 1000MHz 0001 RV164+RV172+RV173+RV174
N15V-GM (23x23) 64bit
(One CH single rank) 128M(X16) CHA DDR3 Samsung 128Mx16 1.5V SA000068U40 K4W2G1646Q-BC1A 1000MHz 1110 RV165+RV166+RV167+RV171

#9/5 RAM_CFG follow RVL‐06891‐001 table 1.
Dule Rank layout with single Rank population. USER Straps
User[3:0]

C 1000-1100 Customer defined C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15V-GM
Size Document Number
MISC Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-A992P
Thursday, March 20, 2014 Sheet 39 of 54
1 2 3 4 5
A B C D E

<MV>Remove R563, delete net +5VS_IN ,4/10.

+5VS

10U_0603_6.3V6M

22U_0805_6.3V6M
1 1

C575

CC56
+3VALW +5VALW
2 2 @
Q21
1 14 <MV>Add 22UF for RF suggestion ,4/10.
2 VIN1 VOUT1 13
+5VALW VIN1 VOUT1
SUSP# 3 12 C554 1 2 100P_0402_50V8J
ON1 CT1 SYSON# SUSP
1 1
4 11
VBIAS GND

3
Q18A Q18B
SUSP# 5 10 C557 1 2 680P_0402_50V7K DMN66D0LDW-7_SOT363-6
ON2 CT2 DMN66D0LDW-7_SOT363-6
6 9 SYSON 2 5 SUSP#
VIN2 VOUT2 <30,48> SYSON SUSP# <30,48,49,52,55>
7 8
VIN2 VOUT2

4
15
GPAD
+3VS
TPS22966DPUR_SON14_2X3-D
1

10U_0603_6.3V6M
C570
2
<MV>Remove R564, delete net +3VS_IN ,4/10.
+5VALW

RPH16
SYSON 8 1
SUSP 7 2
SYSON# 6 3
SUSP# 5 4
+1.05V TO +1.05VS
100K_0804_8P4R_5%
J1 need to short +1.05VS
+1.05V
J1
1 2
2 1 2 2

AO4430L JUMP_43X79
VGS Max=+/- 20V @
VGS(Th) max=2.5V

Rds Max=5.5m @VGS=10V


Rds Max=7.5m @VGS=4.5V

+V1.05A +V1.05DX_MODPHY
+1.05V +1.05VS_MODPHY

short@ R570 1 20_0805_5%

CPU +V1.05DX_MODPHY
Max Rdson <6m ohm
1840mA
3 3

AO4430L
VGS Max=+/- 20V
VGS(Th) max=2.5V
Rds Max=5.5m @VGS=10V
Rds Max=7.5m @VGS=4.5V

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 40 of 54
A B C D E
5 4 3 2 1

NGFF and WLAN

D D

+3VS +3VS_WLAN

2
@
RL25
100K_0402_5%

2
G

1
WAKE# 1 3 MC_WAKE# MC_WAKE# <21>
<8> WAKE#

S
@
QB8
2N7002H_SOT23-3

PV# 2013.01.23 Add QB8 abd RL25 to support OBFF
PV# 2013.02.22 Unpop QB4 and RL23 for not support OBFF

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WAKE and RST-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 41 of 54
5 4 3 2 1
A B C D E

+3VALW Q30 +3V_PCH


AO3413L_SOT23-3
1 1
+3VALW 3 1

D
20mils

G
2
1

2
C590
R559
100K_0402_5% 1U_0402_6.3V6K
2

1
1
D

0.1U_0402_16V7K
<30> PCH_PWR_EN 2 1
G

C591
S Q31 @

3
2N7002_SOT23-3
2

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC DC Device-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 42 of 54
A B C D E
5 4 3 2 1

CMSRC ACDRV
B+
DC IN ACFET RBFET
D D

+3VALWP Jumper +3VALW


RT8243 SY8003 UMA only
+1.5VSP Jumper +1.5VS
Charger
BQ24738 SUSP#
EN
+5VALWP Jumper +5VALW
EC_ON
EN

BATDRV +1.35V_VDDQP Jumper +1.35V_VDDQ


RT8207M
Battery RBFET
BATT
+0.6V_0.675VSP
Jumper
+0.6V_0.675VS
SYSON
EN
SUSP#
C C

SY8208D
+1.05VSP Jumper +1.05VS

SUSP#
EN

TPS51622
+VCC_CORE

VR12.5_VR_ON
EN
B B

RT8813 DIS only


+VGA_CORE
GPU_PWR_EN
EN

SY8208D DIS only


+1.5VDIS Jumper +1.5VS
SUSP#
EN

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
Power Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 43 of 55
5 4 3 2 1
5 4 3 2 1

PL1 EMI@ VIN


ADPIN HCB2012KF-121T50_0805
1 2

PL2 EMI@
HCB2012KF-121T50_0805
1 2 @ PR2
0_0402_5%

1000P_0402_50V7K
@ PJP1 <30> AC_LED# 1 2ACIN_LED

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
ACES_59012-0080N-002
2 1
2 1

1
EMI@ PC1

EMI@ PC2

EMI@ PC3

EMI@ PC4
D D
4 3
4 3 PR3

2
6 5 ADP_SIGNAL 100K_0402_5%
6 5

2
Charge_LED 8 7 ACIN_LED
8 7
PR1
10K_0402_5% PR5
ADP_SIGNAL1 2 2K_0402_5%
ADP_ID <30> 1 2 Charge_LED
<30> BAT_CHG_LED
3

1
1000P_0402_50V7K
100P_0402_50V8J
1

GLZ3.6B_LL34-2

1
10K_0402_5%
PR8

PR7

@ PD3

@ PC5

PC6
100K_0402_5%

2
2

2
ESD@ PD1 ESD@ PD2
1

L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3

+5VS

C +3VALW C

1
@
<30,4> PROCHOT# PR10 @
47K_0402_1% PR11
6

@ PU1A 10K_0402_1%
2

4
PQ2A PC8 LM393DR_SO8

2
L2N7002DW1T1G_SC88-6 0.022U_0402_16V7K 2

G
2 1 2 1 -
O

1
100P_0402_50V8J
3
+
1

1
P
@
1

PC9
@ @ PR12
PD4 PR13 8 54.9K_0402_1%

2
CD4148WN-1_1206-2 1.5M_0402_5% @

2
2

B/I# <30,45>

+5VS
ADP_I <30,46>

+3VALW +3VALW_EC
1

1
B B
PR17 PR26
47K_0402_1% PU1B PR18 PR25 5.9K_0402_1%
3

LM393DR_SO8 10K_0402_1% 10K_0402_1%


2

PQ2B PC12
2

2
L2N7002DW1T1G_SC88-6 0.022U_0402_16V7K 5
P

+ VCIN0_PH <30> VCIN1_PH <30>

0.1U_0402_16V7K

0.1U_0402_16V7K
5 1 2 7
O
1

1
100P_0402_50V8J

6
-
1

1
@ PC15

@ PC16
4

PC13

PR21 PH1 PR27 @ PR28


4

PD5 PR20 100K_0402_1% 100K_0402_1%_NCP15WF104F03RC 10K_0402_1% 10K_0402_1%


2

2
CD4148WN-1_1206-2 1.5M_0402_5%
2

2
ECAGND<30> H_PROCHOT#_EC <30>
2

ACIN <30,45,46,8>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
DC Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 44 of 55
5 4 3 2 1
5 4 3 2 1

@ PJPB2
1 2
1 2
EMI@ PL3 JUMP_43X118
D HCB2012KF-121T50_0805 D
BATT++ 1 2 BATT+ BATT
PQ1 @
EMI@ PL4 SI4483ADY-T1-GE3_SO8
@ PJPB1 HCB2012KF-121T50_0805 1 8
1 1 2 2 7
1 2 3 6
2 3 5
3

1
4 EMI@ PC10 EMI@ PC11 @ PR14
4 5 1000P_0402_50V7K 0.01U_0402_25V7K 470K_0402_5%

4
5 6 1 2

2
6 7
7

1
8
8 9 PR15 @ PR16 @
GND 10
GND 470K_0402_5% 4.7K_0402_5%
PR19
OCTEK_BTJ-08FUAB 100_0402_5%

6 2
1 2
EC_SMB_DA1 <28,30,46>
PR22 PQ3A @
100_0402_5% L2N7002DW1T1G_SC88-6
1 2 2
EC_SMB_CK1 <28,30,46>
1
100_0402_5%

+3VL

1
PR30

1
2

PR29 PR23 @
100K_0402_5% 220K_0402_5%

3
C 1 2 C
+3VL +3VL

2
B/I# <30,44>
5 @
3

1
PQ3B
L2N7002DW1T1G_SC88-6 PR24 @

6
220K_0402_5%
PQ4A @
L2N7002DW1T1G_SC88-6

2
2

3
1

1
ESD@ PD6 ESD@ PD7
1

L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3 PC14 @


100P_0402_50V8J 5
ACIN <30,44,46,8>

2
PQ4B @
L2N7002DW1T1G_SC88-6

4
AC_AND_CHAG <30>
Need to define "AC_AND_CHAG" signal with EC

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
BATT Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 45 of 55
5 4 3 2 1
A B C D

1
D
2 PQ102
G 2N7002KW_SOT323-3
S

3
PR101 PR102
1 2 1 2

1M_0402_5% 3M_0402_5%
1 1

VIN P1 P2 B+
PQ101 PQ103 PR103 EMI@ PL101 PQ104
AON6414AL_DFN8-5 AON7506_DFN33-8-5 0.01_1206_1% 1.2UH_NRS4018T1R2NDGJ_2.6A_30% AON7506_DFN33-8-5
1 1 1 4 1 2 1
2 2 2

2200P_0402_50V7K
5 3 3 5 2 3 5 3

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

@EMI@ PC123

PC104

PC105
1

1
2200P_0402_50V7K

0.01U_0402_50V7K
1

1
VIN
PC101

PC102
4

PC107
2

2
1 2
2

2
3

2
PC106
0.1U_0402_25V6 PR104
ACDRV1_CHG 4.12K_0603_1%

0.1U_0402_25V6
PD101 BATDRV_CHG 1 2 BATDRV1_CHG

0.1U_0402_25V6

PC109
BAS40CW_SOT323-3

1
PC108
PC110
0.047U_0402_25V7K

2
1 2

5
10_1206_1%
PR105

1
2.2_0603_5%
PR106
PD102
RB751V-40_SOD323-2 @ PR107 PQ105
0_0603_5% AON7408L_DFN8-5

2
PC111 DH_CHG 1 2 4

2
1U_0603_25V6K
4.12K_0603_1%

4.12K_0603_1%

1 2
1

REGN_CHG
2 BATT 2

VCC_CHG

BST_CHG
PR108

PR109

DH_CHG
PC112 PL102

LX_CHG

3
2
1
1U_0603_25V6K 4.7UH_ETQP3W4R7WFN_5.5A_20% PR110
1 2 0.01_1206_1%
LX_CHG 1 2 CHG 1 4
2

@EMI@ PR111
4.7_1206_5%
2 3

20

19

18

17

16
PU101

CSON1
CSOP1

RB551V-30_SOD323-2
PQ106

BTST
VCC

PHASE

HIDRV

REGN

10U_0805_25V6K

10U_0805_25V6K
21 AON7506_DFN33-8-5
PAD

1
0.1U_0402_25V6

0.1U_0402_25V6

PC114

PC115
1SNB_CHG 2

1
PD103
ACN_CHG 1 15 DL_CHG 4
ACN LODRV

PC113

PC116
1

2
680P_0603_50V8J
ACP_CHG 2 14 PR112

2
ACP GND

@EMI@ PC117
0_0603_1%

3
2
1

2
BQ24738RGRR_QFN20_3P5X3P5 1 2 CSOP1
CMSRC_CHG 3 13 SRP_CHG
CMSRC SRP

2
PR113 PC118
ACDRV_CHG 4 12 SRN_CHG 0_0603_5% 0.1U_0603_16V7K

2
PR114 ACDRV SRN 1 2 CSON1
10K_0402_1%
+3VL 1 2 5 11 BATDRV_CHG
ACPRES ACDET BATDRV

IOUT

SDA

ILIM
SCL
<30,44,45,8> ACIN
6

10
ACDET_CHG

ILIM_CHG
IOUT_CHG

3 3

PR115
357K_0402_1% +3VL
VIN 1 2

0.01U_0402_25V7K
100K_0402_1%
1
422K_0402_1%

PR116

PC119
1

1
PR117

2
2
2

Vin Dectector
EC_SMB_CK1 <28,30,45>
Min. Typ Max.
0.1U_0402_25V6

66.5K_0402_1%
1
PC120

PR118

H-->L 17.23V
1

EC_SMB_DA1 <28,30,45>
L-->H 17.63V
@ PR119
2

0_0402_5%
2

1 2
ILIM and external DPM ADP_I <30,44>
1

3.61A PC121 @ PC122


100P_0402_50V8J 0.1U_0402_10V7K
2

4
locate the RC Near EC chip 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA‐A992P
Date: Sheet 46 of 55
A B C D
A B C D

PR302
165K_0402_1%
1 2

PR303
56K_0402_1%
1
1 2 1

PR304
@ PC302 143K_0402_1%
100P_0402_50V8J 1 2
1 2

PR301 PR305
14K_0402_1% 30K_0402_1%
1 2 1 2

B+ 3/5V_B+ 3/5V_B+
EMI@ PL301
HCB2012KF-121T50_0805
1 2 +3VALW PR306 PR307

2200P_0402_50V7K
20K_0402_1% 19.1K_0402_1%

ENTRIP_3V

ENTRIP_5V
1 2 1 2

10U_0805_25V6K

10U_0805_25V6K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

TON_35V
@EMI@ PC318

PC303

PC307
1

1
PC304

PC308
FB_3V

FB_5V
PR318
10K_0402_1%
2

2
@

2
@
<8> SPOK

5
PQ301

FB2

ENTRIP2

ENTRIP1

FB1
TON
AON7408L_DFN8-5 21
PC305 PR309 6 PAD
0.1U_0402_10V7K 2.2_0402_1% PGOOD 20 PR310 PC306
4 1 2 BST1_3V 1 2 BYP1 2.2_0402_1% 0.1U_0402_10V7K
BST_3V 7 1 2 BST1_5V 1 2 4
BOOT2 19 BST_5V
2 BOOT1 PQ302 2

DH_3V 8 AON7408L_DFN8-5
1
2
3
PL303 UGATE2 18 DH_5V

3
2
1
3.3UH_PCMB063T-3R3MS_6.5A_20% UGATE1 PL302
1 2 LX_3V 9 2.2UH_ETQP3W2R2WFN_8.5A_20%
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
1

@EMI@ PR311
4.7_1206_5%

@EMI@ PR312
4.7_1206_5%
LG_3V 10
LGATE2
5

16 LG_5V

ENLDO
LGATE1

5
LDO5

LDO3
220U_C6_6.3V_M_R15

ENM
VIN
PQ303
SNUB_3V 2

+
PC316

AON7506_DFN33-8-5

220U_C6_6.3V_M_R15
1

SNUB_5V 2
PU301

11

12

13

14

15
+

PC317
4 RT8243AZQW_WQFN20_3X3

AON7506_DFN33-8-5
2 4

PQ304
+5VLP

+3VLP
680P_0603_50V8J

2
@EMI@ PC311

680P_0603_50V8J
PR313
1

+3VLP

@EMI@ PC312
499K_0402_1%
1
2
3

1
1 2 @ PJ301
3/5V_B+

3
2
1
JUMP_43X39
2

100K_0402_1%
1 2

1U_0603_10V6K
0.1U_0603_25V7K
+3VL

2
1 2

1
PC313

PR314

PC314
1

1
(100mA,40mils ,Via NO.= 2)

1
PC310

2
4.7U_0603_10V6K

2
PR315
2.2K_0402_1%
3
1 2 3

<30> EC_ON @ PR316 @ PJ304


0_0402_5% JUMP_43X39
1 2 1 2 +VL
<30> MAINPWON 1 2

4.7U_0603_6.3V6K
(100mA,40mils ,Via NO.= 2)

1
@ PC315
1

1
@ PR317 PC309
100K_0402_5% 4.7U_0603_10V6K
2

2
2
@ PJ302
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118

@ PJ303
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA‐A992P
Date: Sheet 47 of 55
A B C D
5 4 3 2 1

EMI@
PLM1
HCB2012KF-121T50_0805 PCM2 PRM1
B+ 1 2 B+_DDR 0.22U_0402_10V6K 2.2_0402_1%
1 2 BST_DDR-1 1 2
D D

1
@EMI@
PCM13 PCM1 PCM3
2 2200P_0402_50V7K 10U_0805_25V6K 4.7U_0805_25V6-K

2
+1.35V_VDDQP
+0.6V_0.675VSP

BST_DDR
DH_DDR
LX_DDR

10U_0805_6.3V6K

10U_0805_6.3V6K
1

1
PCM4

PCM5
4

PQM1

16

17

18

19

20

2
AON7408L_DFN8-5

PHASE

UGATE

BOOT

VTT
VLDOIN
1
2
3
21
PAD
PLM2 DL_DDR 15 1
1.5UH_PCMC063T-1R5MN_9A_20% LGATE VTTGND
1 2
+1.35V_VDDQP 14
PGND VTTSNS
2
1

5
PRM3
@EMI@ 13.3K_0402_1%
PRM2 1 2 CS_DDR 13 PUM1 3
4.7_1206_5% CS RT8207PGQW_WQFN20_3X3 GND
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

4 12 4 VTTREF_DDRT
+5VALW VDDP VTTREF
1

1
PCM25

PCM24

PCM23

PCM22

PCM21

PCM26

C PQM2 PRM4 C
1SNB_DDR

AON7506_DFN33-8-5 5.1_0603_5%
1 2 VDD_DDR 11 5 +1.35V_VDDQP
2

+5VALW VDD VDDQ

PGOOD
1
2
3

1
TON
@EMI@ PCM8 PCM9 PCM10

FB
S5

S3
PCM7 1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K

2
680P_0603_50V7K
2

10

6
FB_DDR
S5_DDR

S3_DDR
TON_DDR
PRM5
8.06K_0402_1%
1 2 +1.35V_VDDQP

1
PRM8
10K_0402_1%

2
PRM6
432K_0402_1%
B+_DDR 1 2

@ PRM9 @ PJPM2
B 0_0402_5% 1 2 B

<30,40> SYSON
1 2 +1.35V_VDDQP 1 2 +1.35V_VDDQ
JUMP_43X118

@ PRM11
0_0402_5%
1 2 @ PJPM1
<30,40,49,52,55> SUSP#
JUMP_43X39
1 2
+0.6V_0.675VSP 1 2
+0.6V_0.675VS

1
@ @
PCM11 PCM12
0.1U_0402_10V7K 0.1U_0402_10V7K

2
A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/08/07 Deciphered Date 2016/08/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.35V/0.675VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 48 of 55
5 4 3 2 1
5 4 3 2 1

D D

EN pin don't floating


@ PRH1 If have pull down resistor at HW side, pls delete PR2
0_0402_5%
1 2
SUSP# <30,40,48,52,55>

1
PRH2 @ PCH1
1M_0402_1% 0.22U_0402_10V6K

2
2
@EMI@ @EMI@
PRH3 PCH2
EMI@ 4.7_1206_5% 680P_0603_50V7K
PLH1 PUH1 1 2 SNB_1.05V 1 2
HCB2012KF-121T50_0805 SY8206DQNC_QFN10_3X3
+1.05VSP +1.05VS
B+ 1 2 B+_1.05V 8
IN EN
1 @ PRH4 PCH3
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0_0603_5% 0.1U_0603_25V7K
EMI@ PCH4

6 BST_1.05V 1 2 1
BST_1.05Vn 2 PLH2 @ PJH1
BS
1

1
PCH5

PCH6
1UH_PCMB063T-1R0MS_12A_20% JUMP_43X118
9 10 LX_1.05V 1 2 1 2
GND LX 1 2
2

47U_0805_6.3V6M

47U_0805_6.3V6M

22U_0805_6.3VAM

22U_0805_6.3VAM
1

330P_0402_50V7K
C C

1
4 FB_1.05V
FB

PCH7

PCH8

PCH9

PCH10

PCH11
PRH5
PRH6 ILMT_1.05V 3 7 100K_0402_1%
+3VALW

2
10K_0402_5% ILMT BYP

4.7U_0603_6.3V6K

2
+3VS 1 2 2 5 LDO_3V

4.7U_0603_6.3V6K
PG LDO

PCH13
1

PCH12

1
2
PRH7
133K_0402_1%
<30> +1.05V_VS_PG_PWR

2
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

continuous 6A
peak 12A

+3VALW
1

PRH8 @
B B
0_0402_5%
2

ILMT_1.05V
1

PRH9 @0@
0_0402_5%
2

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
1.05V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 49 of 55
5 4 3 2 1
5 4 3 2 1

100K_0402_1%_NCP15WF104F03RC
VREF

4700P_0402_16V7K
@ PRZ1 EMI@ PLZ1

332K_0402_1%

100K_0402_1%

680K_0402_1%

9.31K_0402_1%
10K_0402_1% HCB2012KF-121T50_0805

1
PHZ1
CPU_B+ 1 2
B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PCZ1

PRZ2

PRZ3

PRZ4

PRZ5
2

33U_25V_M

100U_25V_M
1 1

1
+ +

0.1U_0402_25V6
PCZ9
4.7U_0805_25V6-K

PCZ2

PCZ5

PCZ10

PCZ11

PCZ6

PCZ7

PCZ8
@

2
1
D D

2200P_0402_50V7K

68P_0402_50V8J
PCZ3

PCZ4
PRZ6

2
39K_0402_1% @ @ @ 2@ 2

EMI@
9.09K_0402_1%

.001U_0402_50V7-M
1

1
39K_0402_1%

150K_0402_1%

100K_0402_1%

150K_0402_1%
2

EMI@

RF@
PRZ7

PCZ12

PRZ8

PRZ9

PRZ10

PRZ11
2
2

2
B-RAM
PRZ12 SLEWA EMI@ EMI@

OCP-I
10K_0402_1% F-IMAX PCZ13 PRZ13
CPU_B+ 1 2 680P_0402_50V7K 4.7_1206_5%
O-USR 1 2 1 2

CPU_B+

16

15

14

13

12

11

10

9
PUZ1 PLZ2

9
0.15UH_ETQP4LR15AFM_29A_20%

SLEWA

OCP-I

B-RAMP

F-IMAX
VBAT

THERM

IMON

O-USR
PRZ14 5 PGND2 4 1 4
2.2_0402_1% VIN VSW +VCC_CORE
CSP1 17 8 1 2 6 3 2 3
CSP1 VR_ON VR12.5_VR_ON <11> BOOT_R PGND1 +5VS
CSN1 18 7 SKIP 1 2 7 2 CSN1
CSN1 SKIP# BOOT VDD

10K_0402_1%_TSM0A103F34D1RZ
3K_0402_1%

0.22U_0402_10V6K

0.15U_0402_10V6K
PRZ15 CSN2 19 6 PWM1 PCZ14 8 PWM 1
CSN2 PWM1 SKIP#

1
C 0_0402_5% .1U_0402_16V7K @ C

PRZ17
1 2 CSP2 20 5 PWM2 PUZ2 PRZ16 PCZ15
CSP2 PWM2

12.1K_0402_1%
CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% 1U_0603_10V6K

1
21 TPS51624RSM_QFN32_4X4 4 PWM1
+3VS CSP3 PWM3

1
PRZ18

PCZ16

PCZ17
1 2
1
@ PRZ19 22 3
0_0402_5% CSN3 PGOOD VGATE <11> SKIP

2
1 2 GFB 23 2 @
<13> VSSSENSE

2
GFB VDD
VR_HOT#

ALERT#

10K_0402_1%
DROOP

1 2 VFB 24 1 VR_SVID_DAT
<11> VCCSENSE
COMP

VFB VDIO

1
VREF

VCLK

PHZ2
PRZ23

1_0402_5%
GND

PAD

2
V5A

0_0402_5% 2.43K_0402_1%

PRZ21

PRZ22
@ PRZ20 1 2 CSP1
25

26

27

28

29

30

31

32

33

1
PCZ18

2
1U_0402_6.3V6K
NTC
VR_SVID_ALRT#

2
VR_SVID_CLK

@ PCZ19 B value=3435 K
100P_0402_50V8J
VR_HOT#

1 2 PRZ24 @EMI@ @EMI@


4.87K_0402_1% +3VS PCZ20 PRZ26
PRZ25 1 2 680P_0402_50V7K 4.7_1206_5%
10K_0402_1% 1 2 1 2
1 2 VREF

PRZ27 PCZ21 CPU_B+


1

4.87K_0402_1% 4700P_0402_25V7K @ PLZ3

9
1 2 1 2 PCZ22 0.15UH_ETQP4LR15AFM_29A_20%
0.33U_0402_10V6K @ PRZ28 5 PGND2 4 1 4
+VCC_CORE
2

B 2.2_0402_1% VIN VSW B


1 2 6 3 2 3
PRZ29 BOOT_R PGND1 +5VS
10_0603_1% 1 2 7 2 CSN2
BOOT VDD
1 2

10K_0402_1%_TSM0A103F34D1RZ
+5VS +1.05VS_VCCST

2.43K_0402_1%

0.22U_0402_10V6K

0.15U_0402_10V6K
@ PCZ23 8 PWM 1
SKIP#
1

1
.1U_0402_16V7K @ @

PRZ31
PCZ24 @ PUZ3 PRZ30 PCZ25

36K_0402_1%
1U_0603_10V6K CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% 1U_0603_10V6K
2

1
PRZ32
PWM2
1

1
54.9_0402_1%

130_0402_1%

PHZ3

PCZ27

PCZ28
@

1 2
1

1
PRZ34

SKIP
PRZ33

PCZ26 @

2
.1U_0402_16V7K @ @ @
2

2
2

@ PRZ35

2
VR_SVID_CLK 1.82K_0402_1%
<11> VR_SVID_CLK 1 2 CSP2
VR_SVID_ALRT#
<11> VR_SVID_ALRT#
VR_SVID_DAT
<11> VR_SVID_DAT
VR_HOT#
<30> VR_HOT#
1

@ PCZ29
47P_0402_50V8J
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 50 of 55
5 4 3 2 1
5 4 3 2 1

+VCC_CORE

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

220U_D2 SX_2VY_R9M
D 1 D
1 1 1 1 1
1

1
+

PCZ50

PCZ51

PCZ52

PCZ53

PCZ54

PCZ55

PCZ56

PCZ57

PCZ58

PCZ59

PCZ70
2

2
@ 2@ 2@ 2@ 2@ @ @ @ 2 2

acoustic noise
22U_0603_6.3V6M

2.2U_0402_10V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1
1

1
PCZ60

PCZ61

PCZ62

PCZ63

PCZ64

PCZ65

PCZ66

PCZ67

PCZ68

PCZ69
2

2
2 2 2@ @ @ @ 2

C
acoustic noise C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
PROCESSOR DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 51 of 55
5 4 3 2 1
A B C D

@UMA@
PR1502
0_0402_5%
1 2
SUSP# <30,40,48,49,55>

1
1
1 @UMA@ UMA@ 1

PC1502 PR1503
.1U_0402_16V7K 1M_0402_5%

2
UMA@

2
PU1501
9
FB_1.5V 1 PGND 8
@ FB SGND UMA@ +1.5VSP @ +1.5VS
PJ1501 2 7 EN_1.5V PL1501 PJ1502
JUMP_43X79 PG EN 1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79
+3VALW 1 2 VIN_1.5V 3 6 LX_1.5V 1 2 1 2
1 2 IN LX 1 2
4 5
PGND NC

1
UMA@

1
PC1501 @EMIUMA@ UMA@ UMA@ UMA@ UMA@
22U_0805_6.3VAM SY8003DFC_DFN8_2X2 PR1504 PR1505 PC1503 PC1504 PC1505

2
4.7_0603_5% 30.1K_0402_1% 68P_0402_50V8J 22U_0805_6.3VAM 22U_0805_6.3VAM

2
2

2
1
1
@EMIUMA@ UMA@
PC1506 PR1506
680P_0402_50V7K 20K_0402_1%

2
continuous 3A

2
2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title
1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 52 of 55
A B C D
5 4 3 2 1

D D

@VGA@
PRV1
1K_0402_5%
1 2 +3VGS
@VGA@
PRV2
0_0402_5%
1 2 NVVDD_PWM_VID <32>
GPU_B+
1

VGA@

1
PCV1 Rref1 Operation phase Number PSI Voltage setting
1U_0402_6.3V6K VGA@ @VGA@ PRV26
2

PRV3 1K_0402_5% 1 phase with DEM 0V to 0.8V EMIVGA@


7.5K_0402_1% 1 2 +3VGS PLV1
B+
C @VGA@ 1 phase with CCM 1.2V to 1.8V HCB2012KF-121T50_0805 C

2
@VGA@ VGA@ PRV6 PSI Pull high on HW side 1 2

2200P_0402_50V7K
PRV4 PRV5 0_0402_5% Active phase with CCM 2.4V to 5.5V

100U_25V_M
10U_0805_25V6K

10U_0805_25V6K
0_0402_5% 27K_0402_1% 1 2 1
NVVDD_PSI <32>

EMIVGA@ PCV3

VGA@ PCV4

VGA@ PCV6
1 2 1 2

1
+

VGA@ PCV19
Rboot Rrefadj @VGA@ PRV28

5
10K_0402_5% @VGA@ PRV27

1
VGA@ 1 2 1K_0402_5%

2
PCV8 1 2 @VGA@ 2
+3VGS
@VGA@ 5600P_0402_50V7K PRV10

2
PCV7 C VGA@ PRV9 Pull high on HW side 0_0603_5%
0.01U_0402_16V7K 1K_0402_5% U2_UGATE1 1 2 4
1 2 1 2 VGA@ +VGA_CORE

GPU_VID
DGPU_PWR_EN <30,35,9> PQV1

GPU_FBRTN
VGA@ VGA@ SIR472DP-T1-GE3_POWERPAK8-5 EDP-Continuous 33.5A
Rref2 PRV7 PCV5
EDP-Peak 51.5A

3
2
1
VGA@ VGA@ 2.2_0603_5% 0.22U_0603_25V7K

1
GPU_REFADJ
PRV8 PRV11 @VGA@ U2_BOOT1 1 2 1 2 OCP 66A

U2_BOOT1
U2_UGATE1
6.2K_0402_1% 1.74K_0402_1% PCV9

GPU_PSI

GPU_EN
1 2 1 2 0.1U_0402_25V6

2
Reserve Location VGA@ PLV2 +VGA_CORE
0.22UH_PCME064T-R22MS_28A_20%
U2_PHASE1 1 2

1
@EMIVGA@
6

390U_2.5V_M

390U_2.5V_M
VGA@ PRV14 1 1
VGA@ PRV13 VGA@ 4.7_1206_5%
REFADJ

VID

PSI

EN

UGATE1

BOOT1
+ +

VGA@ PCV12

VGA@ PCV10
PRV12 340K_0402_1% PQV2
100_0402_1% GPU_B+ 1 2 MDU1511RH_POWERDFN56-8-5

1SNB_VGA12
1 2 1 Rton GPU_REFIN 7 24 U2_PHASE1 U2_LGATE1 4
@VGA@ REFIN PHASE1 2 2
PCV14 GPU_VREF 8 23 U2_LGATE1
VREF LGATE1

1
@VGA@ 0.01UF_0402_25V7K
PRV16 2 GPU_TON 9 22 U2_PWM3 U2_PWM3 VGA@

3
2
1
<35> VSSSENSE_VGA 0_0402_5% TON VGA@ GND/PWM3 PRV15 @EMIVGA@
1 2 GPU_FBRTN 10 PUV1 21 12.7K_0402_1% PCV15
RGND RT8813AGQW_WQFN24_4X4 PVCC Rocset 680P_0603_50V7K

2
B B
GPU_FB 11 20 U2_LGATE2
TALERT/ISEN2

VSNS LAGTE2
1

@VGA@
TSNS/ISEN3

Co-Lay Co-Lay
VCC/ISNE1

@VGA@ PCV16 GPU_COMP 12 19 U2_PHASE2


SS PHASE2
UGATE2

PRV17 47P_0402_50V8J
PGOOD

BOOT2
2

0_0402_5% 1
GND

1 2 @VGA@ GPU_B+
PCV17

2200P_0402_50V7K
<34> VCCSENSE_VGA 0.01U_0402_16V7K
25

13

14

15

16

17

18

2 Css

10U_0805_25V6K

10U_0805_25V6K
EMIVGA@ PCV20

VGA@ PCV21

VGA@ PCV22
VGA@

1
PRV18
GPU_DSBL/ISEN1
GPU_TSNS/ISEN3

5
GPU_HOT#

100_0402_1%
1 2
GPU_PGOOD1

U2_UGATE2

2
U2_BOOT2

+VGA_CORE @VGA@
PRV20
0_0603_5%
U2_UGATE2 1 2 4
VGA@
PQV3
VGA@ VGA@ SIR472DP-T1-GE3_POWERPAK8-5
PRV19 PCV18

3
2
1
2.2_0603_5% 0.22U_0603_25V7K
GPU_VREF U2_BOOT21 2 1 2

+3VGS
1

VGA@ VGA@ PLV3 +VGA_CORE


1. VSNS Soft-Start time (Internal) is 0.7ms (PCV17 un-pop) PRV21 0.22UH_PCME064T-R22MS_28A_20%
1

18.7K_0402_1% U2_PHASE2 1 2
Tss=(Css*Vrefin)/Iss+2.3ms VGA@
2

1
=0.01U*0.9V/5uA+2.3ms=4.1ms (PCV17 pop) PRV22

390U_2.5V_M
10K_0402_1% @EMIVGA@ 1
1

5
PRV23
2
1

VGA@ PCV25
2. Switching frequency setting: VGA@ VGA@ 4.7_1206_5%
PCV23 PHV1 VGA@
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=448Khz

1SNB_VGA22
1U_0402_6.3V6K 470K_0402_5%_TSM0B474J4702RE DGPU_PWROK <35> +5VS PQV4
2

MDU1511RH_POWERDFN56-8-5 2
2

A U2_LGATE2 4 A
3. Thermal monitoring: VGA@
PRV24
(VGPU_VREF-VTSNS)/PRV21=VTSNS/Rth 2.2_0603_5% @EMIVGA@
1 2 PCV26

3
2
1
680P_0603_50V7K

2
T_min T_typical T_max VGA@
PRV25 Co-Lay
1

100K_0402_1% VGA@
PRV21=18.7K 96.73C 100C 103.1C +3VS 1 2 PCV27
1U_0402_6.3V6K
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title


PRV21=13K 106.38C 110C 113.4C <30> GPU_HOT# VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 53 of 55
5 4 3 2 1
A B C D E

+VGA_CORE

PLACE UNDER GPU


1 1

1
VGA@ VGA@ VGA@ VGA@ VGA@
PCV51 PCV52 PCV53 PCV54 PCV55
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M

2
1

1
VGA@ VGA@ VGA@ VGA@ VGA@
PCV56 PCV57 PCV58 PCV59 PCV60
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
2

2
2 2
1

1
VGA@ VGA@ VGA@ VGA@
PCV61 PCV62 PCV63 PCV64
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2

2
PLACE NEAR GPU
1

1
VGA@ VGA@ VGA@ VGA@ VGA@
PCV65 PCV66 PCV67 PCV68 PCV69
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
2

2
3 3
1

VGA@ VGA@
PCV70 PCV71
22U_0603_6.3V6M 47U_0805_6.3V6M
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/08/07 Deciphered Date 2016/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA CHIP DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-A992P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 20, 2014 Sheet 54 of 55
A B C D E
5 4 3 2 1

@VGA@
PRW1
0_0402_5%
1 2
SUSP# <30,40,48,49,52>

1
D D

1
VGA@ @VGA@
PRW2 PCW1
1M_0402_1% 0.01UF_0402_25V7K

2
2
@EMIVGA@ @EMIVGA@
PRW3 PCW2
EMIVGA@ 4.7_1206_5% 680P_0603_50V7K
PLW1
HCB2012KF-121T50_0805
VGA@
PUW1 @VGA@ VGA@
1 2 SNB_VRAMPWR 1 2
+1.5VDIS +1.5VS
B+ 1 2 B+_VRAMPWR 8
IN EN
1 EN_VRAMPWR PRW4 PCW5
2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K 0_0603_5% 0.1U_0603_25V7K VGA@ @


EMIVGA@ PCW3

VGA@ PCW4

VGA@ PCW6

6 BST_VRAMPWR 1 2 BST_VRAMPWRn1 2 PLW2 PJW1


BS
1

1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118
9 10 LX_VRAMPWR 1 2 1 2
GND LX 1 2
2

1
4 FB_VRAMPWR VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
FB PRW5 PCW7 PCW8 PCW9 PCW10 PCW11
3 7 30.1K_0402_1% 330P_0402_50V7K 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
+3VALW

2
ILMT BYP

2
2 5
PG LDO

1
VGA@

1
SY8206DQNC_QFN10_3X3 VGA@ PCW12
PCW13 4.7U_0603_6.3V6K

1
4.7U_0603_6.3V6K

2
C VGA@ C
PRW6
19.6K_0402_1%

2
continuous 6A
peak 12A

B B

A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/08/07 Deciphered Date 2016/08/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A992P
Date: Thursday, March 20, 2014 Sheet 55 of 55
5 4 3 2 1

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