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Control word
8255 has 3 modes of operation
• Mode 0: This is simple I/O mode here Port A, Port B and Port C can be
used as either as input or output ports
• Mode 1: Port A and Port B used as 8bit I/O ports. Each port used
three lines from Port C as handshake signals.
Mode 2
Programmable interrupt controller 8259
Control Words of 8259
• ICW2 is used to assign INT type no to
the various interrupts at from IR0 to IR7.
here the D0 to D2 values will vary from
000 to 111 depending on IR0 to IR7.
ICW4
In not special fully nested mode the, if
8259 is already servicing a interrupt from
one of its slave then an another interrupt
from the same slave during the execution
of the previous interrupt will be masked.
In special fully nested mode, it checks
whether the interrupt is of higher priority
or lower. And processes it accordingly.
ICW3
• For a master, defines which of its port is connected to a Slave, if it is 1
then the IR port corresponding to it is a slave. For eg:
If ICW3= 00001010, the IR1 and IR3 are connected to slaves.
• For a Slave it defines port to which it is connected by using the last
three bits. For eg :
if ICW3= 00000011, then it connected to port IR2.
Operational Command Word
DMA Controller 8237
Architecture of DMA Controller
Pin Diagram of DMA Controller
A0 to A3 and internal flipflop will decide
the register accessed. 0000 to 0111 –
address and
counter register
1001 for reading the status register
Command Register
Status Register
Mode Register
• Demand mode where transfer of data
Find the continues till DREQ is Deactivated or if the
value of terminal count has reached.
the • Block mode – the DREQ can be deactivated
mode and the data transfer go until the TC is
register so reached.
as to • In single mode the DREQ is held active till
select one byte of data is being transferred and
then give the control of system bus to the
8086 by deactivating its HRQ for one bus
cycle.
• In cascade mode, several Dma’s can be
cascaded to expand the no of channels.
channel 2 to transfer data from memory to I/O using • In write transfer option the DMA transfers
autoinitialization, address increment, single byte from an I/O device to memory by activating
transfer. IOR and MEMW.
• In Read transfer, from memory to I/O
device.(MEMR and IOW)
Microcontroller 8051
Main features of a micro controller
• As a true computer on a chip – CPU, memory, timer, i/o ports,etc.
• Specific application based systems where we don’t require huge memory
or powerful processors.
• So for such applications the systems are realized with minimum chip
count. Advantages are system is small consumes less power and space
and can be easily designed.
• The system is designed to have a embedded or a single application and
therefore the single application software need not be in the secondary
storage, therefore it is ROM based.
• This makes it even more faster since it is inside the chip and the
instructions are also defined inside the chip. Therefore the execution
becomes faster.
Embedded Applicatons
• House hold applications: Cameras, Toys, Washing Machines,
Microwave ovens, CD Players, Home security systems.
• Office Equipments – Fax machines, Printers, Modem, etc
Key features required
• Requires on chip oscillators
• On chip RAM of limited size • On chip ROM of limited size.
• On chip I/O ports
• Timer – Counter on the chip.
• Large set of special purpose registers.
• Harvard Architecture – Separate Program memory and Data
Memory.
Program Memory that can be used in
microcontroller
• ROM – Industrial Application.
• EPROM – For Development and Testing.
• NVRAM – Non Volatile RAM by using a Lithium Cell
• Flash EPROM – Similar to EEPROM.
Watchdog Timer
• Reset ‐> Initalization ‐>Application Program ‐>Reset Watchdog Timer.
• Loops between Application program and Watchdog Timer.
• If there is any fault then I goes back to initialization state once it
reaches the timer count.
Major Features of 8051
• 8 bit CPU.
• Registers are of 8 bit as well as ALU operations will also be 8 bit.
• One Machine Cycle comprises of 12 clock cycles.
• 4K bytes of On‐chip ROM.
• 128 bytes of On‐chip RAM
• Two timer counters of 16 bits
• Powerful interrupt structure
Memory Organization of 8051
• ROM (0000 – 0FFF) – 4kb
• External ROM can be connected which can have memory upto
64kB(1000H – FFFFH) if the internal ROM is not sufficient.
• External RAM can also be used here of 64kB.
• 21 Special Function registers.
• 4 banks of 8 registers which are mapped to the internal RAM. From
00 to 1F of the RAM is allocated for this purpose.(R0 to R7)
• At a particular instant only one of the bank can be selected by the
programmer.
Special Purpose Registers
• A – Accumulator (E0H)
• B – mainly used while multiplication and divide operation. Also can be
used as general purpose register. (F0H)
• DPH and DPL – Data Pointer high and low – is used for accessing
external memory addresses.(83 and 82)
• IE – Stands for Interrupt Enable( A8H)
• IP – Stands for Interrupt Priority.( B8H)
• P0 to P3 are data buffers of the four input Ports.
• PC – Program Counter
Cont.
• SP‐ Stack Pointer
• TMOD‐ Timer or Counter Mode Controller
• TCON – Timer or Counter Controller
• TL0 – Timer 0 lower order byte
• TH0 – Timer 0 higher order byte
• TL1 – Timer 1 lower order byte
• TH1 – Timer 1 higher order byte
• SCON – Serial Control
• SBUF – Serial Data Buffer
Program Status Word Register
CY AC F0 RS1 RS0 OV X P
Carry Aux Carry User Flag Select Register Bank Overflow Parity
Interrupt Structure
• 5 interrupts apart from reset.
• Each interrupt can be individually enabled or disabled using IE
register. EA X X ES
ETI EX1
ET0 EX0
Interrupt Structure
• 5 interrupts apart from reset.
• Each interrupt can be individually enabled or disabled using IE
register.
Interrupt enable And Interrupt Priority
EA X X ES ETI EX1 ET0 EX0
We can also assign priority to the interrupts by setting it to 1 and 0
PS PT1 PX1 PT0 PX0
Addressing Modes of 8051
• Immediate addressing mode
• MOV A,#05H; Mov immediate value 05 to A
• Register addressing mode:
• MOV A,R0 ;Mov the contents of R0 to A
• Direct addressing mode
• MOV A,30H; Mov the data at the Memory location 30H in the RAM to the
Accumulator
• Register Indirect addressing mode
• MOV A,@R0 ; Copy the data at the address location pointed by R0.
• Indexed Addressing mode
• MOVC A,@A+DPTR ; Here the content of A register is added with content of
DPTR and the resultant is the address of memory location from where the data
is copied to A register
Memory Location Data
1287 30h
• What will be the value at Register A. 1288 45h
128C 26H
128D 44h
Address of the registers in the RAM location
Data Exchange
• XCH A,R5 ; Exchange Bytes between A and R5
• XCH A,@R2 ; Exchange data byte in register A and the data in the
address pointed by R2
• XCHD A,@R1 ; Exchange the lower nibble of A and the data in the
address pointed by R2
Bit
Addresses
PIN Diagram of 8051
Pin Description
• VCC – 5V source.
• P0.0 – P0.7 (Multiplexed with AD0 –AD7)
• P2.0 – P2.7 (Multiplexed with A8 – A15)
• P1.0 – P1.7
• P3.0 (RXD) – Serial Input
• P3.1 (TXD) – Serial Output
• P3.2 (INT0) ‐ External Interrupt 0
• P3.3 (INT1) – External Interrupt 1
• P3.4 (T0) – Clock Input to Timer 1
• P3.5 (T1) – Clock Input to Timer 2
• P3.6 (WR) – External Memory Write (Active Low)
• P3.6 (RD) – External Memory Read (Active Low)
• EA (External Access) – (Active Low)
• (PSEN): Pin 29 is the Program Store Enable Pin (PSEN). Using this
pins, external Program Memory can be read. (Active Low)
• ALE: Pin 30 is the Address Latch Enable Pin. Using this Pins, external
address can be separated from data (as they are multiplexed by
8051)
• XTAL1 , 2 – Connection to the Quartz Crystal
• RST – Reset
• GND‐ Ground
Data Types and Directives
• DB
• Data1: DB 28 ; Decimal
• Data2: DB 01010011B; Binary
• Data3: DB 39H ; Hex
• ORG
• EQU
• END
• Write a Code to Add Two numbers 28D5H and 3572H?
SETB P1.2
LOOP: MOV R1, #FFH
HERE: DJNZ R1, HERE
CPL P1.2
SJMP LOOP
Led Blinking
START: CPL P1.2
WAIT: MOV R4,#05H
WAIT1: MOV R3,#FFH
WAIT2: MOV R2,#FFH
WAIT3: DJNZ R2,WAIT3 DJNZ
R3,WAIT2
DJNZ R4,WAIT1
SJMP START