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Protection Design
ESD simulated directly in the time-domain using the transient solver (FIT or TLM)
Numerical Prediction and Measurement of ESD Radiated Fields by Free-Space Field Sensors
S. Caniggia, F. Maradei, IEEE Trans. Elec. Comp. Vol. 49 No.3, Aug 2007
4 kV applied to
excitation port
NoiseKen ESD
Generator
Induced voltage in
semi-circular loop
Excellent agreement of simulation results and measurements for both discharge current (top) and
induced voltage in one of the semi circular loops (bottom).
www.cst.com | CST workshop series 2011 | February 10 | 14
Quick Approach by CST PCB STUDIO
ESD discharge
voltage 4 kV
Peak voltage at IC Pin: 375 V Peak voltage at IC Pin: 250 V Peak voltage at IC Pin: 75 V
voltage in V
200 200 200
50 50 50
0 0 0