EC 204: ANLOG CIRCUITS LABORATORY

Experiment 5

Programmable Gain Amplifier

Manzil Zaheer 08010252

Sachin Rajoria 08010826
Payoj Kissan 08010823

To design and implement a programmable gain amplifier (PGA) with the given specifications.
Objective:
To design and implement a programmable gain amplifier (PGA) with the given specifications as below
using analogue switch CD4066

Specifications:
a) One analogue input
b) One analogue output
c) Two TTL control inputs (A and B) decide the gain of the PGA as follows:
A B Gain
0 0 1
0 1 20
1 0 50
1 1 100

Instruments/Materials Required:
1. Breadboard x2
2. Function generator x1
3. Split DC Power Supply: +5V, 0V, -5V x1
Design 1 Design 2
4. NPN Transistor: 2N2222A x7 8. NPN Transistor: 2N2222A x8
5. OpAmp : 741 x1 9. OpAmp : 741 x1
6. Analogue Switch: CD4066 x1 10. Analogue Switch: CD4066 x1
7. Resistors: 11. Resistors:
a. 150 Ω x2 a. 1 kΩ x3
b. 560 Ω x1 b. 10 kΩ x8
c. 1 kΩ x1 c. 47 kΩ x2
d. 10 kΩ x7 d. 100 kΩ x4
e. 22 kΩ x1 12. Hex TTL Inverter: 74LS04 x1
f. 100 kΩ x3 13. Quad TTL NAND: 74LS00 x1

Theory:
A programmable gain amplifier (PGA), as the name implies, is a device which produces an amplified
output to an analogue input with the magnitude of gain depending upon two TTL control inputs which
can be given through a programmable device like a computer or a microprocessor. The following shows
the PGA schematically:

Programmable Gain
Amplifier
The PGA can designed using an OpAmp in non-inverting coniguration and processing the input signal
desirably so as to alter the feedback circuit and in turn programme the overall gain.

Analogue
Input 𝑣𝑣𝑖𝑖
Analogue
OpAmp
Output 𝑣𝑣𝑜𝑜

Feedback

Digital Signal
Processing

A B
TTL Control Inputs

Design 1 Analogue
One of the probable solutions to design a PGA is Input 𝑣𝑣𝑖𝑖 U1
by employing a non-inverting amplifier using an 741
OpAmp with the feedback resistances connected Analogue
through switches. Output 𝑣𝑣𝑜𝑜

In the schematic shown, the three resistances

𝑅𝑅1 , 𝑅𝑅2 and 𝑅𝑅3 are connected to the non-
S1 S2 S3
inverting OpAmp setup through the switched
𝑆𝑆1 , 𝑆𝑆2 and 𝑆𝑆3 respectively. We control the
switches through the two digital control inputs,
and thus programme the gain.

Note: We need atleast 3 switches because it is R1 R2 R3

not possible to obtain the desired gains using 2
switches only, as the equations setup in latter
case turn out to be inconsistent. A third control
signal can be generated using AND operation
between A and B. This AND operation can be
easily realized with two BJTs.
The working of switches is desired to be as follows:

Control Signals Analogue Switch Resistances

A B 𝑺𝑺𝟏𝟏 𝑺𝑺𝟐𝟐 𝑺𝑺𝟑𝟑 𝑹𝑹𝟏𝟏 𝑹𝑹𝟐𝟐 𝑹𝑹𝟑𝟑
0 0 Open Open Open Not connected Not connected Not connected
0 1 Open Close Open Not connected Connected Not connected
1 0 Close Open Open Connected Not connected Not connected
1 1 Close Close Close Connected Connected Connected

Now values of all resistances can be calculated as per the gain requirements and using the standard
formula for non-inverting amplifier:

𝑅𝑅𝑓𝑓
𝐴𝐴𝑣𝑣 = �1 + �
𝑅𝑅
1. A=0, B=0, Gain=1
Since none of 𝑅𝑅1 , 𝑅𝑅2 and 𝑅𝑅3 are connected, the OpAmp just acts as a buffer, hence
𝑣𝑣𝑜𝑜 = 𝑣𝑣𝑖𝑖
2. A=0, B=1, Gain=20
𝑅𝑅𝑓𝑓 𝑅𝑅𝑓𝑓
20 = �1 + � 𝑅𝑅2 = − 𝑟𝑟𝑜𝑜𝑜𝑜
𝑅𝑅2 + 𝑟𝑟𝑜𝑜𝑜𝑜 19
3. A=1, B=0, Gain=50
𝑅𝑅𝑓𝑓 𝑅𝑅𝑓𝑓
50 = �1 + � 𝑅𝑅1 = − 𝑟𝑟𝑜𝑜𝑜𝑜
𝑅𝑅1 + 𝑟𝑟𝑜𝑜𝑜𝑜 49
4. A=1, B=1, Gain=100
𝑅𝑅𝑓𝑓 𝑅𝑅𝑓𝑓 𝑅𝑅𝑓𝑓 𝑅𝑅𝑓𝑓
100 = �1 + � 99 = + + 99
(𝑅𝑅1 + 𝑟𝑟𝑜𝑜𝑜𝑜 ) ∥ (𝑅𝑅2 + 𝑟𝑟𝑜𝑜𝑜𝑜 ) ∥ (𝑅𝑅3 + 𝑟𝑟𝑜𝑜𝑜𝑜 ) 𝑅𝑅1 + 𝑟𝑟𝑜𝑜𝑜𝑜 𝑅𝑅2 + 𝑟𝑟𝑜𝑜𝑜𝑜 𝑅𝑅3 + 𝑟𝑟𝑜𝑜𝑜𝑜
𝑅𝑅𝑓𝑓 𝑅𝑅𝑓𝑓
= 49 + 19 + 𝑅𝑅3 = − 𝑟𝑟𝑜𝑜𝑜𝑜
𝑅𝑅3 + 𝑟𝑟𝑜𝑜𝑜𝑜 31

From the above obtained equations possessing 1 degree of freedom, if 𝑅𝑅𝑓𝑓 is set to 22 kΩ and
considering 𝑟𝑟𝑜𝑜𝑜𝑜 to be 150 Ω, then

𝑅𝑅1 = 298.98 Ω𝑅𝑅2 = 1007.89 Ω𝑅𝑅3 = 559.68 Ω

Thus we choose appropriate standard resistor values to obtain the nearest possible gains to the desired
values.

But the biggest drawback of this design is that the gain depends significantly on the 𝑟𝑟𝑜𝑜𝑜𝑜 of the analogue
switch. Since 𝑟𝑟𝑜𝑜𝑜𝑜 cannot be fixed and varies with current and temperature, the gain of the PGA deviates
considerably from the desired values. One more practical drawback of this circuit is the considerable
noise present in the gain one case due to presence of high resistance in the feedback path of OpAmp
when working as a buffer though.
Design 2
In this design also we use basically the non-inverting setup of the OpAmp, but the locations of switches
are changed. The observation to be made is that if effect 𝑟𝑟𝑜𝑜𝑜𝑜 has to removed, then negligible current
should flow through it. Indeed negligible current flows through the inputs of the OpAmp, so if the
switches are placed next to inputs of the OpAmp, then the effect of 𝑟𝑟𝑜𝑜𝑜𝑜 can be eliminated.

So consider the following configuration:

Analogue U1
Input 𝑣𝑣𝑖𝑖 Analogue
741
Output 𝑣𝑣𝑜𝑜

S0

R1
S1

R2
S2

R3
S3

R4

The working of switches is desired to be as follows:

Control Signals Analogue Switch Gain

 A B 𝑺𝑺𝟎𝟎 𝑺𝑺𝟏𝟏 𝑺𝑺𝟐𝟐 𝑺𝑺𝟑𝟑 𝑨𝑨𝒗𝒗 = 𝒗𝒗𝒐𝒐 /𝒗𝒗𝒊𝒊

0 0 Closed Open Open Open 1

𝑅𝑅1
0 1 Open Closed Open Open +1
𝑅𝑅2 + 𝑅𝑅3 + 𝑅𝑅4
𝑅𝑅1 + 𝑅𝑅2
1 0 Open Open Closed Open +1
𝑅𝑅3 + 𝑅𝑅4
𝑅𝑅1 + 𝑅𝑅2 + 𝑅𝑅3
1 1 Open Open Open Close +1
𝑅𝑅4
The above mentioned desired working of switch can be obtained using 2-to-4 decoder.

In this case also we obtain equations having one degree of freedom

𝑅𝑅1 = 95 𝑅𝑅4 𝑅𝑅2 = 3 𝑅𝑅4 𝑅𝑅3 = 𝑅𝑅4

On choosing 𝑅𝑅4 as 1 kΩ, we obtain

𝑅𝑅1 = 95 𝑘𝑘Ω𝑅𝑅2 = 3 𝑘𝑘Ω𝑅𝑅3 = 1 𝑘𝑘Ω

Thus we choose appropriate standard resistor values to obtain the nearest possible gains to the desired
values.

In this case dependence of gain on 𝑟𝑟𝑜𝑜𝑜𝑜 of the analogue switch is eliminated and the noise in gain 1 case
is also removed. But the additional price of the extra processing of the digital control signals and use of 1
more switch has to be paid.

Level-Shifter
CD4066 contains four independent analogue switches. The CD4066 uses single or bipolar power supply
𝑉𝑉𝐷𝐷𝐷𝐷 and 𝑉𝑉𝑠𝑠𝑠𝑠 . The power supply must be greater than the maximum analogue input applied. Since input
signal to the PGA will be in general bipolar, the power supply to CD4066 must be bipolar. We choose the
power supply to be ±5 𝑉𝑉, well within the limit of CD4066 and well above the expected analogue input.
Each switch has one analogue input, one analogue output and a bipolar control signal C such that
𝐶𝐶 = 𝑉𝑉𝐷𝐷𝐷𝐷 ⇒ 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠ℎ 𝑖𝑖𝑖𝑖 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = 𝑉𝑉𝑆𝑆𝑆𝑆 ⇒ 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠ℎ 𝑖𝑖𝑖𝑖 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜

Thus, bipolar control signals for the analogue switches must be generated from the processed digital
control signal, which are directly incompatible. For this purpose a level shifter is used to convert the TTL
control signals to bipolar control signal of +𝑉𝑉𝐷𝐷𝐷𝐷 and −|𝑉𝑉𝑆𝑆𝑆𝑆 |.

Consider the following circuit:

5V
R3
VDD 10k Ω
5V
R2
10k Ω Bipolar Signal, 𝑉𝑉𝑜𝑜
D
Q2
BZV55-B6V8
R1 2N 2222A
1 Q1
100k Ω -5V
2N 2222A
VSS
TTL Signal, 𝑉𝑉𝑖𝑖

1. When TTL digital signal is low, i.e. input is 0 V, transistor Q1 is in cutoff region. Thus, Q1 can be
considered to be disconnected from the circuit. Now reverse voltage across the zener diode
cannot exceed its breakdown voltage, so in whatever region the zener is operating, the voltage
at base of transistor Q2 will be sufficiently higher than 𝑉𝑉𝑆𝑆𝑆𝑆 so as to force it into saturation
region. Therefore final output will be 𝑉𝑉𝑆𝑆𝑆𝑆 + 𝑉𝑉𝐶𝐶𝐸𝐸𝑆𝑆𝑆𝑆𝑆𝑆 ≈ −5 𝑉𝑉.

2. When TTL digital signal is high, i.e. input is 5 V, current flowing through base of transistor Q1 can
be found out using KVL as
𝑉𝑉𝑖𝑖 = 𝐼𝐼𝐵𝐵 𝑅𝑅1 + 𝑉𝑉𝐵𝐵𝐵𝐵
For typical values of 𝑉𝑉𝐵𝐵𝐵𝐵 , we get base current as
𝐼𝐼𝐵𝐵 = 43 𝜇𝜇𝜇𝜇
which a TTL device can easily source at logic high level. This situation is sufficient to drive
transistor Q1 into saturation. So now voltage across the zener diode can never become equal
than its breakdown voltage, as it can be at the most be 5𝑉𝑉 − 𝑉𝑉𝐵𝐵𝐵𝐵 ≈ 4.3 𝑉𝑉. Infact it is much
lower than reverse knee voltage of 6.8V. So, the zener diode acts as a normal diode and does
not allow any current to through in reverse direction. This forces the transistor Q2 to operate in
cutoff region. Therefore final output is 𝑉𝑉𝐷𝐷𝐷𝐷 = +5 𝑉𝑉
We check the effectiveness of our level shifter circuit by considering the worst case values for the TTL
signals, i.e. +2.7 V for logic high and +0.8V for logic low

1. The worst case TTL logic low voltage is +0.8 V, for which the base current to transistor Q1 is
given by
𝑉𝑉𝑖𝑖 = 𝐼𝐼𝐵𝐵 𝑅𝑅1 + 𝑉𝑉𝐵𝐵𝐵𝐵
For typical values of 𝑉𝑉𝐵𝐵𝐵𝐵 , we get base current as
𝐼𝐼𝐵𝐵 = 1 𝜇𝜇𝜇𝜇
Typically 𝛽𝛽 of Q1 will lie in between 100 to 200, so collector current would be around 100 µA to
200 µA, which won’t affect the working of circuit lying ahead. So, the final output will be still
guaranteed as 𝑉𝑉𝑆𝑆𝑆𝑆 + 𝑉𝑉𝐶𝐶𝐸𝐸𝑆𝑆𝑆𝑆𝑆𝑆 ≈ −5 𝑉𝑉

2. The worst case TTL logic high voltage is +2.7 V, for which the base current to transistor Q2 is
given by
𝑉𝑉𝑖𝑖 = 𝐼𝐼𝐵𝐵 𝑅𝑅1 + 𝑉𝑉𝐵𝐵𝐵𝐵
For typical values of 𝑉𝑉𝐵𝐵𝐵𝐵 , we get base current as
𝐼𝐼𝐵𝐵 = 20 𝜇𝜇𝜇𝜇
which a TTL device can easily source at logic high level. This situation is sufficient to drive
transistor Q1 into saturation. The working of circuit lying ahead which depends only on the
saturation of transistor Q1 won’t be affected. . So, the final output will be still guaranteed as
𝑉𝑉𝐷𝐷𝐷𝐷 = +5 𝑉𝑉

Thus our level shifter works well with the TTL level signals.
 Level Shifter
VSS BiPolarTTL
-5V
SC4
1k Ω MC74H C4066D *
Level Shifter
R f4 VSS BiPolarTTL
4EN
4Y 4A
3EN Y4
3Y 3A SC3 Y3
2EN Y2
2Y 2A Level ShifterY1
1k Ω 1EN
1Y 1A BiPolarTTL
R f3 VDD

Y4

Y3

Y2

Y1
U3 SC2
Level Shifter
3k Ω 5V BiPolarTTL
R f2 VDD

74LS04D

74LS04D

74LS04D
SC1

74LS04D
U2D

U2E

U2F
U2C
95k Ω
R f1

74LS00D

74LS00D

74LS00D

74LS00D
U1A

U1B

U1C

U1D
VSS
-5V
4

74LS04D
0°
741 100 Hz

U2A
2
25mVpk
6 U4
3
Vi
5 1 7
5V

74LS04D
2-to-4 Decoder

U2B
I1
 5V
R 13
Level Shifter VDD 10k Ω
5V
BiPolar
R 12
10k Ω
D2
Q6
BZV55-B6V8
TTL R 11 2N 2222A
Q4
100k Ω -5V
2N 2222A
VSS

Design 1
Control Signal Processing Block
 5V

VDD R 34
5V 10k Ω

R 33 AB
VDD 10k Ω
5V D3
Q33
VDD R 19
10k Ω B ZPD6.8
5V 2N 2222A
R 31
R3 Q31
10k Ω 100k Ω -5V
D1 2N 2222A VSS
Q12
ZPD6.8
U5 R 11 2N 2222A
1 Q11
Key = B 100k Ω -5V
2N 2222A
VSS

VDD
5V
R 23
VDD 10k Ω A
5V R 32
Q32
R 22 100k Ω
10k Ω 2N 2222A
D2
Q22
ZPD6.8 -5V
U6 R 21 2N 2222A
VSS
0 Q21
Key = A 100k Ω -5V
2N 2222A
VSS

Amplifier Block
 5V
7 1 5
V2
3
U1 6
25mVpk
100 Hz 2
741
0° Rf RL
4
VSS 22k Ω 10k Ω
-5V

R8
R1 560Ω
299Ω

R2
VDD 1008Ω
5V

U2
MC74H C4066D *
VDD
1Y
2Y
3Y
4Y
1EN
2EN

3EN
4EN
VSS
1A
2A
3A
4A

A B AB

-5V
VSS
Observations
Design 1
Analogue signal input frequency = 500 Hz

Control Inputs (TTL) Analogue Input Analogue Output Gain

A B 𝒗𝒗𝒊𝒊(𝒑𝒑−𝒑𝒑) 𝒗𝒗𝒐𝒐(𝒑𝒑−𝒑𝒑) 𝒗𝒗𝒐𝒐 /𝒗𝒗𝒊𝒊
0 0 400 400 (Noisy) 1
0 1 50 1050 21
1 0 50 2800 56
1 1 50 5260 105.2

Design 2
Analogue signal input frequency = 500 Hz

Control Inputs (TTL) Analogue Input Analogue Output Gain

A B 𝒗𝒗𝒊𝒊(𝒑𝒑−𝒑𝒑) 𝒗𝒗𝒐𝒐(𝒑𝒑−𝒑𝒑) 𝒗𝒗𝒐𝒐 /𝒗𝒗𝒊𝒊
0 0 100 100 1
0 1 50 992 19.84
1 0 50 2490 49.8
1 1 50 5000 100

Conclusion
A programmable gain amplifier whose gain can be controlled was successfully designed and
implemented using discrete components. The two designs proposed works but both have its advantages
and drawbacks.

1. Design 1 is comparatively simple, but it is dependent highly on 𝑟𝑟𝑜𝑜𝑜𝑜 . But if we make 𝑅𝑅1 ,
𝑅𝑅2 and 𝑅𝑅3 larger, to make effect of 𝑟𝑟𝑜𝑜𝑜𝑜 negligible, correspondingly 𝑅𝑅𝑓𝑓 will also increase. This
higher 𝑅𝑅𝑓𝑓 results in larger noise, when gain 1 is required. So, we have to trade-off between noise
in gain stage 1 and independence from effect of 𝑟𝑟𝑜𝑜𝑜𝑜 .
2. Design 2 is relatively complicated and includes use of TTL IC. But this makes the circuit
independent of 𝑟𝑟𝑜𝑜𝑜𝑜 , also noise is reduced. Moreover much closer values of desired gains are
achieved.