Computer Architecture Assignments 1 to 12

A1
1) Where can the program data be stored permanently?
a) Memory
b) Hard Disk

ANS: b

2) Is a computer smarter than human brain? True or False

ANS: false

3) Which instruction is typically not part of an Instruction Set Architecture?

a) mul
b) sub
c) or
d) add14

ANS: d

4) What is an example of CISC instruction set?

a) ARM
b) IBM PowerPC
c) Intel x86
d) HP PA-RISC

ANS: c

5) Is sbn instruction a Turing complete instruction? True or False

ANS: true

6) Which of the following is an Universal operation?

a) AND
b) OR
c) NOR
d) XOR

ANS: c

7) What is the value of 11110101 (8 bit binary in 1’s complement form) in decimal?
a) 10
b) -117
c) 245
d) -10

ANS: d

8) What is the value of (243)5 in decimal?

a) 73
b) 11
c) 55
d) 97

ANS: a

9) What is the value of (4090)10 in hexa-decimal?

(FEA)16
(FFA)16
(EFA)16
(EEA)16

ANS: b

10) What is in 2’s complement binary representation of -4?

1100
0100
1010
0101

ANS: a
A2
1) What is the binary encoding for "ld r0, [sp]"
a) 01110 1 0000 1110 000000000000000000
b) 00000 1 0100 0100 010000000000000011
c) 00001 1 1110 1110 000000000000000100
d) 01000 0 0100 0000 000000000000000101
Ans - (a)

2) Assembly languages are specific to:

a) Compiler
b) Operating System
c) Hardware
d) Instruction set Architecture
Ans - (d)

3) Assemblers are:
a) programs that convert high level language to low level language
b) programs that convert low level language to machine language
c) programs that convert high level language to machine language
d) all of the above
Ans - (b)

4) Program counter contains the address of

a) current instruction
b) next instruction
c) previous instruction
d) It stores data not the address
Ans - (a)

5) How many instructions are present in simple RISC ISA

a) 19
b) 20
c) 21
d) 22
Ans - (c)

6)"mov" instruction is used to:

a) transfer contents of one register to another
b) transfer content of immediate to register
c) both a and b
d) none
Ans - (c)
7) How many Arithmetic instructions are present in simple RISC ISA
a) 5
b) 6
c) 10
d) 8
Ans - (b)

8) Load and store instructions are used to perform:

a) memory operation
b) register operation
c) both
d) none
Ans - (a)

9) Return instruction is used for:

a) puts return address register (ra) value in pc
b) puts ra + 4 value in pc
c) puts pc + 4 value in ra
d) none of the above
Ans - (a)

10) ret instruction is:

a) 0 address instruction
b) 1 address instruction
c) 2 address instruction
d) 3 address instruction
Ans - (a)
A3
1) What is the return PC after a function call?
a) pc
b) pc+1
c) pc+2
d) pc+4

ANS: d

2) The arguments to a function can only be passed using registers. True or False
a) True
b) False

ANS: b

3) Which is the return address register?

a) r0
b) r15
c) r13
d) r14

ANS: b

4) What is the value of r1 after mvn r1, #3 is executed?

a) 0x00000003
b) 0xFFFFFFC
c) 0xFFFFFFE
d) 0xFFFFFFD

ANS: b

5) Which instruction is equivalent to r1 = 8*r2

a) mul r1, r2, #8
b) lsl r1, r2, #3
c) Both a and b
d) None

ANS: c

6) Flags can be set only by the cmp instruction. True or False?

a) True
b) False
ANS: b

7) A stack can solve

a) space problem
b) overwrite problem
c) management of activation blocks
d) all the above

ANS: d

8) What is the actual address to jump in a b offset instruction?

a) PC + offset
b) PC - offset
c) PC + 4*offset
d) PC – 4*offset

ANS: c

9) What is the binary encoding of “add r0, r1, 1” in SimpleRISC ISA?

a) 00000 1 0001 0000 000000000000000001
b) 00000 0 0000 0001 000000000000000001
c) 00000 1 0000 0001 000000000000000001
d) 00000 0 0001 0000 000000000000000001

ANS: c

10) Instruction to compute 2’s complement of a number stored in r0 is

a) rsb r1, r0, #0
b) mvn r1, r0
c) sub r1, r0, #0
d) bic r1, r2, r2

ANS: a
A4
1) Which instruction is used to make a function call in ARM? bl
2) What is the encoding of 0x0B A0 00 00 in 12-bit ARM rot+payload immediate format? 0x6BA
3) Branch target in bl offset instruction in ARM is: PC + 8 + 4*offset
4) What is the preferred method to return from a function call in ARM? bx lr
5) What does stmfd instruction do in ARM? spill a set of registers
6) We can run the 16 bit ISAs on a modern 64 bit x86 processor. True or False? True
7) x86 can even Support 8 bit Registers. True or False? True
8) How many floating point registers are there in x86 ISA? 8
9) How many segment registers are there in x86 ISA? 6
10) Which memory addressing mode is supported by x86? all the above ( base + offset, base +
scale*index, base + scale*index + offset)

A5
1. Is an x86 processor aware of the presence of the stack? True
2. The stack pointer is stored in the register: esp
3. The compare instruction in x86 processor sets the flags. True
4. eax and edx in imul instruction (1 operand form) contain - lower 32 bits and upper 32 bits
resp
5. The call instruction saves the return address on - stack
6. The rep prefix repeats the instruction n times. The value of n is present in -register ecx
7. Integer and Floating point registers are connected through: Memory
8. fild instruction: pushes integer stored in memory to FP stack
9. finit instruction resets the: all of the above (status of FP unit, FP stack, FP registers)
10. fcomi instruction: compares the values of FP registers and sets the flags
A6

1) An NMOS transistor is made up of:

a) two p-type wells in an n-type substrate.
b) two n-type wells in a p-type substrate.
c) None of the above
Ans-b

2) A PMOS transistor is made up of:

a) two p-type wells in an n-type substrate.
b) two n-type wells in a p-type substrate.
c) None of the above
Ans-a

3) A NOR gate consists of:

a) 2 transistors
b) 3 transistors
c) 4 transistors
d) 5 transistors
Ans-c

4) Multiplexer:
a) n inputs, 1 output
b) 1 input, n outputs
c) n inputs, 1 output based on the select bits
d) n inputs, log(n) outputs
Ans-c

5) Encoder:
a) n bits input, log(n) bits output
b) n inputs, log(n) output
c) n inputs, log(n) bits output
d) None of the above
Ans-c

6) In an SR latch, if S=0 and R=0, then Q is

a) 0
b) 1
c) Maintain old value
d) Not defined
Ans-c
7) In a master slave J-K flip flop:
a) master gives the final output
b) slave gives the final output
c) none of the above
Ans-b

8) Implementation of a sram cell compared to a dram cell requires:

a more number of transistors
b less number of transistors
c same number of transistors
Ans a

9) In an array of SRAM cells:

a) Only one row can be enabled at a time
b) Only one column can be enabled at a time
c) all the cells in a column can be enabled at a time
d) none of the above
Ans-a

10) CAM cell:

a) Enable cells by their address
b) Enable cells by their content
Ans-b
A7

1) How long does the n-bit Ripple Carry Adder take? t​h​ is time for half adder and t​f​ is time for full
adder.

a) n*t​f
b) n*t​h
c) t​h​ + (n-1)t​f
d) t​f​ + (n-1)t​h

ANS: c

2) What is the time-complexity of a n-bit Ripple Carry Adder?

a) O(1)
b) O(n​2​)
c) O(n)
d) O(log n)

ANS: c

3) What is the time-complexity of a n-bit Carry Select Adder?

a) O(1)
b) O(√n)
c) O(n)
d) O(log n)

ANS: b

4) What is the time-complexity of a n-bit Carry Look Ahead Adder?

a) O(1)
b) O(√n)
c) O(n)
d) O(log n)

ANS: d

5) What is the time-complexity of a n-bit Booth Multiplier?

a) O(n)
b) O(n*n)
c) O(n*√n)
d) O(n*log(n))
ANS: d

6) What is the time-complexity of a n-bit Tree-based Multiplier?

a) O(n)
b) O(n*√n)
c) O(n*log(n))
d) O(log(n)*log(n))

ANS: d

7) What is the time-complexity of a n-bit Carry Select Adder if k is set to 1?

a) O(1)
b) O(√n)
c) O(n)
d) O(log n)

ANS: c

8) What is the time-complexity of a n-bit Wallace-Tree Multiplier?

a) O(√n)
b) O(n)
c) O(log(n))
d) O(log(n)*log(n))

ANS: d

9) What action should be taken when current value is 0 and previous value was 1 in case of
Booth’s multiplication?

a) Subtract multiplicand from U

b) add multiplicand to U
c) None of the above

ANS: b

10) Can we use Booth’s multiplier for multiplication of negative numbers?

a) Yes
b) No

ANS: a
A8
1) How many iterations are used by Restoring algorithm to divide two 32 bit numbers?
32
2) Restoring division algorithm uses:
Left shift operation
3) Time complexity of each iteration in Restoring algorithm is:
log(n)
4) Assume that U contains remainder and D contains Divisor. If (U-D)>=0,then
Both Restoring and Non Restoring algorithms produces the same results.
5) How many rounding modes are available in IEEE 754 standard?
4
6) What is the condition for incrementing the significand in Round to Nearest mode?
(Residue > 0.5) OR (Residue = 0.5 AND lsb(P)=1)
7) Time complexity of Goldschmidt algorithm is:
log(n)*log(n)
8) Number of steps and complexity of each step in Newton Raphson method is:
log(n) and log(n)
9) Normalization operation in multiplication of floating point numbers can be done by using:
Both (Left shift operation, Right shift operation)
10) Implementation of rounding needs:
Both (sticky bit, round bit)
A9
1) The value of isBranchTaken in case of call, ret and b instruction is

a) 0
b) 1

ANS: b

2) The isImmediate signal choses a value between

a) op1 and op2
b) immx and op1
c) immx and op2

ANS: c

3) The write port Address in RW Unit can be

a) pc
b) ra(15)
c) rd(inst[23:26])
d) both b and c

ANS: d

4) The write port Data in RW Unit can be

a) aluResult
b) ldResult
c) pc+4
d) all the above

ANS: d

5) Which is not an input to the Control Unit?

a) opcode
b) inst[23:26]
c) I bit

ANS: b

6) The isWb signal is not set for which instruction?

a) mul
b) ld
c) b
d) call

ANS: c

7) The isAdd signal is set for which instruction?

a) add
b) ld
c) st
d) all the above

ANS: d

8) The following Microinstructions is an implementation of which SimpleRISC instruction?

mbeq flags.GT, 1, .branch
mb .begin
.branch:
mmov pc, branchTarget
mb .begin

a) beq
b) bgt
c) b
d) call

ANS: b

9) The following Microinstructions is an implementation of which SimpleRISC instruction?

mmov regData, pc
mmovi regSrc, 15, <write>
mmov pc, branchTarget
mb .begin

a) beq
b) bgt
c) b
d) call

ANS: d

10) Which Microprogramming model has a larger instruction size?

a) Horizontal Microprogramming
b) Vertical Microprogramming
ANS: a

A10
1. Microprogrammed processors are much faster than hardwired processors.
a) True
b) False

Ans- b

2) How many instructions are processed simultaneously in a 7 stage pipelined processor.

a) 2
b) 5
c) 7
d) 4

Ans - c

3) How many latches are required in a n stage pipelined processor.

a) n
b) n-1
c) 2n
d) n/2

Ans- b

4) If the two instructions - {add r1, r2, r3} and {mul r5, r1, r4} are passed in the pipeline one after
the other (at two consecutive cycles), it will lead to
a) RAW hazard
b) WAR hazard
c) WAW hazard
d) None of the above

Ans -a

5) Interlocks are:
a) Hardware mechanism
b) Software mechanism

Ans-a

6) Which stage is stalled by the pipeline bubble

a) Same stage
b) next stage
c) previous stage

Ans-c

7) 3 stage forwarding paths are from

a) RW -> OF
b) RW -> EX
c) MA -> OF
d) EX -> OF

Ans -a

8) Load-use Hazard can be handled by forwarding technique.

a) True
b) False

Ans- b

9) Delay slots are used by:

a) Branch lock condition
b) Data lock conditions
c) Both
d) None of the above

Ans-a

10) How many types of interlocks are available:

a) 2
b) 3
c) 4
d) 5

Ans - a
A11
1) The signals for the forwarding multiplexers are generated by the control Unit. True or False?
a) True
b) False

ANS: False

2) In the case when EX stage is a load and the instruction in the OF stage uses its loaded value
then Data Lock Unit creates a
a) Bubble
b) Stall
c) Flush
d) Commit

ANS: b

3) How can the compiler reduce the number of dynamic instructions?

a) Dead code removal
b) Function inlining
c) Both a and b
d) None of the above

4) What is the maximum frequency of a pipelined processor dependent on

a) Maximum clock cycle time of the individual stages
b) Minimum clock cycle time of the individual stages

ANS: a

5) The optimal number of pipeline stages is proportional to (t = Minimum clock cycle time of a
single cycle pipeline, l = latch delay )
a) t/l
b) t*l
c) sqrt(t/l)
d) sqrt(t*l)

6) Which type of memory hardware has least latency?

a) Master Slave D flip flop
b) SRAM cell
c) DRAM cell
ANS: a

7) Which type of memory hardware has least area?

a) Master Slave D flip flop
b) SRAM cell
c) DRAM cell

ANS: c

8) Which type of memory hardware has highest power requirement?

a) Master Slave D flip flop
b) SRAM cell
c) DRAM cell

ANS: a

9) If a resource is accessed at some point of time, then most likely it will be accessed again in a
short period of time. This concept is known as
a) Temporal Locality
b) Spatial Locality

ANS: a

10) If a resource is accessed at some point of time, then most likely similar resources will be
accessed again in the near future. This concept is known as
a) Temporal Locality
b) Spatial Locality

ANS: b

A12
1. Block arrays are used to store:
a. Contents of the blocks
2. Both the tag arrays and block arrays have same number of entries.
a. True
3. A way in a set associative cache is defined as:
a. each entry in a set
4. In write through cache policy
a. Whenever a write is performed in the cache, a write is also performed to its lower
level
5. In write back cache policy
a. The write is just performed in the cache and set the modified bit
6. Global miss rate is defined as:
a. number of misses in a cache at level i divided by the total number of memory
accesses
7. Compulsory misses are:
a. Misses that happen when we read the data for the first time
8. Victim cache is used to eliminate
a. Both conflict and capacity misses
9. Virtual memory refers to:
a. Memory space assumed by program
10. Conflict misses are:
a. Misses that occur due to limited associativity in a set associative cache