INTERNATIONAL JOURNAL FOR RESEARCH & DEVELOPMENT IN
TECHNOLOGY
A NOVEL OPTIMIZED MEMORY ARCHITECTURE
FOR SYSTEM ON CHIP
__________________________________________________________________________________________
Reshma . R1, Anitha. R2, Balaji.G3
Assistant professor of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, Coimbatore
Abstract-Content addressable memory (CAM) is a special
type of computer memory used in certain high speed
searching applications. CAM compares input search data
against a table of stored data and returns the address of the
matching data. CAMs can perform its searching application
in a single clock cycle. The main challenge in designing the
CAM is to reduce the power consumption without reducing
the speed and memory density. In this paper, we introduce a
parity bit that leads to delay reduction, area and power
overhead. The effective gated power technique is proposed to
reduce the dynamic power consumption and enhance the
robustness of the design against process variation.
Index Terms-Content addressable memory (CAM), match-
line, search-line.
I. INTRODUCTION
Most memory devices store and retrieve data by addressing
specific memory locations. For example, a system using RAM
or ROM searches sequentially through memory to locate data.
However this technique reduces the performance of memory
since the searching of data requires multiple clock cycles [1].
It considerably reduces the time required to search by
identifying stored data by content rather than by address.
Memory accessed in this way is called Content addressable
memory (CAM). CAM offers a performance advantage over
other memory search algorithms [2], such as binary based
searches, tree based searches or look aside tag buffers, because
it compares the desired information against the entire list of
pre- sorted entries simultaneously. Thus, CAM provides an
order of magnitude reduction in the search time. CAM is
based on RAM technology [1]. Content addressable memory
(CAM) is a solid state memory in which the data are accessed
by their contents rather than physical location [3], [4].CAM
has simple storage cells; each individual memory bit in a fully
parallel CAM must have its own associated comparison circuit
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Volume-10,Issue-5(Nov-18)
ISSN (O) :- 2349-3585
to detect a match between stored bit and input bit. The match
output from each CAM cell in the data word must be
combined to produce a complete data word match signal.CAM
is almost faster than RAM [3].CAM can offer high speed
search function in a single clock cycle.Generally CAM has
three operation modes: READ, WRITE and COMPARE.in
which compare is the main operation [4]. Fig. 1 shows the
block diagram of conventional CAM. The compare operation
starts by loading an input search word into the search data
register. The search data is then broadcast into the CAM cells
through the pairs of search lines (SLs) and it is compared with
every bit of the stored word by using comparison circuit.
Fig. 1 Block diagram of CAM
Each stored bit will contain a match line (ML) that is shared
between bits in order to obtain the comparison result. The
corresponding matched word obtained will be identified by an
output encoder unit as shown in Fig. 1. Generally, there are
two stages
1. Pre-charge stage
2. Evaluation stage
During pre-charge stage, the Match lines will be held at the
ground level while both SL and SL will be held at VDD.
During evaluation stage, the complementary search data is
then broadcasts into the SLs and ~SLs. When mismatch
occurs in any CAM cell for example, when D = „1‟; ~D =
„0‟; SL =‟1‟; ~SL = „0‟ then the corresponding transistor will
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Paper Title:-A NOVEL OPTIMIZED MEMORY ARCHITECTURE FOR SYSTEM ON CHIP

be turned on charging the ML to a higher voltage level. When
the data is matched then the ML will turn high and the voltage
on the ML will remain unchanged indicating a match. Since
all the words inside the CAM cells are compared in parallel
their results can be obtained in a single clock cycle. Hence, it
is said that CAMs are faster than other search based systems
[1]. Therefore they are preferred for more high speed
applications such as file management, data compressors and
network routers [5]. The full parallel search operation may
often lead to critical challenges in designing a low power
system for high speed CAMs [1], [4]. As said earlier, the
CAM is power hungry due to its parallel ML comparison and
high speed switching activity of the SLs. Therefore numerous
efforts have been taken to reduce both the peak and dynamic
power consumption in CAM [5], [6]. For example [7] and [8]
introduced selective pipeline and hierarchical architecture to
reduce both the peak and average power consumption. In this
paper, a parity bit based CAM is introduced in order to boost
the search speed of the parallel CAM with less area and power
overhead. Also, the effective gated power technique is
introduced in order to improve the performance comparison of
CAM in terms of both area and robustness. The concept of the
conventional CAM is described in section II, and followed by
section III, which introduces the proposed CAM cell design.
Performance comparison, results and the conclusion are
presented in section IV, V and VI.
II. PRE COMPUTATION BASED
CAM DESIGN
The Fig. 2 shows the pre-computation based CAM design. The
The extra information holds the number of ones in the stored
word. For example in Fig. 2, when searching for the data
word, 0000101, the pre-computation circuit counts the number
of ones (which is two in this case). The number two is
compared on the left hand side to the stored 1‟s count. Only
the match lines ML01 and ML03 match, since only they have
a 1‟s count of two. In the stored word stage in Fig. 2, only two
comparisons actively consume power and match line ML13
results in a match.The Pre-computation CAM and all other
existing method share the same property that is, the ML sense
amplifier has to distinguish between the matched and the
mismatch ML. Hence. This makes the CAM designs face
challenges since the driving strength of turned on path is
getting weaker, while the leakage is getting stronger. This
problem is usually referred to as Ion/I0ff. Thus, in order to
boost the searching speed of the ML and also to improve the
Ion/I off of the CAM Parity bit is proposed.
III. BOOSTING SEARCH SPEED
USING PARITY CAM
The Parity bit based CAM design is shown in Fig. 3. It
consists of the original data segment and an extra one bit
segment. The Parity bit can be obtained based on odd and
even number of 1‟s. Hence, with the help of Parity bit data
can be accessed faster. For the even number of 1‟s the entry is
„0‟ and for odd number of 1‟s the entry will be „1‟. The new
CAM design has the same interface as the conventional CAM
with one extra bit.
PARITY BIT DATA BITS
0 0 0 0 0 0 0 0 ML0

0 0 1 0 0 0 0 1 ML1
pre-computation based CAM with low power, low costs and
1 0 0 0 0 0 0 1 ML2
low voltage not only saves power consumption, but also
0 0 0 0 0 1 0 1 ML3
reduces transistor count and operating voltage of CAM. 0 0 0 0 1 1 1 1 ML4
COUNTING DATA BITS

BITS ML00 ML10 SEARCH DATA

0 0 0 0 0 0 0
0

ML01 0 0 0 0 0 1 0 1
2 0 1 0 0 0 0 1 ML11
ML02
ML12
1 0 0 0 0 0 0 1
Fig. 3 Proposed Parity Cam
ML03
ML13
2 0 0 0 0 1 0 1
Hence, this Parity bit based CAM does not improve the power
4 ML04 0 0 0 1 1 1 1 ML14
performance. Theoretically, this additional Parity bit reduces
the sensing delay and boosts the searching speed. The Parity
SEARCH DATA
bit of the search and the stored word is the same in the case of
2 1's count 0 0 0 0 1 0 1
ML3, thus the overall word returns a match. For example, in
Fig. 2 Pre computation based – CAM

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Paper Title:-A NOVEL OPTIMIZED MEMORY ARCHITECTURE FOR SYSTEM ON CHIP
case of ML2 there is a mismatch between the stored data and
the search data and so the number of 1‟s between the stored
and search data must be different by 1. As a result, the
corresponding parity bits are different. If suppose there are
two mismatches in the data segment that is, in the case of Fig.
3 ML0, ML1 and ML4, the parity bits are same and therefore
overall we have two mismatches. Now with the help of sense
amplifier we have to identify the mismatched and the matched
cases. This clearly shows that the driving strength of the 2-
mismatch word is twice as strong as that of the 1-mismatch
word, hence, the proposed Parity bit based CAM greatly
improves the searching speed and the Ion/I off ratio of the
design.
IV.EFFECTIVE GATED –POWER TECHNIQUE ML
DESIGN
The proposed CAM architecture is shown in the Fig. 4. In this
design, the CAM cells are arranged into rows and columns.
The row is indicated as a word and the column is indicated as
a bit. Each cell has the same number of transistor and uses the
similar ML structure as shown in the Fig. 1. From the above
Fig. 4, it is clearly shown that the COMPARISON unit, that is,
transistors M1-M4 and the SRAM unit that is, the cross
coupled inverters are shown by two separate metal rails
VDDML and VDD. The purpose of having VDDML and
VDD can fully isolate the SRAM cell from any power
disturbances during COMPARE cycle.
Fig. 4 Proposed gated ML design
In Fig. 4, the gated power transistor PX, which is controlled
by a feedback loop, denoted as Power Control can
automatically turn off PX, when the voltage on the ML
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reaches a certain threshold value. Now at the beginning of
each cycle, the ML can be initialized by a global control signal
EN. When the signal EN is set low and the Px is turned OFF,
this makes the signal ML and C1 to be held at ground and
VDD respectively. Similarly, when the signal EN is set high,
this initiates the COMPARE phase. When there are more
mismatches in the CAM cells, the ML will be charged high.
Whatever the number of mismatches may be, the current
offered by the power transistor PX will be limited.
V. PERFORMANCE COMPARISON
In this section, the performance of the proposed design is
compared with the conventional circuit. Both the designs are
very power efficient. A similar concept is applied with a
positive feedback loop to boost the searching speed [9]. As
will be shown in Fig. 5, the proposed CAM design slightly
consumes lower power consumption when compared to the
conventional circuit design.The Simulation results of the three
CAM cells are simulated using simulated tool Modelsim SE
6.3f. In the data searching operation, the searching speed
depends on the difference between two compared data,
because more similar data takes more searching latency.
Consequently, for measuring the maximum speed of these
CAM structure, all stored data in these CAM cells are Two-bit
misses. Table I shows the simulation result of conventional
CAM cell and proposed CAM cells with different partial bits.
The simulation result shows that proposed CAM takes less
power consumption than that of the other designs.
Fig. 5 COMPARISON OF THREE DESIGNS
PARAMETER
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Paper Title:-A NOVEL OPTIMIZED MEMORY ARCHITECTURE FOR SYSTEM ON CHIP

VI. RESULT 3, pp. 712- 727, Mar. 2006.

TABLE I COMPARISON RESULT OF ALL THE [5]N. Mohan, W. Fung, D. Wright, and M. Sash dev, “A low-
THREE PARAMETERS power ternary CAM with positive-feedback match-line sense
amplifiers,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56,
no. 3, pp. 566- 573, Mar. 2009.
[6] N. Mohan and M. Sachdev, “Low power dual match-line
content addressable memory,” in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), vol. 2, 2004, pp. 633-636.
[7]K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-
lines and Hierarchical search-lines for low power content-
addressable memories,” in Proc. IEEE Custom Intergrated
Circuits Conf., 2003, pp. 383- 386.
VII. CONCLUSION
[8]K. Pagiamtzis and A. Sheikholeslami, “A low power
In this paper, the proposed CAM based on Parity bit and
content- addressable memory (CAM) using Pipelined
effective gated-power technique offers several advantages
Hierarchical search scheme,” IEEE J. Solid- State Circuits,
when compared to the conventional design. The proposed
vol. 39, no. 9, pp. 1512- 1519, Sep. 2004.
CAM reduces power and boosts the searching speed. It is
[9]Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya,
therefore more stable than the conventional design while
RiichiroTakemura, Takayuki Kawahara, “A large scale and
maintaining the low power consumption property. This feature
low power CAM architecture featuring a one hot spot block
confirms that the proposed design is more suitable for ultra-
code for IP address in a network router,” IEEE J. Solid-State
low power applications in CMOS process. The future work is
Circuits, vol. 40, no. 4, pp. 853-861, Apr.2005.
to design an efficient Content Addressable Memory (CAM)
[10]O. Tyschenko and A. Sheikholeslami, “Matchline sensing
for System-On-Chip. Designed CAM is optimized in terms of
using matchline stability in content addressable
low power, minimum clock cycles for single operation, less
memorys(CAM),” IEEE J. Solid- State Circuits, vol. 43, no. 9,
latency search function, reduces delay for sensing address and
pp. 1972- 1981, Sep. 2008.
robust against process variation.
[11]A.T.Do, S. S. Chen, Z. H. Kong, and K.S. Yeo, “A low
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