Digital Design Lab Manual Overview

FACULTY OF ENGINEERING AND ARCHITECTURE
ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT
COMPUTER ENGINEERING DEPARTMENT
DIGITAL DESIGN LABORATORY MANUAL
Prof. Dr. Murat UZAM
Kayseri - 2015
Faculty of Engineering and Architecture
Electrical and Electronics Eng. Dept. & Computer Eng. Dept.
CONTENTS PAGE
REFERENCES 0_1
GENERAL INFORMATION, LAB REGULATIONS AND WARNINGS 0_2
THE POINTS TO BE CAREFUL DURING EXPERIMENTS 0_3
INFORMATION ABOUT THE LABORATORY 0_4
INTRODUCING THE Y-0016 MAIN UNIT 0_7
GENERAL INFORMATION 0_11
BREADBOARDING TIPS 0_16
EXPERIMENT 1 – DIGITAL LOGIC GATES 1_1

EXAMINATION OF AND GATE 1_3
EXPERIMENT 1.1: OBTAINING THE TRUTH TABLE OF THE AND GATE 1_4
EXPERIMENT 1.2: OBTAINING THE TRUTH TABLE OF THE 3-INPUT AND GATE 1_6
EXAMINATION OF NAND GATE 1_8
EXPERIMENT 1.3: OBTAINING THE TRUTH TABLE OF THE NAND GATE 1_9
EXPERIMENT 1.4: USING A NAND GATE AS AN INVERTER 1_11
EXPERIMENT 1.5: OBTAINING 3-INPUT NAND GATE USING 2-INPUT NAND GATES 1_13
EXAMINATION OF INVERTER 1_15
EXPERIMENT 1.6: OBTAINING THE TRUTH TABLE OF THE INVERTER 1_17
EXPERIMENT 1.7: CONVERTING AN AND GATE INTO AN OR GATE BY USING INVERTERS 1_19
EXPERIMENT 1.8: CONVERTING AN OR GATE INTO AN AND GATE BY USING INVERTERS 1_21
EXAMINATION OF OR GATE 1_23
EXPERIMENT 1.9: OBTAINING THE TRUTH TABLE OF THE OR GATE 1_24
EXPERIMENT 1.10: OBTAINING THE TRUTH TABLE OF THE 3-INPUT OR GATE 1_25
EXAMINATION OF NOR GATE 1_27
EXPERIMENT 1.11: OBTAINING THE TRUTH TABLE OF THE NOR GATE 1_28
EXPERIMENT 1.12: USING A NOR GATE AS AN INVERTER 1_30
EXPERIMENT 1.13: OBTAINING A 3-INPUT NOR GATE USING 2-INPUT NOR GATES 1_31
EXAMINATION OF EXECULISIVE-OR GATE 1_33
EXPERIMENT 1.14 : OBTAINING THE TRUTH TABLE OF THE EXECULISIVE-OR GATE 1_34
EXAMINATION OF EXECULISIVE-NOR GATE 1_36
EXPERIMENT 1.15: OBTAINING THE TRUTH TABLE OF THE EXCLUSIVE-NOR GATE 1_37
EXPERIMENT NO: 2 – LAWS AND THEOREMS OF BOOLEAN ALGEBRA 2_1

LAWS AND THEOREMS OF BOOLEAN ALGEBRA 2_3
EXPERIMENT 2.1: EXAMINATION OF THE COMMUTATIVE LAW (OR GATE) 2_4
EXPERIMENT 2.2: EXAMINATION OF THE COMMUTATIVE LAW (AND GATE) 2_5
EXPERIMENT 2.3: EXAMINATION OF THE ASSOCIATIVE LAW (OR GATE) 1 2_6
EXPERIMENT 2.4: EXAMINATION OF THE ASSOCIATIVE LAW (OR GATE) 2 2_8
EXPERIMENT 2.5: EXAMINATION OF THE ASSOCIATIVE LAW (AND GATE) 1 2_10
EXPERIMENT 2.6: EXAMINATION OF THE ASSOCIATIVE LAW (AND GATE) 2 2_12
EXPERIMENT 2.7: EXAMINATION OF THE DISTRIBUTIVE LAW 1 2_14
DIGITAL DESIGN LABORATORY MANUAL i

Prof. Dr. Murat UZAM 2015

EXPERIMENT 2.11: EXAMINATION OF THE IDEMPOTENT LAW 2_22
EXPERIMENT 2.12: EXAMINATION OF THE AND LAW 2_23
EXPERIMENT 2.13: EXAMINATION OF THE OR LAW 2_24
EXPERIMENT 2.14: EXAMINATION OF COMPLEMENTS 2_25
EXPERIMENT 2.15: EXAMINATION OF THE INVOLUTION LAW 2_26
EXPERIMENT 2.16: EXAMINATION OF THE ABSORPTION LAW 2_28
EXPERIMENT 2.17: EXAMINATION OF THE DE MORGAN’S THEOREM 1 2_30
EXPERIMENT 2.18: EXAMINATION OF THE DE MORGAN’S THEOREM 2 2_32
EXPERIMENT NO: 3 – IMPLEMENTATION OF BOOLEAN FUNCTIONS

3_1
WITH LOGIC GATES
IMPLEMENTATION OF BOOLEAN FUNCTIONS WITH LOGIC GATES 3_3
EXPERIMENT 3.1: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-OR FORM 3_15
EXPERIMENT 3.2: IMPLEMENTATION OF A BOOLEAN FUNCTION IN OR-AND FORM 3_17
EXPERIMENT 3.3: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-OR FORM 1 3_19
EXPERIMENT 3.4: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-OR FORM 2 3_20
EXPERIMENT 3.5: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-OR FORM 3_21
EXPERIMENT 3.6: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NAND-NAND FORM 3_22
EXPERIMENT 3.7: IMPLEMENTATION OF A BOOLEAN FUNCTION IN OR-NAND FORM 3_23
EXPERIMENT 3.8: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NOR-OR FORM 3_24
EXPERIMENT 3.9: IMPLEMENTATION OF A BOOLEAN FUNCTION IN OR-AND FORM 3_25
EXPERIMENT 3.10: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NOR-NOR FORM 3_26
EXPERIMENT 3.11: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-NOR FORM 3_27
EXPERIMENT 3.12: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NAND-AND FORM 3_28
EXPERIMENT 3.13: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING NAND
3_29
EQUIVALENTS
EXPERIMENT 3.14: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING NOR
3_30
EQUIVALENTS
EXPERIMENT NO: 4 – COMBINATIONAL LOGIC CIRCUITS: ADDERS, SUBTRACTORS 4_1

BINARY ADDERS 4_3
EXPERIMENT 4.1: EXAMINATION OF HALF ADDER 4_4
FULL ADDER 4_5
EXPERIMENT 4.2: EXAMINATION OF FULL ADDER 4_6
4-BIT PARALLEL ADDER 4_7
EXPERIMENT 4.3: EXAMINATION OF 4 BIT PARALLEL ADDER 4_9
BINARY SUBTRACTORS 4_11
EXPERIMENT 4.4: EXAMINATION OF HALF SUBTRACTOR 4_12
FULL SUBTRACTOR 4_13
EXPERIMENT 4.5: EXAMINATION OF FULL SUBTRACTOR 4_14
EXPERIMENT 4.6: EXAMINATION OF 4 BIT FULL ADDER / FULL SUBTRACTOR 4_15
EXPERIMENT 4.7: EXAMINATION OF 4 BIT BCD ADDER 4_17
DIGITAL DESIGN LABORATORY MANUAL ii

EXPERIMENT NO: 5 – COMBINATIONAL LOGIC CIRCUITS: DECODERS, ENCODERS 5_1

DECODERS 5_3
EXPERIMENT 5.1: EXAMINATION OF 74LS138 3x8 DECODER 5_8
EXPERIMENT 5.2: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING A 3x8 DECODER 5_11
EXPERIMENT 5.3: EXAMINATION OF 74LS139 2x4 DECODER 5_13
EXPERIMENT 5.4: CONSTRUCTION OF A 3x8 DECODER BY USING 2x4 DECODERS 5_15
ENCODERS 5_17
EXPERIMENT 5.5: EXAMINATION OF 74LS148 8x3 PRIORITY ENCODER 5_20
EXPERIMENT NO: 6 – COMBINATIONAL LOGIC CIRCUITS:

MULTIPLEXERS, DEMULTIPLEXERS 6_1
MULTIPLEXERS 6_3
EXPERIMENT 6.1: EXAMINATION OF 8 x 1 MULTIPLEXER 6_6
EXPERIMENT 6.2: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING AN 8x1
MULTIPLEXER 1 6_8
EXPERIMENT 6.3: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING AN 8x1
MULTIPLEXER 2 6_10
DEMULTIPLEXERS 6_12
EXPERIMENT 6.4: EXAMINATION OF 74LS139 1x4 DEMULTIPLEXER WITH ACTIVE-LOW
INPUT AND ACTIVE-LOW OUTPUTS 6_15
EXPERIMENT 6.5: CONSTRUCTION OF A 1x8 DEMULTIPLEXER WITH ACTIVE-LOW INPUT
AND ACTIVE-LOW OUTPUTS BY USING A 74LS139 6_17
EXPERIMENT 6.6: EXAMINATION OF 74HC237 1 x 8 DEMULTIPLEXER 6_19
DIGITAL DATA TRANSFER BY USING A MUX-DMUX COMBINATION 6_21
EXPERIMENT 6.7: EXAMINATION OF DIGITAL DATA TRANSFER BY USING A MUX-DMUX
COMBINATION 6_22
EXPERIMENT NO: 7 – SEQUENTIAL LOGIC CIRCUITS: SR FLIP-FLOP, JK FLIP-FLOP

D FLIP-FLOP, T FLIP-FLOP 7_1
SR FLIP-FLOP (LATCH) 7_3

EXPERIMENT 7.1 EXAMINATION OF ACTIVE-HIGH INPUT SR FLIP-FLOP 7_5
EXPERIMENT 7.2: EXAMINATION OF ACTIVE-LOW INPUT SR FLIP-FLOP 7_7
EXPERIMENT 7.3: GATED SR FLIP-FLOP 7_9
JK FLIP-FLOP 7_11
EXPERIMENT 7.4: EXAMINATION OF MASTER-SLAVE JK FLIP-FLOP 7_14
D FLIP-FLOP 7_16
EXPERIMENT 7.5: EXAMINATION OF D FLIP-FLOP 7_19
EXPERIMENT 7.6: CONVERTING A JK FLIP-FLOP INTO A D FLIP-FLOP 7_21
T FLIP-FLOP 7_23
EXPERIMENT 7.7: EXAMINATION OF T FLIP-FLOP 7_25
DIGITAL DESIGN LABORATORY MANUAL iii

EXPERIMENT NO: 8 – COUNTERS 8_1

COUNTERS 8_3
ASYNCHRONOUS (RIPPLE) COUNTERS 8_4
EXPERIMENT 8.1: EXAMINATION OF 4 BIT ASYNCHRONOUS BINARY UP COUNTER 8_6
EXPERIMENT 8.2: EXAMINATION OF MOD10 ASYNCHRONOUS UP COUNTER 8_9
EXPERIMENT 8.3: EXAMINATION OF 4 BIT ASYNCHRONOUS BINARY DOWN COUNTER 8_12
74LS93 4 BIT ASYNCHRONOUS BINARY UP COUNTER 8_14
EXPERIMENT 8.4: EXAMINATION OF THE 74LS93 4 BIT ASYNCHRONOUS UP COUNTER 8_15
EXPERIMENT 8.5: EXAMINATION OF THE 74LS93 USED AS A BCD COUNTER 8_17
4024 7 BIT ASYNCHRONOUS BINARY UP COUNTER 8_20
EXPERIMENT 8.6: EXAMINATION OF 4024 7 4 BIT ASYNCHRONOUS UP COUNTER 8_21
SYNCHRONOUS COUNTERS 8_24
EXPERIMENT 8.7: EXAMINATION OF THE SYNCHRONOUS COUNTER WITH THE COUNTING
SEQUENCE OF 0, 2, 4, 6, 1, 3, 5, 7, 0, … 8_29
EXPERIMENT 8.8: EXAMINATION OF THE 4 BIT SYNCHRONOUS UP COUNTER 8_32
EXPERIMENT 8.9: EXAMINATION OF THE BCD SYNCHRONOUS UP COUNTER 8_35
EXPERIMENT NO: 9 – REGISTERS 9_1

SHIFT REGISTERS 9_3
SHIFT REGISTERS COMPOSED OF FLIP-FLOPS 9_4
EXPERIMENT 9.1: EXAMINATION OF THE 4 BIT SERIAL IN/PARALLEL OUT SHIFT RIGHT
9_6
REGISTER COMPOSED OF FLIP-FLOPS
EXPERIMENT 9.2: EXAMINATION OF THE 4 BIT PARALLEL IN/PARALLEL OUT REGISTER
COMPOSED OF FLIP-FLOPS 9_9
74LS194 UNIVERSAL SHIFT REGISTER 9_11
EXPERIMENT 9.3: EXAMINATION OF THE 74LS194 UNIVERSAL SHIFT REGISTER 9_13
74LS195 UNIVERSAL SHIFT REGISTER 9_16
EXPERIMENT 9.4: EXAMINATION OF THE 74LS195 UNIVERSAL SHIFT REGISTER 9_18
74LS165 8 BIT PARALLEL IN/SERIAL OUT SHIFT REGISTER 9_20
EXPERIMENT 9.5: EXAMINATION OF THE 74LS165 8 BIT PARALLEL IN/SERIAL OUT SHIFT
REGISTER 9_22
74LS164 8 8 BIT SERIAL IN/ PARALLEL OUT SHIFT REGISTER 9_24
EXPERIMENT 9.6: EXAMINATION OF THE 74LS164 8 BIT SERIAL IN/ PARALLEL OUT SHIFT
REGISTER 9_26
EXPERIMENT NO: 10 – MEMORY CIRCUITS: RAM, ROM 10_1

RAM (RANDOM ACCESS MEMORY) MEMORIES 10_3
EXPERIMENT 10.1: EXAMINATION OF THE 6116 SRAM IC 10_7
ROM (EEPROM) MEMORIES 10_12
EXPERIMENT 10.2: EXAMINATION OF THE 28C16 EEPROM IC 10_14
EXPERIMENT 10.3: ERASING THE 28C16 EEPROM IC 10_21
DIGITAL DESIGN LABORATORY MANUAL iv

EXPERIMENT NO: 11 – ARITHMETIC LOGIC UNIT 11_1

ARITHMETIC LOGIC UNIT - ALU 11_3
EXPERIMENT 11.1: EXAMINATION OF THE 74LS181 ALU IC 11_6
EXPERIMENT NO: 12 – DIGITAL TO ANALOG CONVERTERS – DAC

ANALOG TO DIGITAL CONVERTERS – ADC 12_1
DIGITAL TO ANALOG CONVERTERS 12_3
EXPERIMENT 12.1: EXAMINATION OF THE DIGITAL TO ANALOG CONVERTER (DAC) 12_10
ANALOG TO DIGITAL CONVERTERS 12_12
EXPERIMENT 12.2: EXAMINATION OF THE ANALOG TO DIGITAL CONVERTER (ADC) 12_17
DIGITAL DATA TRANSFER BY USING ADC & DAC CONVERTERS 12_20
EXAMINATION OF THE DIGITAL DATA TRANSMISSION USING ADC AND DAC CONVERTERS 12_21
DIGITAL DESIGN LABORATORY MANUAL v

REFERENCES
1. “Dijital Elektronik Deney Kitabı”, Yıldırım Elektronik, 2010.
2. “Lojik Devre Laboratuvarı Deney Kılavuzu”, Erciyes Üniversitesi, Mühendislik
Fakültesi, Doç. Dr. Kenan DANIŞMAN, Yük. Müh. Ahmet ÖZEK, Kayseri, 1994.
3. “Digital Design Course Notes”, Prof. Dr. Murat UZAM,
http://www.meliksah.edu.tr/muzam/digital_design.htm
4. “PICBIT_PLC ile LOJİK TASARIM”, Murat UZAM, ISBN: 9755115080, 613 sayfa,
Birsen Yayınevi, Eylül 2008.
5. Integrated Circuits Catalogues
DIGITAL DESIGN LABORATORY MANUAL 0_1

GENERAL INFORMATION, LAB REGULATIONS AND WARNINGS
Experiments must be done in accordance with the following rules to have an efficient laboratory work.
 Students have to attend at least 80% of experiments.
 The materials to be used in experiments are reported in the lab sheets. Go through these
materials before coming to laboratory.
 Do the required Preliminary Work before coming to laboratory. Students who do not do the
preliminary work will not be allowed to do the experiment.
 If you are late more than 15 minutes, you will not be allowed to participate.
 The experiments that a student did not attend will be graded zero.
 It is forbidden to quit during the experiment but the assistant may allow a student to quit in case
of necessity.
 The materials which will be used in experiment (hand tools, cables, experiment tools,
measurement tools) must be received from the assistant. At the end of the experiment, the
materials must be thoroughly given back to the assistant. The lost or damaged materials have to
be replaced by the responsible student.
 Do your experiment step by step as indicated in the lab manual or as requested by your
assistant. After completing each step, call your assistant and make him verify your work.
 “Speaking in a Low Voice” is an obligation in order not to disturb the other students and to
provide an efficient working area.
 During the experiment, the exchange of information or material is certainly prohibited.
 Keep close the electronic devices which may affect the experiment measurements or disturb
other students like mobile phone, radio, etc. in laboratory.
 Do not keep your belongings like bag, coat etc. on the experiment desk.
 Your friends cannot enter the lab during the experiments.

 Care to the general rules of morality and cleanliness must be taken during the experiment. At
the end of the experiment, the experiment desk must be left clean and without any connection
of electricity.
THE POINTS TO BE CAREFUL DURING EXPERIMENTS
 Voltage supply must be turned off during the setup of the experiment.
 The correctness of connections should be checked before giving voltage to the circuit (start-up
voltage).
 Are integrated circuit’s supply (Vcc) and ground (GND) lines correctly connected?
 Is there any short-circuit between supply voltage (Vcc) and ground (GND) lines?
 Is the connection to the all the necessary inputs of integrated circuit made?
 Is the input signal applied to the output by mistake?
 Are the connection performed correctly to achieve what is requested in the experiment.
 The supply voltage must be given with the approval of the assistant in charge after being
sure that all connections are correct. If the circuit does not work as expected, circuit
should be checked immediately with turning off the supply voltage. The previous points
should be mentioned in the verification process.
 The elements which are not working properly should be disconnected and tested one by one.
 The power supply must be switched off when you are making changes on circuit (element
insertion / removal, changing connection)
 If the mistake does not found despite all the trials, assistants in charged should be called to
help.

INFORMATION ABOUT THE LABORATORY
 The grading of the Digital Design (3+2) course is as follows:
1st Midterm Exam 10%,

2nd Midterm Exam 10%,
Laboratory Exam 10%,
Laboratory Work 30%, consisting of the following:
Quiz 10%,
Laboratory Performance 10%,
Laboratory Report 10%.
Final Exam (Make-up Exam) %40.
Quiz consists of 2 or 3 short questions related to the experiment to be done, and taken
before each experiment.
 A student may not participate in just one experiment; however, his/her average of grade is
calculated by using the number of all experiments.
 If a student does not participate in an experiment with an excuse, then he/she must apply the
laboratory coordinator together with the necessary documents such as medical reports and so
on as soon as possible. (To avoid any exam or experiment confliction).
 Each student prepares a lab report for each experiment. Cover of the report must thoroughly
involve the student's name, surname, student number, the date of the experiment, the name of
the experiment and the name and surname of the assistant in charge at that experiment.
 Lab reports which are not delivered on the day and time are invalid.
 Lab reports must be delivered to the assistants in charge in the week after the experiment is
done. (The last due date for the report is before the next experiment).
 Each student must deliver an empty folder which involves the student's name, number and
sheet protectors with his/her first experiment's report in a sheet protector to the assistants in
charge. Each report is accumulated and scored in this folder.

Experiment Works
Evaluation of the student's Laboratory Work is done with taking into account of the preliminary work,
the performance at the experiment setup and the evaluation of the results of measurements.
Preliminary Work
Each student has to take an examination before experiment by the assistants in charge. This
examination is generally a short exam (quiz). At this stage, students are expected to:
 Theoretical knowledge about the experiment on that day should be obtained from the lab
manual and if necessary from other sources (such as lecture notes and books related to the
course). Lab manual can be obtained from the course website. The theoretical knowledge
which is needed to do the experiment is not limited with the lab manual. Students have to
provide enough theoretical knowledge using all kind of sources before coming to experiment.
 Student should come to the laboratory with the knowledge of what will be done in that
experiment, what is the purpose of that experiment, how to do that experiment (for example,
student should know which of the measurement devices will be used in that experiment). The
item's catalog information which will be tested must be acquired.
 Student may perform the experiment on a digital simulation program. So before coming to the
experiment with the results obtained from the digital simulation program he/she will have
preliminary results.
 Laboratory Report contains some questions. It is also very important answer these questions
before coming to laboratory because the quiz may include some of these questions.
Construction of Experiment
The experiment is done individually by each student. For the construction of experiment, the
followings must be taken into account:
 Approach to the problem
 The correctness of the results
 Success of questioning and interpreting the results (Awareness of unrealistic results and
making brain storm about the reasons)
 The use of tools (the ability to use correct and appropriate)
 The ability to cope with the problems
 Efficient use of time
 Attention to the experiment
 The students who finished the experiment will be graded based on the above substances.

The Evaluation of Experiment Results
As the time measurements about experiment are completed, the results are evaluated. The important
points of this evaluation are as follows:
 The interpretation of the experiment results (like what is the meanings of the obtained data and
what is the conclusion)
 If necessary, comparison of the theoretical and experimental results.
Reports
 A Laboratory Report is a technical article that the experiment results are presented and
interpreted; the given information must be easily understood and explained in the shortest way,
the prior knowledge of the lab manual and the figures should not be repeated in the report.
 Be careful about to keep the report brief, and do not forget that the values obtained during the
experiment should be included as a table in the report.
 Format, technical content and results are taking into account when reports are evaluated.
Report must certainly contain the followings:

 A brief introduction part that explains the purpose of the experiment
 The presentation of all measurements in a well-organized charts
 The theoretical calculations required for comparison (formulas are not rebuilded, the results
will be given in table)
 Related comments for each measurement
 A brief conclusion part which consists of the interpretation of the results obtained from
experiment and a common evaluation of experiment.

INTRODUCING THE Y-0016 MAIN UNIT
1 2 3 4 5
6 7 8 9
12
13
14
10
15 11
16
17
18
19
20 21
1. Power ON/OFF
2. 0-36V, 0-1A Current protected, adjustable power supply
3. (-5V)-0(+5V) Electronically protected, symmetric DC power supply
4. (-12V)-0(+12V) Electronically protected symmetric DC power supply
5. 12V-0-12V AC supply
6. Relay (DC 12V)
7. 3xLamp (12V)
8. Buzzer
9. 8 Ohm – 2 W Speaker
10. Hexadecimal Decoder
11. 8 bit Logic Indicator
12. Potentiometers (1k-10k-100k)
13. Switch (on-on)
14. Switch (on-0-on)
15. 1 Hz-100 KHz Function Generator (SINE, TRIANGLE, TTL )
16. 12 bit TTL Binary Switch
17. 1Hz–10Hz-100Hz-1KHz-10KHz- 100KHz Oscillator
18. TTL Pulse
19. One Shot TTL Pulse
20. Set, Reset, Preset Pulse
21. Protoboard (Breadboard)
USING THE CIRCUITRY ON THE FUNDAMENTAL ELECTRICAL – ELECTRONICS

TRAINING SET
1-POWER (ON-OFF)
It is used to give energy to the training set and the experiment circuitry.
2-ADJUSTABLE DC POWER SUPPLY

When the power switch position is “ON”, energy is applied to 0-36V, 0-1A adjustable power supply.
When the energy is given to the power supply, current and voltage potentiometer displays will
illuminate. You can adjust the current using CURRENT potentiometer, and the voltage using
VOLTAGE potentiometer. Make sure that the CURRENT potentiometer is rotated to the leftmost
position. So that there will be no voltage at the circuit and CC LED will be illuminating. At normal
operating condition, CV LED will be illuminating. In order to obtain a desired current, first make the
output nodes short circuited by rotating the CURRENT potentiometer to the leftmost position. Then
rotate the potentiometer to the right up to the desired current value. The voltage is adjusted roughly by
using the COARSE potentiometer first, then the accurate adjustment is done by using the FINE
potentiometer.
3-(-5V) 0 (+5V) SYMMETRIC DC SUPPLY

When the output is shorted, the supply protects itself and the related LED in the TTL power on-off
block becomes off. In order to operate the system again turn off the power on-off switch, wait for 5
seconds and turn on the switch.
NOTE: The ground pin is independent. Be careful about this when connecting the circuit.
4- (-12V) 0 (+12V) SYMMETRIC DC SUPPLY

When the output is shorted, the supply protects itself and the LED in the output socket becomes off. In
order to operate the system again turn off the power on-off switch, wait for 5 seconds and turn on the
switch.
5- 12V-0-12V SYMMETRIC AC SUPPLY

When the output is shorted, the supply protects itself and the LED in the output socket becomes off. In
order to operate the system again turn off the power on-off switch, wait for 5 seconds and turn on the
switch.
6- RELAY
A DC 12V double group contactor relay.
7- LAMPS
3 incandescent lamps (12 V).
8- BUZZER
The element that produces sound with constant frequency when voltage is applied on the input
terminals.
9- SPEAKER
It includes an 8 Ohm - 2 Watt speaker in order to be used in analog experiments. It is connected by
using the input terminals.

10- HEXADECIMAL DECODER

It is the circuit that converts BINARY coded data to HEXADECIMAL form.
It converts the BINARY data in the form of 0’s and 1’s at the input into HEXADECIMAL codes
between 0 and F.
11- 8 BIT LOGIC INDICATOR

It is used for the data in the form of 0-1 to be indicated by LEDs. If the data is “0”, LED does not
illuminate and if the data is “1”, LED illuminates.
12- POTENTIOMETERS
3 Potentiometers (1K, 10K and 100K).
13- SWITCH (ON-ON)

A (on-on) switch.
14- SWITCH (ON-0-ON)

A (on-0-on) switch.
15- FUNCTION GENERATOR

A function generator that can produce sinusoidal, triangular and square waves with frequencies from
1Hz to 100 KHz and with adjustable amplitudes.
16- 12 BIT TTL BINARY SWITCHES

It is used to obtain logic levels “0” and “1”. 12 switches are used for 12 bit data. LEDs are used in
order to show the switch position and output data.
17- CONSTANT FREQUENCY SELECTIVE TTL OSCILLATOR
It is the oscillator circuit that produces 1Hz-10 KHz-100Hz-1 kHz-10 KHz-100 KHz signals in the
TTL level. Desired frequency can be obtained from the output terminals.
18- TTL PULSE CIRCUIT

It is used to obtain logic pulse. When the button is pressed, both negative and positive pulses are
generated. The desired pulse can be taken from the related output terminal.
19- ONE SHOT TTL PULSE CIRCUIT

It is the circuit that can produce positive and negative one shot pulses with adjustable pulse lenght.
Whenever the button is pressed, a pulse is generated at the adjusted frequency.
20- TTL SET-RESET-PRESET PULSE CIRCUIT

It is a general purpose PULSE generator of which output is determined according to the position of its
input switch.
21- PROTOBOARD (BREADBOARD)

It is the component on which the circuits can be set up and external experiments can be done. The
information about usage is given in the below figure.

CONNECTION OF FUNDAMENTAL ELECTRONICS TRAINING SET TO THE

NETWORK
CONNECT THE FEMALE PART OF POWER PLUG GIVEN WITH THE SET TO THE
SOCKET AT THE BACK OF THE SET, AND MALE PART OF IT TO THE NETWORK
SOCKET.
THE SET BECOMES READY TO BE USED BY TURNING ON THE ON/OFF SWITCH ON

THE SET.
2 FUSE BOXES FOR 1A FUSES ARE PLACED AT THE BACK OF THE SET IN ORDER TO
PREVENT THE SET AND ITS SURROUNDINGS IN THE CASE OF BREAKDOWN.
WARNING!!!
THE EXPERIMENT RESULTS THAT YOU OBTAIN MAY BE SLIGHTLY DIFFERENT

FROM THE RESULTS IN THIS MANUEL DUE TO THE ENVIRONMENT, QUALITY OF
THE MEASUREMENT DEVICES AND CHARACTERISTIC PROPERTIES OF THE
MATERIALS USED IN THE EXPERIMENT. UNLESS THERE IS A HUGE DIFFERENCE
THE RESULTS ARE ACCEPTABLE.

GENERAL INFORMATION
INTEGRATED CIRCUITS
Integrated circuits (ICs) are formed by integration of many systems. Integrated circuits are
semiconductor chips composed of circuit elements like transistors, resistors, capacitors and diodes.
These elements are connected each other to form a circuit inside the chip. This circuit is able to
connect the outside world from suitable nodes by the help of pins. Then the chip is covered by metal
and plastic for protection. So the integrated circuit is obtained. The cost of the integrated circuit is as
small as its size. Integrated circuits play an important role in the development of technology.
Integrated circuits’ being smaller, cheaper and faster make them widely used in the industry. Integrated
circuits are shortly represented by IC. ICs generally have standard packages and have pin numbers
from 8 up to 400. All ICs have numerical codes on them. By the use of these numbers, one can
understand the type of the IC and the function of the circuit in it. Integrated circuits can be classified
into two groups: Digital Integrated Circuits and Analog Integrated Circuits.
Analog Integrated Circuits: They are generally used for voltage amplification and rectification. (E.g.
Op-Amps)
Digital Integrated Circuits: They are composed of logic gates.
Nowadays, digital ICs are used in digital circuits. Since they have small size and low cost, they are
widely used in industry. Some of the circuits in which ICs are used are power amplifiers, counters,
arithmetic units, voltage regulators, radio and TV circuits, operational amplifiers, etc. Integrated
circuits are classified according to their structures. They are divided into three groups according to
their packaging: metal, plastic and ceramic. But ceramic ICs are not used since they are brittle and
expensive. ICs are generally not repaired when they break down. They are exchanged with a newer
one. Standard sockets are produced to do these operations more practically. In some circuits, ICs are
placed on these sockets so that fitting and taking apart the IC become more practical.
Digital integrated circuits are classified according to the number of gates they include.
These are:
SSI (Small Scale Integration): They contain gates numbering between 1 and 20, i.e., 7400 IC
contains 4 NAND gates in it.
MSI (Middle Scale Integration): They contain gates numbering between 20 and 100, i.e., flip-flops,
counters.
LSI (Large Scale Integration): They contain gates numbering between 100 and 10000, i.e.,
microprocessors (4 or 8 bit)
VLSI (Very Large Scale Integration): They contain gates numbering more than 10000, i.e.,
microprocessors (16 or 32 bit), memory elements, computer circuits.
Today it is possible to produce chips containing more than 200000 logic gates. Each gate contains
more than two transistors. So we can say that 100 thousands of transistors can be formed in an IC. For
example a Pentium microprocessor contains 5,5 million transistors. Various types of ICs are shown in
Fig. 0.1.

Fig. 0.1. Photos of various types of ICs.
Integrated Circuit Parameters
Digital integrated circuits have some important specifications in order to compare them with each
other and to choose the most suitable IC for the specific application. These specifications are called IC
parameters. The most important parameters are:
1. Power supply voltage: It determines the supply voltage of the IC. Supply voltage tolerance
may also be indicated in some ICs.
2. Propagation delay: It indicates how fast the output changes when the input of the IC changes.
Output of a logic circuit does not change simultaneously when the input changes. It is
measured in nanoseconds. Some amount of delay occurs. This delay is called propagation
delay. It is 5 nsec for TTL. ICs with minimum propagation delay are preferred in systems like
PLC and computer.
3. Power dissipation: It indicates how much power is dissipated in the circuit. It is measured in
milliWatts. It increases with decreasing propagation delay. (ICs with low power dissipation are
preferred in battery-operated circuits.)
4. Fan out: It determines maximum capacity of the load that will be connected to the output of
the circuit. Maximum load capacity determines the number of gates that will be connected to
the output.
5. Noise immunity: It determines the noise tolerance capability of the output data. Noise may
cause logic 0 to appear as logic 1 at the output or vice versa. Output data is free of error how
less the noise amount is. Noise immunity is determined by gate’s noise tolerance capability.
6. Clock frequency: It determines the maximum frequency of the triggering pulse that will be
applied to the input of the circuit.
NAND and NOR gates are the basic circuits for all ICs. Logic ICs are named by the electronics
material that is used when they are fabricated. Some types of integrated circuits are:
1. RTL – Resistor - Transistor Logic

2. DTL – Diode Transistor Logic
3. HTL – High Threshold Logic
4. TTL – Transistor - Transistor Logic
5. ECL – Emitter Coupled Logic
6. DCTL – Direct Coupled Transistor Logic
7. MOS – Metal- Oxide Semiconductor Logic
8. CMOS – Complementary Metal- Oxide Semiconductor Logic
Logic Family Types of Integrated Circuits:
Resistor - Transistor Logic (RTL): They are the first fabricated commercial integrated circuits. They
were widely used at the beginning since they were cheap. Their operating voltage is between 3V and
3,6V, propagation delay is about 12 nsec, power dissipation is 10 mWatts per gate and they are coded
by numbers with 700 and 900.

Diode Transistor Logic (DTL): Their usage is limited in an IC because of their disadvantages. There
is some amount of voltage drop in diodes. This causes a drop in the voltage level. Discharging is also a
problem. In order to deal with these problems, discharging amplifiers are used. So that drops in the
logic levels are also tolerated. They are less used. These ICs are better than RTL in speed, power
dissipation and stability. Their operating voltage is about 5 V, noise immunity is low and they are
coded by numbers with 830 and 930.
Transistor - Transistor Logic (TTL): TTL is the improved version of DTL logic. A multi-emitter
transistor is used instead of the diode at the input of the DTL logic. So TTL ICs operate very fast and
for that reason they are widely used. Today they are one of the most widely used IC groups. They are
also used in computers.
They are divided into 5 groups:

1. Standard TTL: It is the first type of TTL group. Its power dissipation is 10 mW per gate,
propagation delay is 10 nsec and clock frequency is 35 MHz.
2. Low Power TTL: Its power dissipation is 1 mW per gate, propagation delay is 33 nsec.
and clock frequency is 3 MHz.
3. High Speed TTL: Its power dissipation is 22 mW per gate, propagation delay is 6 nsec.
and clock frequency is 50 MHz.
4. Schottky TTL(STTL): It is the fastest element of the TTL group. Its power dissipation is
19 mW per gate, propagation delay is 3 nsec. and clock frequency is 125 MHz.
5. Low Power Schottky TTL (LSTTL): It is the last improved element of the TTL group.
Its power dissipation is 2 mW per gate, propagation delay is 20 nsec. and clock frequency
is 25 MHz.
Fig. 0.2. TTL implementation of a two-input NAND gate.
Fig. 0.2 show the TTL implementation of a two-input NAND gate. TTL group is coded by numbers
with 7400 and 5400. ICs with number 7400 are more widely used. 5400 series is produced for military
purposes. 7400 series covers the ICs operating at temperatures between 0°C and 70°C. 5400 series
operates at temperatures between -55°C and +125°C. The letters after numbers 74 and 54 determine to
which subgroup the TTL IC belongs. For example, 74L00 is used for low power TTL and 7400 is used
for standard TTL.
Emitter Coupled Logic (ECL):
It is not used as widely as TTL family. It is the fastest group of integrated circuits. It has been first
produced by Motorola in 1962. It is more expensive than TTL and it is more difficult to cool. Also it is
difficult to make interconnections and it has lower noise immunity. In many applications, ECL gates
operate faster. On the other hand, they are used in supercomputers and very high speed application
specific computers. Fig. 0.3 shows the ECL implementation of a two-input OR (NOR) gate.
Fig. 0.3. ECL implementation of a two-input OR (NOR) gate.
There are 4 main ECL subgroups.

1- MECL 1 Group: Their power dissipation is 35 mW per gate, propagation delay is 8 nsec. and clock
frequency is 30 MHz. They are coded by numbers with 300 and 350.
2- MECL 2 Group: It is the improved version of MCLE 1 Group. Their power dissipation is 22 mW
per gate, propagation delay is 4 nsec. and clock frequency is 75 MHz. They are coded by numbers with
1000 and 1200.
3- MECL 10K Group: It is one of the most widely used ECL subgroups. Their power dissipation is
25 mW per gate, propagation delay is 2 nsec. and clock frequency is 125 MHz. They are coded by
numbers with 10000.
4- MECL 3 Group: It is the fastest one of the ECL subgroups. Their power dissipation is 60 mW per
gate, propagation delay is 1 nsec. and clock frequency is 400 MHz. They are coded by numbers with
1600.
Logic level 1 is -0.75V and logic level 0 is -1.55 V for ECL gates.
Metal-Oxide Semiconductor Logic (MOS): MOS type ICs have started to be fabricated with the
improvements in field effect transistors (FET). Transistors used in these ICs are called MOSFET.
Since they are slow, endurable and they have low fan out, they are not preferred in some applications.
But in many applications, they are used due to their small chip size, easy fabrication and low power
dissipation. Their operating voltage is between 3V and 15V. You must be careful with the static
charges and when you are working with these ICs;
· You should not touch the pins,

. You should use grounded or DC soldering iron,
· Unused pins should not be left unconnected. They should be connected either to +V or to chassis
whichever is appropriate.
Complementary Metal -Oxide Semiconductor Logic (CMOS):

Some MOSFET circuits are designed especially for space and naval applications. And these circuits
are called complementary MOS circuits. They are constructed with the help of FET and MOSFET
logic. They are improved version of TTLs. Their power dissipation is low and noise immunity is high.
They are slow compared to high speed logic circuits. Many transistors can be implemented in a single
chip and power supply voltage range is high. Their fabrication cost is also low. Latest versions of
CMOS circuits are faster and they are widely used in electronic watches, calculators and
microprocessors. CMOS circuits belong to 40XX series. Supply voltage is between 3V and 18V. Their
propagation delay is high. They operate at 5MHz with maximum supply voltage. So they are not
suitable for high frequency applications. CMOS implementation of a two-input NOR gate is depicted
in Fig. 0.4.

Fig. 0.4. CMOS implementation of a two-input NOR gate.
Integrated Injection Logic (IIL):

It is necessary to follow a different way in the design of IIL logic gates because they have one input
and multiple outputs. But their advantages compensate for the design difficulties. So IIL memory
elements and microprocessors take place in the market. Recent developments in IIL technology have
been insignificant compared to development in CMOS technology. Their operation features are similar
to RTL logic except for some differences. Absence of resistance in their structure makes them cheaper
and capable of being densely packaged.
Fan-out capacity:
This value is 10 for TTL circuits. That means one TTL output can feed at most 10 TTL inputs. The
value is 50 for CMOS of which output impedance is very high.
Unused pins:
There must be no floating pins in TTL and CMOS integrated circuits. Unused pins in the application
should be connected to (+) or (-) pole of the supply whichever is appropriate. Otherwise unexpected
results may appear at the output. Inner structures of TTL and CMOS ICs which have the same
functionality are shown in the following Fig. 0.5. Also their specifications are compared to each other
in Table 0.1.
Fig. 0.5
Parameter TTL CMOS

Supply voltage 5V DC 3 V -18 V DC
Necessary current Miliampere Microampere
Input impedance Low Very high
Switching speed Fast Low
Fan out 10 50
Power dissipation 20mW 2mW
Triggering pulse 50MHz 25MHz
Supply tolerance %20 %50
Table 0.1.

BREADBOARDING TIPS
Remember these points when you wire a circuit that uses a DIP (dual inline package):
 Straightening a Bent Pin
o Before you insert a DIP into the breadboard, look at its pins to make sure they're all
straight. If a pin is bent, use a needle-nose pliers or a mechanical pencil to straighten it.
To use a mechanical pencil:
1. Retract the pencil's lead so that the hole in the pencil's tip is open.
2. Carefully slip the bent pin into the pencil's tip, as shown in the photograph
below.
3. Gently straighten the pin.
 Inserting a DIP
o When you insert a DIP in the breadboard, make sure that the pins on one side of the
DIP are not connected to the pins on the other side of the DIP. This means that the DIP
must straddle one of the long gaps that divide the breadboard into separate sections.
In the photo below, the DIP on the left is inserted incorrectly, because the pins on the
lower side of the chip are connected to the pins on the upper side. The DIP on the right is
inserted correctly, because the DIP straddles the breadboard gap.

o If you look closely at the breadboard, you'll notice that some of the gaps between
sections are wider than others. (See photo below.) You'll have better results if you place
your DIPs so they straddle the wide gaps and avoid the narrow gaps. DIPs placed over
the narrow gaps have a tendency to pop back out of the breadboard because the board
surface is uneven there.
o When building a circuit that uses two or more DIPs, don't place the DIPs right next to
each other. Rather, leave some space between them so that you can run wires between
them. In the photo below, the two DIPs on the left are spaced too close together. The
two DIPs on the right are properly spaced.
o Orient all of your DIPs in the same direction. If you're laying out the DIPs horizontally,
then make sure they're positioned so that each DIP's pin #1 is in the lower-left corner,
not in the upper-right corner.
o On a new DIP that has never been used, the pins are usually spread too far outward to
be inserted into the breadboard. Gently press the pins on both sides of the chip inward
so that their spacing matches the spacing of the holes on the breadboard.

 Using Power and Ground Busses

o For power and ground connections to your DIP, use the busses on the breadboard. On
the trainers in our EET labs, these busses are located at the top, the center, and the
bottom of the breadboard. The photo below shows the busses highlighted in yellow.
o The close-up photo below shows more detail. Notice the red and black lines, which
indicate how far the busses extend. In particular, notice that:
 Each red line extends across twelve holes. These twelve holes are all connected
together. So if you connect a wire from any one of these holes to the trainer's
+5 V power supply, then the other eleven holes will all be at +5 V.
 Each black line extends across twenty-four holes. These twenty-four holes are
all connected together. So if you connect a wire from any one of these holes to
the trainer's ground (GND) terminal, then the other twenty-three holes will all be
at ground.

o You can extend the busses by using short jumper wires to connect two or more busses
together. The photo below shows red jumper wires connecting the red busses together,
and black jumper wires connecting the black busses together. This way, you'll have
busses that extend across the entire width of the breadboard, providing plenty of
connection points for any DIPs that need to be connected to power or ground.
o Once you've placed your DIPs on the breadboard, run power and ground to each DIP by
following these steps:
0. Run a red wire from the trainer's +5 V terminal to a red bus.
1. Run a red wire from the red bus to each DIP's power pin.
2. Run a black wire from the trainer's GND terminal to a black bus.
3. Run a black wire from the black bus to each chip's ground pin.
o The photo below shows two properly placed DIPs whose power and ground pins are
connected to the busses.

 Wire Colors
o Use red wires for connections to power (+5 V).
o Use black wires for connections to ground.
o Use other colors (not red or black) for all other connections.
o In some later electronics courses, you'll build circuits that use +12 V and −12 V power
supplies as well as +5 V. For these circuits, use
 Red for +5 V
 Black for ground
 Yellow for +12 V
 Green for −12 V
 Wire Lengths
o As you wire your circuit, keep the wires short and keep them down low against the
breadboard, not looping up in the air. If you can't find a pre-cut wire of the right length,
then cut one to fit.
o When you cut a wire, cut it at a 45º angle instead of 90º. This will make it easier to
insert the wire into a breadboard hole.
 Straightening and Trimming Wire Ends
o Straighten the stripped end of each wire before you insert it into the breadboard. Bent
ones have a tendency to break off. If the stripped end is so badly bent that you can't
straighten it, then cut it off and strip a new end.
o As mentioned above, your wires will be easier to insert if you cut them at a 45º angle
instead of 90º.
o Trim each wire's stripped end short enough so that when you insert it into a breadboard
hole, no exposed metal is visible above the breadboard.
o The photo below shows a wire that is not properly trimmed. Notice that bare metal is
exposed above the surface of the breadboard.
 Providing Access to the DIP

o As you wire your circuit, be sure to leave yourself easy access to the DIP's pins so that
you can touch them with a probe and so that you can replace the DIP without
disconnecting any wires. In particular:
 Never pass a wire over a DIP. Instead, route the wires around the DIP.
 When you run wires to a DIP, use the breadboard holes farther away from the
DIP before you use the holes that are closer.
o The photos below show two poorly wired circuits. Note that the wires are much longer
than they need to be and that they pass over the DIPs, making it difficult to access the
DIP's pins. Imagine how difficult it would be to replace one of the DIPs.

o The photo below shows a correctly wired circuit. Note that the wires are short, low, and
neatly ordered. Imagine how easily you could replace one of the DIPs without
disconnecting any wires.
 Removing a DIP
o Do not use your fingers to remove a DIP from the breadboard. It's too easy for your
fingers to slip, causing the DIP to twist. This results in bent pins.
o Instead, use a chip puller to gently pull the chip up from the board.

EXPERIMENT 1
DIGITAL LOGIC GATES
EQUIPMENT:
1- Y-0016 main unit.
2- Multimeter.
3- Integrated Circuits (ICs) and other components:
IC number Definition Quantity

74LS00 Quadruple 2-input NAND gates 1
74LS02 Quadruple 2-input NOR gates 1
74LS04 Hex inverters (six independent gates) 1
74LS08 Quadruple 2-input AND gates 1
74LS32 Quadruple 2-input OR gates 1
74LS86 Quadruple 2-input EX-OR gates 1
74HC266 Quadruple 2-input EX-NOR gates 1
4011 Quadruple 2-input NAND gates 1
4030 Quadruple 2-input EX-OR gates 1
4063 Hex inverters (six independent gates) 1
4077 Quadruple 2-input EX-NOR gates 1
4081 Quadruple 2-input AND gates 1
10 KΩ resistor 1
4. Connection wires.
DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_1

PRELIMINARY WORK:
1. Read all explanations about this experiment given in the lab manual.
2. Have a look at your course notes and related books about the topics covered in this experiment.
3. By means of a digital simulation software test and verify the operation of the logic gates shown in the
following table.
1 Fig. 1.4.(a) Examination of a 2-input AND gate (2_in_and_gate).
2 Fig. 1.5.(a) Examination of a 3-input AND gate (3_in_and_gate).
3 Fig. 1.8.(a) Examination of a 2-input NAND gate (2_in_nand_gate).
4 Fig. 1.9.(a) The use of a NAND gate as an INVERTER (nand_inverter).
5 Fig. 1.10.(a) Obtaining a 3-input NAND gate using 2-input NAND gates (3_in_nand_gate).
6 Fig. 1.15.(a) Examination of INVERTER (inverter).
7 Fig. 1.16.(a) Converting an AND gate into an OR gate by using inverters (and_to_or_gate).
8 Fig. 1.17.(a) Converting an OR gate into an AND gate by using inverters (or_to_and_gate).
9 Fig. 1.21.(a) Examination of a 2-input OR gate (2_in_or_gate).
10 Fig. 1.22.(a) Examination of a 3-input OR gate (3_in_or_gate).
11 Fig. 1.26.(a) Examination of a 2-input NOR gate (2_in_nor_gate).
12 Fig. 1.27.(a) The use of a NOR gate as an INVERTER (nor_inverter).
13 Fig. 1.28.(a) Obtaining a 3-input NOR gate using 2-input NOR gates (3_in_nor_gate).
14 Fig. 1.31.(a) Examination of a 2-input EX-OR gate (2_in_xor_gate).
15 Fig. 1.34.(a) Examination of a 2-input EX-NOR gate (2_in_xnor_gate).
4. In the above table there are 15 figures numbered as Fig. 1.XX.(a) referring to the schematic diagrams
of experiments to be done. As preliminary work you are obliged to draw by hand using pencils an
application circuit provided in Fig. 1.XX.(b) for each schematic diagram given in Fig. 1.XX.(a). It is
recommended that you use red colour for Vcc, black colour for GND and other colours for other
connections.
5. There are some questions to be answered in the report form for this experiment. Have a look at these
questions and try to answer them before coming for the experiment. The quiz you will take before the
experiment may contain some of these questions.
NOTE: You are obliged to have a copy of the page number 1_1 from “the experiment report form
1” when you start doing this experiment.

EXAMINATION OF AND GATE
OBJECTIVES:
1- Getting to know digital logic AND gate and verifying its logic operation,
2- Obtaining 3-input and 4-input AND gates by using 2-input AND gates.
PRELIMINARY INFORMATION:
1- In a logic operation, HIGH (H) level is represented by number “1” and LOW (L) level is represented
by number “0”.
2- For TTL ICs, H (1) represents voltage levels between 2,4V and 5V. Similarly, L (0) represents
voltage levels between 0 V and 0,4 V.
3- For CMOS ICs, voltage equivalent of H (1) is approximately the supply voltage and L (0) represents
voltage levels between 0V and 0,5 V.
4- AND gate is the multiplication gate. It has at least two inputs. At least one “0” input makes the output
“0”. The output is “1” only when all the inputs are “1” (Table 1.1).
5- The output of a 2-input AND gate is Y= A . B (Fig. 1.1).
6- As can be seen from Fig. 1.2, both TTL IC 7408 and CMOS IC 4081 contain 4 AND gates.
7- The output of a 3-input AND gate (Fig. 1.3) is Y= A.B.C (Table 1.2).
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Fig. 1.1. 2-input AND gate. Table 1.1. The truth table of 2-input AND gate.
TTL AND 7408 CMOS AND 4081

Fig. 1.2
A B C Y=A.B.C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Fig. 1.3. 3-input AND gate. Table 1.2. The truth table of 3-input AND gate.

EXPERIMENT NO: 1.1

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE AND GATE
Equipment:
1. Y-0016 main unit.
2. Multimeter.
3. Integrated circuits (ICs):
74LS08 Quadruple 2-input AND gates 1 IC
4081 Quadruple 2-input AND gates 1 IC
Fig. 1.4.(a) Examination of a 2-input AND gate (2_in_and_gate).
Note: Do not forget to connect the Vcc pin to +5 V and the GND pin to ground (GND) connection.
Fig. 1.4.(b) Examination of a 2-input AND gate – application circuit.

Procedure:
1- Construct the circuit [as given in Fig. 1.4.(a) and] as drawn by you in Fig. 1.4.(b) and apply the
power.
2- Apply logic 0 (L) to both inputs.
3- Using the LEDs investigate whether the output of 2-input AND gate is 1 (H) or 0 (L) and take note of
the output in Table 1.3.
4- Measure the same output with voltmeter and find the voltage value and take note of the output
voltage in Table 1.3.
5- Repeat steps 3 and 4 for all the input values given in Table 1.3 and take note of the outputs in Table
1.3.
Voltage value measured by voltmeter

A B Y=A.B
For 74LS08 For 4081
0 0
0 1
1 0
1 1
Table 1.3
NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING CMOS IC

(4081).

EXPERIMENT NO: 1.2

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE 3-INPUT AND GATE
Equipment:
2. Multimeter.
Fig. 1.5.(a) Examination of a 3-input AND gate (3_in_and_gate).
Fig. 1.5.(b) Examination of a 3-input AND gate – application circuit.

Procedure:
power.
2- Apply logic 0 (L) to all three inputs.
3- Using the LEDs investigate whether the output of 3-input AND gate is 1 (H) or 0 (L) and take note of
5- Repeat steps 3 and 4 for all the input values given in Table 1.4 and take note of the output in the
Table 1.4.
A B C Y=A.B.C Voltage value measured by voltmeter

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.4

EXAMINATION OF NAND GATE
OBJECTIVES:
1- Getting to know digital logic NAND gate and verifying its logic operation,
2- Deriving its truth table and learning some properties of it.
3- Getting familiar with TTL 74LS00 NAND gate.
4- Analyzing the properties of the circuits composed of 3 or more NAND Gates.
1- NAND Gate provides the output as exactly inverted form of an AND gate.
2- Symbolically this situation is shown with an AND gate having a small circle at the output (Fig. 1.6).
3- The operating principle of a NAND gate can be summarized as; If all inputs are 1(H), the output is 0
(L) and if there is even only one 0 (L) level at any of the inputs, the output is 1(H) (Table 1.5).
4- As can be seen from Fig. 1.7, both TTL IC 7400 and CMOS IC 4011 contain 4 NAND gates.
5- If all inputs of a NAND gate are connected, it can operate as an inverter.
A B A.B Y=(A.B)’
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
Fig. 1.6. 2-input NAND gate. Table 1.5. The truth table of 2-input NAND gate.
TTL NAND 7400 CMOS NAND 4011

Fig. 1.7.

EXPERIMENT NO: 1.3

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE NAND GATE
Equipment:
74LS00 Quadruple 2-input NAND gates 1 IC
4011 Quadruple 2-input NAND gates 1 IC
Fig. 1.8.(a) Examination of a 2-input NAND gate (2_in_nand_gate).
Fig. 1.8.(b) Examination of a 2-input NAND gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input NAND gate is 1 (H) or 0 (L) and take note
of the output in Table 1.6.
4- Repeat step 3 for all remaining input values given in Table 1.6 and take note of the outputs in the
Table.
A B Y=(A.B)’
0 0
0 1
1 0
1 1
Table 1.6.

(4011).

EXPERIMENT NO: 1.4

EXPERIMENT NAME: USING A NAND GATE AS AN INVERTER
Equipment:
Fig. 1.9.(a) The use of a NAND gate as an INVERTER.
Fig. 1.9.(b) The use of a NAND gate as an INVERTER – application circuit.

Procedure:
power.
2- Set the input to logic 0.
3- Using the LEDs investigate whether the output of NAND gate Y is 1 (H) or 0 (L) and take note of the
output in Table 1.7.
5- Using the LEDs investigate whether the output of NAND gate Y is 1 (H) or 0 (L) and take note of the
A (INPUT) Y (OUTPUT)
1
0
Table 1.7.

(4011).

EXPERIMENT NO: 1.5

EXPERIMENT NAME: OBTAINING 3-INPUT NAND GATE USING 2-INPUT NAND GATES
OBJECTIVES:
1- Learning how to increase the number of inputs of a NAND Gate.
2- Deriving the truth table of a 3-input NAND Gate.
Equipment:
Fig. 1.10.(a) Obtaining a 3-input NAND gate using 2-input NAND gates (3_in_nand_gate).
Fig. 1.10.(b) Obtaining a 3-input NAND gate using 2-input NAND gates – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 3-input NAND gate is 1 (H) or 0 (L) and take note
Table.
A B C Y=(A.B.C)’
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.8.
NOTE : DO THE SAME EXPERIMENT AGAIN ON BREADBOARD BY USING CMOS IC

(4011).

EXAMINATION OF INVERTER
OBJECTIVES:
1- Getting to know digital logic INVERTER gate and verifying its logical operation,
2- Deriving its truth table.
3- Getting familiar with 74LS04 INVERTER IC.
4- Learning how to convert "an AND gate into an OR gate" and convert "an OR gate into an AND gate"
using INVERTERS.
1- An inverter reverses the logical level at the input (if input=0 then output=1; if input=1 then output=0)
(Table 1.9).
2- Symbolically this situation is denoted with a small circle at the inputs or outputs (Fig. 1.11).
3- Putting a small bar on the top of the letter representing the input or output means reversed logic.
4- This situation is simply named as "NOT".
5- As can be seen from Fig. 1.12, both TTL IC 7404 and CMOS IC 4063 contain 6 INVERTER gates.
INPUT OUTPUT
0 1
1 0
Fig. 1.11. INVERTER gate. Table 1.9. The truth table of the INVERTER gate.
TTL INVERTER 7404 CMOS INVERTER 4063

Fig. 1.12.
Converting an AND gate into an OR gate by using inverters:

According to the De Morgan's law, in order to change multiplication into addition
a-) Input variables are logically reversed.
b-) Multiplication sign is replaced with Addition sign.
c-) The whole process is reversed.
The connection diagram for converting an AND gate into an OR gate by using inverters is shown in Fig.
1.13. The corresponding truth table is provided in Table 1. 10.

Fig. 1.13. Converting an AND gate into an OR gate by using inverters.
INPUTS OUTPUT
INVERSE
A B X=A’.B’ Y=A+B
A’ B’
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1
Table 1.10.
Converting an OR gate into an AND gate by using inverters:
According to the De Morgan's law, in order to change addition into multiplication

a-) Input variables are logically reversed.
b-) Addition sign is replaced with Multiplication sign.
c-) The whole process is reversed.
The connection diagram for converting an OR gate into an AND gate by using inverters is shown in Fig.
1.14. The corresponding truth table is provided in Table 1.11.
Fig. 1.14. Converting an OR gate into an AND gate by using inverters.
INPUTS OUTPUT
INVERSE
A B X=A’+B’ Y=A.B
A’ B’
0 0 1 1 1 0
0 1 1 0 1 0
1 0 0 1 1 0
1 1 0 0 0 1
Table 1.11.

EXPERIMENT NO: 1.6

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE INVERTER
Equipment:
2. Multimeter.
74LS04 Hex inverters (six independent gates) 1 IC
Fig. 1.15.(a) Examination of INVERTER (inverter).
Fig. 1.15.(b) Examination of INVERTER – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of INVERTER gate Y is 1 (H) or 0 (L) and take note
6- Using the LEDs investigate whether the output of INVERTER gate Y is 1 (H) or 0 (L) and take note
A (INPUT) Y (OUTPUT) Voltage value measured by voltmeter

0
1
Table 1.12.

EXPERIMENT NO: 1.7

EXPERIMENT NAME: CONVERTING AN AND GATE INTO AN OR GATE BY USING
INVERTERS
Equipment:
Fig. 1.16.(a) Converting an AND gate into an OR gate by using inverters (and_to_or_gate).
Note: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Fig. 1.16.(b) Converting an AND gate into an OR gate by using inverters – application circuit.

Procedure:
power.
2- Record the logic level of the output Y for all possible combinations of the inputs A and B in Table
1.13.
INPUTS OUTPUT
INVERSE
Y=A+B
A B A’ B’
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 0
Table 1.13.

EXPERIMENT NO: 1.8

EXPERIMENT NAME: CONVERTING AN OR GATE INTO AN AND GATE BY USING
INVERTERS
Equipment:
74LS32 Quadruple 2-input OR gates 1 IC
Fig. 1.17.(a) Converting an OR gate into an AND gate by using inverters (or_to_and_gate).
Fig. 1.17.(b) Converting an OR gate into an AND gate by using inverters – application circuit.

Procedure:
power.
2- Record the logic level of the output Y for all possible combinations of the inputs A and B in Table
1.14.
INPUTS OUTPUT
INVERSE
Y=AB
A B A’ B’
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 0
Table 1.14.

EXAMINATION OF OR GATE
OBJECTIVES:
1- Getting to know digital logic OR Gate and verifying its logic operation.
2- Obtaining 3-input or 4-input OR Gates using several 2-input OR Gates.
1- OR Gate is the addition gate. It has at least two inputs. For any of the inputs' 1 (H) condition the
output will be at level 1(H). Only for all inputs are 0 (L), the output will be 0 (L) (Table 1.15).
2- The output of a 2-input OR gate is Y= A+B (Fig. 1.18). The truth table of 2-input OR gate is given in
Table 1.15.
3- The output of a 3-input OR gate is Y= A+B+C (Fig. 1.19). The truth table of 3-input OR gate is given
in Table 1.16.
4- TTL IC 74LS32 contains quadruple 2-input TTL OR gates (Fig. 1.20).
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Fig. 1.18. 2-input OR gate. Table 1.15. The truth table of 2-input OR gate.
A B C Y=A+B+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Fig. 1.19. 3-input OR gate. Table 1.16. The truth table of 3-input OR gate.
Fig. 1.20. 2-input TTL OR gate 7432.

EXPERIMENT NO: 1.9

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE OR GATE
Equipment:
Fig. 1.21.(a) Examination of a 2-input OR gate (2_in_or_gate).
Fig. 1.21.(b) Examination of a 2-input OR gate – application circuit.
Procedure
power.
3- Using the LEDs investigate whether the output of 2-input OR gate is 1 (H) or 0 (L) and take note of
4- Repeat step 3 for all other input values given in Table 1.17 and take note of the output in the Table.
A B Y
0 0
0 1
1 0
1 1
Table 1.17.

EXPERIMENT NO: 1.10

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE 3-INPUT OR GATE
Equipment:
Fig. 1.22.(a) Examination of a 3-input OR gate (3_in_or_gate).
Fig. 1.22.(a) Examination of a 3-input OR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 3-input OR gate is 1 (H) or 0 (L) and take note of
A B C Y (OUTPUT)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.18.

EXAMINATION OF NOR GATE
OBJECTIVES:
1- Getting to know digital logic NOR gate and verify its logic operation,
2- Obtaining the truth table and analyzing some properties of it.
3- Getting familiar with TTL 74LS02 NOR Integrated Circuit.
4- Obtaining a 3-input NOR gate by using three 2-input NOR gates.
1- NOR Gate provides the output as exactly inverted form of an OR Gate.
2- Symbolically this situation is shown with an OR gate having a small circle at the output (Fig. 1.23).
3- If any of the inputs is 1 (H) then the output is 0 (L) and when all inputs are 0 (L) then the output is 1
(H) (Table 1.19).
4- If the inputs of the NOR Gate are connected, it can operate as an inverter (Fig. 1.24, Table 1.20).
5- TTL IC 74LS02 contains quadruple 2-input TTL NOR gates (Fig. 1.25).
INPUTS OUTPUT
A B A+B Y=(A+B)’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
Fig. 1.23. 2-input NOR gate. Table 1.19. The truth table of 2-input NOR gate.
INPUT OUTPUT
0 1
1 0
Fig. 1.24. Using a NOR gate as INVERTER. Table 1.20. The truth table of INVERTER gate.
Fig. 1.25. 2-input TTL NOR gate 7402.

EXPERIMENT NO: 1.11

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE NOR GATE
Equipment:
74LS02 Quadruple 2-input NOR gates 1 IC
Fig. 1.26.(a) Examination of a 2-input NOR gate (2_in_nor_gate).
Fig. 1.26.(b) Examination of a 2-input NOR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input NOR gate is 1 (H) or 0 (L) and take note of
INPUTS OUTPUT
A B Y = (A+B)’
0 0
0 1
1 0
1 1
Table 1.21.

EXPERIMENT NO : 1.12
EXPERIMENT NAME: USING A NOR GATE AS AN INVERTER
Equipment:
Fig. 1.27.(a) The use of a NOR gate as an INVERTER (nor_inverter).
Fig. 1.27.(b) The use of a NOR gate as an INVERTER – application circuit.
Procedure:
power.
3- Using the LEDs investigate whether the output of NOR gate Y is 1 (H) or 0 (L) and take note of the
5- Using the LEDs investigate whether the output of NOR gate Y is 1 (H) or 0 (L) and take note of the
A(INPUT) Y(OUTPUT)
0
1
Table 1.22.
EXPERIMENT NAME: OBTAINING A 3-INPUT NOR GATE USING 2-INPUT NOR GATES
Equipment:
Fig. 1.28.(a) Obtaining a 3-input NOR gate using 2-input NOR gates (3_in_nor_gate).
Fig. 1.28.(b) Obtaining a 3-input NOR gate using 2-input NOR gates – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 3-input NOR gate is 1 (H) or 0 (L) and take note of
Table.
INPUTS OUTPUT
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.23.

EXAMINATION OF EXCLUSIVE-OR GATE
OBJECTIVES:
1- Getting to know digital logic EX-OR Gate and verifying its logic operation.
2- Getting familiar with TTL 7486 and CMOS 4030 Integrated Circuits.
1- 2-Input EX-OR gate (Fig. 1.29) compares two bits. If the bits are different from each other then the
output becomes 1 (H). If the bits are the same then the output becomes 0 (L) (Table 1.24).
2- EX-OR gate can be formed not only by the help of other gates but also by standard integrated circuits.
3- These circuits are also called Inequality Comparers
4- The parity code, which is an equality code is checked by an EX-OR gate.
4- TTL IC 7486 and CMOS IC 4030 contain quadruple 2-input TTL EX-OR gates (Fig. 1.30).
A B Y=A  B
0 0 0
0 1 1
1 0 1
1 1 0
Fig. 1.29. 2-input EX-OR gate. Table 1.24. The truth table of 2-input EX-OR gate.
TTL EX-OR gate 7486 CMOS EX-OR gate 4030

Fig. 1.30.

EXPERIMENT NO: 1.14

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE EXCLUSIVE-OR GATE
Equipment:
74LS86 Quadruple 2-input EX-OR gates 1 IC
Fig. 1.31.(a) Examination of a 2-input EX-OR gate (2_in_xor_gate).
Fig. 1.31.(b) Examination of a 2-input EX-OR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input EX-OR gate is 1 (H) or 0 (L) and take note
4- Repeat step 3 for all other input values given in Table 1.25 and take note of the outputs in the Table.
INPUTS OUTPUT
A B Y=A  B
0 0
0 1
1 0
1 1
Table 1.25.

EXAMINATION OF EXCLUSIVE-NOR GATE
OBJECTIVES:
1- Getting to know digital logic EX-NOR gate and verifying its logic operation.
2- Observing the parity bit generator circuit and deriving its truth table.
3- Forming an EX-NOR Gate using 7486 or 4077 CMOS EX-OR Gate and 7404 Inverter.
1- 2-Input EX-NOR gate (Fig. 1.32) compares two bits. If the bits are the same then the output becomes
1(H). If the bits are different from each other, then the output becomes 0 (L). (Table 1.26).
2- EX-NOR is the inverted form of EX-OR.
3- EX-NOR gate can be formed not only by the help of other gates but also by standard integrated
circuits.
4- The parity code, i.e. equality code, is produced with EX-NOR Gate.
5- TTL IC 74HC266 and CMOS IC 4077 contain quadruple 2-input TTL EX-NOR gates (Fig. 1.33).
Since the outputs of 74HC266 IC are open-drain, in order to observe a logic signal from an output it is
necessary to connect a pull-up resistor from the output to the power supply.
A B A B Y= (A  B)’ = AB
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
Fig. 1.32. 2-input EX-NOR gate. Table 1.26. The truth table of 2-input EX-NOR gate.
TTL EX-NOR gate 74HC266 CMOS EX-NOR gate 4077

Fig. 1.33

EXPERIMENT NO: 1.15

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE EXCLUSIVE-NOR GATE
Equipment:
2. Integrated Circuits (ICs) and other components:
74HC266 Quadruple 2-input EX-NOR gates 1 IC
10 KΩ resistor 1
Fig. 1.34.(a) Examination of a 2-input EX-NOR gate (2_in_xnor_gate).
Fig. 1.34.(b) Examination of a 2-input EX-NOR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input EX-NOR gate is 1 (H) or 0 (L) and take
note of the output in Table 1.27.
4- Repeat step 3 for all other input values given in Table 1.27 and take note of the outputs in the Table.
INPUTS OUTPUT
A B Y = (A  B)’ = AB
0 0
0 1
1 0
1 1
Table 1.27.

EXPERIMENT 2
LAWS AND THEOREMS OF BOOLEAN ALGEBRA
EQUIPMENT:
2- Integrated Circuits (ICs):

74LS11 Triple 3-input AND gates 1
4075 Triple 3-input OR gates 1

PRELIMINARY WORK:
3. By means of a digital simulation software test and verify the operation of the logic circuits shown in
the following table.
1 Fig. 2.1.(a) Examination of the commutative law – OR gate (2_in_or_gate).
2 Fig. 2.2.(a) Examination of the commutative law – AND gate (2_in_and_gate).
3 Fig. 2.3.(a) Examination of the associative law – OR gate – 1 (birlesme_kurali_veya_1).
4 Fig. 2.4.(a) Examination of the associative law – OR gate – 2 (birlesme_kurali_veya_2).
5 Fig. 2.5.(a) Examination of the associative law – AND gate – 1 (birlesme_kurali_ve_1).
6 Fig. 2.6.(a) Examination of the associative law – AND gate – 2 (birlesme_kurali_ve_2).
7 Fig. 2.7.(a) Examination of the distributive law – 1 (dagilma_kurali_1).
11 Fig. 2.11.(a) Examination of the idempotent law (ozdeslik_kurali).
12 Fig. 2.12.(a) Examination of the AND law (2_in_and_gate).
13 Fig. 2.13.(a) Examination of the OR law (2_in_or_gate).
14 Fig. 2.14.(a) Examination of complements (tamamlayici_kurali).
15 Fig. 2.15.(a) Examination of the involution law (cift_tersleme_kurali).
16 Fig. 2.16.(a) Examination of the absorption law (yutma_kurali).
17 Fig. 2.17.(a) Examination of the De Morgan’s theorem 1 (demorgan_kurali_1).
18 Fig. 2.18.(a) Examination of the De Morgan’s theorem 2 (demorgan_kurali_2).
4. In the above table there are 18 figures numbered as Fig. 2.XX.(a) referring to the schematic
diagrams of experiments to be done. As preliminary work you are obliged to draw by hand using
pencils an application circuit provided in Fig. 2.XX.(b) for each schematic diagram given in Fig.
2.XX.(a). It is recommended that you use red colour for Vcc, black colour for GND and other colours
for other connections.
NOTE: You are obliged to have a copy of the page number 2_1 from “the experiment report
form 2” when you start doing this experiment.

LAWS AND THEOREMS OF BOOLEAN ALGEBRA
OBJECTIVES:
1- Analyzing relations between logic operations,
2- Verifying laws and theorems of Boolean algebra.
1- English mathematician George BOOLE (1815-1864) analyzed logic operations in mathematics, put
forward and proved some laws and theorems which are called by his name.
2- In a logic operation, True or its voltage equivalent H (HIGH) is represented by “1” and False or its
voltage equivalent L (LOW) is represented by “0”.
3- For TTL ICs H (1) represents voltages between 2,4 V and 5 V, L (0) represents voltages between 0
V and 0,4 V.
4- Commutative Law : A+B=B+A

: A.B=B.A
5- Associative Law : A+B+C=(A+B)+C=A+(B+C)

: A.B.C=(A.B).C=A.(B.C)
6- Distributive Law : A.(B+C)=(A.B)+(A.C)

: A+(B.C)=(A+B).(A+C)
7- Indempotent Law : A+A=A

: A.A=A
8- AND Law : A.1=A

: A.0=0
9- OR Law : A+0=A
: A+1=1
10- Complements : A+A’=1

: A.A’=0
11- Involution Law :
12- Absorption Law : A+A.B=A

: A.(A+B)=A
13- De Morgan’s Theorems :

EXPERIMENT NO: 2.1

EXPERIMENT NAME: EXAMINATION OF THE COMMUTATIVE LAW (OR GATE)
OBJECTIVE: To examine the commutative law : A+B=B+A
: A.B=B.A
Equipment:
2. Integrated Circuit (IC):
Fig. 2.1.(a) Examination of the commutative law – OR gate (2_in_or_gate).
Fig. 2.1.(b) Examination of the commutative law – OR gate – application circuit.
Procedure:
power.
2- Set the inputs A and B according to the Table 2.1 and note the results.
3- Then exchange the inputs A and B and repeat part 2.
A B A+B B+A
0 0
0 1
1 0
1 1
Table 2.1

EXPERIMENT NO: 2.2

EXPERIMENT NAME: EXAMINATION OF THE COMMUTATIVE LAW (AND GATE)
OBJECTIVE: To examine the commutative law : A+B=B+A
: A.B = B.A
Equipment:
2. Integrated Circuits (ICs):
Fig. 2.2.(a) Examination of the commutative law – AND gate (2_in_and_gate).
Fig. 2.2.(b) Examination of the commutative law – AND gate – application circuit.
Procedure:
power..
2- Set the inputs A and B according to the Table 2.2 and note the results.
3- Then exchange the inputs A and B and repeat part 2.
A B A.B B.A
0 0
0 1
1 0
1 1
Table 2.2

EXPERIMENT NO: 2.3

EXPERIMENT NAME: EXAMINATION OF THE ASSOCIATIVE LAW (OR GATE) 1
OBJECTIVE: To examine the associative law : A+B+C = (A+B)+C = A+(B+C)
: A.B.C = (A.B).C = A.(B.C)
Equipment:
4075 Triple 3-input OR gates 1 IC
Fig. 2.3.(a) Examination of the associative law – OR gate – 1 (birlesme_kurali_veya_1).
Note: Do not forget to connect the Vcc and VDD pins to +5 V and
GND and VSS pins to ground (GND) connection.
Fig. 2.3.(b) Examination of the associative law – OR gate – 1– application circuit.

Procedure:
power.
2- Apply all possible combinations to the inputs of the circuit and experimentally obtain the output
values given in Table 2.3 and take note of the outputs in the Table.
A B C (A+B) Y=(A+B)+C Y=A+B+C

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.3

EXPERIMENT NO: 2.4

EXPERIMENT NAME: EXAMINATION OF THE ASSOCIATIVE LAW (OR GATE) 2
OBJECTIVE: To examine the associative law : A+B+C=(A+B)+C=A+(B+C)

: A.B.C = (A.B).C = A.(B.C)
Equipment:
4075 Triple 3-input OR gates 1 IC
Fig. 2.4.(a) Examination of the associative law – OR gate – 2 (birlesme_kurali_veya_2).
Note: Do not forget to connect the Vcc and VDD pins to +5 V and GND and VSS pins to ground (GND)
connection.
Fig. 2.4.(b) Examination of the associative law – OR gate – 2 – application circuit.

Procedure:
power.
A B C (B+C) Y=A+(B+C) Y=A+B+C

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.4

EXPERIMENT NO: 2.5

EXPERIMENT NAME: EXAMINATION OF THE ASSOCIATIVE LAW (AND GATE) 1

: A.B.C = (A.B).C = A.(B.C)
Equipment:
74LS11 Triple 3-input AND gates 1 IC
Fig. 2.5.(a) Examination of the associative law – AND gate – 1 (birlesme_kurali_ve_1).
Fig. 2.5.(b) Examination of the associative law – AND gate – 1 – application circuit.

Procedure:
power.
A B C (A.B) Y=(A.B).C Y=A.B.C

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.5

EXPERIMENT NO: 2.6

EXPERIMENT NAME: EXAMINATION OF THE ASSOCIATIVE LAW (AND GATE) 2

: A.B.C = (A.B).C = A.(B.C)
Equipment:
74LS11 Triple 3-input AND gates 1 IC
Fig. 2.6.(a) Examination of the associative law – AND gate – 2 (birlesme_kurali_ve_2).
Fig. 2.6.(b) Examination of the associative law – AND gate – 2 – application circuit.

Procedure:
power.
A B C (B.C) Y=A.(B.C) Y=A.B.C

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.6

EXPERIMENT NO: 2.7

EXPERIMENT NAME: EXAMINATION OF THE DISTRIBUTIVE LAW 1
OBJECTIVE: To examine the distributive law : A.(B+C) = (A.B)+(A.C)

: A+(B.C) = (A+B).(A+C)
Equipment:
Fig. 2.7.(a) Examination of the distributive law – 1 (dagilma_kurali_1).
Fig. 2.7.(b) Examination of the distributive law – 1 – application circuit.

Procedure:
power.
A B C (B+C) Y=A.(B+C)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.7

EXPERIMENT NO: 2.8


: A+(B.C) = (A+B).(A+C)
Equipment:

Procedure:
power.
A B C A.B A.C Y=A.B+A.C

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.8

EXPERIMENT NO: 2.9


: A+(B.C) = (A+B).(A+C)
Equipment:

Procedure:
power.
A B C (B.C) Y=A+(B.C)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.9

EXPERIMENT NO: 2.10


: A+(B.C) = (A+B).(A+C)
Equipment:

Procedure:
power.
A B C (A+B) (A+C) Y=(A+B).(A+C)

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.10

EXPERIMENT NO: 2.11

EXPERIMENT NAME: EXAMINATION OF THE IDEMPOTENT LAW
OBJECTIVE: To examine the idempotent law : A+A = A
: A.A = A
Equipment:
Fig. 2.11.(a) Examination of the idempotent law (ozdeslik_kurali).
Fig. 2.11.(b) Examination of the idempotent law – application circuit.
Procedure:
power.
2- Apply two combinations of the variable A to the circuit and experimentally obtain the output values
given in Table 2.11 and take note of the outputs in the Table.
A Y1=A+A=A Y2=A.A=A
0
1
Table 2.11

EXPERIMENT NO: 2.12

EXPERIMENT NAME: EXAMINATION OF THE AND LAW
OBJECTIVE: To examine the AND law : A.1=A
: A.0=0
Equipment:
Fig. 2.12.(a) Examination of the AND law (2_in_and_gate).
Fig. 2.12.(b) Examination of the AND law – application circuit.
Procedure:
power.
A Y=A.0=0 Y=A.1=A
(B=0) (B=1)
0
1
Table 2.12

EXPERIMENT NO: 2.13

EXPERIMENT NAME: EXAMINATION OF THE OR LAW
OBJECTIVE: To examine the OR law : A+0=A
: A+1=1
Equipment:
Fig. 2.13.(a) Examination of the OR law (2_in_or_gate).
Fig. 2.13.(b) Examination of the OR law – application circuit.
Procedure:
power.
A Y=A+0=A Y=A+1=1
(B=0) (B=1)
0
1
Table 2.13

EXPERIMENT NO: 2.14

EXPERIMENT NAME: EXAMINATION OF COMPLEMENTS
OBJECTIVE: To examine complements :
Equipment:
74LS04 Hex inverters (six independent 1 IC
gates)
Fig. 2.14.(a) Examination of complements (tamamlayici_kurali).
Fig. 2.14.(b) Examination of complements – application circuit.
Procedure:
power.
A Y1=A+A’=1 Y2=A.A’=0
0
1
Table 2.14

EXPERIMENT NO: 2.15

EXPERIMENT NAME: EXAMINATION OF THE INVOLUTION LAW
OBJECTIVE: To examine the involution law :
Equipment:
gates)
Fig. 2.15.(a) Examination of the involution law (cift_tersleme_kurali).

Fig. 2.15.(b) Examination of the involution law – application circuit.
Procedure:
power.
A B A’ (A+B) (A+B)’ (A+B)’’ (A.B) (A.B)’ (A.B)’’

0 0
0 1
1 0
1 1
Table 2.15

EXPERIMENT NO: 2.16

EXPERIMENT NAME: EXAMINATION OF THE ABSORPTION LAW
OBJECTIVE: To examine the absorption law : A+(A.B)=A

: A.(A+B)=A
Equipment:
Fig. 2.16.(a) Examination of the absorption law (yutma_kurali).
Fig. 2.16.(b) Examination of the absorption law – application circuit.

Procedure:
power.
A B A.B A+B Y1=A+A.B Y2=A.(A+B)

0 0
0 1
1 0
1 1
Table 2.16

EXPERIMENT NO: 2.17

EXPERIMENT NAME: EXAMINATION OF THE DE MORGAN’S THEOREM 1
OBJECTIVE: To examine the De Morgan’s theorem 1 :

:
Equipment:
gates)
Fig. 2.17.(a) Examination of the De Morgan’s theorem 1 (demorgan_kurali_1).
Fig. 2.17.(b) Examination of the De Morgan’s theorem 1 – application circuit.

Procedure:
power.
A B A’ B’ A.B Y1=(A.B)’ Y2=A’+B’

0 0
0 1
1 0
1 1
Table 2.17

EXPERIMENT NO: 2.18

EXPERIMENT NAME: EXAMINATION OF THE DE MORGAN’S THEOREM 2
OBJECTIVE: To examine the De Morgan’s theorem 2 :

:
Equipment:
gates)
Fig. 2.18.(a) Examination of the De Morgan’s theorem 2 (demorgan_kurali_2).
Fig. 2.18.(b) Examination of the De Morgan’s theorem 2 – application circuit.

Procedure:
power.
A B A’ B’ A+B Y1=(A+B)’ Y2=A’.B’

0 0
0 1
1 0
1 1
Table 2.18

EXPERIMENT 3
IMPLEMENTATION OF BOOLEAN FUNCTIONS

WITH LOGIC GATES
EQUIPMENT:

74LS02 Quadruple 2-input NOR gates 2

PRELIMINARY WORK:
1 Fig. 3.22.(a) The implementation of the function f(a,b,c,d) = a b + ad + acd in AND-OR form
(bf1).
Fig. 3.23.(a) The implementation of the function f(a,b,c,d) =( a  d )( a  c )( a  b  d ) in OR-
2
AND form (bf2).
Fig. 3.24.(a) The implementation of the function F3 = A’B’C+A’BC+AB’ in AND-OR form
3
(F3).
4 Fig. 3.25.(a) The implementation of the function F4 = AB’+A’C in AND-OR form (F4).
5 Fig. 3.26.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = ab  a c in AND-OR
form (and_or).
6 Fig. 3.27.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = (ab).(a c) in NAND-
NAND form (nand_nand).
7 Fig. 3.28.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = (a  b).(a  c) in

OR-NAND form (or_nand).
8 Fig. 3.29.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = (a  b)  (a  c) in

NOR-OR form (nor_or).
Fig. 3.30.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) =
9
(a+b).( a + c ) in OR-AND form (or_and).
10
(a  b)  (a  c) in NOR-NOR form (nor_nor).
11
(a.b)  (a.c) in AND-NOR form (and_nor).
12
(a.b).(a.c) in NAND-AND form (nand_and).
13 Fig. 3.34.(a) The implementation of the function f(a,b,c) = ab  a c by using NAND

equivalents (nand_only2).
14 Fig. 3.35.(a) The implementation of the function f(a,b,c) = ab  a c by using NOR equivalents
(nor_only2).

IMPLEMENTATION OF BOOLEAN FUNCTIONS WITH LOGIC GATES
OBJECTIVES:
1- Simplification of Boolean functions by means of Boolean algebra and Karnough maps
2- Implementation of simplified Boolean functions with different logic gate combinations
In this experiment the realization (implementation) of Boolean functions (expressions) by using logic
gate integrated circuits (ICs) is investigated. Before the implementation of Boolean functions, it is
necessary to simplify these functions, because simple functions mean the following: the
implementation is more economical, the implementation space will be smaller and you save power.
Therefore it is desirable to simplify Boolean functions. Secondly, the simplified logic expression is
implemented by using logic gate ICs. Finally, all possible combinations of the inputs are applied as
logic 0 and logic 1 and the output values experimentally are obtained.
Simplification of Boolean Functions
There are a few well-known methods to simplify Boolean functions, namely by using Boolean
algebra, Karnough maps (K-map) and Quine McCluskey method. It is very difficult to simplify
Boolean functions by using Boolean algebra. Karnough maps solve this problem in an easy way but
they are practical to simplify Boolean functions up to 4 variables. If there are more than 4 variables in
that case Quine McCluskey method is preferred to simplify Boolean functions.
3-Variable Karnough Maps
As can be seen from Fig. 3.1, in a 3-variable Karnough map there are eight minterms (or maxterms),
each of which is represented by a cell within the map. The order of numbers 00, 01, 11 and 10 in the
row (left) and column (right) are of Gray code type rather than binary form. Simplification of a
function in a 3-variable K-map is shown in Fig. 3.2.
Fig. 3.1. 3-variable Karnough maps.
Fig. 3.2. Simplification of a function in a 3-variable K-map.

4-Variable Karnough Maps
As can be seen from Fig. 3.3, in a 4-variable Karnough map there are sixteen minterms (or maxterms),
each of which is represented by a cell within the map. The order of numbers 00, 01, 11 and 10 in the
rows and columns are of Gray code type rather than binary form. Simplification of two functions in 4-
variable K-maps are shown in Fig. 3.4. On the left (respectively right) a 4-variable Boolean function
represented by a sum of minterms (respectively product of maxterms) is simplified by a 4-variable K-
map.
Fig. 3.3 4-variable Karnough maps.
f1(a, b, c, d)  m (0, 1, 2, 4, 5, 6, 8,10, 12, 13, 14, 15)

f2(a, b, c, d)  M (0, 1, 2, 4, 5, 6, 8,10, 12, 13, 14, 15)
Fig. 3.4 Simplification of two functions in 4-variable K-maps.
Don’t-Care Conditions
Don’t-care conditions are related with incompletely specified functions. In this case, the function is not
specified for certain combinations of the variables. These combinations may be assigned either 0 or 1
and they are represented by ‘×’ in a K-map. The following is an example function, where minterms 0,
2 and 5 are the variable combinations that make the function equal to 1. The minterms of don’t-care
conditions 1, 3 and 7 may be assigned either 0 or 1.
f(a, b, c)  m (0,2,5)  d (1,3,7)
We can simplify the given function f(a, b, c)  m (0,2,5)  d (1,3,7) as shown in Fig. 3.5. In this
example, don’t-care conditions, represented by ‘×’, are all assigned 1.

Fig. 3.5. The simplification of function f(a, b, c)  m (0,2,5)  d (1,3,7) in a 3-variable K-map.
Function
f(a, b, c)  m (0,2,5)  d (1,3,7)
can be represented as follows.
f(a, b, c)  M (4,6).D (1,3,7)
We can simplify the given function f(a, b, c)  M (4,6).D (1,3,7) as shown in Fig. 3.6. In this
example, don’t-care conditions, represented by ‘×’, are all assigned 1.
Fig. 3.6. The simplification of function f(a, b, c)  M (4,6).D (1,3,7) in a 3-variable K-map.
A given Boolean function can be implemented in several logic gate forms. In the following sections
these forms are considered.
Sum of Minterms
For ‘n’ Boolean variables there may be 2n different minterms. Every Boolean function can be
represented as sum of minterms. The binary numbers from 0 to 2n-1 are listed under the n variables.
Each minterm is obtained from an AND term of n variables, with each variable being primed if the
corresponding bit of the binary number is a 0 and unprimed if a 1. Sometimes it is more convenient to
express a Boolean function as sum of minterms. If a function is not in standard sum of minterms form
it can be converted into the standard form. The first step is to represent the function as sum of
products. Secondly in this case each product form (if it is not a standard product) is converted into
standard product. For example if a product term is missing variable ‘a’ or its complement then this
term is ANDed with the term ( a  a ). Sixteen minterms for four variables, together with their
symbolic designation are listed in Table 3.1.

Product of Maxterms
For ‘n’ Boolean variables there may be 2n different maxterms. Every Boolean function can be
represented as product of maxterms. The binary numbers from 0 to 2n-1 are listed under the n variables.
Each maxterm is obtained from an OR term of n variables, with each variable being unprimed if the
corresponding bit of the binary number is a 0 and primed if a 1. Sometimes it is more convenient to
express a Boolean function as product of maxterms. If a function is not in standard product of
maxterms form it can be converted into the standard form. The first step is to represent the function as
product of sums. Secondly in this case each sum form (if it is not a standard sum) is converted into a
standard sum. For example if a sum term is missing variable ‘a’ or its complement then this term is
ORed with the term a.a . Sixteen maxterms for four variables, together with their symbolic designation
are listed in Table 3.1. A function given in a sum of minterms form can be converted into product of
maxterms form and vice versa. For example the function f(a,b,c,d) = m(0,2,10,11,12,14) is given as
sum of minterms form. This function is converted into product of maxterms form as follows: f(a,b,c,d)
= M (1,3,4,5,6,7,8,9,13,15). As can be seen the total number of distinct terms (minterms and
maxterms) for four variables are 16 for a given function when considering its sum of minterms form
and product of maxterms form.
Table 3.1. Minterms and maxterms for four binary variables.

Variables Minterms Maxterms
a b c d Term Name Term Name
0 0 0 0 a.b.c.d m0 a + b + c +d M0
0 0 0 1 a.b.c.d m1 abcd M1
0 0 1 0 a.b.c.d m2 abcd M2
0 0 1 1 a.b.c.d m3 abcd M3
0 1 0 0 a.b.c.d m4 abcd M4
0 1 0 1 a.b.c.d m5 abcd M5
0 1 1 0 a.b.c.d m6 abcd M6
0 1 1 1 a.b.c.d m7 abcd M7
1 0 0 0 a.b.c.d m8 abcd M8
1 0 0 1 a.b.c.d m9 abcd M9
1 0 1 0 a.b.c.d m10 a  b  c  d M10
1 0 1 1 a.b.c.d m11 a  b  c  d M11
1 1 0 0 a.b.c.d m12 a  b  c  d M12
1 1 0 1 a.b.c.d m13 a  b  c  d M13
1 1 1 0 a.b.c.d m14 a  b  c  d M14
1 1 1 1 a.b.c.d m15 a  b  c  d M15
Possible Implementation Forms of a Boolean Function
It is desirable to simplify a Boolean function before its implementation with logic gates. A Boolean
function can be implemented in ten different forms as can be seen in this section. Firstly eight of these
forms are considered. First two forms are the sum of products form (AND-OR form) and the product
of sums form (OR-AND form). By using the involution law ( x = x) and De Morgan’s Theorems
( x  y = x.y ; x.y = x  y ) of Boolean algebra, AND-OR form can be converted into NAND-NAND,
OR-NAND and NOR-OR forms as can be seen from Fig. 3.7. Similarly, OR-AND form can be

converted into NOR-NOR, AND-NOR and NAND-AND forms. It is also possible to convert AND-
OR form into OR-AND form and vice versa. Finally as seen from Fig. 3.7, it is possible to implement
a Boolean function in these eight different forms. Now let’s consider these forms in more detail.
AND OR
OR AND
NOR NAND NAND NOR

OR NAND AND NOR
OR AND
NAND NOR
Fig. 3.7. 8 possible implementation forms of a Boolean function.
Example: For a Boolean function given as the sum of minterms f(a,b,c) = m(2,3,4,6) =
m2+m3+m4+m6 = abc + abc + a bc + ab c :
a). Simplify this function by using Boolean algebra.

b). Implement the simplified sum of products function in AND-OR form.
c). Implement the simplified sum of products function in NAND-NAND form.
d). Implement the simplified sum of products function in OR-NAND form.
e). Implement the simplified sum of products function in NOR-OR form.
f). Express the given function as product of maxterms.

g). Simplify the function ‘f’ expressed as product of maxterms in the previous step by using Boolean
algebra.
h). Implement the simplified product of sums function in OR-AND form.
i). Implement the simplified product of sums function in NOR-NOR form.
j). Implement the simplified product of sums function in AND-NOR form.
k). Implement the simplified product of sums function in NAND-AND form.
a). First of all let’s simplify the Boolean function given as the sum of minterms by using Boolean
algebra:
f(a,b,c) = ab  a c (the simplified form of the function)  AND-OR
b). The simplified form of the function as sum of products is as follows: f(a,b,c) = ab  a c . In this
form this function can directly be implemented by two level AND-OR logic gates. The implementation
of this simplified function in AND-OR form is shown in Fig. 3.8. Table 3.2 shows the truth table of the
function f(a,b,c) = m(2,3,4,6).

Fig. 3.8. The implementation of the simplified function

f(a,b,c) = m(2,3,4,6) = ab  a c in AND-OR form (and_or).
Table 3.2. The truth table of the function f(a,b,c) = m(2,3,4,6).

minterm a b c f
m0 0 0 0 0
m1 0 0 1 0
m2 0 1 0 1
m3 0 1 1 1
m4 1 0 0 1
m5 1 0 1 0
m6 1 1 0 1
m7 1 1 1 0
c). In order to obtain two level NAND-NAND logic gate form for the function f(a,b,c) = ab  a c , we
first use involution law ( x = x) as follows:
f(a,b,c) = f(a, b, c) = ab  a c = ab  a c
Then we apply De Morgan’s theorem ( x  y = x.y ):
f(a,b,c) = ab  a c = (ab).(a c) NAND-NAND
In this form this function can be implemented by two level NAND-NAND logic gates. The
implementation of this simplified function in NAND-NAND form is shown in Fig. 3.9.

f(a,b,c) = m(2,3,4,6) = (ab).(a c) in NAND-NAND form (nand_nand).
d). In order to obtain two level OR-NAND logic gate form for the function, we apply De Morgan’s
theorem ( x.y = x  y ):
f(a,b,c) = (ab).(a c) = (a  b).(a  c) OR-NAND

In this form this function can be implemented by two level OR-NAND logic gates. The
implementation of this simplified function in OR-NAND form is shown in Fig. 3.10.

f(a,b,c) = m(2,3,4,6) = (a  b).(a  c) in OR-NAND form (or_nand).
e). In order to obtain two level NOR-OR logic gate form for the function, we apply De Morgan’s
theorem ( x.y = x  y ):
f(a,b,c) = (a  b).(a  c) = (a  b)  (a  c) NOR-OR
In this form this function can be implemented by two level NOR-OR logic gates. The implementation
of this simplified function in NOR-OR form is shown in Fig. 3.11.

f(a,b,c) = m(2,3,4,6) ) = (a  b)  (a  c) in NOR-OR form (nor_or).
f). The Boolean function f(a,b,c) = m(2,3,4,6) = m2+m3+m4+m6 = abc + abc + a bc + ab c is given as
sum of minterms. Now let us express it as product of sums:
f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = M0.M1.M5.M7

f(a,b,c) = M (0,1,5,7) = (a  b  c) . (a  b  c) . (a  b  c) . (a  b  c)
g). The Boolean function f(a,b,c) = M (0,1,5,7) expressed as product of sums is simplified by using
Boolean algebra as follows:
f(a,b,c) = (a+b).( a + c ) (the simplified form of the function)  OR-AND
h). The simplified form of the function as product of sums is as follows: f(a,b,c) = (a+b).( a + c ). In this
form this function can directly be implemented by two level OR-AND logic gates. The implementation
of this simplified function in OR-AND form is shown in Fig. 3.12.


f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a+b).( a + c ) in OR-AND form (or_and) .
i). In order to obtain two level NOR-NOR logic gate form for the function f(a,b,c) = (a+b).( a + c ), we
first use involution law ( x = x) as follows:
f(a,b,c) = f(a, b, c) = (a + b).( a + c ) = (a + b).(a + c )
Then we apply De Morgan’s theorem ( x.y = x  y ):
f(a,b,c) = (a + b).(a + c ) = (a  b)  (a  c) NOR-NOR
In this form this function can be implemented by two level NOR-NOR logic gates. The
implementation of this simplified function in NOR-NOR form is shown in Fig. 3.13.

f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a  b)  (a  c) in NOR-NOR form (nor_nor) .
j). In order to obtain two level AND-NOR logic gate form for the function, we apply De Morgan’s
theorem ( x  y = x.y ):
f(a,b,c) = (a  b)  (a  c) = (a.b)  (a.c) AND-NOR
In this form this function can be implemented by two level AND-NOR logic gates. The
implementation of this simplified function in AND-NOR form is shown in Fig. 3.14.

f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a.b)  (a.c) in AND-NOR form (and_nor).

k). In order to obtain two level NAND-AND logic gate form for the function, we apply De Morgan’s
theorem ( x  y = x.y ):
f(a,b,c) = (a.b)  (a.c) = (a.b).(a.c) NAND-AND
In this form this function can be implemented by two level NAND-AND logic gates. The
implementation of this simplified function in NAND-AND form is shown in Fig. 3.15.

f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a.b).(a.c) in NAND-AND form (nand_and).
Equivalents of NAND and NOR Gates
In the previous section eight implementation forms of Boolean functions by using logic gates are
considered. In addition there are two more methods considered here. These methods are based on
equivalents of NAND and NOR gates. NAND gates are one of the two basic logic gates (along with
NOR gates) from which any other logic gate can be built as can be seen from Table 3.3. These
methods can be called as
1. The implementation of a Boolean function by using NAND Equivalents.

2. The implementation of a Boolean function by using NOR Equivalents.
It is assumed that the function to be implemented is given in a simplified form. In the first method the
function is implemented either in the simplified sum of products form with AND-OR gates (plus
inverter – NOT gates) or in the simplified product of sums form with OR-AND gates (plus inverter –
NOT gates). Then, AND, OR and NOT gates used in the implementation of the function are replaced
with their NAND equivalents as shown in Table 3.3. As a result we obtain the implementation of a
Boolean function by using NAND Equivalents. The second method is similar, in which AND, OR and
NOT gates used in the implementation of the function are replaced with their NOR equivalents. Once
we obtain the implementation of a function with NAND or NOR equivalents, in the final step
successively connected two NOT gates can be deleted to further simplify the implementation.

Table 3.3. Equivalents of NAND and NOR gates.

Gate name symbol NAND equivalent NOR equivalent
NOT
gate a a a a a a
a
AND a.b
a a a.b
gate a.b
b b b
a
OR a a+b a
a+b a+b
gate b b b
a
NAND a a
a.b a.b
gate b b b a.b
a
NOR a a
gate a+b b a+b
b a+b b
Let us now consider two examples.
Example: For a Boolean function given as the sum of products f(a,b,c) = ab  a c :
a). Implement this function by using NAND equivalents.

b). Implement this function by using NOR equivalents.
a). The function f(a,b,c) = ab  a c can directly be implemented by two level AND-OR logic gates.
The implementation of this function in AND-OR form is shown in Fig. 3.16.
Fig. 3.16. The implementation of the function f(a,b,c) = ab  a c in AND-OR form (and_or).
When AND, OR and NOT gates used in the implementation of the function are replaced with their
NAND equivalents as shown in Table 3.3, we obtain the implementation of the Boolean function by
using NAND equivalents as shown in Fig. 3.17. It can be seen that there are two sets of successively
connected two NOT gates, namely gates 5 and 7, and gates 6 and 8. This means that these gates can be
deleted to further simplify the implementation.

Fig. 3.17. The implementation of the function

f(a,b,c) = ab  a c by using NAND equivalents (nand_only1).
When gates 5, 6, 7 and 8, shown in Fig. 3.17, are deleted we obtain the implementation of the function
f(a,b,c) = ab  a c by using NAND equivalents as shown in Fig. 3.18.

f(a,b,c) = ab  a c by using NAND equivalents (further simplified) (nand_only2)
b). The function f(a,b,c) = ab  a c can be implemented by two level AND-OR logic gates. The
implementation of this function in AND-OR form is shown in Fig. 3.19.
Fig. 3.19. The implementation of the function f(a,b,c) = ab  a c in AND-OR form (and_or).
When AND, OR and NOT gates used in the implementation of the function are replaced with their
NOR equivalents as shown in Table 3.3, we obtain the implementation of the Boolean function by
using NOR equivalents as shown in Fig. 3.20. It can be seen that there are two sets of successively
connected two NOT gates, namely gates 1 and 3, and gates 2 and 6. This means that these gates can be
deleted to further simplify the implementation.


f(a,b,c) = ab  a c by using NOR equivalents (nor_only1).
When gates 1, 2, 3 and 6, shown in Fig. 3.20, are deleted we obtain the implementation of the function
f(a,b,c) = ab  a c by using NOR equivalents as shown in Fig. 3.21.

f(a,b,c) = ab  a c by using NOR equivalents (further simplified) (nor_only2).

EXPERIMENT NO: 3.1

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-OR
FORM
OBJECTIVE: Implementing a Boolean function in AND-OR form.
Equipment:

Fig. 3.22.(a) The implementation of the function f(a,b,c,d) = a b + ad + acd in AND-OR form (bf1).
Fig. 3.22.(b) The implementation of the function f(a,b,c,d) = a b + ad + acd in AND-OR form –
application circuit.

Procedure:
power.
2- Apply all possible combinations to the inputs and obtain and take note of the outputs in the Table
3.4.
a b c d f
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 3.4

EXPERIMENT NO: 3.2

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN OR-AND
FORM
OBJECTIVE: Implementing a Boolean function in OR-AND form.

Equipment:
gates)
Fig. 3.23.(a) The implementation of the function f(a,b,c,d) =( a  d )( a  c )( a  b  d ) in OR-AND

form (bf2).
Fig. 3.23.(b) The implementation of the function f(a,b,c,d) =( a  d )( a  c )( a  b  d ) in OR-AND
form – application circuit.

Procedure:
power.
3.5.
a b c d f
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 3.5

EXPERIMENT NO: 3.3

FORM 1
Equipment:
74LS08 Quadruple 2-input AND gates 2 ICs
Fig. 3.24.(a) The implementation of the function F3 = A’B’C+A’BC+AB’ in AND-OR form (F3).
Fig. 3.24.(b) The implementation of the function F3 = A’B’C+A’BC+AB’ in AND-OR form –
Procedure:
power.
3.6.
A B C F3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.6

EXPERIMENT NO: 3.4

FORM 2
Equipment:
Fig. 3.25.(a) The implementation of the function F4 = AB’+A’C in AND-OR form (F4).
Fig. 3.25.(b) The implementation of the function F4 = AB’+A’C in AND-OR form – application
circuit.
Procedure:
power.
3.7.
A B C F4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.7

EXPERIMENT NO: 3.5

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-OR FORM
Equipment:
Fig. 3.26.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = ab  a c in AND-OR form
(and_or).
Fig. 3.26.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = ab  a c in AND-OR form –
Procedure:
power.
3.8.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.8

EXPERIMENT NO: 3.6

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NAND-
NAND FORM
OBJECTIVE: Implementing a Boolean function in NAND-NAND form.
Equipment:
Fig. 3.27.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = (ab).(a c) in NAND-NAND
form (nand_nand).
Fig. 3.27.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = (ab).(a c) in NAND-NAND
Procedure:
power.
3.9.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.9

EXPERIMENT NO: 3.7
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN OR-NAND
FORM
OBJECTIVE: Implementing a Boolean function in OR-NAND form.
Equipment:
Fig. 3.28.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = (a  b).(a  c) in OR-NAND
form (or_nand).
Fig. 3.28.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = (a  b).(a  c) in OR-NAND
Procedure:
power.
3.10.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.10

EXPERIMENT NO: 3.8

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NOR-OR
FORM
OBJECTIVE: Implementing a Boolean function in NOR-OR form.
Equipment:
Fig. 3.29.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = (a  b)  (a  c) in NOR-OR

form (nor_or).
Fig. 3.29.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = (a  b)  (a  c) in NOR-OR
Procedure:
power.
3.11.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.11

EXPERIMENT NO: 3.9
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN OR-AND
FORM
OBJECTIVE: Implementing a Boolean function in OR-AND form.
Equipment:
Fig. 3.30.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a+b).( a + c )
in OR-AND form (or_and).
Fig. 3.30.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a+b).( a + c )
in OR-AND form – application circuit.
Procedure:
power.
3.12.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.12

EXPERIMENT NO: 3.10
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NOR-NOR
FORM
OBJECTIVE: Implementing a Boolean function in NOR-NOR form.
Equipment:

(a  b)  (a  c) in NOR-NOR form (nor_nor).
Fig. 3.31.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) =
(a  b)  (a  c) in NOR-NOR form – application circuit.
Procedure:
power.
3.13.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.13

EXPERIMENT NO: 3.11
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN AND-NOR
FORM
OBJECTIVE: Implementing a Boolean function in AND-NOR form.
Equipment:
Fig. 3.32.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a.b)  (a.c) in
AND-NOR form (and_nor).
Fig. 3.32.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a.b)  (a.c) in
AND-NOR form – application circuit.
Procedure:
power.
3.14.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.14

EXPERIMENT NO: 3.12
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION IN NAND-AND
FORM
OBJECTIVE: Implementing a Boolean function in NAND-AND form.
Equipment:
Fig. 3.33.(a) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a.b).(a.c) in
NAND-AND form (nand_and).
Fig. 3.33.(b) The implementation of the function f(a,b,c) = m(2,3,4,6) = M (0,1,5,7) = (a.b).(a.c) in
NAND-AND form – application circuit.
Procedure:
power.
3.15.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.15

EXPERIMENT NO: 3.13
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING
NAND EQUIVALENTS
OBJECTIVE: Implementing a Boolean function by using NAND equivalents.
Equipment:
74LS00 Quadruple 2-input NAND gates 2 ICs
Fig. 3.34.(a) The implementation of the function f(a,b,c) = ab  a c by using NAND equivalents
(nand_only2).
Fig. 3.34.(b) The implementation of the function f(a,b,c) = ab  a c by using NAND equivalents –
Procedure:
power.
3.16.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.16

EXPERIMENT NO: 3.14
EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING NOR
EQUIVALENTS
OBJECTIVE: Implementing a Boolean function by using NOR equivalents.
Equipment:
74LS02 Quadruple 2-input NOR gates 2 ICs
Fig. 3.35.(a) The implementation of the function f(a,b,c) = ab  a c by using NOR equivalents
(nor_only2).
Fig. 3.35.(b) The implementation of the function f(a,b,c) = ab  a c by using NOR equivalents –
Procedure:
power.
3.17.
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.17

EXPERIMENT 4
COMBINATIONAL LOGIC CIRCUITS:

ADDERS, SUBTRACTORS
EQUIPMENT:

74LS83 4-bit binary adder 2
74LS86 Quadruple 2-input EXOR gates 1

PRELIMINARY WORK:
1 Fig. 4.2.(a) The half adder circuit (half_adder).
2 Fig. 4.5.(a) The full adder circuit (full_adder).
3 Fig. 4.9.(a) 74LS83 4-bit parallel adder circuit (74LS83).
4 Fig. 4.11.(a) The half subtractor circuit (half_subtractor).
5 Fig. 4.13.(a) The full subtractor circuit (full_subtractor).
6 Fig. 4.14.(a) 4 bit full adder / full subtractor circuit (4_bit_adder_subtractor).
7 Fig. 4.15.(a) 4 bit BCD adder circuit (4_bit_BCD_adder).
connections.

BINARY ADDERS
OBJECTIVES:
1- Investigating the binary adder circuits,
2- Observing their operation and obtaining their truth tables,
3- Getting to know IC binary adder circuits.
Circuits that perform addition, subtraction multiplication and division with binary numbers are called
arithmetic circuits. It seems that there are four operations but actually consecutive additions are
performed for multiplication, consecutive subtractions are performed for division. There are basically
two types of addition in logic circuits. Circuits that perform addition of two bits are called “half
adders”, circuits that perform addition of three bits are called “full adders”.
Following rules are applicable for adders.
0+0=0
0+1=1
1+0=1
1 + 1 = 1 0 (Sum=0, Carry=1)
The half adder circuit is shown in Fig. 4.1, and its truth table is provided in Table 4.1.
INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Fig. 4.1. The half adder circuit. Table 4.1. The truth table of the half adder.

EXPERIMENT NO: 4.1

EXPERIMENT NAME: EXAMINATION OF HALF ADDER
Equipment:
74LS86 Quadruple 2-input EXOR gates 1 IC
Fig. 4.2.(a) The half adder circuit (half_adder).
Fig. 4.2.(b) The half adder – application circuit.
Procedure:
power.
2. Apply all possible combinations to the inputs of the circuit and experimentally obtain the output
INPUTS OUTPUTS
A B S C
0 0
0 1
1 0
1 1
Table 4.2

FULL ADDER
OBJECTIVES:
1- Examination of full adder circuit,
2- Observing its operation and obtaining its truth table,
3- Getting to know adder circuits.
A full adder is a combinational circuit that performs the arithmetic sum of three input bits. The symbol
of a full adder is shown in Fig. 4.4. It consists of three inputs and two outputs. Two of the input
variables, denoted by A and B, represent the two significant bits to be added. The third input, Ci (input
carry), represents the carry from previous lower significant position. Two outputs are S (Sum) and Co
(output carry). A full adder can be obtained by connecting two half adders, as seen from Fig. 4.3. The
truth table of the full adder is provided in Table 4.3.
Fig. 4.4. The symbol of the full adder.

Fig. 4.3. The full adder circuit.
INPUTS OUTPUTS
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 4.3. The truth table of the full adder.

EXPERIMENT NO: 4.2

EXPERIMENT NAME: EXAMINATION OF FULL ADDER
Equipment:
Fig. 4.5.(a) The full adder circuit (full_adder).
Fig. 4.5.(b) The full adder – application circuit.
Procedure:
1. Construct the circuit [as given in Fig. 4.5.(a) and] as drawn by you in Fig. 4.5.(b) and apply the
power.
INPUTS OUTPUTS
A B Ci S Co
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 4.4

4-BIT PARALLEL ADDER

OBJECTIVES:
1- Investigating the 4 bit parallel adder circuit,
3- Getting to know 4 bit parallel adder IC 74LS83.
Figure 4.6 shows an example of a parallel adder: a 4-bit ripple-carry adder. It is composed of four full
adders. The augend’s bits of “B” are added to the addend bits of “A” respectfully of their binary
position. Each bit addition produces a sum (S) and a carry out (Co). The carry out is then transmitted
to the carry in (Ci) of the next higher-order bit. The final result produces a sum of four bits S
(S4S3S2S1) plus a carry out (Cout) bit.
Fig. 4.6. 4 bit parallel adder circuit.
74LS83 is an IC parallel adder. It adds two 4-bit binary numbers [A (A4A3A2A1) and B
(B4B3B2B1)] and a carry in bit (Cin). The sum is expressed in binary form as Cout(output carry), s4,
s3, s2, and s1. It is possible to add BCD or base-16 numbers with 74LS83 IC by using 4-bit numbers.
The truth table of 74LS83 IC full adder is given in Fig. 4.7. Both connection diagram and logic
diagram of 74LS83 parallel adder are shown in Fig. 4.8. Table 4.5 provides some example operations
for 74LS83 parallel adder.
Fig. 4.7. The truth table of 74LS83 parallel adder.

Fig. 4.8. Connection diagram and logic diagram of 74LS83 parallel adder.
1. NUMBER 2. NUMBER OUTPUTS

A4 A3 A2 A1 B4 B3 B2 B1 Cin Cout s4 s3 s2 s1
0 0 1 1 + 1 0 0 0 0 = 0 1 0 1 1
1 1 1 1 + 1 1 1 1 1 = 1 1 1 1 1
0 0 0 1 + 1 1 0 0 0 = 0 1 1 0 1
1 0 1 0 + 1 0 1 1 1 = 1 0 1 1 0
1 1 0 1 + 0 1 1 1 1 = 1 0 1 0 1
0 1 0 1 + 0 1 1 1 0 = 0 1 1 0 0
Table 4.5. Some example operations for 74LS83 parallel adder.

EXPERIMENT NO: 4.3

EXPERIMENT NAME: EXAMINATION OF 4 BIT PARALLEL ADDER
Equipment:
74LS83 4-bit binary adder 1 IC
Fig. 4.9.(a) 74LS83 4-bit parallel adder circuit (74LS83).
Fig. 4.9.(b) 74LS83 4-bit parallel adder – application circuit.

Procedure:
power.
2. Apply all possible combinations to the inputs (A4 A3 A2 A1 B4 B3 B2 B1) of the circuit and
experimentally obtain the output values given in Table 4.6 and take note of the outputs (Cout S4 S3 S2
S1) in the Table.
A 1. NUMBER 2. NUMBER B OUTPUTS

OUTPUTS
(base (base
A4 A3 A2 A1 B4 B3 B2 B1 Cin Cout S4 S3 S2 S1 (base 10)
10) 10)
10 1 0 1 0 1 0 1 1 11 0 =
14 1 1 1 0 1 0 1 0 10 0 =
12 1 1 0 0 0 1 0 0 4 0 =
5 0 1 0 1 0 0 1 1 3 0 =
4 0 1 0 0 0 1 0 1 5 0 =
8 1 0 0 0 1 1 0 1 13 0 =
15 1 1 1 1 1 0 0 1 9 1 =
2 0 0 1 0 1 1 1 1 15 1 =
13 1 1 0 1 0 0 1 0 2 1 =
6 0 1 1 0 1 1 1 0 14 1 =
7 0 1 1 1 0 1 1 1 7 1 =
9 1 0 0 1 0 1 1 0 6 1 =
Table 4.6

BINARY SUBTRACTORS
OBJECTIVES:
1- Investigating the binary subtractor circuits,
3- Getting to know IC binary subtractor circuits.
A half-subtractor is a combinational circuit that subtracts two bits (x – minuend, y – subtrahend) and
produces their difference (D – difference). It also has an output to specify if a 1 has been borrowed (B
– borrow). Following rules are applicable for subtractors.
x y B D
0–0 = 0
0 – 1 = 1 1 (Borrow = 1, Difference = 1)
1 – 0 = 1 (Difference = 1)
1–1 = 0
The half subtractor circuit is shown in Fig. 4.10, and its truth table is provided in Table 4.7.
INPUTS OUTPUTS
x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Fig. 4.10. The half subtractor circuit. Table 4.7. The truth table of the half subtractor.

EXPERIMENT NO: 4.4

EXPERIMENT NAME: EXAMINATION OF HALF SUBTRACTOR
Equipment:
Fig. 4.11.(a) The half subtractor circuit (half_subtractor).
Fig. 4.11.(b) The half subtractor – application circuit.
Procedure:
power.
INPUTS OUTPUTS
x y B D
0 0
0 1
1 0
1 1
Table 4.8

FULL SUBTRACTOR
OBJECTIVES:
1- Examination of full adder subtractor circuit,
3- Getting to know subtractor circuits.
A full-subtractor is a combinational circuit that performs subtraction between two bits taking account
that a 1 may have been borrowed by a lower significant stage. The three inputs x, y and z, denote the
minuend, subtrahend and previous borrow, respectively. The two outputs D and B represent the
difference and output borrow, respectively. A full subtractor can be obtained by connecting two half
subtractors, as seen from Fig. 4.12. The truth table of the full subtractor is provided in Table 4.9.
Fig. 4.12. The full subtractor circuit.
INPUTS OUTPUTS
x y z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Table 4.9. The truth table of the full subtractor.

EXPERIMENT NO: 4.5

EXPERIMENT NAME: EXAMINATION OF FULL SUBTRACTOR
Equipment:
Fig. 4.13.(a) The full subtractor circuit (full_subtractor).
Fig. 4.13.(b) The full subtractor – application circuit.
Procedure:
power.
INPUTS OUTPUTS
x y z B D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 4.10

EXPERIMENT NO: 4.6

EXPERIMENT NAME: EXAMINATION OF 4 BIT FULL ADDER / FULL SUBTRACTOR
Equipment:
74LS83 4-bit binary adder 1 IC
Circuit Description: Fig. 4.14.(a) shows a 4 bit full adder / full subtractor circuit. There are two 4 bit
inputs A (A4A3A2A1) and B (B4B3B2B1). The outputs are Cout,S4,S3,S2,S1. In this circuit, if D = 0
then two 4 bit inputs A and B are added: A+B. In this case, the XOR-gates act as non-inverting
buffers, and the carry-input (Cin) to the adder is 0. Therefore, the adder calculates a four-bit sum plus
carry-out:
(Cout,S4,S3,S2,S1) = (A4,A3,A2,A1) + (B4,B3,B2,B1)
If D = 1 then subtraction is applied based on two’s complement as follows: A+B’+1. In this case, the
XOR-gates act as inverting buffers, and the carry-input (Cin) to the adder is 1. Therefore, the circuit
calculates a four-bit subtraction based on two’s complement:
(Cout,S4,S3,S2,S1) = (A4,A3,A2,A1) – (B4,B3,B2,B1)
Fig. 4.14.(a) 4 bit full adder / full subtractor circuit (4_bit_adder_subtractor).

Procedure:
power.
2. Apply the combinations given in Table 4.11 to the inputs (D A4 A3 A2 A1 B4 B3 B2 B1) of the
circuit and experimentally obtain the output values and take note of the outputs (Cout S4 S3 S2 S1) in
the Table.

Fig. 4.14.(b) 4 bit full adder / full subtractor – application circuit.
A NUMBER A NUMBER B B OUTPUTS

(base
D (base (base
A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1 10)
10) 10)
0 10 1 0 1 0 1 0 1 1 11
0 14 1 1 1 0 1 0 1 0 10
0 12 1 1 0 0 0 1 0 0 4
0 5 0 1 0 1 0 0 1 1 3
0 4 0 1 0 0 0 1 0 1 5
0 13 1 1 0 1 1 1 0 1 13
0 6 0 1 1 0 1 0 0 1 9
0 2 0 0 1 0 1 0 0 0 8
0 1 0 0 0 1 0 0 1 0 2
0 7 0 1 1 1 0 0 0 1 1
0 15 1 1 1 1 0 1 1 0 6
0 9 1 0 0 1 1 1 1 1 15
1 10 1 0 1 0 1 0 1 1 11
1 14 1 1 1 0 1 0 1 0 10
1 12 1 1 0 0 0 1 0 0 4
1 5 0 1 0 1 0 0 1 1 3
1 4 0 1 0 0 0 1 0 1 5
1 13 1 1 0 1 1 1 0 1 13
1 6 0 1 1 0 1 0 0 1 9
1 2 0 0 1 0 1 0 0 0 8
1 1 0 0 0 1 0 0 1 0 2
1 7 0 1 1 1 0 0 0 1 1
1 15 1 1 1 1 0 1 1 0 6
1 9 1 0 0 1 1 1 1 1 15
Table 4.11

EXPERIMENT NO: 4.7

EXPERIMENT NAME: EXAMINATION OF 4 BIT BCD ADDER
Equipment:
74LS83 4-bit binary adder 2 ICs
Circuit Description: Fig. 4.15.(a) shows a 4 bit BCD (Binary Coded Decimal) adder circuit. In this
circuit BCD inputs A (A4A3A2A1) and B (B4B3B2B1) are added. Since A and B inputs are defined
as BCD it is expected that they are applied as one of the following values: 0, 1, 2, …, 9, because the
remaining values, namely 10, 11, 12, 13, 14, 15 (A, B, C, D, E and F hexadecimal values) are
undefined for BCD arithmetic. Naturally, it would be easy to design a special circuit for the binary
coded decimal arithmetic. However, this is seldom done. The circuit shown here relies on the same
trick that is often used in microprocessors for BCD arithmetic instructions. For example, many
microprocessors including the Intel 808x and Motorola 68xx families provide a special decimal adjust
accumulator instruction (DAA). A BCD addition is then performed in two steps, namely a standard
addition followed by the DAA instruction. The basic operation performed by DAA is to add a constant
value of 6 for each BCD-digit that overflowed during the first addition. Only very little logic is
required to implement this operation. To make this behaviour explicit, the circuit shown in Fig.
4.15.(a) uses two stages of binary adders, each built with a single 74LS83 4-bit adder. The first stage
consists of just the binary adder. The second stage uses a few gates to check for a decimal overflow,
that is, output values larger than 9. If an overflow is detected, the second adder is hardwired to add the
value 6 (0110) to the output of the first adder - which is equivalent to a subtraction of 10, thereby
undoing the overflow of the first stage. The resulting 4-bit output value (Z4Z3Z2Z1) and 1-bit carry
(Z5) are the correct sum in BCD arithmetic.
Fig. 4.15.(a) 4 bit BCD adder circuit (4_bit_BCD_adder).

Fig. 4.15.(b) 4 bit BCD adder – application circuit.

Procedure:
power.
2. Apply the combinations given in Table 4.12 to the inputs (A4 A3 A2 A1 B4 B3 B2 B1) of the
circuit and experimentally obtain the output values and take note of the outputs (Z5 Z4 Z3 Z2 Z1) in
the Table.
INPUTS OUTPUTS
Binary Binary
A A B B Z
Z
(base (base
A4 A3 A2 A1 B4 B3 B2 B1 Z5 Z4 Z3 Z2 Z1 (base 10)
10) 10)
5 0 1 0 1 0 1 0 0 4
9 1 0 0 1 1 0 0 1 9
3 0 0 1 1 0 1 1 1 7
6 0 1 1 0 0 0 1 0 2
8 1 0 0 0 0 0 1 0 2
6 0 1 1 0 0 1 1 0 6
2 0 0 1 0 1 0 0 0 8
1 0 0 0 1 0 1 1 1 7
9 1 0 0 1 0 1 1 1 7
Table 4.12.
the Table.
INPUTS OUTPUTS
Binary Binary
A A B B Z
Z
(base (base
10) 10)
10 1 0 1 0 1 0 0 1 9
11 1 0 1 1 0 1 1 0 6
12 1 1 0 0 0 1 1 1 7
13 1 1 0 1 0 1 0 0 4
14 1 1 1 0 0 0 1 0 2
15 1 1 1 1 0 0 0 1 1
9 1 0 0 1 1 0 1 0 10
3 0 0 1 1 1 0 1 1 11
6 0 1 1 0 1 1 0 0 12
5 0 1 0 1 1 1 0 1 13
2 0 0 1 0 1 1 1 0 14
1 0 0 0 1 1 1 1 1 15
Table 4.13

the Table.
INPUTS OUTPUTS
Binary Binary
A A B B Z
Z
(base (base
10) 10)
10 1 0 1 0 1 1 0 1 13
11 1 0 1 1 1 1 1 0 14
12 1 1 0 0 1 1 1 1 15
13 1 1 0 1 1 0 1 0 10
14 1 1 1 0 1 0 1 1 11
15 1 1 1 1 1 1 0 0 12
10 1 0 1 0 1 1 0 1 13
11 1 0 1 1 1 1 1 0 14
12 1 1 0 0 1 1 1 1 15
13 1 1 0 1 1 0 1 0 10
14 1 1 1 0 1 0 1 1 11
15 1 1 1 1 1 1 0 0 12
Table 4.14

EXPERIMENT 5

DECODERS, ENCODERS
EQUIPMENT:

74LS138 3x8 decoder 1
74LS139 Dual independent 2x4 decoders 1
74LS148 8x3 priority encoder 1

PRELIMINARY WORK:
1 Fig. 5.7.(a) 74LS138 3x8 decoder circuit (74LS138).
2 Fig. 5.9.(a) 74LS139 2x4 decoder circuit (74LS139).
3 Fig. 5.14.(a) 74LS148 8x3 priority encoder circuit (74LS148).
connections.
5. Implement the function S(x,y,z,) = m(1,2,4,7) by using a 3x8 decoder with active low outputs,
inverters and a four-input-OR gate provided in Fig. 5.8.(a). By means of a digital simulation software
test and verify the operation of your implementation. Then, you are obliged to draw by hand using
pencils an application circuit provided in Fig. 5.8.(b) for the completed schematic diagram of Fig.
5.8.(a). It is recommended that you use red colour for Vcc, black colour for GND and other colours for
other connections.
6. Construct a 3x8 decoder with active low outputs by using two 2x4 decoders with active low outputs
and an inverter provided in Fig. 5.10.(a). By means of a digital simulation software test and verify the
operation of your implementation. Then, you are obliged to draw by hand using pencils an application
circuit provided in Fig. 5.10.(b) for the completed schematic diagram of Fig. 5.10.(a). It is
connections.

DECODERS
OBJECTIVES:
1- Investigating the decoder circuits,
3- Getting to know decoder circuits.
In digital circuit theory, combinational logic (sometimes also referred to as combinatorial logic) is a
type of digital logic which is implemented by Boolean circuits, where the output is a pure function of
the present input only. This is in contrast to sequential logic, in which the output depends not only on
the present input but also on the history of the input. In other words, sequential logic has memory
while combinational logic does not. Combinational logic is used in computer circuits to do Boolean
algebra on input signals and on stored data. Practical computer circuits normally contain a mixture of
combinational and sequential logic. For example, the part of an arithmetic logic unit, or ALU, that
does mathematical calculations is constructed using combinational logic. Other circuits used in
computers, such as half adders, full adders, half subtractors, full subtractors, multiplexers,
demultiplexers, encoders and decoders are also made by using combinational logic. Experiment 5
deals with decoders and encoders.
DECODERS
A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the
reverse of encoding. A common type of decoder is the line decoder which takes an m-bit binary input
data and decodes it into 2m data lines. As a standard combinational component, a decoder, asserts one
out of n output lines, depending on the value of an m bit binary input data. The outputs of a decoder
can be either active-low or active-high. When the outputs are active high (respectively active low) the
asserted output is high (respectively low) and the rest of the other outputs are low (respectively high).
The general form of an m-to-n decoder can be seen from Fig. 5.1. In general, an m-to-n decoder has m
input lines, im-1, …, i1, i0, and n output lines, dn-1, …, d1, d0, where n = 2m. As shown in Figure 5.1, in
addition to input lines and output lines, a decoder has an enable line, E, for enabling the decoder.
When the decoder is disabled with E set to 0 (for active high enable input E), all the output lines are
de-asserted. When the decoder is enabled, then the output line whose index is equal to the value of the
input binary data is asserted (set to 1 for active high), while the rest of the output lines are de-asserted
(set to 0 for active high). A decoder is used in a system having multiple components, and we want only
one component to be selected or enabled at any time.
Fig. 5.1. The general form of an m-to-n decoder, where n = 2m.

In general, decoders are produced in integrated circuits as 2x4, 3x8 and 4x16 decoders. The schematic
symbol, the truth table and the logic diagram of a 2x4 decoder with active high enable input (E) and
active high outputs (d0, d1, d2 and d3) are provided in Fig. 5.2. In this decoder, the active high enable
input E, select inputs A and B, active high output signals “d0”, “d1”, “d2”, and “d3” are all Boolean
variables. When this decoder is disabled with E set to 0, all active high output lines are de-asserted (set
to 0). When this decoder is enabled with E set to 1: if the select inputs are AB = 00, (respectively, 01,
10, 11), then the output line, d0 (respectively, d1, d2, d3), is asserted (set to 1) and all other output lines
are de-asserted (set to 0).
Schematic Symbol
2x4
DECODER
Logic Diagram
d0
d1
A d2
B d3
E
Truth Table
INPUTS OUTPUTS
E A B d0 d1 d2 d3
0   0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
: don’t care.
Fig. 5.2. The schematic symbol, the truth table and the logic diagram of a 2x4 decoder with
active high enable input and active high outputs (decoder_2_4_E_1).
The schematic symbol, the truth table and the logic diagram of a 3x8 decoder with active low enable
input (E) and active low outputs (d0, d1, d2, d3, d4, d5, d6, and d7) are provided in Fig. 5.3. In this
decoder, the active low enable input E, select inputs A, B and C, active low output signals “d0”, “d1”,
“d2”, “d3”, “d4”, “d5”, “d6”, and “d7” are all Boolean variables. When this decoder is disabled with E
set to 1, all active low output lines are de-asserted (set to 1). When this decoder is enabled with E set to
0, i.e., when E = 0: if the select inputs are ABC = 000, (respectively, 001, 010, 011, 100, 101, 110,
111), then the output line, d0 (respectively, d1, d2, d3, d4, d5, d6, d7), is asserted (set to 0) and all other
output lines are de-asserted (set to 1).

Logic Diagram
Schematic Symbol
Truth Table
INPUTS OUTPUTS
E A B C d0 d1 d2 d3 d4 d5 d6 d7
1    1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1
0 1 1 0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 0
: don’t care.
Fig. 5.3. The schematic symbol, the truth table and the logic diagram of a 3x8 decoder with active low
enable input and active low outputs (decoder_3_8_AL_E_AL_O).
Two or more small decoders such as 2x4, 3x8, 4x16 with enable inputs can be combined to form a
larger decoder. For example a 4x16 decoder is constructed from two 3x8 decoders as shown in Fig.
5.4. In this circuit when A3 = 0 the upper 3x8 decoder is enabled and based on the logic values applied
to inputs A2, A1, A0 one of the outputs (D0, D1, D2, D3, D4, D5, D6 or D7) is asserted and set to 1.
When A3 = 0 the lower 3x8 decoder is disabled and all of its outputs, namely D8, D9, D10, D11, D12,
D13, D14 and D15 are de-asserted. When A3 = 1 the upper 3x8 decoder is disabled and all of its
outputs, namely D0, D1, D2, D3, D4, D5, D6 and D7 are de-asserted. When A3 = 1 the lower 3x8
decoder is enabled and based on the logic values applied to inputs A2, A1, A0 one of the outputs (D8,
D9, D10, D11, D12, D13, D14 or D15) is asserted and set to 1.

Fig. 5.4. Construction of a 4x16 decoder from two 3x8 decoders.
74LS138 – 3x8 Decoder IC
Fig. 5.5 shows the schematic symbol, the logic diagram and the truth table of 74LS138 3x8 decoder
IC. The 74LS138 decodes one-of-eight lines (O7’, O6’, O5’, O4’, O3’, O2’, O1’ and O0’), based upon
the conditions at the three binary select inputs (A2, A1 and A0) and the three enable inputs (E1’, E2’
and E3). The outputs of 74LS138 are active low. Two active-low (E1’, E2’) and one active-high (E3)
enable inputs reduce the need for external gates or inverters when expanding.

Schematic Symbol
Fig. 5.5. The schematic symbol, the logic diagram and the truth table of 74LS138 3x8 decoder IC.

74LS139 – 2x4 Decoder IC
Fig. 5.6 shows the schematic symbol, the logic diagram and the truth table of 74LS139 two
independent 2x4 decoder IC. As can be seen from the logic diagram, 74LS139 contains two fully
independent 2x4 decoders. Each 2x4 decoder of 74LS139 decodes one-of-four lines (O3’, O2’, O1’
and O0’), based upon the conditions at the two binary select inputs (A1 and A0) and the active low
enable input (E’). The outputs of each 2x4 decoder of 74LS139 are active low.
Schematic Symbol
Fig. 5.6. The schematic symbol, the logic diagram and the truth table of 74LS139 two 2x4 decoder IC.

EXPERIMENT NO: 5.1

EXPERIMENT NAME: EXAMINATION OF 74LS138 3x8 DECODER
Equipment:
74LS138 3x8 decoder 1 IC
Fig. 5.7.(a) 74LS138 3x8 decoder circuit (74LS138).
Fig. 5.7.(b) 74LS138 3x8 decoder – application circuit.

Procedure:
power.
2. Apply the combinations to the inputs of the circuit given in Table 5.1 and experimentally obtain the
output values and take note of the outputs in the Table.
INPUTS OUTPUTS
E3 E2’ E1’ A2 A1 A0 Q7’ Q6’ Q5’ Q4’ Q3’ Q2’ Q1’ Q0’
0 × × × × ×
× 1 × × × ×
× × 1 × × ×
1 0 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
×: Don’t care.
Table 5.1

EXPERIMENT NO: 5.2

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING A
3x8 DECODER
Equipment:
74LS138 3x8 decoder 1 IC
Fig. 5.8.(a) Implementation of a Boolean function by using a 3x8 decoder with active low
outputs (74LS138_2).
Note1: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Note2: To obtain an inverter function use a two-input-NAND gate.
Note3: To obtain a four-input-OR gate use two-input-OR gates.
Fig. 5.8.(b) Implementation of a Boolean function by using a 3x8 decoder with active low
outputs – application circuit.

Procedure:
1. PRELIMINARY WORK: Implement the function S(x,y,z,) = m(1,2,4,7) by using a 3x8 decoder
with active low outputs, inverters and a four-input-OR gate provided in Fig. 5.8.(a). By means of a
digital simulation software test and verify the operation of your implementation. Then, draw by hand
using pencils an application circuit provided in Fig. 5.8.(b) for the completed schematic diagram of
Fig. 5.8.(a). It is recommended that you use red colour for Vcc, black colour for GND and other
colours for other connections.
2. Construct the circuit [as designed by you in Fig. 5.8.(a) and] as drawn by you in Fig. 5.8.(b) and
apply the power.
values given in Table 5.2 and take note of the output values in the Table.
INPUTS OUTPUT
E3 E2’ E1’ x y z S
1 0 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
Table 5.2

EXPERIMENT NO: 5.3

EXPERIMENT NAME: EXAMINATION OF 74LS139 2x4 DECODER
Equipment:
74LS139 Dual independent 2x4 decoders 1 IC
Fig. 5.9.(a) 74LS139 2x4 decoder circuit (74LS139).
Fig. 5.9.(b) 74LS139 2x4 decoder – application circuit.

Procedure:
power.
INPUTS OUTPUTS
Ea’ A1a A0a Q3’ Q2’ Q1’ Q0’
1 × ×
0 0 0
0 0 1
0 1 0
0 1 1
×: Don’t care.
Table 5.3

EXPERIMENT NO: 5.4

DENEY ADI: CONSTRUCTION OF A 3x8 DECODER BY USING 2x4 DECODERS
Equipment:
74LS139 Dual independent 2x4 decoders 1 IC
Fig. 5.10.(a) Construction of a 3x8 decoder with active low outputs by using two 2x4 decoders
with active low outputs and an inverter (74LS139_2).
Fig. 5.10.(b) Construction of a 3x8 decoder with active low outputs by using two 2x4 decoders
with active low outputs and an inverter – application circuit.

Procedure:
1. PRELIMINARY WORK: Construct a 3x8 decoder with active low outputs by using two 2x4
decoders with active low outputs and an inverter provided in Fig. 5.10.(a). By means of a digital
simulation software test and verify the operation of your implementation. Then, draw by hand using
pencils an application circuit provided in Fig. 5.10.(b) for the completed schematic diagram of Fig.
5.10.(a). It is recommended that you use red colour for Vcc, black colour for GND and other colours
apply the power.
values given in Table 5.4 and take note of the output values in the Table.
INPUTS OUTPUTS
A2 A1 A0 Q7’ Q6’ Q5’ Q4’ Q3’ Q2’ Q1’ Q0’
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 5.4

ENCODERS
OBJECTIVES:
1- Investigating the encoder circuits,
3- Getting to know encoder circuits.
An encoder is a circuit that changes a set of signals into a code. As a standard combinational
component, an encoder is almost like the inverse of a decoder where it encodes a 2n-bit input data into
an n-bit code. As shown by the general form of an m-to-n encoder in Fig. 5.11, the encoder has m = 2n
input lines and n output lines. For active high inputs, the operation of the encoder is such that exactly
one of the input lines should have a 1, while the remaining input lines should have 0’s. The output is
the binary value of the index of the input line that has the 1. It is assumed that only one input line can
be a 1. Encoders are used to reduce the number of bits needed to represent some given data either in
data storage or in data transmission. Encoders are also used in a system with 2 n input devices, each of
which may need to request for service. One input line is connected to one input device. The input
device requesting for service will assert the input line that is connected to it. The corresponding n-bit
output value will indicate to the system which of the 2n devices is requesting for service. However, this
only works correctly if it is guaranteed that only one of the 2n devices will request for service at any
one time. If two or more devices request for service at the same time, then the output will be incorrect.
To resolve this problem, a priority is assigned to each of the input lines so that when multiple requests
are made, the encoder outputs the index value of the input line with the highest priority. This modified
encoder is known as a priority encoder. In this experiment, we are concerned with the priority
encoders. Although, not shown in Fig. 5.11, the priority encoder may have an enable line, E, for
enabling it. When the priority encoder is disabled with E set to 0 (for active-high enable input E), all
the output lines will have 0’s (for active-high outputs). When the priority encoder is enabled, then the
output lines issues the binary data representation of the highest priority input signal asserted (set to 1
for active-high).
d0
d1
y0
. y1 .
m input line s . . n o utput line s
. .
. yn-1
.
.
.
. d m-1
Fig. 5.11. The general form of an m-to-n encoder, where m = 2n.
As an example let us consider an 8x3 encoder. Table 5.5 shows the truth table of an 8x3 encoder, while
Fig. 5.12 shows the logic diagram of this encoder. In this encoder there are eight active-high inputs,
namely D0, D1, D2, D3, D4, D5, D6, and D7, and there are three active-high outputs, namely X, Y, and
Z. You should notice that the truth table is not a full table. Since we have eight inputs a full table
should have 28 or 256 entries. These other combinations correspond to either all zero inputs or inputs
with more than a single input set to 1. We say these other combinations are Not Allowed. If more than
a single input set to 1, then the encoder cannot produce correct outputs. As discussed above, this

problem is solved by means of priority encoders. Therefore we will concentrate on priority encoders.
Let us consider such an encoder IC: 74LS148.
INPUTS OUTPUTS
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Table 5.5. The truth table of an 8x3 encoder with active high inputs and active high outputs.
Fig. 5.12. The logic diagram of an 8x3 encoder with active high inputs and active high outputs.
74LS148 – 8x3 Priority Encoder IC
Fig. 5.13 shows the schematic symbol, the logic diagram and the function table of 74LS148 8x3
priority encoder IC. The 74LS148 provides priority encoding of the inputs to ensure that only the
highest order data line is encoded. The 74LS148 encodes eight data lines (I7’, I6’, I5’, I4’, I3’, I2’, I1’
and I0’) to three-line (A2’, A1’ and A0’) (4-2-1) binary (octal). All inputs and outputs of 74LS148 are
organized as active low. The input I7’ (respectively, I0’) has the highest (lowest) priority. In addition
to active low outputs A2 (MSB), A1 and A0 (LSB), there are active low GS’ (group select output) and
EO’ (enable output) outputs. If one of the inputs (I7’, I6’, I5’, I4’, I3’, I2’, I1’ or I0’) is low then GS’ =
0. This indicates that at least one of the inputs is active. If none of the inputs is active then EO’ = 0.
This indicates that none of the inputs is active. By providing cascading circuitry (Enable Input EI and
Enable Output EO) octal expansion is allowed without needing external circuitry.

Schematic Symbol Logic Diagram
Fig. 5.13. The schematic symbol, the logic diagram and the function table of
74LS148 8x3 priority encoder IC.

EXPERIMENT NO: 5.5

EXPERIMENT NAME: EXAMINATION OF 74LS148 8x3 PRIORITY ENCODER
Equipment:
74LS148 8x3 priority encoder 1 IC
Fig. 5.14.(a) 74LS148 8x3 priority encoder circuit (74LS148).
Fig. 5.14.(b) 74LS148 8x3 priority encoder – application circuit.

Procedure:
power.
INPUTS OUTPUTS
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO
1 × × × × × × × ×
0 1 1 1 1 1 1 1 1
0 × × × × × × × 0
0 × × × × × × 0 1
0 × × × × × 0 1 1
0 × × × × 0 1 1 1
0 × × × 0 1 1 1 1
0 × × 0 1 1 1 1 1
0 × 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
×: Don’t care.
Table 5.6

EXPERIMENT 6

MULTIPLEXERS, DEMULTIPLEXERS
EQUIPMENT:

74LS139 Dual independent 1x4 demultiplexer / 2x4 decoder 1
74LS151 8x1 multiplexer 1
74HC237 1x8 demultiplexer / 3x8 decoder 1

PRELIMINARY WORK:
1 Fig. 6.5.(a) 74LS151 8x1 multiplexer circuit (74LS151).
2 Fig. 6.11.(a) 74LS139 1x4 demultiplexer circuit with active-low input and active low outputs
(74LS139_1_4_dmux).
3 Fig. 6.12.(a) Construction of a 1x8 demultiplexer with active-low input and active low outputs
by using a 74LS139 IC (74LS139_1_8_dmux).
4 Fig. 6.13.(a) 74HC237 1x8 demultiplexer circuit with active-low or active-high input and
active high outputs.
5 Fig. 6.16.(a) Digital data transfer circuit by means of 74LS151 multiplexer and 74HC237
demultiplexer combination.
connections.
5. Implement the function F(A,B,C)=m(1,3,5,6) by using the 74LS151 8x1 multiplexer provided in
Fig. 6.6.(a). By means of a digital simulation software test and verify the operation of your
implementation. Then, you are obliged to draw by hand using pencils an application circuit provided in
Fig. 6.6.(b) for the completed schematic diagram of Fig. 6.6.(a). It is recommended that you use red
colour for Vcc, black colour for GND and other colours for other connections.
6. Implement the function F(A,B,C,D)=m(0,1,5,7,9,10,11,15) by using the 74LS151 8x1 multiplexer

provided in Fig. 6.7.(a). By means of a digital simulation software test and verify the operation of your

MULTIPLEXERS
OBJECTIVES:
1- Investigating the multiplexer (MUX) circuits,
3- Getting to know multiplexer integrated circuits (ICs).
As a standard combinational component, the multiplexer, abbreviated MUX, allows the selection of
one input signal among n signals, where n > 1, and is a power of two. Select lines connected to the
multiplexer determine which input signal is selected and passed to the output of the multiplexer. As
can be seen from Fig. 6.1, in general, an n-to-1 multiplexer has n data input lines, m select lines where
m = log2n, i.e. 2m = n, and one output line. As shown in Fig. 6.1, in addition to the other inputs, the
multiplexer has an enable line, E, for enabling it. When the multiplexer is disabled with E set to 0 (for
active-high enable input E), no input signal is selected and passed to the output. When the multiplexer
is enabled with E set to 1 (for active-high enable input E), an input signal is selected and passed to the
output based on the logic values applied select inputs.
Fig. 6.1. The general form of an n-to-1 multiplexer, where n = 2m.
In general, multiplexers are produced in integrated circuits as 2x1, 4x1, 8x1 and 16x1 multiplexers. In
the case of a 2-to-1 (2x1) multiplexer, a logic value of 0 applied to the select input s0 would connect d0
to the output y, while a logic value of 1 applied to the select input s0 would connect d1 to the output y.
In other words, the binary value expressed on the selector pins determines the selected input pin. In
larger multiplexers, the number of selector pins is equal to [log2(n)] where n is the number of inputs.
Therefore for a 4x1 (respectively 8x1, 16x1) multiplexer the number of select inputs is 2 (respectively
3, 4).
Fig. 6.2 shows the schematic symbol, the logic diagram and the truth table of a 41 MUX with active
high enable (E) input. In this multiplexer, the active-high enable input E, select inputs S1, S0, input
signals I0, I1, I2 and I3, and the output Y are all Boolean variables. When this multiplexer is disabled
with E set to 0, no input signal is selected and passed to the output. When this multiplexer is enabled
with E set to 1: if S1S0 = 00, (respectively, 01, 10, 11), then the input signal I0 (respectively, I1, I2, I3) is
selected and passed to the output “Y”.

Schematic Symbol Logic Diagram Truth Table
E S1 S0 Y
0 × × 0
1 0 0 I0
1 0 1 I1
1 1 0 I2
1 1 1 I3
×: Don’t care.
Fig. 6.2. The schematic symbol, the logic diagram and the truth table of
a 41 MUX with active high enable (E) input.
Multiplexers are also called as data selectors. When the data to be selected have more than one bit we
can construct a multiplexer to select these data. For example if we have two-four bits of data A (A4 A3
A2 A1) and B (B4 B3 B2 B1) to be selected then we can use a multiplexer as shown in Fig. 6.3. This
multiplexer is called a quad 2x1 multiplexer with active low enable input (E). When this multiplexer is
enabled (i.e., when E = 0) if S = 0 then the output Y(Y4 Y3 Y2 Y1) = A (A4 A3 A2 A1) and if S = 1 then
the output Y(Y4 Y3 Y2 Y1) = B (B4 B3 B2 B1).
Fig. 6.3. A quad 2x1 multiplexer with active low enable input(E).
Fig. 6.4 shows the schematic symbol, the logic diagram and the truth table of the 74LS151 8x1 MUX.
In this multiplexer, the active-low enable input E’, select inputs S2, S1, S0, input signals “I0”, “I1”, “I2”,
“I3”, “I4”, “I5”, “I6”, and “I7”, and the output Y (and its complement Y’) are all Boolean variables.

Schematic Symbol
Fig. 6.4. The schematic symbol, the logic diagram and the truth table of 74LS151 8x1 multiplexer.

EXPERIMENT NO: 6.1

EXPERIMENT NAME: EXAMINATION OF 8 x 1 MULTIPLEXER
Equipment:
74LS151 8x1 multiplexer 1 IC
Fig. 6.5.(a) 74LS151 8x1 multiplexer circuit (74LS151).
Fig. 6.5.(b) 74LS151 8x1 multiplexer – application circuit.

Procedure:
power.
output values and take note of the Y and Y’ outputs in the Table.
SELECT
DATA INPUTS OUTPUTS
INPUTS E’
S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Y Y’
× × × 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 0 1 1 0 I0 I0’
0 0 0 1 0 1 1 1 0 1 1 0 I0 I0’
0 0 1 0 1 0 1 0 1 0 1 0 I1 I1’
0 0 1 0 0 0 1 0 1 0 1 0 I1 I1’
0 1 0 0 0 1 0 0 0 0 0 0 I2 I2’
0 1 0 0 0 0 0 0 0 0 0 0 I2 I2’
0 1 1 0 0 1 0 0 0 1 1 0 I3 I3’
0 1 1 0 0 1 1 0 0 1 1 0 I3 I3’
1 0 0 0 1 1 1 1 1 1 1 0 I4 I4’
1 0 0 0 1 1 1 0 1 1 1 0 I4 I4’
1 0 1 1 1 1 0 1 1 1 0 0 I5 I5’
1 0 1 1 1 1 0 1 0 1 0 0 I5 I5’
1 1 0 1 1 0 0 1 1 1 0 0 I6 I6’
1 1 0 1 1 0 0 1 1 0 0 0 I6 I6’
1 1 1 1 0 1 0 1 0 1 0 0 I7 I7’
1 1 1 1 0 1 0 1 0 1 1 0 I7 I7’
×: Don’t care.
Table 6.1.

EXPERIMENT NO: 6.2

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING AN
8x1 MULTIPLEXER 1
Equipment:
Fig. 6.6.(a) Implementation of a Boolean function by using a 74LS151 8x1 multiplexer 1

(74LS151_1).
Fig. 6.6.(b) Implementation of a Boolean function by using a 74LS151 8x1 multiplexer 1 –

Procedure:
1. PRELIMINARY WORK: Implement the function F(A,B,C)=m(1,3,5,6) by using a 74LS151 8x1

multiplexer provided in Fig. 6.6.(a). By means of a digital simulation software test and verify the
operation of your implementation. Then, draw by hand using pencils an application circuit provided in
apply the power.
values given in Table 6.2 and take note of the output values F and F’ in the Table.
SELECT INPUTS INPUTS OUTPUTS

S2 S1 S0
I0 I1 I2 I3 I4 I5 I6 I7 E’ F F’
(A) (B) (C)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Table 6.2.

EXPERIMENT NO: 6.3

EXPERIMENT NAME: IMPLEMENTATION OF A BOOLEAN FUNCTION BY USING AN
8x1 MULTIPLEXER 2
Equipment:
Fig. 6.7.(a) Implementation of a Boolean function by using a 74LS151 8x1 multiplexer 2

(74LS151_2).
Fig. 6.7.(b) Implementation of a Boolean function by using a 74LS151 8x1 multiplexer 2 –

Procedure:
1. PRELIMINARY WORK: Implement the function F(A,B,C,D)=m(0,1,5,7,9,10,11,15) by using a

74LS151 8x1 multiplexer provided in Fig. 6.7.(a). By means of a digital simulation software test and
verify the operation of your implementation. Then, draw by hand using pencils an application circuit
provided in Fig. 6.7.(b) for the completed schematic diagram of Fig. 6.7.(a). It is recommended that
you use red colour for Vcc, black colour for GND and other colours for other connections.
I0 I1 I2 I3 I4 I5 I6 I7
A’
A
apply the power.
values given in Table 6.3 and take note of the output values F and F’ in the Table.
INPUTS OUTPUTS
B C D
A E’ F F’
(S2) (S1) (S0)
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Table 6.3.

DEMULTIPLEXERS
OBJECTIVES:
1- Investigating the demultiplexer (DMUX) circuits,
3- Getting to know 74HC237 1x8 demultiplexer IC.
A demultiplexer, abbreviated DMUX, is used when a circuit is to send a signal to one of many devices.
This description sounds similar to the description given for a decoder, but a decoder is used to select
among many devices while a demultiplexer is used to send a signal among many devices. However,
any decoder having an enable line can function as a demultiplexer. If the enable line of a decoder is
used as a data input, then the data can be routed to any one of the outputs and thus in that case the
decoder can be used as a demultiplexer. As the name infers, a demultiplexer performs the opposite
function to that of a multiplexer. A single input signal can be connected to any one of the output lines
provided by the choice of an appropriate select signal. The general form of a 1-to-n demultiplexer can
be seen from Fig. 6.8. If there are “m” select inputs then the number of output lines to which the data
can be routed is n = 2m. As can be seen from Fig. 6.8, in addition to the other inputs, the demultiplexer
may have an enable line, E, for enabling it. The demultiplexer is enabled with E set to 1 (for active-
high enable input E). When the demultiplexer is disabled with E set to 0 (for active-high enable input
E), no output line is selected and therefore the input signal is not passed to any output line.
Fig. 6.8. The general form of a 1-to-n demultiplexer, where n = 2m.
The schematic symbol, the logic diagram and the truth table of a 1×4 demultiplexer are provided in
Fig. 6.9. When the input i is considered as an active high enable input this circuit can be used as a 2x4
decoder. As there are 4 output lines for a 1x4 DMUX, there are 2 select inputs (when 2n = 4, n = 2).
Likewise as there are 8 output lines for a 1x8 DMUX, there are 3 select inputs (when 2n = 8, n = 3).

Schematic Symbol Logic Diagram Truth Table
INPUTS OUTPUTS
A1 A0 Y0 Y1 Y2 Y3
0 0 i 0 0 0
0 1 0 i 0 0
1 0 0 0 i 0
1 1 0 0 0 i
Fig. 6.9. The schematic symbol, the logic diagram and the truth table of a 1×4 demultiplexer.
74HC237 – 3x8 decoder/1x8 demultiplexer IC
Fig. 6.10 shows the schematic symbol, the logic diagram and the truth table of the 74HC237 IC. The
74HC237 can be used as a 3-to-8 line decoder or a 1-to-8 demultiplexer with latches at the three
address inputs (A2, A1, A0). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-
bit storage latch. When the latch is enabled (LE’ = LOW), the 74HC237 acts as a 3-to-8 active LOW
decoder. When the latch enable (LE’) goes from LOW-to-HIGH, the last data present at the inputs
before this transition, is stored in the latches. Further address changes are ignored as long as LE’
remains HIGH. The output enable inputs (E1’ and E0) controls the state of the outputs independent of
the address inputs or latch operation. All outputs are HIGH unless E1’ is LOW and E0 is HIGH. The
74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems. Two output enable inputs (E1’ and E0) are
provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is
accomplished by using the A2, A1, A0 address inputs to select the desired output and using one of the
other Output Enable inputs as the data input while holding the other output enable input in its active
state. This is to say that when using the 74HC237 as a 1-to-8 demultiplexer, address inputs A2, A1, A0
are used to select the desired output Y7, Y6, Y5, Y4, Y3, Y2, Y1, or Y0. In this case if we would like
to use the active high input signal then E1’ is set to 0 and E0 is used as the active high input. Likewise,
if we would like to use the active low input signal then E0 is set to 1 and E1’ is used as the active low
input.

Schematic Symbol
Fig. 6.10. The schematic symbol, the logic diagram and

the truth table of the 74HC237 1x8 demultiplexer IC.

EXPERIMENT NO: 6.4

EXPERIMENT NAME: EXAMINATION OF 74LS139 1x4 DEMULTIPLEXER WITH
ACTIVE-LOW INPUT AND ACTIVE-LOW OUTPUTS
Equipment:
74LS139 Dual independent 1x4 demultiplexer / 2x4 decoder 1 IC
Fig. 6.11.(a) 74LS139 1x4 demultiplexer circuit with active-low input and active low outputs
(74LS139_1_4_dmux).
Fig. 6.11.(b) 74LS139 1x4 demultiplexer with active-low input and active low outputs –

Procedure:
power.
INPUTS OUTPUTS
A1 A0 i Y3 Y2 Y1 Y0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 6.4

EXPERIMENT NO: 6.5

EXPERIMENT NAME: CONSTRUCTION OF A 1x8 DEMULTIPLEXER WITH ACTIVE-
LOW INPUT AND ACTIVE-LOW OUTPUTS BY USING A 74LS139
Equipment:
74LS139 Dual independent 1x4 demultiplexer / 2x4 decoder 1 IC
Fig. 6.12.(a) Construction of a 1x8 demultiplexer with active-low input and active low outputs
by using a 74LS139 IC (74LS139_1_8_dmux).
Fig. 6.12.(b) Construction of a 1x8 demultiplexer with active-low input and active low outputs
by using a 74LS139 IC – application circuit.

Procedure:
power.
INPUTS OUTPUTS
A2 A1 A0 i Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 6.5

EXPERIMENT NO: 6.6

EXPERIMENT NAME: EXAMINATION OF 74HC237 1 x 8 DEMULTIPLEXER
Equipment:
74HC237 1x8 demultiplexer / 3x8 decoder 1 IC
Fig. 6.13.(a) 74HC237 1x8 demultiplexer circuit with active-low or

active-high input and active high outputs.
Fig. 6.13.(b) 74HC237 1x8 demultiplexer circuit with active-low or
active-high input and active-high outputs – application circuit.

Procedure:
power.
INPUTS OUTPUTS
A2 A1 A0 LE’ E1’ E0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 0 0 1
0 0 0 0 1 1
0 0 1 0 0 1
0 0 1 0 1 1
0 1 0 0 0 1
0 1 0 0 1 1
0 1 1 0 0 1
0 1 1 0 1 1
1 0 0 0 0 1
1 0 0 0 1 1
1 0 1 0 0 1
1 0 1 0 1 1
1 1 0 0 0 1
1 1 0 0 1 1
1 1 1 0 0 1
1 1 1 0 1 1
0 0 0 0 0 0
0 0 0 0 0 1
0 0 1 0 0 0
0 0 1 0 0 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 1 0 0 0
0 1 1 0 0 1
1 0 0 0 0 0
1 0 0 0 0 1
1 0 1 0 0 0
1 0 1 0 0 1
1 1 0 0 0 0
1 1 0 0 0 1
1 1 1 0 0 0
1 1 1 0 0 1
Table 6.6.

DIGITAL DATA TRANSFER BY USING A MUX-DMUX COMBINATION
OBJECTIVES:
1- Analyzing connection of the MUX-DMUX circuit used for digital data transfer,
2- Observing its operation.
Data transfer is a very important topic in electronics world. Different methods are used for this
operation. Mainly, data are transferred in two ways.
a- Wired systems
b- Wireless systems.
There are many types of wired systems. Most important ones are digital and analog systems. The same
variation is also valid for wireless systems. Today, digital systems are more popular. One method used
for data transfer through a single line (wired or wireless) is the “multiplexing” method. To explain this
method, let us consider the system that was used for analog telephone communication in the past. In
Fig. 6.14, how data are transferred through a single line by two synchronously operating analog
switches is depicted basically.
Fig. 6.14. Data transfer through a single line by two synchronously operating analog switches.
How five different transfers can be achieved through a single line is shown basically in Fig. 6.14. As
the switches operate synchronously, the same positions match each time, such as D1-D1 or D2-D2.
However this system has the following disadvantages: it is mechanical, prone to failure, slow and its
data transfer capacity is low. To overcome these problems, digital systems are used. The principal
structure of which is shown in Fig. 6.15.
Fig. 6.15. The connection of the MUX-DMUX circuit used for digital data transfer.

DENEY NO: 6.7

DENEY ADI: EXAMINATION OF DIGITAL DATA TRANSFER BY USING A MUX-DMUX
COMBINATION
Equipment:
74HC237 1x8 demultiplexer / 3x8 decoder 1 IC
Fig. 6.16.(a) Digital data transfer circuit by means of 74LS151 multiplexer and 74HC237
demultiplexer combination.
Fig. 6.16.(b) Digital data transfer circuit by means of 74LS151 multiplexer and 74HC237
demultiplexer combination – application circuit.

Procedure:
power.
NOTE: Don’t forget to connect the pins S2-S1-S0 and E’ as shown in Fig. 6.16.(a); so that the ICs
will operate synchronously.
74LS151 74HC237
SELECT INPUTS
MUX DATA INPUTS DEMUX DATA OUTPUTS
S2 S1 S0 E I7 I6 I5 I4 I3 I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
× × × 1 × × × × × × × ×
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0
1 1 1 0 1 0 0 0 0 0 0 0
×: Don’t care.
Table 6.7

EXPERIMENT 7
SEQUENTIAL LOGIC CIRCUITS:

SR FLIP-FLOP, JK FLIP-FLOP
D FLIP-FLOP, T FLIP-FLOP
EQUIPMENT:
2- A two-channel oscilloscope.

74LS00 Quad 2-input NAND gates 1
74LS02 Quad 2-input NOR gates 1
74LS74 Dual rising edge triggered D flip-flops 1
74LS76 Dual master-slave J-K flip-flops 1
4001 Quad 2-input NOR gates 1
4011 Quad 2-input NAND gates 1

PRELIMINARY WORK:
1 Fig. 7.4.(a) Active-high input SR flip-flop circuit (SR_latch_nor).
2 Fig. 7.5.(a) Active-low input SR flip-flop circuit (SR_latch_nand).
3 Fig. 7.6.(a) Gated SR flip-flop circuit (gated_SR_latch).
4 Fig. 7.10.(a) The master-slave JK flip-flop circuit with active-low asynchronous inputs (JK_FF).
5 Fig. 7.18.(a) Rising edge triggered D flip-flop circuit (D_FF).
6 Fig. 7.19.(a) Converting a JK flip-flop into a D flip-flop (D_FF).
7 Fig. 7.22.(a) Converting a JK flip-flop into a T flip-flop (T_FF).
8 Fig. 7.23.(a) Observing the operation of the T flip-flop by using an oscilloscope (T_FF).
connections.

SR FLIP-FLOP (LATCH)
OBJECTIVES:
1- Getting to know RS flip-flop and learning its operations,
2- Obtaining its truth table,
3- Forming SR flip-flop by using 74LS02 and CMOS 4011 ICs,
4- Getting to know gated SR flip-flop and learning its operations.
In the previous experiments, combinational logic circuits such as decoders, encoders, multiplexers and
demultiplexers were considered. On the other hand, in a sequential logic circuit; in addition to logic
gates there are also memory elements. Flip-flops are basic memory elements used in a sequential logic
circuit. When the memory elements are removed from a sequential logic circuit the remaining part of
the circuit is just the combinational part. In the experiment 7, flip-flops are considered. One of the
basic devices storing and processing the digital data (1s and 0s) is the flip-flop. There are basically
four types of flip-flops:
1- SR flip-flop (latch)
2- D flip-flop
3- JK flip-flop
4- T flip-flop
First of all let us consider SR (Set-Reset) flip-flops. There are two types of SR flip-flops: 1. Active-
high input SR flip-flop (FF), 2. Active-low input SR flip-flop (FF). Note that an SR flip-flop is also
called an SR latch. An active-high input SR FF is formed with two cross-coupled NOR gates, as
shown in Fig. 7.1. Inputs are S (set) and R (reset), while the output is Q and its complement is Q’. The
truth table of the active-high input SR FF is provided in Table 7.1. The following explains its
operation:
If S = 0 and R = 0, then SR FF preserves its previous output.

If S = 0 and R = 1, then SR FF is reset so Q = 0.
If S = 1 and R = 0, then SR FF is set so Q = 1.
If S = 1 and R = 1, then both Q and Q’ are 0. This is called invalid operation for the active-high input
SR FF.
INPUTS OUTPUTS
S R Q Q’
Q0 Q0’
0 0
No change
0 1 0 1
1 0 1 0
0 0
1 1
Invalid
Fig. 7.1. Active-high input SR flip-flop. Table 7.1. The truth table of the active-
high input SR flip-flop.

An active-low input SR FF is formed with two cross-coupled NAND gates, as shown in Fig. 7.2.
Inputs are S’ (set) and R’ (reset), while the output is Q and its complement is Q’. The truth table of the
active-low input SR FF is provided in Table 7.2. The following explains its operation:
If S = 0 and R = 0, then then both Q and Q’ are 1. This is called invalid operation for the active-low
input SR FF.
If S = 0 and R = 1, then SR FF is set so Q = 1.
If S = 1 and R = 0, then SR FF is reset so Q = 0.
If S = 1 and R = 1, SR FF preserves its previous output.
INPUTS OUTPUTS
S’ R’ Q Q’
1 1
0 0
Invalid
0 1 1 0
1 0 0 1
Q0 Q0’
1 1
No change
Fig. 7.2. Active-low input SR flip-flop. Table 7.2. The truth table of the
active-low input SR flip-flop.
As can be seen from the previous explanations there are differences between an active-high input SR
FF and an active-low input SR FF. These SR flip-flops work in an asynchronous manner. This means
that when the logic values applied to S and R inputs are changed, the outputs will be changed
accordingly. It is possible to obtain an SR FF working a synchronous manner. This is achieved by
introducing an additional control input to an SR FF. Such an SR FF is shown in Fig. 7.3. The truth
table of this flip-flop is provided in Table 7.3. This flip-flop is called gated SR flip-flop, which
requires an enable (or clock) input. The S and R inputs control the state to which the FF will go when a
high (logic 1) level is applied to the CLK input. The FF will not change until CLK = 1; but as long as it
remains high, the output is controlled by the state of the S and R inputs. In this circuit, the invalid state
occurs when both S and R are simultaneously high.
INPUTS OUTPUTS
CLK S R Q Q’
0 × × No change
Q0 Q0’
1 0 0
No change
1 0 1 0 1
1 1 0 1 0
1 1
1 1 1
Invalid
×: Don’t care.
Fig. 7.3. Gated SR flip-flop. Table 7.3. The truth table of the gated SR flip-
flop.

EXPERIMENT NO: 7.1

EXPERIMENT NAME: EXAMINATION OF ACTIVE-HIGH INPUT SR FLIP-FLOP
Equipment:

74LS02 Quad 2-input NOR gates 1 IC
4001 Quad 2-input NOR gates 1 IC
Fig. 7.4.(a) Active-high input SR flip-flop circuit (SR_latch_nor).
Fig. 7.4.(b) Active-high input SR flip-flop – application circuit.

Procedure:
power.
2. Apply the combinations to the inputs of the circuit given in Table 7.4 (follow the given steps) and
experimentally obtain the output values and take note of the Q and Q’ outputs in the Table.
INPUTS OUTPUTS
STEPS
S R Q Q’
1 0 1
2 0 0
3 1 0
4 0 0
5 1 1
Table 7.4
Note: Repeat this experiment by using CMOS 4001 quad two-input NOR gates and compare the
results.
CMOS 4001 quad two-input NOR gates.

EXPERIMENT NO: 7.2

EXPERIMENT NAME: EXAMINATION OF ACTIVE-LOW INPUT SR FLIP-FLOP
Equipment:

74LS00 Quad 2-input NAND gates 1 IC
4011 Quad 2-input NAND gates 1 IC
Fig. 7.5.(a) Active-low input SR flip-flop circuit (SR_latch_nand).
Fig. 7.5.(b) Active-low input SR flip-flop – application circuit.

Procedure:
power.
INPUTS OUTPUTS
STEPS
S’ R’ Q Q’
1 0 1
2 1 1
3 1 0
4 1 1
5 0 0
Table 7.5
NOTE: Repeat this experiment by using CMOS 4011 quad two-input NAND gates and compare
the results.
CMOS 4011 quad two-input NAND gates.

EXPERIMENT NO: 7.3

EXPERIMENT NAME: GATED SR FLIP-FLOP
Equipment:

Fig. 7.6.(a) Gated SR flip-flop circuit (gated_SR_latch).
Fig. 7.6.(b) Gated SR flip-flop – application circuit.

Procedure:
power.
INPUTS OUTPUTS
STEPS
S R CP Q Q’
1 1 0 1
2 0 0 1
3 0 1 1
4 0 0 1
5 1 1 1
6 1 0 1
7 1 0 0
8 0 0 0
9 0 1 0
10 0 0 0
11 1 1 0
Table 7.6

JK FLIP-FLOP
OBJECTIVES:
1- Getting to know JK flip-flop, verifying its logic operation and obtaining its truth,
2- Getting familiar with TTL 74LS76 JK flip-flop.
JK flip-flop is versatile and is a widely used type of flip-flop. The functioning of the JK FF is identical
to that of the SR FF in the SET, RESET, and No change conditions of operation. The difference is that
the JK FF has no invalid state as does the SR FF. Inputs J and K behave like inputs S and R to set and
clear (reset) the flip-flop, respectively. The input marked J is for set and the input marked K is for
reset. When both inputs J and K are equal to 1, the flip-flop switches to its complement state, that is, if
Q = 1, it switches to Q = 0, and vice versa. There are different types of JK FFs. Flip-flops can be
classified in two groups based on how they are triggered: edge-triggered and level-triggered. The first
group can be divided into two sub-groups as rising edge (or positive edge) and falling edge (or
negative edge) triggered flip-flops. This fact is made visible with the symbol > in their schematic
symbol. The rising edge (or positive edge) trigger is symbolized by  or . The rising edge triggered
flip-flops change their states when the state of clock pulse CLK is changed from OFF to ON. Likewise
falling edge trigger is symbolized by  or . The falling edge triggered flip-flops change their states
when the state of clock pulse CLK is changed from ON to OFF. The second group can be divided into
two sub-groups as logic 1 ( ) level trigger and logic 0 ( __ ) level trigger. The logic 1 level triggered
flip-flops change their states when the clock pulse CLK = 1. Likewise, the logic 0 level triggered flip-
flops change their states when the clock pulse CLK = 0. Fig. 7.7 shows the logic diagram and the
symbol of the rising edge triggered JK flip-flop. The truth table of the rising edge triggered JK flip-
flop is provided in Table 7.7.
Fig. 7.7. The logic diagram and the symbol of the rising edge triggered JK flip-flop (JK_flip_flop_r).

INPUTS OUTPUTS
CLK J K Q Q’
0 × × No change
1 × × No change
 × × No change
Q0 Q0’
 0 0
No change
 0 1 0 1
 1 0 1 0
Q0’ Q0
 1 1
Toggle
×: Don’t care.
Table 7.7. The truth table of the rising edge triggered JK flip-flop.
It can be seen that J and K inputs are effective on the rising edges of the CLK input. This means that J
and K inputs are synchronous with the CLK input. Therefore these inputs are called synchronous
inputs because data on these inputs are transferred to the flip-flop’s output on the triggering edge of the
clock pulse; that is, the data are transferred synchronously with the clock. Most integrated circuit flip-
flops also have asynchronous inputs. These are inputs that affect the state of the flip-flop independent
of the clock. They are normally labeled PRESET (or PRE or S) and CLEAR (CLR or R). An active
level (high or low) on the PRESET input will set the flip-flop, and an active level (high or low) on the
CLEAR input will reset the flip-flop. Fig. 7.8 shows the falling edge triggered JK flip-flop with active-
low asynchronous inputs. The truth table of this flip-flop is provided in Table 7.8.
In this flip-flop: when S’=0 and R’=1 the output is set (Q=1).When S’=1 and R’=0 the output is reset
(Q=0). When S’=0 and R’=0 both the output and its complement are set (Q=1 and Q’=1). This is an
invalid operation. When S’=1 and R’=1, both asynchronous inputs are not active. In this case, when
the state of the clock signal CLK is changed from ON to OFF (): if JK = 00, then no state change is
issued; if JK = 01, then Q is reset; if JK = 10, then Q is set; and finally if JK = 11, then Q is toggled. In
the toggle mode, the frequency of the input signal is divided by two. Due to this feature JK flip-flops
are used to obtain counters.
INPUTS OUTPUTS
S’ R’ CLK J K Q Q’
0 1 × × × 1 0
1 0 × × × 0 1
1 1
0 0 × × ×
Invalid
1 1 0 × × No change
1 1 1 × × No change
1 1  × × No change
Q0 Q0’
1 1  0 0
No change
1 1  0 1 0 1
1 1  1 0 1 0
Q0’ Q0
1 1  1 1
Toggle
×: Don’t care.
Fig. 7.8. The falling edge triggered JK flip- Table 7.8. The truth table of the falling edge
flop with active-low asynchronous inputs. triggered JK flip-flop with active-low asynchronous
inputs.

In addition to rising edge, falling edge, logic 1 level and logic 0 level triggered JK flip-flops, there are
also master-slave JK flip-flops. They can be positive pulse triggered or negative pulse triggered
master-slave JK flip-flops. As an example, Fig. 7.9 shows the schematic symbol and the function table
of 74LS76 dual positive pulse triggered master-slave JK flip-flops. This device contains two
independent positive pulse (  ) triggered J-K flip-flops with complementary outputs. The J and K
data are processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is
isolated from the master. On the positive transition of the clock (  ), the data from the J and K inputs
are transferred to the master. While the clock is HIGH ( ), the J and K inputs are disabled. On the
negative transition of the clock (  ), the data from the master are transferred to the slave. The logic
state of J and K inputs must not be allowed to change while the clock is HIGH ( ). The data are
transferred to the outputs on the falling edge of the clock pulse. A LOW logic level on the preset or
clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Schematic Symbol
Fig. 7.9. The schematic symbol and the function table of 74LS76 dual master-slave JK flip-flops.

EXPERIMENT NO: 7.4

EXPERIMENT NAME: EXAMINATION OF MASTER-SLAVE JK FLIP-FLOP
Equipment:
74LS76 Dual master-slave J-K flip-flops 1 IC
Fig. 7.10.(a) The master-slave JK flip-flop circuit with active-low asynchronous inputs (JK_FF).
Fig. 7.10.(b) The master-slave JK flip-flop circuit with active-low asynchronous inputs – application
circuit.

Procedure:
power.
2. Apply first the following S, R, J and K and then the CLK to the inputs of the circuit, given in Table
7.9 (follow the given inputs from top to down) and experimentally obtain the output values and take
note of the Q and Q’ outputs in the Table.
ASYNCHRONOUS SYNCHRONOUS
OUTPUTS
INPUTS INPUTS
COMMENT
PRESET CLEAR
J K CLK Q Q’
(S’) (R’)
1 0 × × ×
0 1 × × ×
0 0 × × ×
1 1 0 1 
1 1 0 0 
1 1 1 0 
1 1 0 0 
1 1 1 1 
×: Don’t care.
Note: When the CLK () input is being applied do not change the values of J and K inputs.
Table 7.9.

D FLIP-FLOP
OBJECTIVES:
1- Getting to know D flip-flop, verifying its logic operation and obtaining its truth table,
2- Forming a D flip-flop by using a JK FF and an INVERTER.
The D ﬂip-ﬂop is widely used. It is also known as a data flip-flop. The D flip-flop captures the value of
the D input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured
value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be
viewed as a memory cell. Fig. 7.11 shows the logic 1 level triggered D flip-flop (LATCH). The truth
table of this flip-flop is provided in Table 7.10. The truth table shows that when the clock input is 0,
the D input has no effect on the output. When the clock input is high, the output equals D. A D type
flip-flop can be obtained easily by using an SR flip-flop and an inverter. Fig. 7.12 shows how to obtain
a logic 1 level triggered D flip-flop (LATCH) by using a gated SR flip-flop.
INPUTS OUTPUTS
CLK D Q Q’
Q0 Q0’
0 ×
No change
1 1 1 0
1 0 0 1
×: Don’t care.
Fig. 7.11. Logic 1 level triggered D flip-flop Table 7.10. The truth table of the logic 1 level
(LATCH). triggered D flip-flop (LATCH).
Fig. 7.12. Logic 1 level triggered D flip-flop (LATCH) obtained by using a gated SR flip-flop.
D flip-flops can also be classified as rising edge (  ), falling edge (  ), logic 1 level ( ) and logic 0
level ( __ ) triggered D flip-flops. In general level triggered D flip-flops are called as LATCH. Edge
triggered D flip-flops are made visible with the symbol > in their schematic symbol. As an example,
Fig. 7.13 shows the falling edge triggered D flip-flop. The truth table of this flip-flop is provided in
Table 7.11.
CLK D Q Q’
1 × No change
0 × No change
Q0 Q0’
 ×
No change
 1 1 0
 0 0 1
×: Don’t care.
Fig. 7.13. The falling edge triggered D flip-flop. Table 7.11. The truth table of the falling edge
triggered D flip-flop.

An example timing diagram for a rising edge triggered D flip-flop is given in Fig. 7.14. Here, output Q
holds its current state until the rising edge of the CLK input signal. When the state of clock input
signal CLK is changed from OFF to ON (), the output Q is loaded with the state of the input D.
Fig. 7.14. An example timing diagram for a rising edge triggered D flip-flop.
An example timing diagram for a logic 1 level triggered D flip-flop is given in Fig. 7.15. As can be
seen from the figure when the CLK input signal is in logic 1 level, the output Q follows and stores the
state of the input D. When the state of the clock input signal CLK is changed from ON to OFF (), the
output Q is latched with the latest state of the input D and this value will be kept until the next logic 1
level of the CLK input signal.
Fig. 7.15. An example timing diagram for a logic 1 level triggered D flip-flop.
The input D is synchronous with the CLK input. As explained for JK flip-flops, it is possible to
introduce asynchronous inputs PRESET (or PRE or S) and CLEAR (CLR or R) for D type flip-flops.
They can be active high or low. An active level (high or low) on the PRESET input will set the flip-
flop, and an active level (high or low) on the CLEAR input will reset the flip-flop. Fig. 7.16 shows the
rising edge triggered D flip-flop with active-low asynchronous inputs. The truth table of this flip-flop
is provided in Table 7.12.
In this flip-flop: when S’=0 and R’=1 the output is set (Q=1). When S’=1 and R’=0 the output is reset
(Q=0). When S’=0 and R’=0 both the output and its complement are set (Q=1 and Q’=1). This is an
invalid operation. When S’=1 and R’=1, both asynchronous inputs are not active. In this case, when
the state of clock signal CLK is changed from OFF to ON (), the output Q is loaded with the state of
the input D.

INPUTS OUTPUTS
S’ R’ CLK D Q Q’
0 1 × × 1 0
1 0 × × 0 1
0 0 × × 1 1
1 1 0 × No change
1 1 1 × No change
× Q0 Q0’
1 1 
No change
1 1  0 0 1
1 1  1 1 0
×: Don’t care.
Fig. 7.16. The rising edge triggered D flip- Table 7.12. The truth table of the rising edge
flop with active-low asynchronous inputs. triggered D flip-flop with active-low asynchronous
inputs.
The schematic symbol and the function table of 74LS74 dual rising edge triggered D flip-flops are
shown in Fig. 7.17. This device contains two independent rising-edge-triggered D flip-flops with
complementary outputs. The information on the D input is accepted by the flip-flops on the positive
going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on the D input may be changed while the clock
is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not
violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Schematic Symbol
Fig. 7.17. The schematic symbol and the function table of 74LS74 dual rising edge triggered D flip-
flops.

EXPERIMENT NO: 7.5

EXPERIMENT NAME: EXAMINATION OF D FLIP-FLOP
Equipment:
74LS74 Dual rising edge triggered D flip-flops 1 IC
Fig. 7.18.(a) Rising edge triggered D flip-flop circuit (D_FF).
Fig. 7.18.(b) Rising edge triggered D flip-flop – application circuit.

Procedure:
power.
2. Apply first the following S, R, D and then the CLK to the inputs of the circuit, given in Table 7.13
(follow the given inputs from top to down) and experimentally obtain the output values and take note
of the Q and Q’ outputs in the Table.
OUTPUTS
INPUTS INPUTS
COMMENT
PRESET CLEAR
D CLK Q Q’
(S’) (R’)
0 0 × ×
1 0 × ×
0 1 × ×
1 1 0 0
1 1 1 0
1 1 0 1
1 1 1 1
1 1 0 
1 1 1 
1 1 0 
1 1 1 
×: Don’t care.
Note : The input D must always be provided before the CLK input.
Table 7.13.

EXPERIMENT NO: 7.6

EXPERIMENT NAME: CONVERTING A JK FLIP-FLOP INTO A D FLIP-FLOP
Equipment:
Fig. 7.19.(a) Converting a JK flip-flop into a D flip-flop (D_FF).
Fig. 7.19.(b) Converting a JK flip-flop into a D flip-flop – application circuit.

Procedure:
power.
2. Apply first the following S, R, D and then the CLK to the inputs of the circuit, given in Table 7.14
OUTPUTS
INPUTS INPUTS
COMMENT
PRESET CLEAR
D CLK Q Q’
(S’) (R’)
0 0 × ×
0 1 × ×
1 0 × ×
1 1 0 
1 1 1 
×: Don’t care.
Note: The input D must always be provided before the CLK input.
When the CLK () input is being applied do not change the value of the input D.
Table 7.14.

T FLIP-FLOP
OBJECTIVES:
1- Getting to know T flip-flop,
2- Verifying its logic operation and obtaining its truth table.
The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is obtained from the JK
type if both inputs are tied together. Therefore T flip-flop does not have an invalid state. A T flip-flop
has two inputs (T and CLK) and two outputs (Q and its complement Q’). If the T input is high, the T
flip-flop changes state ("toggles") whenever it is triggered. If the T input is low, the flip-flop holds the
previous output value. As explained for JK and D flip-flops, T flip-flops can also be classified as rising
edge (  ), falling edge (  ), logic 1 level ( ) and logic 0 level ( __ ) triggered T flip-flops. It is also
possible to introduce asynchronous inputs PRESET (or PRE or S) and CLEAR (CLR or R) for T type
flip-flops. As an example, Fig. 7.20 shows the rising edge triggered T flip-flop. The truth table of this
flip-flop is given in Table 7.15. When the clock input signal CLK is ON (1), or OFF (0), or changes its
state from ON to OFF (), no state change is issued for the output Q and it holds its current state.
When the state of the clock input signal CLK is changed from OFF to ON (), if T = 0, then no state
change is issued for the output Q and it holds its current state. When the state of the clock input signal
CLK is changed from OFF to ON (), if T = 1, then the output Q is toggled.
CLK T Q Q’
1 × No change
0 × No change
 × No change
Q0 Q0’
 0
No change
Q0 ’ Q0
 1
Toggle
×: Don’t care.
Fig. 7.20. The rising edge triggered T flip-flop. Table 7.15. The truth table of the rising edge
triggered T flip-flop.

In Fig. 7.21 and in Table 7.16 the falling edge triggered T flip-flop with active-low asynchronous
inputs and its truth table are shown respectively. In this flip-flop: when S’=0 and R’=1 the output is set
(Q=1). When S’=1 and R’=0 the output is reset (Q=0). When S’=0 and R’=0 both the output and its
complement are set (Q=1 and Q’=1). This is an invalid operation. When S’=1 and R’=1, both
asynchronous inputs are not active. In this case, when the state of clock signal CLK is changed from
ON to OFF (), if T = 0, then no state change is issued for the output Q and it holds its current state; if
T = 1, then the output Q is toggled.
INPUTS OUTPUTS
S’ R’ CLK T Q Q’
0 1 × × 1 0
1 0 × × 0 1
0 0 × × 1 1
1 1 0 × No change
1 1 1 × No change
1 1  × No change
Q0 Q0’
1 1  0
No change
Q0’ Q0
1 1  1
Toggle
×: Don’t care.
Fig. 7.21. The falling edge triggered T flip- Table 7.16. The truth table of the falling edge
flop with active-low asynchronous inputs. triggered T flip-flop with active-low asynchronous
inputs.

EXPERIMENT NO: 7.7

EXPERIMENT NAME: EXAMINATION OF T FLIP-FLOP
Equipment:
3. A two-channel oscilloscope.
Fig. 7.22.(a) Converting a JK flip-flop into a T flip-flop (T_FF).
Fig. 7.22.(b) Converting a JK flip-flop into a T flip-flop – application circuit.

Procedure:
power.
2. Apply first the following S, R, T and then the CLK to the inputs of the circuit, given in Table 7.17
OUTPUTS
INPUTS INPUTS
COMMENT
PRESET CLEAR
T CLK Q Q’
(S’) (R’)
0 0 × ×
0 1 × ×
1 0 × ×
1 1 0 
1 1 1 
×: Don’t care.
Note: The input T must always be provided before the CLK input.
When the CLK () input is being applied do not change the value of the input T.
Table 7.17.
3. Turn the POWER ON/OFF switch into OFF position. Then, construct the circuit [as given in Fig.
7.23.(a) and] as drawn by you in Fig. 7.23.(b) and apply the power.
Fig. 7.23.(a) Observing the operation of the T flip-flop by using an oscilloscope (T_FF).

Note1: Do not forget to connect the Vcc pin to +5 V and the GND pin to ground (GND) connection.
Note2: To start the function generator turn on its ON/OFF switch.
Note3: In order to observe low frequency TTL signals produced by the function generator you must
connect the GND connection of the function generator and the GND connection of the power supply
by means of a connection wire.
Fig. 7.23.(b) Observing the operation of the T flip-flop by using an oscilloscope – application circuit.
4- Apply logic 1 to both Preset (S’) and Clear (R’) inputs.

3- Apply logic 1 to the T input.
4- Adjust the frequency of the CLK signal to approximately 500 Hz.
5- Connect the first channel of the oscilloscope to the CLK signal and the second channel of the
oscilloscope to the output Q of the flip-flop.
6- Observe the input and the output signals via the oscilloscope and draw their shapes in Fig. 7.24. Do
not forget to write down the periods and magnitudes of the signals you have observed.
Fig. 7.24.

EXPERIMENT 8
COUNTERS
EQUIPMENT:

74LS00 Quad 2-input NAND gates 1
74LS08 Quad 2-input AND gates 1
74LS76 Dual master-slave J-K flip-flops 2
74LS93 4 bit binary counter 1
4024 7 bit binary counter 1

PRELIMINARY WORK:
1 Fig. 8.5.(a). The 4 bit asynchronous binary up counter circuit (count_4bit_as_u).
2 Fig. 8.6.(a). MOD10 asynchronous up counter circuit (count_4bit_as_u_md10).
3 Fig. 8.7.(a). The 4 bit asynchronous binary down counter circuit (count_4bit_as_d).
4 Şekil. 8.9.(a). The 74LS93 4 bit asynchronous up counter circuit (74LS93).
5 Fig. 8.10.(a). Configuration of the 74LS93 as a decade counter (74LS93).
6 Fig. 8.12.(a). The 4024 7 bit asynchronous up counter circuit (4024).
7 Fig. 8.19.(a). The synchronous counter circuit to count in the count sequence of 0, 2, 4, 6, 1,
3, 5, 7, 0, 2, ... (count_s_02461357).
8 Fig. 8.20.(a). The 4 bit synchronous up counter circuit (count_s_mod16_7seg).
9 Fig. 8.21.(a). The BCD synchronous up counter circuit (count_s_dec_7seg).
connections.
5. Design MOD8 and MOD12 counters by using the 74LS93 counter ICs (page 8_19).

COUNTERS
OBJECTIVES:
1- Investigating the binary counters,
2- Observing their operation principles,
3- Getting to know the binary counter ICs 74LS93 and 4024.
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock signal. Counters are
the logic circuits that take specific state with the clock ticks applied to their inputs. They are widely
used in the digital electronics area. Some of those application areas are, Digital Clocks, Frequency
Counters, Decoders, Digital Alarms, Traffic Lights etc.
The base of the counters are logic circuits and the flip-flops. Generally counters are obtained with
cascade connection of flip-flops in a specific rule. With each clock tick the counter changes its state. A
counter composed of n flip-flops with no feedback may have 2n different states depending on the
number of clock ticks. For example, if 4 flip-flops are used in the counter structure, there will totally
be 24=16 different states. So, the counter can count from 0 to 15.
The total number of counts or stable states a counter can indicate is called MODULUS (MOD). For
instance, the modulus of a four-stage counter would be 1610, since it is capable of indicating 00002 to
11112. The term modulo is used to describe the count capability of counters; that is, modulo-16
(MOD16) for a four-stage binary counter, modulo-10 (MOD10) for a decade counter, modulo-8
(MOD8) for a three-stage binary counter, and so forth. Counters can be up counters, whose count
value increments, and down counters, whose count value decrements, A counter is usually considered
in conjunction with a finite-state machine (FSM). Fig. 8.1 shows an FSM for a 3 bit binary up counter.
In this figure each state (circle) represents a different count value. The counter will move from one
state to the next one with a clock signal. When the count value is 111 the counter is in its largest value
and with the next clock signal it moves from the value of 111 to the initial value, namely 000.
Counters can be divided into two groups: 1. asynchronous (ripple) counters, 2. synchronous counters.
Fig. 8.1. An FSM for a 3-bit binary up counter.

ASYNCHRONOUS (RIPPLE) COUNTERS
OBJECTIVES:
1- Observing the operation principles of asynchronous counters,
2- Analyzing up and down counting,
3- Defining the counting limits.
Asynchronous counters are counters that are configured such that all flip-flops are not triggered
simultaneously by a common clock. Since each flip-flop in the counter is triggered by the flip-flop in
series before it, these counters are also referred to as ripple counters. There are many types of
asynchronous counters. An UP counter counts in an ascending sequence while a DOWN counter
counts in a descending sequence. A counter can also count UP and DOWN on command; such a
counter is known as an UP/DOWN counter.
Asynchronous counters are limited in speed since all the flip-flops are not synchronized by the same
clock. Therefore the propagation delay in each flip-flop often affects the counting sequence at very
high operation frequencies. The flip-flops used in asynchronous counters are usually “T” flip-flops or
JK or D type flip-flops that have been configured as T flip-flops.
Counter decoding is a technique that is used with asynchronous counters to stop or recycle the
counting sequence at a particular count. This involves a circuit known as a count decoder that monitors
the output of the counter for a particular count and resets the counter when that count is detected.
Asynchronous counters can be constructed from discrete flip-flops or are readily available in the form
of ICs. The IC implementations are designed so that the counters can be configured for a wide variety
of applications ranging from simple counting to frequency division.
The flip-flop output in an asynchronous counter is used to trigger the next flip-flop. In other words, all
the flip-flops except for the first one are triggered with the state transition of the previous flip-flops.
However, in synchronous counters the input ticks are applied to all the Clk inputs of the flip-flops at
the same time. The fact that a flip-flop changes state depends on the states of other flip-flops. All flip-
flops work in toggle mode in an asynchronous counter.
A 4-bit asynchronous binary up counter is shown in Fig. 8.2. It can be seen that this asynchronous
counter is composed of four JK flip-flops. All JK flip-flops are working in toggle mode. When J and K
inputs are 1, with each clock signal the output is toggled. The flip-flop storing the Least Significant Bit
(LSB) gets the Clk pulses. The flip-flops are falling edge triggered type, so the flip-flops change their
states with high to low transition () of the signal in their Clk input.
Fig. 8.2. 4-bit asynchronous binary up counter.

Fig. 8.3. Sample timing diagram for a 4-bit asynchronous binary up counter.
Sample timing diagram for this counter is provided in Fig. 8.3. Observe the waveforms in Fig. 8.3 to
fully understand the operating principle of the 4-bit asynchronous binary up counter. Initially, all flip-
flop outputs are zero (0):
Q1=0 , Q2=0 , Q3=0 , Q4=0
When the Clk pulse 0 falls from “1” to “0”, the FF1 is triggered and its output becomes “1”. The Q
outputs of the other flip-flops are all at level “0” because suitable clock pulses haven't yet been applied
to their Clk inputs. So after the Clk pulse 0, flip-flop outputs are as follows:
Q1=1, Q2=0, Q3=0, Q4=0
When the 1st Clk pulse falls from “1” to “0”, the FF1 is triggered again and its output Q1 falls from
“1” to “0”. As the Q1 output is connected to the Clk input of the FF2, that input will see a high to low
transition which triggers the FF2 and makes the Q2 output “1”. (Q1 output is the triggering input of
FF2). So, with the 1st clock pulse the output of the FF1 becomes “0” and the output of the FF2
becomes “1”. Finally, after the 1st Clk pulse, flip-flop outputs are as follows:
Q1=0, Q2=1, Q3=0, Q4=0
With the 2nd clock pulse, the FF1 is once again triggered and has Q1 output as “1”. The other flip-flops
conserve their states. So after the 2nd Clk pulse, flip-flop outputs are as follows:
Q1=1, Q2=1, Q3=0, Q4=0
With the 3rd clock pulse the FF1 is again triggered and its Q1 output falls from “1” to “0”. Therefore
this negative transition (falling edge) will trigger the FF2 and its Q2 output will also fall from “1” to
“0”. With this negative transition the FF3 is also triggered and its Q3 output rises to “1”. So after the
3rd Clk pulse, flip-flop outputs are as follows:
Q1=0, Q2=0, Q3=1, Q4=0
And the rest of the counting operation is performed similarly.
With the 15th clock pulse all the flip-flops are reseted (cleared).
Q1=0, Q2=0, Q3=0, Q=0

When the waveforms of Fig. 8.3 are examined it can be seen that the signal frequency of the output of
FF1 is 1/2, FF2 is 1/4, FF3 is 1/8 and FF4 is 1/16 of the input clock pulse. Consequently, the counters
can be used as frequency dividers.
In the asynchronous binary down counters, with each clock pulse the count value is decremented by 1.
For example, if a 4-bit binary down counter starts counting from 15, then it falls to 14, 13, 12, ..., 1, 0
with each clock pulse and then turns back to 15. In the circuit of Fig. 8.2, if we connect the Clk inputs
of the flip-flops (except for the first one) from the previous flip-flop's Q’ output and read the counting
value from the Q outputs the counter becomes a 4-bit binary down counter.
Modulus Counters with Asynchronous Recycling
Counters can be designed to have a number of states in their sequence that is less than the maximum of
2n. This type of sequence is called a truncated sequence. To obtain such a counter, one of the methods
that can be used is “recycling with respect to the modulus” technique. One common modulus for
counters with truncated sequences is ten (called MOD10). Counters with ten states in their sequence
are called decade counters. A decade counter with a count sequence of zero (0000) through nine
(1001) is a BCD decade counter because its ten-state sequence produces the BCD code. This type of
counter is useful in display applications in which BCD is required for conversion to a decimal readout.
To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all
of its possible states. For example, the BCD decade counter must recycle back to the 000 state after the
1001 state. A decade counter requires four flip-flops (three flip-flops are insufficient because 23=8).
One way to make a BCD counter from a 4-bit asynchronous up counter is to modify its sequence as
shown in Fig. 8.4, which shows a Mod10 (decade or BCD) asynchronous up counter circuit obtained
by JK flip-flops. To force this counter to recycle after the count of nine (1001) is to decode count ten
with a NAND gate and connect the output of the NAND gate to the clear (R) inputs of the flip-flops, as
shown in Figure 8.4. Notice in Fig. 8.4 that only Q4 and Q2 are connected to the NAND gate inputs.
This arrangement is an example of partial decoding, in which the two unique states (Q4 = 1 and Q2 =
1) are sufficient to decode the count of ten because none of the other states (zero through nine) has
both Q4 and Q2 HIGH at the same time. When the counter goes into count ten (1010), the output of
the decoding gate goes LOW (both inputs are HIGH) and asynchronously resets all the flip-flops. Then
the count sequences start from the 0000 state with the next clock signal.
Fig. 8.4. MOD10 (decade or BCD) asynchronous up counter circuit.

EXPERIMENT NO: 8.1

EXPERIMENT NAME: EXAMINATION OF 4 BIT ASYNCHRONOUS BINARY UP
COUNTER
Equipment:
74LS76 Dual master-slave J-K flip-flops 2 ICs
Fig. 8.5.(a). The 4 bit asynchronous binary up counter circuit (count_4bit_as_u).
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.5.(b). The 4 bit asynchronous binary up counter – application circuit.

Procedure:
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.
2. Set the inputs A and B as follows: A=0, B=1 (this means that all preset inputs of flip-flops are
active). Observe the outputs QD(MSB), QC, QB and QA(LSB) and the value shown in the
“HEXADECIMAL DECODER”. Note down your observations here. What does this process mean?
3. Set the inputs A and B as follows: A=1, B=0 (this means that all clear inputs of flip-flops are
4. Set the inputs A and B as follows: A=1, B=1 (this means that clear and preset inputs of flip-flops are
inactive). By pressing the PULSE button generate clock signals and observe the outputs QD(MSB),
QC, QB and QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
observations in Table 8.1.
OUTPUTS HEX DECIMAL
PULSE
QD QC QB QA VALUE VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Table 8.1.
7. Set the inputs A and B as follows: A=1, B=1. Position the SPDT switch such that it connects the
clock input of the counter from the TTL oscillator. Change the oscillator frequencies starting from 1
Hz., 10 Hz., 100 Hz., etc. and observe the operation of the counter. After which frequencies you
cannot observe the changing of count values by your eyes? Explain why?

EXPERIMENT NO: 8.2

EXPERIMENT NAME: EXAMINATION OF MOD10 ASYNCHRONOUS UP COUNTER
Equipment:

Fig. 8.6.(a). MOD10 asynchronous up counter circuit (count_4bit_as_u_md10).

Fig. 8.6.(b). MOD10 asynchronous up counter – application circuit.

Procedure:
2. Set the input A to the logic 1 state (this means that all preset inputs of flip-flops are inactive).
3. In order to produce a clock signal to be applied to the counter press the PULSE button. After
applying a clock signal observe the output of the counter and note down the output in Table 8.2.
Successively press the PULSE button until all flip-flop outputs are zero.
4. Describe the operation of this counter here.
OUTPUTS DECIMAL
PULSE
QD QC QB QA VALUE
CLEAR
1
2
3
4
5
6
7
8
9
10
11
12
Table 8.2.
5. Keep the input A at the logic 1 state (this means that all preset inputs of flip-flops are inactive).
Position the SPDT switch such that it connects the clock input of the counter from the TTL oscillator.
Change the oscillator frequencies starting from 1 Hz., 10 Hz., 100 Hz., etc. and observe the operation
of the counter.

EXPERIMENT NO: 8.3

EXPERIMENT NAME: EXAMINATION OF 4 BIT ASYNCHRONOUS BINARY DOWN
COUNTER
Equipment:
Fig. 8.7.(a). The 4 bit asynchronous binary down counter circuit (count_4bit_as_d).
Fig. 8.7.(b). The 4 bit asynchronous binary down counter – application circuit.

Procedure:
2. Set the inputs A and B as follows: A=1, B=0 (this means that all clear inputs of flip-flops are
3. Set the inputs A and B as follows: A=0, B=1 (this means that all preset inputs of flip-flops are
4. Set the inputs A and B as follows: A=1, B=1 (this means that clear and preset inputs of flip-flops are
inactive). By pressing the PULSE button generate clock signals and observe the outputs QD(MSB),
QC, QB and QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
OUTPUTS HEX DECIMAL

PULSE
QD QC QB QA VALUE VALUE
PRESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Table 8.3
5. Set the inputs A and B as follows: A=1, B=1. Position the SPDT switch such that it connects the
clock input of the counter from the TTL oscillator. Change the oscillator frequencies starting from 1
Hz., 10 Hz., 100 Hz., etc. and observe the operation of the counter.

74LS93 4 BIT ASYNCHRONOUS BINARY UP COUNTER

The 74LS93 is an example of a specific TTL IC asynchronous up counter. Fig. 8.8 shows the
schematic symbol, the logic diagram, the reset/count truth table and the count sequence of the 74LS93
4 bit asynchronous up counter IC. As the logic diagram in Fig. 8.8 shows, this device actually consists
of a single flip-flop and a 3-bit asynchronous counter. This arrangement is for flexibility. It can be
used as a divide-by-2 device if only the single flip-flop is used, or it can be used as a MOD8 counter if
only 3-bit counter is used. This device also provides gated reset inputs, MR1 and MR2. When both of
these inputs are HIGH, the counter is reset to 0000 state. The 74LS93 can be used as a 4-bit MOD16
counter (counts 0 through 15). It can also be configured as a decade counter (counts 0 through 9) with
asynchronous recycling by using the gated reset inputs MR1 and MR2.
Schematic Symbol
Logic Diagram
NC: Not Connected
Fig. 8.8. The schematic symbol, the logic diagram, the reset/count truth table and the count sequence
of the 74LS93 4 bit asynchronous up counter IC.

EXPERIMENT NO: 8.4

EXPERIMENT NAME: EXAMINATION OF THE 74LS93 4 BIT ASYNCHRONOUS UP
COUNTER
Equipment:
74LS93 4 bit binary counter 1 IC
Fig. 8.9.(a). The 74LS93 4 bit asynchronous up counter circuit (74LS93).
Fig. 8.9.(b). 74LS93 4 bit asynchronous up counter – application circuit.

Procedure:
2. Set the input A to the logic 1 state (this means that all clear inputs of flip-flops are active).
Successively press the PULSE button a few times. Then observe the output of the counter and note
down the output value here. What does this process mean?
3. Set the input A to the logic 0 state (this means that clear inputs of flip-flops are inactive). By
pressing the PULSE button generate clock signals and observe the outputs Q3(MSB), Q2, Q1 and
Q0(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your observations
in Table 8.4.
OUTPUTS HEX DECIMAL

PULSE A
Q3 Q2 Q1 Q0 VALUE VALUE
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0
11 0
12 0
13 0
14 0
15 0
16 0
17 0
18 0
Table 8.4.
4. Keep the input A at the logic 0 state (this means that clear inputs of flip-flops are inactive). Position
the SPDT switch such that it connects the clock input of the counter from the TTL oscillator. Change
the oscillator frequencies starting from 1 Hz., 10 Hz., 100 Hz., etc. and observe the operation of the
counter.

EXPERIMENT NO: 8.5

EXPERIMENT NAME: EXAMINATION OF THE 74LS93 USED AS A BCD COUNTER
Equipment:
74LS93 4 bit binary counter 1 IC
Fig. 8.10.(a). Configuration of the 74LS93 as a decade counter (74LS93).
Fig. 8.10.(b). Configuration of the 74LS93 as a decade counter – application circuit.

Procedure:
2. By pressing the PULSE button generate clock signals and observe the outputs Q3(MSB), Q2, Q1
and Q0(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
DECIMAL
PULSE Q3 Q2 Q1 Q0
VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 8.5.

3. In the circuit shown below, design and implement a MOD8 counter. Then construct the circuit and
apply the power.
4. In the circuit shown below, design and implement a MOD12 counter. Then construct the circuit and
apply the power.

4024 7 BIT ASYNCHRONOUS BINARY UP COUNTER
The 4024 is a 7 bit asynchronous binary up counter CMOS IC. Fig. 8.11 shows the schematic symbol
and the function table of the 4024 7 bit asynchronous up counter IC. The 4024 has an active HIGH
asynchronous master reset input (MR), a clock input (CP’) and seven fully buffered parallel outputs
(Q6, Q5, …, Q0). The counter advances (counts 0000000 through 1111111) on the HIGH to LOW
transition () of CP’. A HIGH on MR clears all counter stages and forces all outputs LOW,
independent of CP’. Each counter stage is a static toggle flip-flop.
Schematic Symbol
NC: Not Connected
Fig. 8.11. The schematic symbol and the function table of the 4024 7 bit asynchronous up counter IC.

EXPERIMENT NO: 8.6

EXPERIMENT NAME: EXAMINATION OF 4024 7 4 BIT ASYNCHRONOUS UP COUNTER
Equipment:
4024 7 bit binary counter 1 IC
Fig. 8.12.(a). The 4024 7 bit asynchronous up counter circuit (4024).
Note1: Do not forget to connect the VDD pin to +5 V and the VSS pin to ground (GND) connection
Fig. 8.12.(b). The 4024 7 bit asynchronous up counter – application circuit.

Procedure:
2. Set the input A to the logic 1 state (this means that all clear inputs of flip-flops are active).
Successively press the PULSE button a few times. Then observe the outputs of the counter, i.e.
Q6(MSB), Q5, Q4, Q3, Q2, Q1 and Q0(LSB), and note down the output value here. What does this
process mean?
3. Set the input A to the logic 0 state. By pressing the PULSE button generate clock signals and
observe the counter outputs Q6(MSB), Q5, Q4, Q3, Q2, Q1 and Q0(LSB). Note down your
observations in Table 8.6. What does this process mean?
4. Keep the input A at the logic 0 state. Position the SPDT switch such that it connects the clock input
of the counter from the TTL oscillator. Change the oscillator frequencies starting from 1 Hz., 10 Hz.,
100 Hz., etc. and observe the operation of the counter. Discuss the results obtained in this step.
5. Keep the input A at the logic 0 state. Position the SPDT switch such that it connects the clock input
of the counter from the TTL oscillator. Remove the logic switch A from the MR input. Then
sequentially connect the outputs from Q1 to Q6 to the MR input and observe the count values for each
connection. For each connection chose an appropriate clock signal from the TTL oscillator. Note down
the different count sequences here. Discuss the results obtained in this step.
When Q1 is connected to MR the counter counts ……..
6. Connect the logic switch A to the MR input and set the input A to the logic 0 state. Remove the CP
input from the SPDT switch. Then connect the CP input to one of the unused “TTL BINARY
SWITCH”es (i.e., B, C, …, or L). This means that the clock input of the counter will be provided from
one of the TTL binary switches rather than TTL PULSE input or TTL OSCILLATOR. Then, toggle
the binary switch used as the clock input from the ON state to the OFF state only once and observe the
output of the counter, i.e. Q6(MSB), Q5, Q4, Q3, Q2, Q1 and Q0(LSB). Does the counter increment
only one count value? If not explain what this means.

INPUTS OUTPUTS
PULSE A Q6 Q5 Q4 Q3 Q2 Q1 Q0 DECIMAL
0 0 0 0 0 0 0 0 0 0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0
11 0
12 0
13 0
14 0
15 0
20 0
25 0
30 0
35 0
40 0
45 0
50 0
55 0
60 0
65 0
70 0
75 0
80 0
85 0
90 0
95 0
100 0
105 0
110 0
115 0
120 0
128 0
Table 8.6.

SYNCHRONOUS COUNTERS
OBJECTIVES:
1- Observing the operation principles of synchronous counters,
2- To study the design and construction of synchronous counters,
3- To study different synchronous counter examples.
Synchronous counters are counters that are configured such that all flip-flops are triggered
simultaneously by a common clock. All flip-flops are therefore “synchronized” by the same clock.
Like asynchronous counters there are many types of synchronous counters. They can be designed to
provide the same functions as asynchronous counters. Therefore many applications requiring counters
can have either asynchronous counters or synchronous counters.
Unlike asynchronous counters, synchronous counters are not limited in speed since all the flip-flops
are synchronized by the same clock. Since the clock of each flip-flop is not affected by propagation
delays, synchronous counters are not susceptible to adverse effects of high frequency operations.
Therefore synchronous counters are often used in applications that require that the counter be operated
at frequencies beyond those that an asynchronous counter can handle. In an asynchronous counter the
count sequence must follow the regular ascending or descending sequence but in a synchronous
counter in addition to the regular ascending or descending sequences different types of irregular count
sequences can also be obtained.
Synchronous counters can be constructed from discrete flip-flops or are readily available in the form
of ICs. The IC implementations are designed so that the counters can be configured for a wide variety
of applications ranging from simple counting to frequency division.
Design Steps of Synchronous Counters:
1- Specify the counter sequence and draw a state diagram which describes the operation of
counter.
2- Define the type and the number of the flip-flops to be used.
3- Drive a next state table from the state diagram.
4- Develop a transition table, showing the flip-flop inputs required for each transition by using the
chosen flip-flop’s excitation table.
5- Obtain flip-flop input functions based on the present states and then simplify them. If you use
Karnough maps do not forget to put  (don’t care) in the Karnough maps for the unused count
values.
6- Draw the schematic diagram of the counter.
Synchronous Counter Design Example:
Design a synchronous counter to count in the following sequence

0246135702...
Let us now follow the design steps:
1- For this synchronous counter, the counter sequence 0246135702... is drawn

as a state diagram as shown in Fig. 8.13.

Fig. 8.13. The state diagram (Moore machine) for the synchronous counter to count in the count
sequence of 0246135702... and flip-flop outputs assigned to each state.
2- The type of the flip-flop to design this counter is chosen as JK flip-flop. The largest number within
the count values is 7, therefore 3 flip-flops are enough to design this counter.
3- The next state table for the synchronous counter to count in the count sequence of
0246135702... is driven from the state diagram of Fig. 8.13 as shown in Table
8.7.
Present state (tn) Next state (tn+1)
(binary) Decimal (binary) Decimal
Q2Q1Q0 number Q2Q1Q0 number
000 0 010 2
010 2 100 4
100 4 110 6
110 6 001 1
001 1 011 3
011 3 101 5
101 5 111 7
111 7 000 0
Table 8.7. The next state table for the synchronous counter to count in the count sequence of
0246135702....
4- The transition table (Table 8.8) for the synchronous counter to count in the count sequence of
0246135702.... driven from the next state table of Table 8.7 by using the
excitation table given in Table 8.9.
flip-flop outputs transition of flip-flop outputs flip-flop input functions

CP Q2Q1Q0 Q2Q1Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
tn tn tn+1 tn tn+1 tn tn+1 tn tn+1 tn tn tn tn tn tn
0 000 010 00 01 00 0  1  0 
1 010 100 01 10 00 1   1 0 
2 100 110 11 01 00  0 1  0 
3 110 001 10 10 01  1  1 1 
4 001 011 00 01 11 0  1   0
5 011 101 01 10 11 1   1  0
6 101 111 11 01 11  0 1   0
7 111 000 10 10 10  1  1  1
Table 8.8. The transition table for the synchronous counter to count in the count sequence of
0246135702.... driven from the next state table of Table 8.7 and the excitation
table given in Table 8.9.

Qtn Qtn+1 J K
00 0 
01 1 
10  1
11  0
Table 8.9. The excitation table for the JK flip-flop.
5- Flip-flop input functions based on the present states are obtained as follows from the transition table
given in Table 8.8:
J2(Q2,Q1,Q0) = m(2, 3) + d(4, 5, 6, 7),

K2(Q2,Q1,Q0) = m(6, 7) + d(0, 1, 2, 3),
J1(Q2,Q1,Q0) = m(0, 1, 4, 5) + d(2, 3, 6, 7),
K1(Q2,Q1,Q0) = m(2, 3, 6, 7) + d(0, 1, 4, 5),
J0(Q2,Q1,Q0) = m(6) + d(1, 3, 5, 7),
K0(Q2,Q1,Q0) = m(7) + d(0, 2, 4, 6).
These input functions are simplified by using Karnough maps as shown in Fig. 8.14.
Fig. 8.14. The simplification of the input functions by using Karnough maps.
6-. The implementation of the synchronous counter to count in the following sequence
0246135702... by using JK flip-flops is shown in Fig. 8.15.

Q0 (LSB) Q1
Q2 (MSB)
J Q J Q J Q
C FF0 C FF1 C FF2

K Q K Q K Q
Tetikleme
sinyali
Fig. 8.15. The implementation of the synchronous counter to count in the following sequence
0246135702... by using JK flip-flops.
4 Bit Synchronous Up Counter: The 4 bit synchronous up counter circuit constructed with T flip-
flops is shown in Fig. 8.16. T flip-flop input functions based on the present states are obtained as
follows:
T3 = Q2Q1Q0, T2 = Q1Q0, T1 = Q0, T0 = 1
Fig. 8.16. The 4 bit synchronous up counter circuit constructed with T flip-flops.
BCD (MOD10) Synchronous Up Counter: The BCD (MOD10) synchronous up counter circuit
constructed with D flip-flops is shown in Fig. 8.17. D flip-flop input functions based on the present
states are obtained as follows:
D3 = Q3 Q0 + Q2Q1Q0, D2 = Q2 Q1 + Q2 Q0 + Q2 Q1Q0,
D1 = Q1 Q0 + Q3 Q1 Q0, D0 = Q0

Fig. 8.17. The BCD (MOD10) synchronous up counter circuit constructed with D flip-flops.
4 Bit Synchronous Up/Down Counter: The 4 bit synchronous up/down counter circuit constructed
with T flip-flops is shown in Fig. 8.18. T flip-flop input functions based on the present states are
obtained as follows:
T3 = KQ2Q1Q0 + K Q2 Q1 Q0 , T2 = KQ1Q0 + K Q1 Q0 ,
T1 = KQ0 + K Q0 , T0 = 1
Fig. 8.18. The 4 bit synchronous up/down counter circuit constructed with T flip-flops.

EXPERIMENT NO: 8.7

EXPERIMENT NAME: EXAMINATION OF THE SYNCHRONOUS COUNTER WITH THE
COUNTING SEQUENCE OF 0, 2, 4, 6, 1, 3, 5, 7, 0, …
Equipment:

74LS08 Quad 2-input AND gates 1 IC
Fig. 8.19.(a). The synchronous counter circuit to count

in the count sequence of 0, 2, 4, 6, 1, 3, 5, 7, 0, 2, ... (count_s_02461357).

Fig. 8.19.(b). The synchronous counter to count
in the count sequence of 0, 2, 4, 6, 1, 3, 5, 7, 0, 2, ... – application circuit.

Procedure:
2. Set the input A to the logic 0 state temporarily. Then set the input A to the logic 1 state
permanently.
3. By pressing the PULSE button generate clock signals and observe the outputs QC(MSB), QB and
QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your observations
in Table 8.10.
OUTPUTS DECIMAL
PULSE
QC QB QA VALUE
CLEAR
1
2
3
4
5
6
7
8
9
10
11
12
Table 8.10.
4. Set the input A to the logic 1. Position the SPDT switch such that it connects the clock input of the
counter from the TTL oscillator. For different oscillator frequencies starting from 1 Hz., 10 Hz., 100
Hz., etc. observe the operation of the counter.

EXPERIMENT NO: 8.8

EXPERIMENT NAME: EXAMINATION OF THE 4 BIT SYNCHRONOUS UP COUNTER
Equipment:

Fig. 8.20.(a). The 4 bit synchronous up counter circuit (count_s_mod16_7seg).

Fig. 8.20.(b). The 4 bit synchronous up counter – application circuit.

Procedure:
permanently.
3. By pressing the PULSE button generate clock signals and observe the outputs QD(MSB), QC, QB
and QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
OUTPUTS HEXADECIMAL
PULSE
QD QC QB QA VALUE
CLEAR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Table 8.11.

EXPERIMENT NO: 8.9

EXPERIMENT NAME: EXAMINATION OF THE BCD SYNCHRONOUS UP COUNTER
Equipment:

Fig. 8.21.(a). The BCD synchronous up counter circuit (count_s_dec_7seg).

Fig. 8.21.(b). The BCD synchronous up counter – application circuit.

Procedure:
permanently.
3. By pressing the PULSE button generate clock signals and observe the outputs QD(MSB), QC, QB
and QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
OUTPUTS DECIMAL
PULSE
QD QC QB QA VALUE
CLEAR
1
2
3
4
5
6
7
8
9
10
11
12
Table 8.12.

EXPERIMENT 9
REGISTERS
EQUIPMENT:

74LS164 8 bit serial in/parallel out shift register 1
74LS165 8 bit parallel in/serial out shift register 1
74LS174 Hex rising edge triggered D flip-flops 1
74LS194 4 bit universal shift register 1
74LS195 4 bit universal shift register 1

PRELIMINARY WORK:
3. By means of a digital simulation software, test and verify the operation of the logic circuits shown in
Fig. 9.4.(a). 4 bit serial in/parallel out shift right register circuit constructed by using 74LS174
1
IC (4_bit_SIPO_SR).
2 Fig. 9.6.(a). 4 bit parallel in/parallel out register circuit (4_bit_PIPO_R).
3 Fig. 9.9.(a). The 74LS194 4 bit universal shift register circuit (74LS194_IC).
4 Fig. 9.12.(a). The 74LS195 4 bit universal shift register circuit (74LS195_IC).
5 Fig. 9.15.(a). The 74LS165 8 bit parallel in/serial out shift register circuit (74LS165_IC).
6 Fig. 9.18.(a). The 74LS164 8 bit serial in/parallel out shift register circuit (74LS164_IC).
connections.
5. Construct and implement a 4 bit serial in/parallel out shift left register by using 74LS174 IC provided
in Fig. 9.5.(a). By means of a digital simulation software test and verify the operation of your
NOTE: You are obliged to have a copy of the page number 9_1 from “the experiment report form
9” when you start doing this experiment.

SHIFT REGISTERS
OBJECTIVES:
1- Learning operation principles of shift registers.
2- Learning how to use shift registers as shift right registers.
3- Learning how to use shift registers as shift left registers.
4- Learning "Parallel Input, Parallel Output, Serial Input, Serial Output" principles.
5- Getting familiar with 74LS174, 74LS194, 74LS195, 74LS165 and 74LS164 ICs.
Shift registers can store and shift binary data. Due to this property, they are used in processes like
registering data, binary adding-subtracting and data transfers in the computer. They are also used in
binary multiplication and division. Multiplication and division is another form of shifting in binary
numbers. For example, if a binary number is shifted to the left, the decimal value of the number will be
multiplied by 2. Similarly, if a binary number is shifted to the left, the decimal value of it will be divided
by 2. Shift registers are composed of several flip-flops connected one after the other, i.e. the output of
one is connected to the input of the next. All flip-flops have the same clock so the data transfer is done
simultaneously with clock ticks. The reason why they operate with a common clock is to ensure the
synchronous data transfer from one flip-flop to the other. The data transfer occurs with falling edge or
rising edge of the clock according to the type of the flip-flop. The shift registers can be classified with
the number of bits they process, input-output type and shifting direction of the bits. The number of flip-
flops in a shift registers depends on the number of the bits stored or processed (Each flip-flop stores one
bit of data). There are 4-bit, 8-bit, 16-bit type registers.
Basic data movement in a register can be one of the following:
Serial in/shift right/serial out

Serial in/shift left/serial out
Parallel in/serial out
Serial in/parallel out
Parallel in/parallel out
Rotate Right
Rotate left

SHIFT REGISTERS COMPOSED OF FLIP-FLOPS
OBJECTIVES:
1- Analysing shift registers composed of flip-flops,
2- Observing their operation.
Shift registers consists of flip-flops and are important in applications involving the storage of data in a
digital system. A register, unlike a counter, has no specified sequence of states, except in certain
specialised applications. A register, in general, is used solely for storing and shifting data (1s and 0s)
entered into it from an external source. Fig. 9.1 shows a 4 bit serial in parallel out shift register
composed of 4 D flip-flops. Sample timing diagram and sample output table for a 4 bit serial in parallel
out shift register are also provided in Fig. 9.2 and Table 9.1 respectively.
Fig. 9.1. 4 bit serial in parallel out shift register composed of 4 D flip-flops.
INPUTS OUTPUTS
CLOCK DATA Q0 Q1 Q2 Q3
0 1 1 0 0 0
1 0 0 1 0 0
2 0 0 0 1 0
3 0 0 0 0 1
4 0 0 0 0 0
Fig. 9.2. Sample timing diagram for a 4 bit serial in Table 9.1. Sample output table for a 4 bit serial
parallel out shift register. in parallel out shift register.

74LS174 – HEX RISING EDGE TRIGGERED D FLIP-FLOPS
The 74LS174 includes six D-type flip-flops. These positive(rising edge)-edge-triggered flip-flops utilize
TTL circuitry to implement D-type flip-flop logic. All have a direct clear input. Information at the D
inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going (rising)
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to
the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect at the output. Fig. 9.3 shows the schematic symbol, the function
table and the logic diagram of the 74LS174 hex D-type flip-flops with clear IC. The 74LS174 can easily
be used when implementing shift registers. Therefore, the first two experiments include registers
composed of the 74LS174 IC.
Schematic Symbol
Logic Diagram
Fig. 9.3. The schematic symbol, the function table and the logic diagram of the 74LS174 Hex D-type
flip-flops with clear IC.

EXPERIMENT NO: 9.1

EXPERIMENT NAME: EXAMINATION OF THE 4 BIT SERIAL IN/PARALLEL OUT SHIFT
RIGHT REGISTER COMPOSED OF FLIP-FLOPS
Equipment:
74LS174 Hex rising edge triggered D flip-flops 1 IC
Fig. 9.4.(a). 4 bit serial in/parallel out shift right register circuit constructed by using 74LS174 IC
(4_bit_SIPO_SR).
Fig. 9.4.(b). 4 bit serial in/parallel out shift right register constructed by using 74LS174 IC –

Procedure:
power.
2. Apply the combinations of RESET (A) and SERIAL INPUT (B) and then apply a clock signal to the
inputs of the circuit as given in Table 9.2 (follow the given steps) and experimentally obtain the output
values and take note of them in the Table.
NOTE: RESET(A) and SERIAL INPUT (B) must always be provided before the CLOCK signal.
INPUTS OUTPUTS
CLOCK RESET(A) SERIAL INPUT (B) Q0 Q1 Q2 Q3
0 0 1
1 1 1
2 1 0
3 1 0
4 1 0
Table 9.2.
3. Construct and implement a 4 bit serial in/parallel out shift left register by using 74LS174 IC provided
in Fig. 9.5.(a). By means of a digital simulation software test and verify the operation of your
implementation. Then, draw by hand using pencils an application circuit provided in Fig. 9.5.(b) for the
completed schematic diagram of Fig. 9.5.(a). It is recommended that you use red colour for Vcc, black
colour for GND and other colours for other connections.
Fig. 9.5.(a). A circuit to construct a 4 bit serial in/parallel out shift left register by using a 74LS174 IC.

4. Construct the circuit [as designed by you in Fig. 9.5.(a) and] as drawn by you in Fig. 9.5.(b) and apply
the power.
Fig. 9.5.(b). A 4 bit serial in/parallel out shift left register constructed by using a 74LS174 IC –
5. Apply the combinations of RESET (A) and SERIAL INPUT (B) and then apply a clock signal to the
inputs of the circuit as given in Table 9.3 (follow the given steps) and experimentally obtain the output
values and take note of them in the Table.
NOTE: RESET(A) and SERIAL INPUT (B) must always be provided before the CLOCK signal.
INPUTS OUTPUTS
CLOCK RESET(A) SERIAL INPUT (B) Q0 Q1 Q2 Q3
0 0 1
1 1 1
2 1 0
3 1 0
4 1 0
Table 9.3.

EXPERIMENT NO: 9.2

EXPERIMENT NAME: EXAMINATION OF THE 4 BIT PARALLEL IN/PARALLEL OUT
REGISTER COMPOSED OF FLIP-FLOPS
Equipment:
74LS174 Hex rising edge triggered D flip-flops 1 IC
Fig. 9.6.(a). 4 bit parallel in/parallel out register circuit (4_bit_PIPO_R).
Fig. 9.6.(b). 4 bit parallel in/parallel out register – application circuit.

Procedure:
power.
2. Apply the combinations of RESET (A) and PARALLEL INPUTS (B) and then apply a clock signal
to the inputs of the circuit as given in Table 9.4 (follow the given steps) and experimentally obtain the
output values and take note of them in the Table.
NOTE: RESET(A) and PARALEL INPUTS must always be provided before the CLOCK signal.
INPUTS OUTPUTS
PARALLEL INPUTS
CLOCK RESET (A) Q0 Q1 Q2 Q3
P0 P1 P2 P3
0 0 0 1 0 1
1 1 1 1 1 0
2 1 0 1 1 0
3 1 1 0 0 1
4 1 1 0 1 0
Table 9.4.

74LS194 UNIVERSAL SHIFT REGISTER
OBJECTIVES:
1- Learning different shift register operation principals.
2- Getting to know the 74LS194 shift register IC.
3- Observing its operation and obtaining its truth table.
The shift registers can be composed of separate ICs or they can be implemented in a single IC. The
74LS194 is a single IC universal shift register. Fig. 9.7 shows the pin definitions of the 74LS194. The
logic diagram and the truth table of the 74LS194 shift register are shown in Fig. 9.8 and in Table 9.5
respectively. When MR = 0, regardless of the all inputs the register is cleared and therefore all outputs
are forced to 0. When master reset input is not active, i.e. when MR = 1, S1 and S0 inputs are used to
select the operation mode. As can be seen from Table 9.5 there are 4 types of modes: hold, shift left,
shift right and parallel load.
When inputs S1 and S0 are 00, the outputs (Q0, Q1, Q2 and Q3) hold their previous values (Hold).
When inputs S1 and S0 are 10, the data stored in the register is shifted left with the rising edge of the
clock signal (Shift left). In this case the serial input is taken from DSL input.
When inputs S1 and S0 are 01, the data stored in the register is shifted right with the rising edge of the
clock signal (Shift right). In this case the serial input is taken from DSR input.
When inputs S1 and S0 are 11, the data in the parallel inputs P0, P1, P2, and P3 are loaded in the register
(i.e. in the flip-flops Q0, Q1, Q2 and Q3 respectively) with the rising edge of the clock signal (Parallel
load).
Fig. 9.7. Pin definitions of the 74LS194 4 bit universal shift register.

Fig. 9.8. Logic diagram of the 74LS194 shift register.
Table 9.5. The truth table of the 74LS194 shift register IC.

EXPERIMENT NO: 9.3

EXPERIMENT NAME: EXAMINATION OF THE 74LS194 UNIVERSAL SHIFT REGISTER
Equipment:
74LS194 4 bit universal shift register 1 IC
Fig. 9.9.(a). The 74LS194 4 bit universal shift register circuit (74LS194_IC).
Fig. 9.9.(b). The 74LS194 4 bit universal shift register – application circuit.

Procedure:
power.
2. Set the select inputs as S1=0 and S0=1 (the register is ready to shift right the stored data). In this
mode the data will be shifted from Q0 to Q3.
3. Set the MR input to the logic 0 state temporarily. Then set the MR input to the logic 1 state
permanently. This will clear all the outputs.
4. Set the shift right input DSR to the logic 1 state.
5. Press the PULSE button four times to generate 4 clock signals and observe the outputs Q0, Q1, Q2,
Q3.
6. Note down your observations in Table 9.6.(a).
INPUTS OUTPUTS
CLOCK MR P0 P1 P2 P3 S1 S0 DSR DSL Q0 Q1 Q2 Q3
0 0 × × × × 0 1 1 ×
1 1 × × × × 0 1 1 ×
2 1 × × × × 0 1 1 ×
3 1 × × × × 0 1 1 ×
4 1 × × × × 0 1 1 ×
×: Don’t care.
Table 9.6.(a).
7. Set the select inputs as S1=1 and S0=0 (the register is ready to shift left the stored data). In this mode
the data will be shifted from Q3 to Q0.
8. Set the MR input to the logic 0 state temporarily. Then set the MR input to the logic 1 state
permanently. This will clear all the outputs.
9. Set the shift left input DSL to the logic 1 state.
10. Press the PULSE button four times to generate 4 clock signals and observe the outputs Q0, Q1, Q2,
Q3.
11. Note down your observations in Table 9.6.(b).
INPUTS OUTPUTS
0 0 × × × × 1 0 × 1
1 1 × × × × 1 0 × 1
2 1 × × × × 1 0 × 1
3 1 × × × × 1 0 × 1
4 1 × × × × 1 0 × 1
×: Don’t care.
Table 9.6.(b).

12. Set the select inputs as S1=1 and S0=1 (the register is ready to parallel load). In this mode the data
present in parallel data inputs P0, P1, P2, and P3 will be loaded to flip-flops Q0, Q1, Q2, and Q3
respectively with the rising edge of the clock signal.
13. Set the parallel data inputs as P0 = 1, P1 = 1, P2 = 0, P3 = 0.
14. Press the PULSE button once and observe the outputs Q0, Q1, Q2, Q3. Are the outputs Q0, Q1, Q2,
Q3 the same as the parallel data inputs P0, P1, P2, and P3?
15. Repeat the steps 13 and 14 for the parallel data input values provided in Table 9.6.(c) and then note
down the output values in the Table.
INPUTS OUTPUTS
1 1 1 1 0 0 1 1 × ×
2 1 1 1 0 0 1 1 × ×
3 1 0 1 1 0 1 1 × ×
4 1 0 1 1 0 1 1 × ×
5 1 1 1 1 1 1 1 × ×
6 0 1 1 1 1 1 1 × ×
×: Don’t care.
Table 9.6.(c).

74LS195 UNIVERSAL SHIFT REGISTER
OBJECTIVES:
The 74LS195 is another single IC universal shift register. Fig. 9.10 shows the pin definitions of the
74LS195. The logic diagram and the truth table of the 74LS195 shift register are shown in Fig. 9.11 and
in Table 9.7 respectively.
The logic diagram and truth table indicate the functional characteristics of the LS195A 4-bit shift
register. The device is useful in a wide variety of shifting, counting and storage applications. It performs
serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has
two primary modes of operation, shift right (Q0  Q1  Q2  Q3) and parallel load which are
controlled by the state of the active low Parallel Enable (PE’) input. When the PE’ input is HIGH, serial
data enters the first flip-flop Q0 via the J and K’ inputs and is shifted one bit in the direction Q0  Q1
 Q2  Q3 following each LOW to HIGH clock transition. The JK’ inputs provide the flexibility of
the JK type input for special applications, and the simple D type input for general applications by tying
the two pins together. When the PE’ input is LOW, the LS195A appears as four common clocked D
flip-flops. The data on the parallel inputs P0, P1, P2, P3 are transferred to the respective Q0, Q1, Q2, Q3
outputs following the LOW to HIGH clock transition. Shift left operations (Q0  Q1  Q2  Q3) can
be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE’ input LOW. All serial and
parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the
LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K’, Pn and PE inputs for
logic operation — except for the set-up and release time requirements. A LOW on the asynchronous
active low Master Reset (MR’) input sets all Q outputs LOW, independent of any other input condition.
Fig. 9.10. Pin definitions of the 74LS195 4 bit universal shift register.


EXPERIMENT NO: 9.4

EXPERIMENT NAME: EXAMINATION OF THE 74LS195 UNIVERSAL SHIFT REGISTER
Equipment:
74LS195 4 bit universal shift register 1 IC
Fig. 9.12.(a). 74LS195 4 bit universal shift register circuit (74LS195_IC).
Fig. 9.12.(b). The 74LS195 4 bit universal shift register – application circuit.

Procedure:
power.
2. Apply all possible combinations to the inputs of the circuit as given in Table 9.8 and experimentally
obtain the output values and take note of the output values in the Table. Whenever MR = 1, firstly apply
the inputs PE’, J, K’, P0, P1, P2, P3 as shown in the Table; then press the PULSE button to generate a
clock signal and observe the outputs Q0, Q1, Q2, Q3.
INPUTS OUTPUTS
CLOCK MR PE’ J K’ P0 P1 P2 P3 Q0 Q1 Q2 Q3
0 0 × × × × × × ×
1 1 1 1 1 × × × ×
2 1 1 1 1 × × × ×
3 1 1 1 1 × × × ×
4 1 1 0 0 × × × ×
5 1 1 0 0 × × × ×
6 1 1 0 0 × × × ×
7 1 1 0 0 × × × ×
8 1 1 1 0 × × × ×
9 1 1 1 0 × × × ×
10 1 1 1 0 × × × ×
11 1 1 1 0 × × × ×
12 1 1 0 1 × × × ×
13 1 1 0 1 × × × ×
14 1 1 0 1 × × × ×
15 1 1 0 1 × × × ×
16 0 × × × × × × ×
17 1 0 × × 1 0 1 0
18 1 0 × × 0 1 0 1
19 1 0 × × 1 0 1 1
20 1 0 × × 0 1 1 0
21 1 0 × × 1 1 1 1
22 1 0 × × 1 1 1 0
×: Don’t care.
Table 9.8.

74LS165 8 BIT PARALLEL IN/SERIAL OUT SHIFT REGISTER
OBJECTIVES:
Fig. 9.13 shows the pin definitions of the 74LS165. The logic diagram and the truth table of the
74LS165 shift register are shown in Fig. 9.14 and in Table 9.9 respectively.
The 74LS165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7
and Q7’) available from the last stage. When the active low Parallel Load (PL’) input is LOW, parallel
data from the D0 to D7 inputs are loaded into the register asynchronously. When PL’ is HIGH, data
enters the register serially at the Ds input and shifts one place to the right (Q0  Q1  Q2, etc.) with
each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying
the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which
allows one input to be used as an active LOW clock enable (CE’) input. The pin assignments for the CP
and CE’ inputs are arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition
of input CE’ should only take place while CP HIGH for predictable operation. Either the CP or the CE’
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL’ is
activated.
Fig. 9.13. Pin definitions of the 74LS165 shift register.


EXPERIMENT NO: 9.5

EXPERIMENT NAME: EXAMINATION OF THE 74LS165 8 BIT PARALLEL IN/SERIAL
OUT SHIFT REGISTER
Equipment:
74LS165 8 bit parallel in/serial out shift register 1 IC
Fig. 9.15.(a). 74LS165 8 bit parallel in/serial out shift register circuit (74LS165_IC).
Fig. 9.15.(b). The 74LS165 8 bit parallel in/serial out shift register – application circuit.

Procedure:
power.
obtain the output values and take note of the output values in the Table. Firstly, apply the inputs PL’,
CE’, Ds, P0, P1, P2, P3, P4, P5, P6, P7 as shown in the Table; then press the PULSE button to generate
a clock signal and observe the output Q7 and its complement Q7’. Note that you can follow the stored
data within the register by writing 8 bits within the table. Although you cannot observe it from outside
you can still track the data already stored inside.
INPUTS OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CLOCK
PL’ CE’ Ds P0 P1 P2 P3 P4 P5 P6 P7 (Data stored Q7 Q7’
(CP)
within the register)
0 0 × × 1 0 1 0 1 0 1 1
1 1 1 × × × × × × × × ×
2 1 1 × × × × × × × × ×
3 1 1 × × × × × × × × ×
4 1 1 × × × × × × × × ×
5 1 0 1 × × × × × × × ×
6 1 0 1 × × × × × × × ×
7 1 0 1 × × × × × × × ×
8 1 0 1 × × × × × × × ×
9 1 0 1 × × × × × × × ×
10 1 0 1 × × × × × × × ×
11 1 0 1 × × × × × × × ×
12 1 0 1 × × × × × × × ×
13 1 0 1 × × × × × × × ×
14 0 × × 1 0 1 1 1 1 0 0
15 1 0 0 × × × × × × × ×
16 1 0 0 × × × × × × × ×
17 1 0 0 × × × × × × × ×
18 1 0 0 × × × × × × × ×
19 1 0 0 × × × × × × × ×
20 1 0 0 × × × × × × × ×
21 1 0 0 × × × × × × × ×
22 1 0 0 × × × × × × × ×
×: Don’t care.
Table 9.10.

74LS164 8 8 BIT SERIAL IN/ PARALLEL OUT SHIFT REGISTER
OBJECTIVES:
Fig. 9.16 shows the pin definitions of the 74LS164. The logic diagram and the truth table of the
74LS164 shift register are shown in Fig. 9.17 and in Table 9.11 respectively.
The 74LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of
the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be
used as an active HIGH enable for data entry through the other input. An unused input must be tied
HIGH, or both inputs connected together. Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q0 the logical AND of the two data inputs (A•B) that existed
before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs
and clears the register asynchronously, forcing all Q outputs LOW.
Fig. 9.16. Pin definitions of the 74LS164 shift register.


EXPERIMENT NO: 9.6

EXPERIMENT NAME: EXAMINATION OF THE 74LS164 8 BIT SERIAL IN/ PARALLEL
OUT SHIFT REGISTER
Equipment:
74LS164 8 bit serial in/ parallel out shift register 1 IC
Fig. 9.18.(a). The 74LS164 8 bit serial in/parallel out shift register circuit (74LS164_IC).
Fig. 9.18.(b). The 74LS164 8 bit serial in/parallel out shift register – application circuit.

Procedure:
power.
obtain the output values and take note of the output values in the Table. Whenever MR’ = 1, firstly
apply the inputs MR’, A, B as shown in the Table; then press the PULSE button to generate a clock
signal and observe the outputs Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7.
INPUTS OUTPUTS
CLOCK
MR’ A B Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
(CP)
0 0 × ×
1 1 1 1
2 1 1 1
3 1 1 1
4 1 1 1
5 1 0 1
6 1 0 1
7 1 1 1
8 1 1 1
9 1 1 0
10 1 1 0
11 1 1 0
12 1 1 0
13 1 0 1
14 0 × ×
15 1 1 1
16 1 1 1
17 1 1 1
18 1 1 1
19 1 1 1
20 1 1 1
21 1 1 1
22 1 1 1
×: Don’t care.
Table 9.12.

EXPERIMENT 10
MEMORY CIRCUITS: RAM, ROM
EQUIPMENT:

74LS04 Hex inverter gates 1
6116 2048x8 bit SRAM 1
28C16 2048x8 bit EEPROM 1
74LS244 Octal buffer/line driver with three state outputs 1

PRELIMINARY WORK:
3. (If possible) By means of a digital simulation software, test and verify the operation of the logic
circuits shown in the following table.
1 Fig. 10.4.(a). The circuit diagram for the examination of the 6116 2048x8 SRAM IC.
2 Fig. 10.6.(a). The circuit diagram for the examination of the 28C16 2048x8 EEPROM IC
3 Fig. 10.7.(a). The circuit diagram for erasing the 28C16 2048x8 EEPROM IC.

RAM (RANDOM ACCESS MEMORY) MEMORIES
OBJECTIVES:
1- Gaining information about memories,
3- Getting familiar with 6116 SRAM IC.
The digital circuits that digital data, output or elementary data can be stored in binary form are called
memory units. Memories can be divided into 2 subgroups; internal memory and external memory.
The internal memory is the main unit that is used inside the computer. For example, magnetic
memories, semiconductor memories etc. The external memories are the ones that help the internal
memories, such as floppy disks, hard discs etc. Semiconductor memories are divided into two groups:
1- RAM (Random Access Memory), 2- ROM (Read Only Memory)
RAM, is a kind of memory that can be both read and written. When the supply voltage is cut off, the
data in it is lost. However, ROM is a memory type that can only be read and when the supply voltage
is cut off the data in it is not lost. The two main forms of modern RAM are static RAM (SRAM) and
dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state of a flip-flop. This form of
RAM is more expensive to produce, but is generally faster and requires less power than DRAM and,
in modern computers, is often used as cache memory for the CPU. DRAM stores a bit of data using a
transistor and capacitor pair, which together comprise a memory cell. The capacitor holds a high or
low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on
the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to
produce than static RAM, it is the predominant form of computer memory used in modern computers.
Both static and dynamic RAMs are considered volatile, as their state is lost or reset when power is
removed from the system. By contrast, Read-only memory (ROM) stores data by permanently
enabling or disabling selected transistors, such that the memory cannot be altered. Writeable variants
of ROM (such as EEPROM and flash memory) share properties of both ROM and RAM, enabling
data to persist without power and to be updated without requiring special equipment. These persistent
forms of semiconductor ROM include USB flash drives, memory cards for cameras and portable
devices, etc.
ROM memory has many different programmable types: PROM (Programmable Read Only
Memory), EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically
Erasable Programmable Read Only Memory). EPROM is programmed by a special hardware and
erased with ultraviolet light. Also there is a MASK ROM type which is specially produced by the
manufacturers in huge volumes. Mask ROM is a type of ROM whose contents are programmed by the
integrated circuit manufacturer (rather than by the user). The terminology "mask" comes from
integrated circuit fabrication, where regions of the chip are masked off during the process of
photolithography.
In Fig. 10.1, the internal structure of a 16x8 RAM is shown. As it has 4 address inputs, it can address
24 = 16 registers. In total, 16 different input values can be applied to the address inputs (Table 10.1).
CS' (chip select) input is the IC select input and when it is at level "1" data can be neither written to
nor read from the RAM, i.e., the IC cannot be used. When CS' input is at level "0", data can be either
written to or read from the RAM. R/W' input is used to select read or write process. . When CS' input
is at level "0"; If R/W' input is at level "1" then RAM can be read. If R/W' is at level "0" then data can
be written to the RAM. Each register of the RAM shown in Fig. 10.1 has 8-bits. Therefore, data
inputs and data outputs have 8 pins. On some RAM devices, the inputs and outputs are separate as
shown in Fig. 10.1, on others; they are common, with the input and output using the same pin on the
memory device.

Writing to RAM:
When CS' and R/W' pins of the RAM are set to "0", RAM gets into the WRITE cycle. The input
buffers become open and output buffers become closed. 8-bit binary data are placed to the input pins
of the register that is chosen by the address select inputs. For example, if the address inputs are (A3
A2 A1 A0) = 0 0 0 1, then the REGISTER 1 is chosen. When the data inputs are provided as follows:
(D7 D6 D5 D4 D3 D2 D1 D0) = 1 0 0 0 0 0 0 1 1, these data are written to the REGISTER 1 of the
RAM. Later, when CS' = 0 and R/W' pin is set to "1", the RAM gets into the READ cycle. The input
buffers become closed and the output buffers become open. The data at the selected register whose
address is defined by the address inputs are send out to the data outputs. For example, let us read the
data that was written to the RAM in the previous step. First, CS' input is set to "0" and R/W' is set to
"1". The address of the register that is needed to be read is applied to the address input of the RAM.
According to the example, when "0 0 0 1" is applied to the address inputs (A3 A2 A1 A0) of the
RAM the previously written data, i.e. 1 0 0 0 0 0 0 1 1, is acquired.
As an SRAM example, the 6116 SRAM is considered. In addition 74LS244 octal buffer/line driver
with three state outputs is also used. Therefore these two ICs are briefly considered in the next
sections.
Fig. 10.1. The internal structure of a 16x8 RAM.

ADDRESS SELECT INPUTS

SELECTED REGISTER
A3 A2 A1 A0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Table 10.1. Possible address inputs and selected registers for a 16 x 8 RAM.
74LS244 – Octal Buffer/Line Driver with Three State Outputs

The 74LS244 is an octal bus buffer. It is a non-inverting 3-STATE buffer having two active-LOW
output enables, namely 1G’ and 2G’. These devices are designed to be used as 3-STATE memory
address drivers, clock drivers, and bus oriented transmitter/receivers. Fig. 10.3 shows the schematic
symbol, the truth table and the logic diagram of the 74LS244 IC. When the active low input 1G’
(respectively 2G’) is set to 0, the logic values applied to the inputs 1A1, 1A2, 1A3 and 1A4
(respectively 2A1, 2A2, 2A3 and 2A4) are send to the outputs 1Y1, 1Y2, 1Y3 and 1Y4 (respectively
2Y1, 2Y2, 2Y3 and 2Y4). When the active low input 1G’ (respectively 2G’) is set to 1, the inputs
1A1, 1A2, 1A3 and 1A4, (respectively 2A1, 2A2, 2A3 and 2A4) are electrically disconnected from
the outputs 1Y1, 1Y2, 1Y3 and 1Y4 (respectively 2Y1, 2Y2, 2Y3 and 2Y4).
Logic Diagram
Schematic Symbol
Fig. 10.3. The schematic symbol, the truth table and the logic diagram of the 74LS244 IC.

6116 – 2048x8 Bit SRAM IC

Fig. 10.2 shows the schematic symbol, the truth table and the logic diagram of the 6116 SRAM IC.
The 6116 is a 2048x8 bit SRAM with 11 address lines (A10, A9, A8, A7, A6, A5, A4, A3, A2, A1,
A0) and 8 data lines (I/O7, I/O6, I/O5, I/O4, I/O3, I/O2, I/O1, I/O0). It has three control pins, CS’
(Chip select), OE’ (Output enable), and WR’ (Write enable). All these control lines are active low. As
can be seen from the truth table when CS=1 the 6116 is not selected and input and output lines are in
high impedance condition. When CS=0, OE=0 and WE=1, the data are read from the 6116 (in this
case the inputs are in high impedance condition). When CS=0, OE=1 and WE=0 or CS=0, OE=0 and
WE=0, the data are written to the 6116 (in this case the outputs are in high impedance condition).
Schematic Symbol
Logic Diagram
Fig. 10.2. The schematic symbol, the truth table and the logic diagram of the 6116 2048x8 SRAM IC.

EXPERIMENT NO: 10.1

EXPERIMENT NAME: EXAMINATION OF THE 6116 SRAM IC
Equipment:
74LS244 Octal buffer/line driver with three state outputs 1 IC
6116 2048x8 bit SRAM 1 IC
Fig. 10.4.(a). The circuit diagram for the examination of the 6116 2048x8 SRAM IC.

Note2: Use the ON/ON SWITCH as the R/W’ input. To do so, connect the upper pin of the ON/ON
SWITCH to +5 V, the lower pin to GND and the middle pin to the related parts of the circuit.
Fig. 10.4.(b). The examination of the 6116 2048x8 SRAM IC – application circuit.

Procedure:
power.
NOTE: In this experiment, the operation of the 6116 SRAM IC is examined. As can be seen from Fig.
10.4.(a) when CS’=0 and OE’=0, the 6116 SRAM IC is in operation. In this case, R/W’ is used to
select the read or the write operation. When R/W’ =1 (respectively R/W’ =0), the read (respectively
the write) operation is selected. The data to be written to the 6116 SRAM are provided through the
data inputs D7, D6, D5, D4, D3, D2, D1, and D0, and by means of the 74LS244 IC. When R/W’ =0,
the data at the inputs (D7, D6, D5, D4, D3, D2, D1, and D0) are transferred to the outputs of the
74LS244 (and then to the input/output pins of the 6116 SRAM, namely I/O7, I/O6, I/O5, I/O4, I/O3,
I/O2, I/O1 and I/O0). It is possible to read or write data from the same input/output pins (I/O7, I/O6,
I/O5, I/O4, I/O3, I/O2, I/O1 and I/O0). When reading from the 6116 SRAM, the three state buffers of
the 74LS244 must be in high impedance condition. To do so, the R/W’ must be set to high (1). Then the
inputs and the outputs of the 74LS244 three state buffers are isolated. Finally when R/W’=1, the data
stored in the 6116 SRAM is read from the input/output pins (I/O7, I/O6, I/O5, I/O4, I/O3, I/O2, I/O1
and I/O0). The address inputs A3, A2, A1, A0 are used to select the address of the data to be read or to
be written. As there are only 4 address inputs established in the circuit shown in Fig. 10.4.(a), the
number of bytes to be written to or to be read from the 6116 SRAM are 16.
2. According to the given steps in Table 10.2 write the provided data to the given addresses of the
6116 SRAM. Since R/W’ = 0 (and also due to the connection of the circuit CS = 0 and OE = 0) the
data provided in the data inputs based on the address values will be written to the 6116 SRAM
immediately. Therefore, the data to be written must be provided through the data inputs D7, D6, D5,
D4, D3, D2, D1, and D0, before their address values (A3, A2, A1, A0). Repeat this process to write all
the data provided in the Table.
ADDRESS DATA TO BE WRITTEN TO 6116

STEPS R/W’ HEX HEX
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 11
2 0 0 0 1 0 2 0 0 1 0 0 0 1 0 22
3 0 0 0 1 1 3 0 0 1 1 0 0 1 1 33
4 0 0 1 0 0 4 0 1 0 0 0 1 0 0 44
5 0 0 1 0 1 5 0 1 0 1 0 1 0 1 55
6 0 0 1 1 0 6 0 1 1 0 0 1 1 0 66
7 0 0 1 1 1 7 0 1 1 1 0 1 1 1 77
8 0 1 0 0 0 8 1 0 0 0 1 0 0 0 88
9 0 1 0 0 1 9 1 0 0 1 1 0 0 1 99
10 0 1 0 1 0 A 1 0 1 0 1 0 1 0 AA
11 0 1 0 1 1 B 1 0 1 1 1 0 1 1 BB
12 0 1 1 0 0 C 1 1 0 0 1 1 0 0 CC
13 0 1 1 0 1 D 1 1 0 1 1 1 0 1 DD
14 0 1 1 1 0 E 1 1 1 0 1 1 1 0 EE
15 0 1 1 1 1 F 1 1 1 1 1 1 1 1 FF
Table 10.2.
3. After completing the write process. Now you are requested to read back the same set of data from
the 6116 SRAM. Follow the steps provided in Table 10.3, read all the data from the 6116 SRAM and
then record them in the Table. Since R/W’ = 1 (and also due to the connection of the circuit CS = 0 and

OE = 0) just change the address values, read and record the data in the Table. It is expected that the
data recorded in Table 10.3 will be the same as the ones in Table 10.2. If some values are different,
then go back and try to write the correct data to the related address until you obtain exactly the same
set of data.
ADDRESS DATA READ FROM 6116

A3 A2 A1 A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
0 1 0 0 0 0 0
1 1 0 0 0 1 1
2 1 0 0 1 0 2
3 1 0 0 1 1 3
4 1 0 1 0 0 4
5 1 0 1 0 1 5
6 1 0 1 1 0 6
7 1 0 1 1 1 7
8 1 1 0 0 0 8
9 1 1 0 0 1 9
10 1 1 0 1 0 A
11 1 1 0 1 1 B
12 1 1 1 0 0 C
13 1 1 1 0 1 D
14 1 1 1 1 0 E
15 1 1 1 1 1 F
Table 10.3.
4. Now there are two tasks to do. In the first one, you are expected to define your set of data to be
written to the 6116 SRAM in Table 10.4. Then write these data to the SRAM as you did in the 2 nd
procedure.
ADDRESS DATA TO BE WRITTEN TO 6116

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0
1 0 0 0 0 1 1
2 0 0 0 1 0 2
3 0 0 0 1 1 3
4 0 0 1 0 0 4
5 0 0 1 0 1 5
6 0 0 1 1 0 6
7 0 0 1 1 1 7
8 0 1 0 0 0 8
9 0 1 0 0 1 9
10 0 1 0 1 0 A
11 0 1 0 1 1 B
12 0 1 1 0 0 C
13 0 1 1 0 1 D
14 0 1 1 1 0 E
15 0 1 1 1 1 F
Table 10.4.

5. Having completed the writing process of the data to the 6116 SRAM in the previous procedure, now
you are requested to read back the same set of data from the 6116 SRAM. To do so follow the steps
provided in Table 10.5, read all the data the 6116 SRAM and then record them in the Table as you did
in the 3rd procedure. It is expected that the data recorded in Table 10.5 will be the same as the ones in
Table 10.4. If some values are different, then go back and try to write the correct data to the related
address until you obtain exactly the same set of data.
ADDRESS DATA READ FROM 6116

0 1 0 0 0 0 0
1 1 0 0 0 1 1
2 1 0 0 1 0 2
3 1 0 0 1 1 3
4 1 0 1 0 0 4
5 1 0 1 0 1 5
6 1 0 1 1 0 6
7 1 0 1 1 1 7
8 1 1 0 0 0 8
9 1 1 0 0 1 9
10 1 1 0 1 0 A
11 1 1 0 1 1 B
12 1 1 1 0 0 C
13 1 1 1 0 1 D
14 1 1 1 1 0 E
15 1 1 1 1 1 F
Table 10.5.
6. If you have read all the data correctly in the previous procedure then turn ON the POWER ON/OFF
switch and keep it in this position for about 10 seconds. Then turn it ON. Try to read the all data from
the 6116 SRAM. Can you read the same data? Explain why?
Note: Do not remove the connections you have done for this experiment from the protoboard as
you will need the same connections in the next experiment. In the next experiment you will replace
the 6116 SRAM with the 28C16 EEPROM and you will change a few wires.

ROM (EEPROM) MEMORIES
OBJECTIVES:
1- Analysing PROM (EPROM) memory,
3- Getting familiar with 28C16 EEPROM IC.
EPROMs are special PROMs and can be erased and written many times when necessary. A
special kind of MOSFET cell is used in the EPROMs. In the programming, the charge is stored
in all cells. However, with a special modification the data is kept constantly. UV (Ultra Violet)
lights are exposed on the transparent window of the EPROM in order to erase the data from the
static memory. The radiation at this moment increases the conductivity of the cells and causes
discharge. As the radiation is applied to all the cells in the matrix system, all the data in the
EPROM are erased. 28C16 IC is a 16834-bit read-write memory which can be electrically
programmable and electrically erasable. It is a kind of memory that works with single 5 V DC
supply voltage and has a property to get into low static power mode and fast single address
programmability. These properties enable the EEPROM to work faster, easier and more
economical. Its pin diagram is similar to 2716 EPROM and 6116 RAM. As 28C16 is supplied
from a single 5 V DC voltage source it can work compatibly with high performance
microprocessors and microcontrollers.
Fig. 10.5 shows the schematic symbol, the truth table and the logic diagram of the 28C16
2048x8 bit EEPROM IC. It has 11 address lines (A10, A9, A8, A7, A6, A5, A4, A3, A2, A1,
A0), 8 data lines (I/O7, I/O6, I/O5, I/O4, I/O3, I/O2, I/O1, I/O0), active low CE’ (chip
enable), OE’ (output enable) and WE’ (write enable) control inputs. The address inputs (A10-
A0) select an 8-bit memory location during a read or write operation. Data are written to or read
from the 28C16 through the I/O pins (I/O7-I/O0). The chip enable input (CE’) must be low to
enable all read/write operations. When chip enable (CE’) is high, power consumption is reduced.
The output enable input (OE’) controls the data output buffers and is used to initiate read
operations. The write enable input (WE’) controls the writing of data to the 28C16. The 28C16 is
accessed like an SRAM. When CE’ and OE’ are low with WE’ high, the data addressed are
presented on the I/O pins. The I/O pins are high impedance when either OE’ or CE’ is high.
Write operations are initiated when both WE’ and CE’ are low and OE’ is high. The 28C16
supports both CE’ and WE’ controlled write cycles. The address is latched by the falling edge
() of CE’ or WE’ whichever occurs last and the data on the rising edge of () CE’ or WE’
whichever occurs first. Once initiated the write operation is internally timed until completion.
The write operation takes about 0,5 – 1 ms to complete. The contents of the entire memory may
be erased to FFh by use of the Chip Erase command by setting Chip Enable (CE’) low and
Output Enable (OE’) to VCC +12V. The entire chip is cleared when a 10 ms low pulse () is
applied to the Write Enable (WE’) pin.

Truth Table
Schematic Symbol
Logic Diagram
Fig. 10.5. The schematic symbol, the truth table and the logic diagram of the 28C16 2048x8
EEPROM.

EXPERIMENT NAME : EXAMINATION OF THE 28C16 EEPROM IC
Equipment:
74LS244 Octal buffer/line driver with three state outputs 1 IC
28C16 2048x8 bit EEPROM 1 IC
Fig. 10.6.(a). The circuit diagram for the examination of the 28C16 2048x8 EEPROM IC.

Note2: Use the ON/ON SWITCH as the OE’ input. To do so, connect the upper pin of the ON/ON
SWITCH to +5 V, the lower pin to GND and the middle pin to the related parts of the circuit.
Fig. 10.6.(b). The examination of the 28C16 2048x8 EEPROM IC – application circuit.

Procedure:
power. This circuit is similar to the one considered in the previous experiment where the 6116 SRAM
IC was examined.
NOTE: In this experiment, the operation of the 28C16 EEPROM IC is examined. As can be seen from
Fig. 10.6.(a) when CE’=0, the 28C16 IC is in operation. When CE’=0, to select either read or write
operation, control inputs OE’ and WE’ are used together. When CE’=0, if OE’=0 and WE’ =1, then
read operation is carried out. When reading from the 28C16 EEPROM, the three state buffers of the
74LS244 must be in high impedance condition. To do so, the OE’ input must be set to low (0). Then the
inputs and the outputs of the 74LS244 three state buffers are isolated. Finally when OE’=0, the data
stored in the 28C16 EEPROM is read from the input/output pins (I/O7, I/O6, I/O5, I/O4, I/O3, I/O2,
I/O1 and I/O0).The data to be written to the 28C16 are provided through the data inputs D7, D6, D5,
D4, D3, D2, D1, and D0, and then by means of the 74LS244 IC. When CE’=0, if OE’=1 and WE’ =1,
the data at the inputs (D7, D6, D5, D4, D3, D2, D1, and D0) are transferred to the outputs of the
74LS244 (and then to the input/output pins of the 28C16 EEPROM, namely I/O7, I/O6, I/O5, I/O4,
I/O3, I/O2, I/O1 and I/O0). In this case a low pulse () applied to the WE’ input will write the data
provided in the inputs to the selected register of the 28C16 EEPROM. It is possible to read or write
data from the same input/output pins (I/O7, I/O6, I/O5, I/O4, I/O3, I/O2, I/O1 and I/O0). The address
inputs A3, A2, A1, A0 are used to select the address of the data to be read or to be written. As there
are only 4 address inputs established in the circuit shown in Fig. 10.6.(a), the number of bytes to be
written to or to be read from the 28C16 EEPROM are 16.
To initiate a write operation for the 28C16 EEPROM IC the steps provided below must be followed:
write operation steps to write a byte in the 28C16 EEPROM:

1- Address is applied.
2- Data are provided.
3- While CE’=0, OE’=1 and WE’=1, apply WE’=0, i.e. (WE).
4- WE’= 1.
5- OE’= 0.

2. According to the given steps in Table 10.6 write the provided data to the given addresses of the
28C16 EEPROM. To write the provided data to the 28C16 EEPROM follow the write-operation-steps
provided above. Repeat this operation for each data byte given in the Table 10.6.
ADDRESS DATA TO BE WRITTEN TO 28C16

STEPS HEX HEX
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 1 0 0 0 1 0 0 0 88
1 0 0 0 1 1 1 0 0 1 1 0 0 1 99
2 0 0 1 0 2 1 0 1 0 1 0 1 0 AA
3 0 0 1 1 3 1 0 1 1 1 0 1 1 BB
4 0 1 0 0 4 1 1 0 0 1 1 0 0 CC
5 0 1 0 1 5 1 1 0 1 1 1 0 1 DD
6 0 1 1 0 6 1 1 1 0 1 1 1 0 EE
7 0 1 1 1 7 1 1 1 1 1 1 1 1 FF
8 1 0 0 0 8 0 0 0 0 0 0 0 0 00
9 1 0 0 1 9 0 0 0 1 0 0 0 1 11
10 1 0 1 0 A 0 0 1 0 0 0 1 0 22
11 1 0 1 1 B 0 0 1 1 0 0 1 1 33
12 1 1 0 0 C 0 1 0 0 0 1 0 0 44
13 1 1 0 1 D 0 1 0 1 0 1 0 1 55
14 1 1 1 0 E 0 1 1 0 0 1 1 0 66
15 1 1 1 1 F 0 1 1 1 0 1 1 1 77
Table 10.6.

3. After completing the write process. Now you are requested to read back the same set of data from
the 28C16 EEPROM. Follow the steps provided in Table 10.7, read all the data the 28C16 EEPROM
and then record them in the Table. Since OE’= 0, and WE’=1 (and also due to the connection of the
circuit CE’ = 0) just change the address values, read and record the data in the Table. It is expected that
the data recorded in Table 10.7 will be the same as the ones in Table 10.6. If some values are different,
then go back and try to write the correct data to the related address until you obtain exactly the same
set of data.
ADDRESS DATA READ FROM 28C16

STEPS HEX HEX
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 1 0 1 0 A
11 1 0 1 1 B
12 1 1 0 0 C
13 1 1 0 1 D
14 1 1 1 0 E
15 1 1 1 1 F
Table 10.7.

4. Now there are two tasks to do. In the first one, you are expected to define your set of data to be
written to the 28C16 EEPROM in Table 10.8. Then write these data to the EEPROM as you did in the
2nd procedure.
ADDRESS DATA TO BE WRITTEN TO 28C16

STEPS HEX HEX
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 1 0 1 0 A
11 1 0 1 1 B
12 1 1 0 0 C
13 1 1 0 1 D
14 1 1 1 0 E
15 1 1 1 1 F
Table 10.8.
5. Having completed the writing process of the data to the 28C16 EEPROM in the previous procedure,
now you are requested to read back the same set of data from the 28C16 EEPROM. To do so follow
the steps provided in Table 10.9, read all the data from the 28C16 EEPROM and then record them in
the Table as you did in the 3rd procedure. It is expected that the data recorded in Table 10.9 will be the
same as the ones in Table 10.8. If some values are different, then go back and try to write the correct
data to the related address until you obtain exactly the same set of data.


STEPS HEX HEX
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 1 0 1 0 A
11 1 0 1 1 B
12 1 1 0 0 C
13 1 1 0 1 D
14 1 1 1 0 E
15 1 1 1 1 F
Table 10.9.
6. If you have read all the data correctly in the previous procedure then turn ON the POWER ON/OFF
switch and keep it in this position for about 10 seconds. Then turn it ON. Try to read all the data from
the 28C16 EEPROM. Can you read the same data? Explain why?
Note: Do not remove the connections you have done for this experiment from the protoboard as
you will need the same connections in the next experiment (Erasing the 28C16 EEPROM).

EXPERIMENT NAME : ERASING THE 28C16 EEPROM IC
Equipment:
28C16 2048x8 bit EEPROM 1 IC
Fig. 10.7.(a). The circuit diagram for erasing the 28C16 2048x8 EEPROM IC.
In addition, connect the GND pin and “0” pin of the DC POWER SUPPLY.
Fig. 10.7.(b). Erasing the 28C16 2048x8 EEPROM IC – application circuit.

Procedure:
1. Draw the application circuit in Fig. 10.7.(b) based on the circuit given in Fig. 10.7.(a).
2. Turn OFF the POWER ON/OFF switch. Just remove the 28C16 EEPROM from the protoboard and
leave the rest of the circuit as it is. Then place the 28C16 EEPROM in another part of the protoboard.
Construct the circuit as drawn by you in Fig. 10.7.(b) and apply the power (Turn ON the POWER
ON/OFF switch).
3. As explained before all stored data in the 28C16 EEPROM can be erased by chip erase operation.
When CE’=0, OE=12V DC, if a 10 ms low pulse is applied to the Write Enable (WE’) pin then the
entire chip is erased. Therefore press the PULSE button once. Then the 28C16 EEPROM will be
erased.
4. Turn OFF the POWER ON/OFF switch and remove the 28C16 EEPROM from where it is and put
it back to the previous circuit as shown in Fig. 10.6.(b).
5. Turn ON the POWER ON/OFF switch and read the data from the 28C16 EEPROM and record
these data in Table 10.10. In this case keep the control inputs as follows: OE’=0 (due to the circuit
CE’=0) and WE’=1.

STEPS HEX HEX
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 1 0 1 0 A
11 1 0 1 1 B
12 1 1 0 0 C
13 1 1 0 1 D
14 1 1 1 0 E
15 1 1 1 1 F
Table 10.10.
6. Are all the read values 0? Why?

EXPERIMENT 11
ARITHMETIC LOGIC UNIT
EQUIPMENT:
2- Integrated Circuit (IC) and electronic component:

74LS181 4 bit ALU 1
10 KΩ resistor 1

PRELIMINARY WORK:
3. By means of a digital simulation software, test and verify the operation of the logic circuit shown in
the following table
Fig. 11.3.(a). The circuit diagram for the examination of the 74LS181 ALU IC (74LS181).
4. As preliminary work you are obliged to draw by hand using pencils an application circuit provided
in Fig. 11.3.(b) for each schematic diagram given in Fig. 11.3.(a). It is recommended that you use red

ARITHMETIC LOGIC UNIT - ALU
OBJECTIVES:
1- Gaining information about the ALU which is a fundamental building block of the central processing
unit of a microprocessor and a microcontroller,
2- Getting familiar with 74LS181 ALU IC.
An arithmetic logic unit (ALU) is a major component of the central processing unit of a computer
system. It does all processes related to arithmetic and logic operations that need to be done on
instruction words. In some microprocessor architectures, the ALU is divided into the arithmetic unit
(AU) and the logic unit (LU).
ALUs routinely perform the following operations:
 Logical Operations: These include AND, OR, NOT, XOR, NOR, NAND, etc.
 Bit-Shifting Operations: This pertains to shifting the positions of the bits by a certain number
of places to the right or left, which is considered a multiplication operation.
 Arithmetic Operations: This refers to bit addition and subtraction. Although multiplication and
division are sometimes used, these operations are more expensive to make. Addition can be
used to substitute for multiplication and subtraction for division.
74LS181 Arithmetic Logic Unit
The 74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four
Function Select inputs (S3, S2, S1 and S0) and the Mode Control input (M), it can perform all the 16
possible logic operations or 16 different arithmetic operations on active HIGH or active LOW
operands. Fig. 11.1 shows the schematic symbol and the function tables of the 74LS181 ALU IC. The
logic diagram of the 74LS181 ALU IC is given in Fig. 11.2. When the Mode Control input (M) is
HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits
as listed. When the Mode Control input is LOW, the carries are enabled and the device performs
arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and
provides for either ripple carry between devices using the Cn+4 output, or for carry lookahead between
packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD mode, P’
indicates that F’ is 15 or more, while G’ indicates that F’ is 16 or more. In the SUBTRACT mode, P’
indicates that F’ is zero or less, while G’ indicates that F’ is less than zero. P’ and G’ are not affected
by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by
connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high speed
operation the 74LS181 is used in conjunction with 74LS182 carry lookahead circuit. One carry
lookahead package is required for each group of four 74LS181 devices. Carry lookahead can be
provided at various levels and offers high speed capability over extremely long word lengths. The A =
B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate
logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-
collector and can be wired-AND with other A = B outputs to give a comparison for more than four
bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The
Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry
adds a one to each operation. Thus, select code S3S2S1S0=0110 generates A minus B minus 1 (2s
complement notation) without a carry in and generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition (1s complement), a carry out means
borrow; thus a carry is generated when there is no underflow and no carry is generated when there is
underflow. As indicated, this device can be used with either active LOW inputs producing active LOW
outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the
operations that are performed to the operands labeled inside the logic symbol.

Schematic Symbol
Fig. 11.1. The schematic symbol and the function tables of the 74LS181 ALU IC.

Fig. 11.2. The logic diagram of the 74LS181 ALU IC.

EXPERIMENT NO: 11.1

EXPERIMENT NAME: EXAMINATION OF THE 74LS181 ALU IC
Equipment:
2. Integrated Circuit (IC) and electronic component:
74LS181 4 bit ALU 1 IC
10 KΩ resistor 1 resistor
Fig. 11.3.(a). The circuit diagram for the examination of the 74LS181 ALU IC (74LS181).
Note2: Use the ON/ON SWITCH as the Cn input. To do so, connect the upper pin of the ON/ON
SWITCH to +5 V, the lower pin to GND and the middle pin to the Cn input.
Note3: Use the ON/0/ON SWITCH as the M input. To do so, connect the upper pin of the ON/ON
SWITCH to +5 V, the lower pin to GND and the middle pin to the M input.
Fig. 11.3.(b). The examination of the 74LS181 ALU IC – application circuit.

Procedure:
power.
2. Apply the inputs as shown in Table 11.1 and obtain and take note of the outputs in the Table.
(As M=1, here logic operations are carried out)
INPUTS OUTPUTS
S A B F
M Cn Cn+4 A=B
S3 S2 S1 S0 A3 A2 A1 A0 B3 B2 B1 B0 F3 F2 F1 F0
1 × 0 0 0 0 0 1 1 0 × × × × × ×
1 × 0 0 0 0 0 1 0 1 × × × × × ×
1 × 0 0 0 1 0 0 1 0 1 0 0 1 × ×
1 × 0 0 0 1 0 0 1 0 1 0 1 0 × ×
1 × 0 0 1 0 0 1 0 0 1 0 1 1 × ×
1 × 0 0 1 0 0 1 0 1 1 1 0 0 × ×
1 × 0 0 1 1 × × × × × × × × × ×
1 × 0 1 0 0 1 0 1 0 1 1 1 1 × ×
1 × 0 1 0 0 1 0 0 1 0 0 1 0 × ×
1 × 0 1 0 1 × × × × 0 1 1 1 × ×
1 × 0 1 0 1 × × × × 1 0 1 0 × ×
1 × 0 1 1 0 1 1 0 0 0 0 1 1 × ×
1 × 0 1 1 0 1 1 0 1 0 1 0 1 × ×
1 × 0 1 1 1 1 1 1 0 0 1 0 1 × ×
1 × 0 1 1 1 1 1 1 1 0 1 1 0 × ×
1 × 1 0 0 0 0 0 0 1 0 1 1 0 × ×
1 × 1 0 0 0 0 1 0 1 1 0 1 0 × ×
1 × 1 0 0 1 0 0 1 0 1 0 0 1 × ×
1 × 1 0 0 1 0 0 1 1 1 0 1 0 × ×
1 × 1 0 1 0 × × × × 1 0 1 1 × ×
1 × 1 0 1 0 × × × × 1 1 0 0 × ×
1 × 1 0 1 1 0 1 1 0 1 1 0 1 × ×
1 × 1 0 1 1 0 1 1 1 1 1 1 0 × ×
1 × 1 1 0 0 × × × × × × × × × ×
1 × 1 1 0 1 1 0 1 0 0 0 0 1 × ×
1 × 1 1 0 1 1 0 1 1 1 1 1 0 × ×
1 × 1 1 1 0 0 1 0 0 0 0 1 0 × ×
1 × 1 1 1 0 0 1 0 1 0 1 0 0 × ×
1 × 1 1 1 1 1 0 0 0 × × × × × ×
1 × 1 1 1 1 0 1 0 0 × × × × × ×
×: Don’t care.
Table 11.1.
NOTE: Both A and B inputs must be considered as active high.

3. Apply the inputs as shown in Table 11.2 and obtain and take note of the outputs in the Table.
(As M=0, here arithmetic operations are carried out)
INPUTS OUTPUTS
S A B F
M Cn Cn+4 A=B
0 1 0 0 0 0 0 1 1 0 × × × × ×
0 0 0 0 0 0 0 1 1 0 × × × × ×
0 1 0 0 0 1 0 0 1 0 1 0 0 1 ×
0 0 0 0 0 1 0 0 1 0 1 0 1 0 ×
0 1 0 0 1 0 0 1 0 0 1 0 1 1 ×
0 0 0 0 1 0 0 1 0 1 1 1 0 0 ×
0 1 0 0 1 1 × × × × × × × × ×
0 0 0 0 1 1 × × × × × × × × ×
0 1 0 1 0 0 1 0 1 0 0 0 1 1 ×
0 0 0 1 0 0 1 0 0 1 0 0 1 0 ×
0 1 0 1 0 1 0 1 0 0 0 1 1 1 ×
0 0 0 1 0 1 0 1 0 1 1 0 1 0 ×
0 1 0 1 1 0 1 1 0 0 0 0 1 1 ×
0 0 0 1 1 0 0 1 0 1 1 1 0 1 ×
0 1 0 1 1 1 1 1 1 0 0 1 0 1 ×
0 0 0 1 1 1 1 1 1 1 0 1 1 0 ×
0 1 1 0 0 0 0 1 0 1 0 1 1 0 ×
0 0 1 0 0 0 0 1 1 1 1 0 1 0 ×
0 1 1 0 0 1 0 0 1 0 1 0 0 1 ×
0 0 1 0 0 1 0 0 1 1 1 0 1 0 ×
0 1 1 0 1 0 1 0 0 1 1 0 1 1 ×
0 0 1 0 1 0 1 0 1 0 1 1 0 0 ×
0 1 1 0 1 1 0 1 1 0 1 1 0 1 ×
0 0 1 0 1 1 0 1 1 1 1 1 1 0 ×
0 1 1 1 0 0 1 0 0 1 × × × × ×
0 0 1 1 0 0 1 1 0 1 × × × × ×
0 1 1 1 0 1 1 0 1 0 0 0 0 1 ×
0 0 1 1 0 1 1 0 1 1 1 1 1 0 ×
0 1 1 1 1 0 0 1 0 0 0 0 1 0 ×
0 0 1 1 1 0 0 1 0 1 0 1 0 0 ×
0 1 1 1 1 1 1 0 1 0 × × × × ×
0 0 1 1 1 1 0 1 0 1 × × × × ×
×: Don’t care.
Table 11.2.

In this case if Cn=1 then this shows the absence of the carry input.
if Cn=0 then this shows the presence of the carry input.

4. Apply the inputs as shown in the Table 11.3 and obtain and take note of the outputs in the Table.
(As M=0, Cn=1 and S3S2S1S0=0110, here A and B are compared)
INPUTS OUTPUTS
S A B F
M Cn Cn+4 A=B B / L / E*
0 1 0 1 1 0 1 1 0 0 0 0 1 1
0 1 0 1 1 0 0 1 0 1 0 1 0 1
0 1 0 1 1 0 1 1 0 0 0 1 0 1
0 1 0 1 1 0 0 1 0 1 0 1 1 1
0 1 0 1 1 0 1 1 0 0 1 0 0 1
0 1 0 1 1 0 1 1 0 1 1 1 0 1
0 1 0 1 1 0 1 1 0 0 0 1 0 1
0 1 0 1 1 0 0 1 0 1 1 1 1 0
Table 11.3.
In this case, as Cn=1 the carry input is absent.
Operation carried out is (A minus B minus 1)
*A is
B / L / E : Bigger than / Less than / Equal to
B
In the table put one of these three letters based on the comparison results you obtained.

EXPERIMENT 12
DIGITAL TO ANALOG CONVERTERS – DAC

ANALOG TO DIGITAL CONVERTERS – ADC
EQUIPMENT:
2. Integrated circuits (ICs) and other electronic components:

ADC0804 8 bit ADC 1
DAC0800 8 bit DAC 1
LM741 Op-amp 1
150 pF Capacitor 1
0.01 F Capacitor 1
10 F Capacitor 1
4.7 KΩ Resistor 3
10 KΩ Resistor 1
10 KΩ Potentiometer (variable resistor). 1
It exists on the Y-0016 main unit
START switch Use the lower two pins of the ON/ON 1
(normally open contact) SWITCH as the START switch
Multimeter To measure current and/or voltage 1

PRELIMINARY WORK:
3. (If possible) By means of a digital simulation software, test and verify the operation of the circuits
shown in the following table.
Fig. 12.13.(a). The test circuit for the DAC0800 8 bit digital to analog converter.
Fig. 12.20.(a) The test circuit for the ADC0804 8 bit analog to digital converter.
Fig. 12.22.(a). The test circuit for the digital data transmission using the ADC0804 and the DAC0800.

DIGITAL TO ANALOG CONVERTERS

OBJECTIVES:
1- Learning operation principles of DACs.
2- Getting familiar with DAC0800 IC.
Connecting digital circuitry to sensor devices is simple if the sensor devices are inherently digital
themselves. Switches, relays, and encoders are easily interfaced with gate circuits due to the on/off
nature of their signals. However, when analog devices are involved, interfacing becomes much more
complex. What is needed is a way to electronically translate analog signals into digital (binary)
quantities, and vice versa. An analog-to-digital converter, or ADC, performs the former task while a
digital-to-analog converter, or DAC, performs the latter.
An ADC inputs an analog electrical signal such as voltage or current and outputs a binary number. In
block diagram form, it can be represented as shown in Fig. 12.1.
Fig. 12.1. The block diagram of the Analog to Digital Converter (ADC).
A DAC, on the other hand, inputs a binary number and outputs an analog voltage or current signal. In
block diagram form, it looks like as shown in Fig. 12.2.
Fig. 12.2. The block diagram of the Digital to Analog Converter (DAC).

Together, they are often used in digital systems to provide complete interface with analog sensors and
output devices for control systems such as those used in automotive engine controls. Fig. 12.3 shows
the block diagram of a digital control system with analog I/O (input/output).
Fig. 12.3. The block diagram of a digital control system with analog I/O.
It is much easier to convert a digital signal into an analog signal than it is to do the reverse. Therefore,
we will begin with DAC circuitry and then move to ADC circuitry.
Digital to Analog Converter (DAC)

In electronics, a digital-to-analog converter (DAC or D-to-A) is a device that converts a digital
(usually binary) code to an analog signal. The analog output signal (current or voltage) obtained from
the conversion is proportional to the applied digital input signal. For example, Fig. 12.4 shows the
simplified functional diagram of a 4 bit DAC and its value table.
Digital inputs Analog outputs

D3 D2 D1 D0 Vout
0 0 0 0 0 Volt
0 0 0 1 1 Volt
0 0 1 0 2 Volt
0 0 1 1 3 Volt
0 1 0 0 4 Volt
0 1 0 1 5 Volt
0 1 1 0 6 Volt
0 1 1 1 7 Volt
1 0 0 0 8 Volt
1 0 0 1 9 Volt
1 0 1 0 10 Volt
1 0 1 1 11 Volt
1 1 0 0 12 Volt
1 1 0 1 13 Volt
1 1 1 0 14 Volt
1 1 1 1 15 Volt
Fig. 12.4. A simplified functional diagram of a 4 bit DAC and its value table.

In Fig. 12.4, digital inputs D3, D2, D1, and D0 may be taken from the output register of a digital
system. As there are 4 inputs, 24=16 different output values can be produced as shown in the value
table. Ideally, a DAC should produce a linear relationship between a digital input and the analog
output. The DAC is designed to produce an analog voltage that is equivalent to the binary number
applied to its digital inputs. For example for digital inputs D3D2D1D0 = 1111, the output voltage is
Vout=15 Volt.
Fig. 12.5. A 4 bit DAC with a 4 bit counter connected to its digital inputs and the waveform of the
output voltage.
Fig. 12.5 shows a counter circuit that produces as incremental sequence of binary numbers from 0000
to 1111. When highest binary number 1111 (or 15 in decimal) is reached, the counter will recycle to
0000 and begin incrementing again. The waveform shows this behaviour. In this waveform two
important parameters of a DAC are shown. The first one is the step size.
maximum DAC output

Step size = 2n − 1
The second important parameter is the percent resolution, which indicates the smallest increment of
DAC’s output corresponding to a 1 LSB input code change. It is obtained as follows:
step size
percent resolution = maximum DAC output
1V
In the circuit shown in Fig. 12.5 the percent resolution is: = 15 V = 6,7 %
For example for a 10 bit DAC, 210 = 1024 codes, the percent resolution is 1/1024 = 0,097 % of the
output range.
The output of the digital-analog converter “Vo” is obtained as follows:
Vo = Step size x number of steps
The structure of the digital-analog converter is seen from Fig. 12.6. No element other than resistor
group is needed if current is used as an output signal. An Op-Amp circuit should be used if voltage is
used as the output signal. Digital-to-analog converters are analyzed in two groups according to the
connection of the resister group: the weighted resistor DAC and the R-2R ladder network DAC.

Fig. 12.6. The general structure of DAC.
Binary Weighted Resistor DAC
In Fig. 12.7, a 4 bit binary weighted resistor DAC is shown. Op-amp is the main element of the circuit.
If “R” is used for the most significant bit, “2n . R” should be used for the other inputs. Here “n” is the
number of steps. Step number of the most significant bit is “0” and step number of the least significant
bit is “3” if the circuit is 4 bit. Each input is applied to resistors with different values. Input number of
a 4 bit circuit is 24 =16. So, 16 different analog output signals which are multiple of each other can be
obtained. In order to obtain accurate results in binary weighted resistor DAC, the standard resistors
should be used. This is usually the simplest textbook example of a DAC. However, this DAC is not
inherently monotonic and is actually quite hard to manufacture successfully at high resolutions due to
the large spread in component (resistor) values. In addition, the output impedance of the voltage mode
binary weighted resistor DAC changes with the input code.
Fig. 12.7. A 4 bit binary weighted resistor DAC.
R-2R Ladder Network DAC
The circuit shown in Fig. 12.8 is a 4 bit R-2R ladder type DAC. It is actually just a variant of a simple
op-amp summer circuit, i.e., an operational amplifier configured to output a voltage that is proportional
to the sum of the input voltages (Fig. 12.7). In this circuit, the inputs are binary weighted with respect
to each other, with the binary weighting of the inputs achieved by the R-2R ladder resistor network at
the non-inverting input of the op-amp.
As its name implies, the R-2R network consists of resistors with only two values, R and 2R (for
example 10K and 20K, respectively). The output Vo of the 4-bit R-2R ladder DAC in Fig. 12.8 is:
RF D3 D2 D1 D0
Vo = × Vref × [ + + + 16 ] Volt
R 2 4 8

where D3, D2, D1, and D0 are the logic inputs ('1' or '0') for bits 3, 2, 1, and 0, respectively. To form
converters with higher resolution it is necessary to add more R/2R resistors and switches above D3.
Commercially available DACs with resolutions of 8, 10, 12 are commonly made this way.
Fig. 12.8. 4 bit R-2R ladder type DAC.
(a)
(b)
Fig. 12.9. R-2R ladder networks for two different binary inputs.

To understand how the R-2R ladder networks works consider Fig. 12.9, where VR output voltage is
calculated for two different binary inputs in an R-2R ladder network. In Fig. 12.9.(a), when binary
inputs are D3D2D1D0 = 1000, VR = Vref/2. Likewise, In Fig. 12.9.(b), when binary inputs are
D3D2D1D0 = 0010, VR = Vref/8.
DAC0800 IC
Digital-to-analog converter ICs are widely used. The DAC0800 is an example DAC IC for an “R-2R”
ladder method. The DAC0800, whose schematic symbol is given in Fig. 12.10, is a monolithic 8-bit
high-speed current-output digital-to-analog converter (DAC) featuring typical settling times of 100 ns.
When used as a multiplying DAC, monotonic performance over a 40 to 1 reference current range is
possible. The DAC0800 also features high compliance complementary current outputs to allow
differential output voltages of 20 Vp-p with simple resistor loads. The reference-to-full-scale current
matching of better than ±1 LSB eliminates the need for full-scale trims in most applications, while the
nonlinearities of better than ±0.1% over temperature minimizes system error accumulations. The noise
immune inputs will accept a variety of logic levels. The performance and characteristics of the device
are essentially unchanged over the ±4.5V to ±18V power supply range and power consumption at only
33 mW with ±5V supplies is independent of logic input levels. D7, D6, D5, D4, D3, D2, D1, and D0
are 8 bit digital inputs. IOUT and IOUT’ are two analog current outputs
Fig. 12.10. The schematic symbol of the DAC0800 IC.
Fig. 12.11. The block diagram of the DAC0800 IC.

The block diagram of the DAC0800 IC is shown in Fig. 12.11, while Fig. 12.12 shows a test circuit for
the DAC0800 IC which will be used in this experiment.
Fig. 12.12. A test circuit for the DAC0800 IC.
The output voltage has a single polarisation. In other words output voltage is always positive with
respect to the ground. So that, these type of connections are called unipolar. The reference current
passing through resistor R1 is;
VR
IR 
R1
The output current from pin 4 is:
VR  D7 D6 D5 D4 D3 D2 D1 D0 
IOUT          
R1  2 4 8 16 32 64 128 256 
D7, D6, D5, D4, D3, D2, D1, and D0 can take the values 0 or 1. The operation amplifier (Op-amp) is
used to convert the output current to the output voltage.
The output voltage of the circuit is
Vo = IOUT.RF

EXPERIMENT NO: 12.1

EXPERIMENT NAME: EXAMINATION OF THE DIGITAL TO ANALOG CONVERTER
(DAC)
Equipment:
1. Y-0016 main unit
DAC0800 8 bit DAC 1
LM741 Op-amp 1
4.7 KΩ Resistor 3
Fig. 12.13.(a). The test circuit for the DAC0800 8 bit digital to analog converter.

Note1: Do not forget to connect the V– pin to -12 V DC, the V+ pin to +12 V DC.
Note2: Do not forget to connect the +5 V and the GND ( ) connections.
Note3: You must connect the “0” pin of the SYMETRIC POWER SUPPLY and the GND pin of the
DC power supply by means of a connection wire.
Fig. 12.13.(b). The test circuit for the DAC0800 8 bit digital to analog converter – application circuit.
Procedure:
power.
2. Apply the digital inputs as shown in Table 12.1. Then for each applied digital input measure the
analog output voltage Vout and the output current IOUT by means of a multimeter and record it in the
table.
DIGITAL INPUTS
Vout (VOLT) IOUT
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Table 12.1.
Note: Leave the circuit as it is on the breadboard, because you will use it in the experiment 12.3.

ANALOG TO DIGITAL CONVERTERS
OBJECTIVES:
1- Learning operation principles of ADCs.
2- Getting familiar with the ADC0804 IC.
If the values of a variable change say between “0” and “1”, and the values like “0,1 0,2 … 0,9” can be
observed via using a voltmeter, an ammeter or a similar device, this variable is an analog signal. If the
variable takes only the discrete values “0” or “1”, in other words if it can take values in between, it is
called a digital signal. If a device or circuit converts analog signal to digital, it is called analog to
digital converter (ADC). Digital signals prevent the effect of noise. They are easily coded and stored.
An ADC must be able to sample an analog electrical signal (voltage or current) and produce a
corresponding digital code of N bits. This involves a three step process: (1) discretization of a
continuous analog signal into exact samples at discrete times, (2) quantization of the analog signal into
a finite number of states, and (3) encoding of the states into an N-bit digital code.
An ideal ADC uniquely represents all analog inputs within a certain range by a limited number of
digital output codes. The diagram in Fig. 12.14 shows that each digital code represents a fraction of the
total analog input range. Since the analog scale is continuous, while the digital codes are discrete, there
is a quantization process that introduces an error. As the number of discrete codes increases, the
corresponding step width gets smaller and the transfer function approaches an ideal straight line. The
steps are designed to have transitions such that the midpoint of each step corresponds to the point on
this ideal line. The width of one step is defined as 1 LSB (one least significant bit) and this is often
used as the reference unit for other quantities in the specification. It is also a measure of the resolution
of the converter since it defines the number of divisions or units of the full analog range. Hence, ½
LSB represents an analog quantity equal to one half of the analog resolution. The resolution of an
ADC is usually expressed as the number of bits in its digital output code. For example, an ADC with
an N-bit resolution has 2N possible digital codes which define 2N step levels. However, since the first
(zero) step and the last step are only one half of a full width, the full-scale (FS) range is divided into
2N – 1 step widths. Resolution defines the number of possible ADC output states. The result is a
digital or whole number, so for an 8-bit converter the possible states will be: zero, one, two, three and
so on, with 255 as the maximum state. A 10-bit converter will have 1023 as the maximum state, and a
12-bit converter will have 4095 as the maximum state. If the input range remains constant, a higher
resolution converter will have less quantization error because the range is divided into smaller steps.
This is similar in concept to the process of rounding a number to the nearest hundredths, having
potentially less error than rounding to the nearest tenths.
A linear analog-to-digital converter must provide a 1-to-1 mapping between any analog input level and
post-quantization finite level. Additionally, a linear converter must have equal analog quantization
steps Q such that
FS
Q
2N
Where FS: Full Scale range. The number of bits, i.e. N, used should be selected such that the converter
will register the smallest analog signal of interest and will have enough resolution to record the signal
at the desired level of detail. As a general rule of thumb, N should be selected such that Q = level of
noise in the analog signal. In order to provide meaningful data conversion, the duration of sampling
(aperture time) must be less than the amount of time it takes the analog signal to change by one Q.

Also, according to the Nyquist requirement, the ADC must sample the analog input at a rate of at least
twice the highest frequency component, i.e., fsampling > 2 fcutoff.
Fig. 12.14 depicts a simplified functional diagram for a 3 bit ADC and its ideal transfer function with
reference points at code transition boundaries. The digital output code will be its lowest (000) at less
than 1/8 of the full-scale (the size of this ADC's code width). Also, note that the ADC reaches its full-
scale output code (111) at 7/8 of full scale, not at the full-scale value. Thus, the transition to the
maximum digital output does not occur at full-scale input value. There is a range of analog input over
which the ADC will produce a given output code; this range is the quantization uncertainty (shown in
Fig. 12.15) and is equal to 1 LSB. Note that the width of the transition regions between adjacent codes
is zero for an ideal ADC. In practice, however, there is always transition noise associated with these
levels, and therefore the width is non-zero. It is customary to define the analog input corresponding to
a given code by the code center which lies halfway between two adjacent transition regions (illustrated
by the black dots in the diagram). This requires that the first transition region occur at ½ LSB. The
full-scale analog input voltage is defined by 7/8 FS, (FS – 1 LSB).
Fig. 12.14. A simplified functional diagram for a 3 bit ADC and its transfer function.
Fig. 12.15. The quantization uncertainty.
Different methods are used for analog-to-digital conversion. Some of them are; Digital Ramp ADC,
Flash ADC, Tracking ADC, and ADC with successive approximation.

ADC0804 IC
The ADC0804 is an 8 bit successive approximation ADC. Firstly, let us consider the operation
principle of successive approximation ADCs. Block diagram of a successive approximation ADC with
8 bit resolution, can be seen from Fig. 12.16. The successive approximation ADC circuit typically
consists of four chief sub-circuits:
1. A sample and hold circuit to acquire the input voltage (Vin).

2. An analog voltage comparator that compares Vin to the output of the internal DAC and outputs
the result of the comparison to the successive approximation register (SAR).
3. A successive approximation register sub-circuit designed to supply an approximate digital code
of Vin to the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog voltage equivalent of
the digital code output of the SAR for comparison with Vin.
The successive approximation register is initialized so that the most significant bit (MSB) D7 is equal
to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital
code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog
voltage exceeds Vin, then the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1.
Then the next bit D6 is set to 1 and the same test is done, continuing this binary search until every bit
in the SAR has been tested. The resulting code is the digital approximation of the sampled input
voltage and is finally output by the DAC at the end of the conversion.
Fig. 12.16. The block diagram of an 8 bit successive approximation ADC.
The ADC0804 IC has 20 pins. Its supply voltage is 5 V DC and its analog input is between 0-5 volts. It
consumes 15 mW power and it completes conversion in 100 µsec. It has 28 =256 quantization size for
8 bit resolution. If we take reference voltage as 5 V, its quantization error is 5V / 256=0.0195V. It
means that error of 0804 ADC is ±1 LSB= 0.0195V. It includes step size, offset and linearization
errors. The schematic diagram and the block diagram of the ADC0804 IC are depicted in Fig. 12.17
and in Fig. 12.18 respectively.

Fig. 12.17. The schematic diagram of the ADC0804 IC.
Fig. 12.18. The block diagram of the ADC0804 IC.
The clock for the ADC can be derived from an external source such as the CPU clock or an external
RC network can be added to provide self-clocking. The CLK IN (pin 4) makes use of a Schmitt trigger
as shown in Fig. 12.19.

Fig. 12.19. Self-clocking the ADC0804 by RC components.
The clock frequency is:
1
FCLK= (Hz)
1.1RC
Where “R” is in ohms, “C” is in farads. The frequency of the clock pulse generated by the ADC0804 is
100 KHz-800 KHz. It also includes a Schmitt-Trigger as seen in Fig. 12.19. WR’ is control signal for
write operation. Clear operation is performed when CS’ and WR’ are “0”. When WR’ is set to “1”
again, analog-digital conversion starts. (ADC takes floating pins as “1”). During the conversion,
INTR’ is “1”. It becomes “0” when the conversion is completed. The ADC0804 has two GND pins.
These pins are analog ground (AGND), and digital ground (DGND). The 9th pin must be set to half of
the reference voltage. In our experiment 5 V supply voltage is used for reference voltage.
In this case, 5/2=2,5V must be applied to the 9th pin. Since the reference voltage is 5V DC, step size
will be 5V / 256 = 0.0195V. Then;
00000000 (00H) will represent 0.00V and 11111111 (11F) will represent 4.9805V.

EXPERIMENT NO: 12.2

EXPERIMENT NAME: EXAMINATION OF THE ANALOG TO DIGITAL CONVERTER
(ADC)
Equipment:
1. Y-0016 main unit
ADC0804 8 bit ADC 1
150 pF Capacitor 1
10 F Capacitor 1
10 KΩ Resistor 1
Fig. 12.20.(a) The test circuit for the ADC0804 8 bit analog to digital converter.

Note1: Do not forget to connect the +5 V and the GND ( ) connections..

Note2: Use the lower two pins of the ON/ON SWITCH as the START switch.
Note3: A 10 KΩ potentiometer (variable resistor) must be connected as follows: connect the left pin of
the 10 K potentiometer to GND, the right pin to +5 V and the middle pin to the pin 6 [VIN(+)] of the
ADC0804.
Fig. 12.20.(b) The test circuit for the ADC0804 8 bit analog to digital converter – application circuit.

Procedure:
power.
2. By using the 10 KΩ potentiometer and the START button apply the analog voltages shown in Table
12.2 in the given order. For each analog value applied record the digital output value you observed
from the outputs. Note that the ideal digital output values are also provided in the table.
ANALOG IDEAL DIGITAL OUTPUTS OBSERVED DIGITAL OUTPUTS

INPUT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0.0 V 0 0 0 0 0 0 0 0
0.5 V 0 0 0 1 1 0 1 0
1.0 V 0 0 1 1 0 0 1 1
1.5 V 0 1 0 0 1 1 0 1
2.0 V 0 1 1 0 0 1 1 1
2.5 V 1 0 0 0 0 0 0 0
3.0 V 1 0 0 1 1 0 1 0
3.5 V 1 0 1 1 1 0 0 0
4.0 V 1 1 0 0 1 1 0 1
4.5 V 1 1 1 0 1 1 1 1
5.0 V 1 1 1 1 1 1 1 1
Table 12.2.
Note1: Use a multimeter to adjust the analog input voltage.

Note2: Leave the circuit as it is on the breadboard,
because you will use it in the experiment 12.3.

DIGITAL DATA TRANSFER BY USING ADC & DAC CONVERTERS
OBJECTIVES:
1- Analysing the digital data transmission by using ADC and DAC converters,
2- Observing their operation,
In the modern telecommunication systems, both analog and digital data can be transmitted. However,
recently transmitting and dealing with digital data has gained more importance. The transmitted data
can be related to voice, heat, light, pressure, etc.
The data can be transmitted in many ways and forms. The binary coding is one of the widely used
ways. The binary data can be transmitted either in parallel or serial. In serial transmission, data are
presented one bit at a time; however, all data can be transmitted at a time in parallel transmission. The
transmission speed is faster in parallel data transmission, but it costs more compared with the serial
transmission, due to more data lines. In serial transmission the speed is relatively slow, however it is
less expensive. In applications where the speed is not very important serial data transmission is
preferred.
The advantage of digital telecommunication systems is that the data can be transmitted at very high
speeds and with very little errors. In many telecommunication systems, there are some special codes
that make error check (parity check). These kinds of codes minimize the possible errors that can occur.
In the Fig. 12.21, the analog data are converted into digital and transmitted in parallel. At the receiver
side the data are converted back into analog.
Fig. 12.21. The digital data transmission by using ADC-DAC converters.

EXPERIMENT NO: 12.3

EXPERIMENT NAME: EXAMINATION OF THE DIGITAL DATA TRANSMISSION USING
ADC AND DAC CONVERTERS
Equipment:
1. Y-0016 main unit
ADC0804 8 bit ADC 1
DAC0800 8 bit DAC 1
LM741 Op-amp 1
150 pF Capacitor 1
10 F Capacitor 1
4.7 KΩ Resistor 3
10 KΩ Resistor 1
Fig. 12.22.(a). The test circuit for the digital data transmission using the ADC0804 and the DAC0800.

Note1: Do not forget to connect the V– pin to -12 V DC, the V+ pin to +12 V DC.
Note2: Do not forget to connect the +5 V and the GND ( ) connections.
Note3: You must connect the “0” pin of the SYMETRIC POWER SUPPLY and the GND pin of the
DC power supply by means of a connection wire.
Note4: Use the lower two pins of the ON/ON SWITCH as the START switch.
Note5: A 10 KΩ potentiometer (variable resistor) exists on the Y-0016 main unit.
Fig. 12.22.(b). The test circuit for the digital data transmission using the ADC0804 and the DAC0800.
– application circuit.

Procedure:
power.
2. By using the 10 KΩ potentiometer and the START button apply the analog voltages shown in Table
12.3 in the given order.
3. For each analog input value applied record the observed digital outputs in Table 12.3.
4. For each analog input value applied measure the analog output voltage Vout by means of a
multimeter and record it in the table.
ANALOG INPUT DIGITAL (OUTPUTS) INPUTS ANALOG OUTPUT

VG (VOLT) D7 D6 D5 D4 D3 D2 D1 D0 Vout (VOLT)
0.000
0.019
0.039
0.078
0.156
0.312
0.624
1.25
2.56
4.98
Table 12.3.


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FACULTY OF ENGINEERING AND ARCHITECTURE

ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT

COMPUTER ENGINEERING DEPARTMENT

DIGITAL DESIGN LABORATORY MANUAL

Prof. Dr. Murat UZAM

EXPERIMENT 1 – DIGITAL LOGIC GATES 1_1

EXPERIMENT NO: 2 – LAWS AND THEOREMS OF BOOLEAN ALGEBRA 2_1

DIGITAL DESIGN LABORATORY MANUAL i

EXPERIMENT 2.9: EXAMINATION OF THE DISTRIBUTIVE LAW 3 2_18

EXPERIMENT NO: 3 – IMPLEMENTATION OF BOOLEAN FUNCTIONS

EXPERIMENT NO: 4 – COMBINATIONAL LOGIC CIRCUITS: ADDERS, SUBTRACTORS 4_1

DIGITAL DESIGN LABORATORY MANUAL ii

EXPERIMENT NO: 5 – COMBINATIONAL LOGIC CIRCUITS: DECODERS, ENCODERS 5_1

EXPERIMENT NO: 6 – COMBINATIONAL LOGIC CIRCUITS:

EXPERIMENT NO: 7 – SEQUENTIAL LOGIC CIRCUITS: SR FLIP-FLOP, JK FLIP-FLOP

SR FLIP-FLOP (LATCH) 7_3

DIGITAL DESIGN LABORATORY MANUAL iii

EXPERIMENT NO: 8 – COUNTERS 8_1

EXPERIMENT NO: 9 – REGISTERS 9_1

EXPERIMENT NO: 10 – MEMORY CIRCUITS: RAM, ROM 10_1

DIGITAL DESIGN LABORATORY MANUAL iv

EXPERIMENT NO: 11 – ARITHMETIC LOGIC UNIT 11_1

EXPERIMENT NO: 12 – DIGITAL TO ANALOG CONVERTERS – DAC

DIGITAL DESIGN LABORATORY MANUAL v

1. “Dijital Elektronik Deney Kitabı”, Yıldırım Elektronik, 2010.

2. “Lojik Devre Laboratuvarı Deney Kılavuzu”, Erciyes Üniversitesi, Mühendislik

3. “Digital Design Course Notes”, Prof. Dr. Murat UZAM,

Birsen Yayınevi, Eylül 2008.

5. Integrated Circuits Catalogues

DIGITAL DESIGN LABORATORY MANUAL 0_1

GENERAL INFORMATION, LAB REGULATIONS AND WARNINGS

 Students have to attend at least 80% of experiments.

materials before coming to laboratory.

preliminary work will not be allowed to do the experiment.

be replaced by the responsible student.

provide an efficient working area.

 During the experiment, the exchange of information or material is certainly prohibited.

other students like mobile phone, radio, etc. in laboratory.

 Your friends cannot enter the lab during the experiments.

DIGITAL DESIGN LABORATORY MANUAL 0_2

THE POINTS TO BE CAREFUL DURING EXPERIMENTS

 Is the input signal applied to the output by mistake?

should be mentioned in the verification process.

insertion / removal, changing connection)

DIGITAL DESIGN LABORATORY MANUAL 0_3

INFORMATION ABOUT THE LABORATORY

 The grading of the Digital Design (3+2) course is as follows:

1st Midterm Exam 10%,

DIGITAL DESIGN LABORATORY MANUAL 0_4

DIGITAL DESIGN LABORATORY MANUAL 0_5

The Evaluation of Experiment Results

Report must certainly contain the followings:

DIGITAL DESIGN LABORATORY MANUAL 0_6

INTRODUCING THE Y-0016 MAIN UNIT

USING THE CIRCUITRY ON THE FUNDAMENTAL ELECTRICAL – ELECTRONICS

2-ADJUSTABLE DC POWER SUPPLY

3-(-5V) 0 (+5V) SYMMETRIC DC SUPPLY

4- (-12V) 0 (+12V) SYMMETRIC DC SUPPLY

5- 12V-0-12V SYMMETRIC AC SUPPLY

DIGITAL DESIGN LABORATORY MANUAL 0_8

10- HEXADECIMAL DECODER

11- 8 BIT LOGIC INDICATOR