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CHAPTER 2
LITERATURE REVIEW
The research shows that the adopted power clock with gradually
changing process during its rising and falling dissipates only less energy
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for charging and discharging the node capacitance through the conducting
of MOS transistor. The “adiabatic” switching operation is resulted, by
which a new approach to design low power CMOS circuits is proposed.
Clocked CMOS circuits with gradually rising and falling power-clock were
expected to obtain a significant energy saving. It attracts many researchers
to study this issue in recent years. However, the operational constraint that
the output signal should track the power clock’s gradually rising and
falling behavior to accomplish the charging and discharging process
increases the difficulty in the circuit design. At present, the existing
research either adopts retractile cascade power clock or adopts multiple-
phase power clock with memory schemes (Pedram et al 2000).
A variety of full adders using static and dynamic logic styles has
been reported in literature, 34 of which have been stated by (Jiang et al
2008) alone, including the most well known static complementary CMOS
adders using 28 transistors and 40 transistors.
sum outputs. SERF has been shown to consume 26% less power than a
Transmission Function Adder.
A B C SUM CARRY
0 0 0 0 0
0 0 1 Vdd - Vt 0
0 1 0 1 Vt
0 1 1 0 1
1 0 0 1 >Vtp
1 0 1 0 1
1 1 0 Power consuming Vdd – 2 Vth
causes to failure
1 1 1 >Vdd – 2 Vth Vdd - Vth
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For instance, to have a correct output for SUM it seems that the
supply voltage cannot be lowered more than Vdd/2 + 2Vtn indicating that
the supply voltage must be higher than Vdd/2 + 0.28V in a 65 nm CMOS
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technology. However this limit depends on the circuit design topology and
also the sizing and the device types that were employed. To mitigate this
problem, the gates of power consuming transition for Cout signal must be
connected to Vdd during the challenging state (A = B = 1, Cin = 0). Then the
supply voltage may be reduced to as low as Vdd/2+Vth which was estimated
to be Vdd/2+0.14. For example when Vdd = 0.3V, in the worst case Cout
will be Vdd - Vth = 0.16V, which can be used as a high logic. In addition the
NMOS pass transistor may be upsized to further lower the supply voltage.
It seems possible to lower supply voltage to 0.25V. In A = 1, B = 1 and Cin
= 0, it can be seen that the output cannot be decided exactly, because in this
case, two PMOS devices and also the NMOS transistors are ON, then the
output state was roughly dependant on the transistor (Junming et al 2001
and Wu et al 2001).
In most of these systems, the adder lies in the critical path that
determines the overall speed of the system thereby enhancing the
performance of the 1-bit full adder cell, a significant goal. Demands for the
low power VLSI have been pushing the development of aggressive design
methodologies to reduce the power consumption drastically.
To meet the growing demand, a new low power adder cell, by sacrificing
the MOS Transistor count, reduces the serious threshold loss problem.
It considerably increases the speed and decreases the power when
compared to the static energy recovery full (SERF) adder. A new improved
14T CMOS l-bit full adder cell was presented by Vigneswaran et al (2006).
the dependence of the leakage current on the input vector to the gate.
With additional control logic, the circuit was put into a low-leakage
standby state when it was idle and restored to the original state when
reactivated. Reactivation state forces the need to remember the original
state information before going to low-leakage standby state. This requires
special latches, thereby increasing the area of the circuit by about five
times in the worst case (Temel et al 2004). Also, the amount of time for
which the unit remains in idle state should be long enough so that the
dynamic power consumed in forcing the circuit to low-leakage state and
the leakage power dissipated in the standby state together was less than the
leakage power without the technique.
This additional hardware consumes power in both idle and active states of
the circuit.
The high wake-up latency and wake-up power penalty of traditional power
gating limit its application to large stretches of inactivity. The multiple-
mode feature allowed a processor to enter power saving modes more
frequently. Hence, it resulted in enhanced leakage savings (Harmander
Singh et al 2007).
The increasing demand for the high fidelity portable devices has
laid emphasis on the development of low power and high performance
systems. In the next generation processors, the low power design has to be
incorporated into fundamental computation units, such as multipliers.
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The ALU is the core of a CPU in a computer and the adder cell
was the elementary unit of an ALU. The adder is satisfied by the area,
power and speed requirements. Some of the conventional types of adders
are ripple-carry adder, carry-look ahead adder, carry-skip adder and
Manchester carry chain adder (Harrison et al 2005). The delay in an adder
is dominated by the carry chain. Carry chain analysis must consider
transistor and wiring delays.
the power consumed and the various aspects of reversible computing and
reversible logic gates. Furthermore, it was important to design a reversible
implementation of eight bit arithmetic and logic unit and it was optimal in
terms of number of gates used and number of garbage outputs produced
(Keskar et al 2011).
2.1 SUMMARY
2.2 OBJECTIVE