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4B-3 (Invited)

(Invited) FinFET/Nanowire Design for 5nm/3nm Technology Nodes: Channel Cladding and Introducing a “Bottleneck” Shape to Remove Performance Bottleneck

Victor Moroz, Joanne Huang and Munkang Choi

Synopsys, Inc., 690 East Middlefield Road, Mountain View, CA, USA, victorm@synopsys.com

Abstract Transition from planar MOSFETs to FinFETs enabled scaling beyond 28nm node. At 5nm/3nm design rules, a transition from FinFETs to nanowires has to be evaluated. We explore with rigorous NEGF (Non- Equilibrium Green’s Functions) and sub-band Boltzmann transport models the impact of nanowire shape and SiGe/Si cladding layers on its performance and variability. Outside of the nanowire channel, a “bottleneck” shape of the source/drain extensions can either boost or ruin the performance, requiring NEGF- driven meticulous shape engineering. (Keywords: Nanowire, FinFET, scaling, TCAD, NEGF, sub-band Boltzmann, SiGe channel cladding, band structure engineering)

Introduction To avoid FinFET short-channel effects, the fin width W scaling has to be in sync with channel length L scaling. Scaling towards 5nm/3nm design rules requires key transistor specifications listed in Table 1. It will be difficult to reproducibly manufacture tall fins with the required fin widths. This is when nanowires can be introduced due to the better channel control by gate-all- around nanowire design [1]. Here, we benchmark FinFET and nanowire designs for 5nm/3nm nodes.

Modeling Methodology We use 3D sub-band Boltzmann transport analysis for the PMOS FinFETs and nanowires, with 2D Schrödinger equation in the fin cross-section and 1D Boltzmann transport along the fin [2]. Considering that FinFETs have close to 80% ballistic transport [3], we do ballistic FinFET analysis. For the nanowires, ballistisity drops towards 50% [3], and therefore we include scattering mechanisms into nanowire analysis. The PMOS source/drain (S/D) extensions have 1 . 10 20 cm -3 doping and 3 . 10 -9 Ohm . cm 2 contact resistance. For the NMOS FinFETs and nanowires, our analysis did not show any noticeable benefits by going to SiGe or cladded SiGe/Si channels, so we are not reporting such results in this work. For the NMOS nanowire S/D extension engineering, we use 3D NEGF approach based on 3D Schrödinger transport [2] with explicit Coulomb scattering off atomistic dopants in S/D extensions.

PMOS FinFETs with Si, SiGe, and Cladded Fins Si fin cladding with a 30% Ge SiGe layer for PMOS can

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be introduced to gain an equivalent of about 2 nm in terms of fin width scaling. Conformal and faceted fin cladding options are illustrated on Fig. 1. Conformal cladding exhibits slight advantage over faceted, so we focus on conformal cladding results here. Figure 2 shows that holes tend to stay within the SiGe quantum well in the on-state, whereas homogeneous 30% Ge SiGe and Si fins tend to have most of the current flowing through the middle of the fin width. Somewhat similar patterns are observed for the off-state (Fig. 3). At all bias conditions, cladded fins bring the holes closer to the surface, where gate has a stronger control. Benchmarking different fin designs for L ranging from 15 nm down to 11 nm, we see that cladded fin has the

best Ion/Ioff trade-off (Fig. 4), whereas SiGe fin is the

worst option at L=15 nm, but challenges Si at L=11 nm.

This drastic improvement of SiGe channel performance

happens due to the beneficial changes in SiGe band

structure when fin width scales down to 5.5 nm. The source barrier height in the off-state increases by 137

mV (see Fig. 5, where different channel materials are

compared in the off-state for a fixed on-state current).

The flip side of such drastic performance improvement

of SiGe fin is a strong performance variability due to inevitable fin width fluctuations.

PMOS Si, SiGe and Cladded Nanowires

The structure of a nanowire cross-section and the hole

density distribution across the channel are depicted on Fig. 6, where most of the holes are located inside the SiGe cladding layer, similarly to the cladded fin. Cladding-induced stress patterns are very favorable for the PMOS performance (Fig. 7), with high compressive longitudinal and lateral stress values. Peak cladding

stresses are: 1.4 GPa compressive longitudinal and lateral stress components and 843 MPa compressive vertical stress. Benchmarking of different nanowire

designs is summarized on Fig. 8, where cladded channel is consistently the best, and Si channel is consistently

the worst. As opposed to the FinFETs, nanowire

performance is insensitive to scaling from 5nm to 3nm design rules.

NMOS Si Nanowire Access Resistance One of the major issues for nanowire performance is source/drain extension resistance [1]. One seemingly obvious solution is to increase the extension cross- section (Fig. 9). However, rigorous NEGF analysis

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2017 IEEE Electron Devices Technology and Manufacturing Conference Proceedings of Technical Papers

shows that it causes severe performance degradation due to the additional barrier when the band structure morphs according to geometric confinements of a wider extension and a narrow channel. Fortunately, moving the "bottleneck" shaped transition point 3 nm inside the extension solves the problem and provides additional performance boost (Fig. 10) by moving the band offset inside the heavily doped SID where it has no effect on transistor behavior. Simultaneously, extension resis- tance reduces due to the wider cross-section area.

Conclusions

We have demonstrated a wide design space for the 5nm/3nm nodes that can be explored and optimized with rigorous physics-based modeling. One common observation for all described results is that behavior of transistors scaled down to 5nm/3nm design rules is determined by the band structure of underlying materials that is sensitive to specific shapes of the channel and SID extensions. Therefore, accounting for band structure changes is critical and band structure

engineering

becomes

a

key

part

of

transistor

optimization.

 
 

References

 

[1]

H. Mertens, R. Ritzenthaler, A. Hikavyy, M. S. Kim,

[2]

z. Tao, K. Wostyn, S. A. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel, T. Schram, K. Devriendt, D. Tsvetanova, H. Dekkers, S. Demuynck, A. Chasin, E. Van Besien, A. Dangol, S. Godny, B. Douhard, N. Bosman, 0 Richard, J Geypen, H Bender, K Barla, D. Mocuta, N. Horiguchi, and A. V-Y Thean, "Gate-all- around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates" VLSI Technology Digest, (2016). Sentaurus Device QTX User's Guide, (2016).

[3]

Munkang Choi, Victor Moroz, Lee Smith, and Joanne Huang, "Extending Drift-Diffusion Paradigm into the Era of FinFETs and Nanowires", SISPAD Pro- ceedings, pp. 242 - 245, (2015).

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Fig:. 1. FinFET with Si fill core 31ld SiGle fin clad.diIlg. Co no m' 1 cladding (left) an face .Ied clad, ing (righ ).

1 cladding (left) an face .Ied clad, ing (righ ). F· g. 2,. 0, malize,. ho

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2017 IEEE Electron Devices Technology and Manufacturing Conference Proceedings of Technical Papers

Fig. 3. Nonnalized hole distributiollS at off-state biases across the fm. FinFET with confonnal SiGe

Fig. 3. Nonnalized hole distributiollS at off-state biases across the fm. FinFET with confonnal SiGe cladding

(left), SiGe fill (Cetlter)

and Si fill (rigllt).

cladding (left), SiGe fill (Cetlter) and Si fill (rigllt). Fig. 4. FinFET perfonnance benchmarkulg for L==15mn

Fig. 4. FinFET perfonnance benchmarkulg for L==15mn (solid IUles) and L==llnm (dashed lines).

for L==15mn (solid IUles) and L==llnm (dashed lines). Fig. 5. Zerotll etlergy sub-band for SiGe &

Fig. 5. Zerotll etlergy sub-band for SiGe & Si fins with differetlt design rules under off-state bias conditiollS.

differetlt design rules under off-state bias conditiollS. Fig. 7. A 3D nanowire (upper left) and nanowire

Fig. 7. A 3D nanowire (upper left) and nanowire stress cOlnponents due to the SiGe claddulg layer.

nanowire stress cOlnponents due to the SiGe claddulg layer. Fig. 6. NOllnalized hole density map in

Fig. 6. NOllnalized hole density map in Si natlowire witll SiGe cladding Ul the on-state.

map in Si natlowire witll SiGe cladding Ul the on-state. Fig. 8. Natlowire perfOllnaIlCe benclnnarking for

Fig. 8. Natlowire perfOllnaIlCe benclnnarking for L==15mn (solid lines) atld L==llmn (dashed lines).

for L==15mn (solid lines) atld L==llmn (dashed lines). Fig. 9. Nanowire SID extension ellgineering to reduce

Fig. 9. Nanowire SID extension ellgineering to reduce access resistance.

SID extension ellgineering to reduce access resistance. Fig. 10. Nanowire with a sharply wider source/dralll

Fig. 10. Nanowire with a sharply wider source/dralll extension (left) and nanowire on-stateloff-state currents for different source/drain extension desigtls.

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2017 IEEE Electron Devices Technology and Manufacturing Conference Proceedings of Technical Papers