5 4 3 2 1

1 2 3 4

DCT700 Phase 0 Main Board Schematic

Revision History Table of Contents
D D
Schematic MODIFICATION RECORDS
Sheet Rev. Description Ref
A A
Rev. .00 Initial Proto Rev.
1 .00 DCT700 Phase 0 Title Sheet 1
DMR SD_284 , DMR SD_286 , DMR SD_287, DMR SD_288, DMR SD_289, DMR SD_290, DMR SD_291, DMR SD_292, DMR
REV.1 DCT.SCH. Top level connections 1
SD_293, DMR SD_294, DMR BCST_1, DMR BCST_2, DMR SD_295, DMR SD_297 2 .00
DIGITAL.SCH Hierarchical Grouping 1
DMR SD_299, DMR SD_301, DMR SD_303, DMR SD_304 3 .00
REV.2
4 .00 ANALOG.SCH Hierarchical Analog Grouping 1

REV.3 DMR SD_307-1, DMR SD_311-1, DMR SD_309, DMR SD_312, DMR BCST_3, DMR BCST_4 5 .00 PWR.SCH Power Distribution
6 .00 POR.SCH Power On Reset 100
DMR SD_317,DS_321,BCST_021,SD_326,SD_330,SD_332,SD_335,SD_341,SD_342,BCST_022
REV.4 200
7 .00 QUAKE_RP_DIGITAL.SCH QUAKE_RP Digital I/O
8 .00 PLATFORM_FLASH & SRAM.SCH 300
REV.A Release for mass production(REV.A=REV.4)
9 .00 DDR_SDRAM.SCH 400

10 .00 SECURITY.SCH MC1.7, Battery, and TVPC 900

11 .00 QUAKE_RP_ANALOG.SCH 7114 Analog I/O 200/400

C
B 700/800 B C

12 .00 VIDEO_AUDIO.SCH Baseband / Remod Output

13 .00 AFE.SCH. Analog front end. 1100

14 .00 TUNER_UPSTREAM.SCH Tuner, Upstream Amp & Diplexer 500/600

Acceptable Dielectric Material for 10 uF Multilayer Chip Capacitors.

For power supply bypass applications (not AC signals).
Dielectric Voltage Cap change at Acceptable
Applied Material & Rating applied for use?
Voltage
PCB Requirements 5V
Size
Y5V 0805 10V
voltage.
-85% NO
X7R 1206 6.3V -10% YES
Place all terminating resistors as close to source as possible. The series terminating resistors will X5R 1206 10V -10% YES
X6S 1206 10V -28% NO
have a value of 0, 33, or 51 Ohms. 3.3V Y5V 0805 10V -75% NO
X7R 1206 6.3V -3% YES
C X5R 1206 10V -2% YES C
X6S 1206 10V -15% YES
B 2.5V Y5V 0805 10V -65% NO B
X7R 1206 6.3V -2% YES
X5R 1206 10V -2% YES
X6S 0805 6.3V -15% YES
1.2V Y5V 0805 10V -20% YES
Notes : X7R 1206 6.3V <1% YES
1. These schematics are grouped heirachically by function X5R 1206 10V <1% YES
X6S 0805 6.3V -2% YES
2. Each page in the schematics is assigned a set of reference designators (Ref)
This reference is the starting designator for all parts on the page
Chiang Raph Chang
9-24-03'

DCT_2
APVD

9-24-03'
INCORP
Matt
REVISION

C031282 Release for mass production of

D D
DESCRIPTION

THIS DOCUMENT CONTAINS PROPRIETARY DATA AND

A IS INTENDED ONLY TO CONVEY INFORMATION TO A
Phase 1

CUSTOMERS, PROSPRECTIVE CUSMERS, AND

VENDORS. IT SHALL NOT BE COPIED, REPRODUCED,
Sheet_02 Atlanta, Georgia, U.S.A. Taipei, Taiwan R.O.C.
COMMUNICATED TO OTHERS, OR USED AS A BASIS Title
FOR THE MANUFACTURE OR SALE OF APPARATUS SCHEMATIC,MAIN,DCT700 P0
WITHOUT THE WRITTEN PERMISSION OF GENERAL
NUMBER

INSTRUMENT CORPORATION. Document Number File Name Rev

ECO

A
864684-049
Date: Friday, September 26, 2003 Sheet 1 of 14

REVISION
REV

A
A

328-039-001

1 2 3 4
5 4 3 2 1
 5 4 3 2 1

+5V
DIGITAL

R2
3.3K_s
R3
100_s J1
DIAG_TXD
R4 3
2

3
1K_s
Q3 1
1 D
2sc2712
D header_3_pins D

2
TP1 TP2 TP3
TESTPIN TESTPIN TESTPIN D

ANALOG
J5 +3.3V
2T 1 LINE_OUT_LEFT
LINE_OUT_LEFT D
MANF_TXD
LINE_OUT_RIGHT CH3/4_SEL MANF_TXD R5
1T 2
LINE_OUT_RIGHT CH3/4_SEL CH3/4_SEL MANF_RXD 1K_s
S 3
MANF_RXD
R8
hsp_242v2 1K_s
Q4 R6

3
2sc2712 3.3K_s
D 1 DIAG_RXD

3
J6 R7 D1

2
T 1 COMP_OUT 10K_s mmbd4148
COMP_OUT
2
S 3

1
hsp_241v1y
D
D

S1
QUAKE_SHIELD

TP6
GND
GND
GND
GND
GND
GND

TP10 TESTPIN
C C
TP4
TP8 TESTPIN
6
5
4
3
2
1

REMOD_OUT 1
J4 TP5 WRPROT_GND
conn_f_female_007 TP9 TESTPIN
185243-007-99 WRPROT_1
WRPROT_1

3
WRPROT_3 TP7 D
D WRPROT_3 TESTPIN
A

HARD_RESETB
HARD_RESETB

Sheet_04

D2
hlmp_1401 +3.3V
YELLOW - POWER
R10
PWR_LEDB 1 2

3
R11 330_s
PWR_LED 1 Q1
PWR_LED
4.7K_s 2sc2712 D3
led

2
RED - MESSAGE
R12
D MSG_LEDB 1 2

3
R13 330_s
MSG_LED 1 Q2
MSG_LED
B
4.7K_s 2sc2712 B

2
D
+5V

R14
POWER IR_IN
IR_IN
See option 4.7K_s
Table 3
Table 3
J3 D4

1
1 gp1um281yk
VDC_IN
2 D4 R15 R16 R17 R18

VOUT
3 5 MTG2
4 MIM-5383H4 INSTALL DNI INSTALL DNI
MTG1
conn_power_jack1

VCC(GND)
D SFH5110-38 DNI INSTALL DNI INSTALL

R15 0_s
3 GND(VCC)
Sheet_05
R17 0_s

2
R18 0_s

R16 C1
Sheet_03 0.1U_s
0_s
A A

<Variant Name>

Atlanta, Georgia, U.S.A. Taipei, Taiwan R.O.C.

Title
DCT.SCH
Document Number File Name Rev
864684-049 A

Date: Friday, September 26, 2003 Sheet 2 of 14

5 4 3 2 1
 5 4 3 2 1

QUAKE_RP_ DIGITAL_1

SECURITY_1

SYS_RESETB
SYS_RESETB
SPI_MOSI WRPROT_1
SPI_MOSI SPI_MISO SPI_MOSI WRPROT_1 WRPROT_3 WRPROT_1
SPI_MISO MC_SPI_CSB SPI_MISO WRPROT_3 WRPROT_3
MC_SPI_CSB SPI_CLK MC_SPI_CSB
SPI_CLK SPI_CLK

MC_CLK27
MC_CLK27 MC_CLK40 MC_CLK27
D MANF_TXD MANF_TXD MC_CLK40 MC_CLK40 D
MANF_RXD MANF_RXD
POR_RESETB
POR_RESETB POR_RAM_ENB
POR_RAM_ENB SRAM_VBATT
MC_IRQB SRAM_VBATT
POR MC_IRQB MC_IRQB

INFO_SYNC
INFO_SYNC INFO_DATA INFO_SYNC PKT_SYNC
INFO_DATA INFO_CLK INFO_DATA PKT_DATA
INFO_CLK INFO_CLK PKT_CLK
HARD_RESETB
HARD_RESETB HARD_RESETB
EJTAG_RESETB
EJTAG_RESETB EJTAG_RESETB
Sheet_10
POR_RESETB
POR_RESETB POR_IRQB POR_RESETB
POR_IRQB POR_IRQB
PKT_CLK
PKT_DATA
PKT_SYNC
Sheet_06

C C

PLATFORM_FLASH & SRAM_1

EBI_DATA_[15:0]
EBI_DATA_[15:0] EBI_ADDR_[24:0] EBI_DATA_[15:0]
EBI_ADDR_[24:0] EBI_ADDR_[24:0]
EBI_RDB
EBI_RDB EBI_R/WB EBI_RDB
EBI_R/WB EBI_R/WB
B B
SRAM_VBATT
POR_RAM_ENB
DDR_SDRAM_1

SD_CSB_0
SD_CSB_0 SD_CSB_0
SD_CLKE ROM_CSB
SD_CLKE SD_CLKB SD_CLKE ROM_CSB FLASH1_CSB ROM_CSB
SD_CLKB SD_CLK SD_CLKB FLASH1_CSB FLASH1_CSB
SD_CLK SD_BA_1 SD_CLK SRAMLB_CSB
SD_BA_1 SD_BA_0 SD_BA_1 SRAMLB_CSB SRAMUB_CSB SRAMLB_CSB
SD_BA_0 SD_CASB SD_BA_0 SRAMUB_CSB SEL_FLASH1/ROMB SRAMUB_CSB
SD_CASB SD_RASB SD_CASB SEL_FLASH1/ROMB SEL_FLASH1/ROMB
SD_RASB SD_WEB SD_RASB SYS_RESETB
SD_WEB SD_LDQS_0 SD_WEB SYS_RESETB
SD_LDQS_0 SD_UDQS_1 SD_LDQS_0
SD_UDQS_1 SD_LDM SD_UDQS_1
SD_LDM SD_UDM SD_LDM
SD_UDM SD_UDM
SD_ADDR_[12:0]
SD_ADDR_[12:0] SD_ADDR_[12:0]
SD_DATA_[15:0]
SD_DATA_[15:0] SD_DATA_[15:0]
Sheet_09
IR_IN
IR_IN IR_IN

CH3/4_SEL CH3/4_SEL
SYS_RESETB CH3/4_SEL
SYS_RESETB Sheet_08

MSG_LED
MSG_LED PWR_LED MSG_LED
PWR_LED PWR_LED
A A

Sheet_07

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
DIGITAL.SCH
Size Document Number File Name Rev
C A
864684-049
Date: Friday, September 26, 2003 Sheet 3 of 14

5 4 3 2 1
 A B C D E

4 4

AFE QUAKE_RP_ANALOG VIDEO_AUDIO.SCH

QAM_IF+
QAM_IF+
QAM_IF- IB_IF_POS
QAM_IF- IB_IF_POS IB_IF_NEG IB_IF_POS
IB_IF_NEG QAM_AGCI IB_IF_NEG
QAM_AGCI QAM_AGCI DIG_COMPOSITE
DIG_COMPOSITE DIG_COMPOSITE
OOB_IF_POS
OOB_IF_POS OOB_IF_NEG OOB_IF_POS COMP_OUT
OOB_IF_NEG OOB_AGC OOB_IF_NEG COMP_OUT COMP_OUT
OOB_AGC OOB_AGC REMOD_OUT
AUDIO_LEFT_POS REMOD_OUT REMOD_OUT
AUDIO_LEFT_NEG AUDIO_LEFT_NEG AUDIO_LEFT_NEG LINE_OUT_RIGHT
OOB_VCO_POS AUDIO_LEFT_POS AUDIO_LEFT_POS LINE_OUT_RIGHT LINE_OUT_LEFT LINE_OUT_RIGHT
OOB_VCO_POS OOB_VCO_NEG OOB_VCO_POS LINE_OUT_LEFT LINE_OUT_LEFT
OOB_VCO_NEG OOB_VCO_NEG AUDIO_RIGHT_NEG
AUDIO_RIGHT_NEG AUDIO_RIGHT_POS AUDIO_RIGHT_NEG
AUDIO_RIGHT_POS AUDIO_RIGHT_POS

OOB_TAP
OOB_TAP
CH3/4_SEL
CH3/4_SEL CH3/4_SEL

Sheet_13

3 3

Sheet_12

TUNER_UPSTREAM.SCH

TX_DAC+
TX_DAC+ TX_DAC- TX_DAC+
TX_DAC- TX_DAC-
US_CTL_DATA
US_CTL_DATA US_CTL_CLK US_CTL_DATA
US_CTL_CLK US_CTL_CSB US_CTL_CLK
US_CTL_CSB US_CTL_CSB
TX_OEN
TX_OEN TX_OEN

TUNER_SDA
TUNER_SDA TUNER_SCLK TUNER_SDA
TUNER_SCLK TUNER_SCLK
OOB_TAP
OOB_TAP
QAM_IF+
2 QAM_AGCT 2
QAM_AGCT QAM_AGCT QAM_IF-

Sheet_11 Sheet_14

1 1

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
ANALOG.SCH
Size Document Number File Name Rev
C A
864684-049
Date: Friday, September 26, 2003 Sheet 4 of 14
A B C D E
 A B C D E

Table 1
Reference Vendor and PN Motorola MCN ESR max. at 20 deg C Notes
Designator and 100 kHz
C113 United Chemi-Con
KMF25VB471M10X16 507629-001 0.19 ohms
KZE25VB471M10X16 496616-002 0.038 ohms
C101, C102 United Chemi-Con
KMF16VB471M10X12 507630-001 0.25 ohms
KMF25VB471M10X16 507629-001 0.19 ohms
KZE series Do not use. Do not use.
C105, C106 United Chemi-Con
KMF16VB471M10X12 507630-001 0.25 ohms C121 = 1000pF
KMF25VB471M10X16 507629-001 0.19 ohms C121 = 1000pF
KZE16VB471M10X12 496616-001 0.053 ohms C121 = 1000pF
4 4

Input DC Power Filter and +1.25V DC-DC Converter

Protection +12V_UNREG +12V_UNREG VOUT = VFB*(1+R1/R2)
Overcurrent Reverse voltage VFB = 1.242V nominal
protection protection EMI Filter Surge Q100
U100 FDC640P VOUT = 1.242V*(1 +
F100 D105 L102 Protection +12V_UNREG LM3485
mbrs340 1 DRAIN DRAIN 6 1K/47K) = 1.268V
fuse2a 32uh_2a 1 8 2 5
ISENSE VIN DRAIN DRAIN L100 +1.2V
VDC_IN 2 1 2 7 3 4
502130-001 GND PGATE GATE SOURCE 22uh_1_9a
3 6

1
1
138194-000 NC PWRGND
1

503458-001 4 5 506626-001
C114 + C112 C111 FB ADJ 501238-001
+ D104 C113

1
0.1U_s 0.1U_s 1000P_s D D

1
C115 1smb20a 470uf_22 495633-001-26
100uf_07 R100 +
488524-001 + C102 C122 C100

2
R102 D100 1K_s C101
2

mbrs340 180P_s 100P_s

470uf_21

2
17.4K_s 470uf_21
138194-000

2
1%

2
Low ESR

2
D Low ESR Low ESR
See table 1
D D
See table 1 See table 1
C103 R101
1000P_s 47K_s

3 3

+3.4V LDO Voltage Regulator +5V DC-DC Converter

+12V_UNREG +12V_UNREG

+12V_UNREG +5V Q101 VOUT = VFB*(1+R1/R2)

U101 FDC640P
LM3485 VFB = 1.242V nominal
1 6
1

DRAIN DRAIN VOUT = 1.242V*(1 +

1 ISENSE VIN 8 2 DRAIN DRAIN 5
C118 2 7 3 4
R107 R108 0.1U_s GND PGATE GATE SOURCE 10K/3.24K) = 5.075V
3 6 L101 +5V
1K_s 1K_s NC PWRGND
2

4 5 506626-001 22uh_1_9a
FB ADJ 501238-001
R109 D D D
495633-001-26
4

1
1

1
20_s
1 Q102 R105 R103 + + C104
2SD2118 VOUT = VFB*(1+R1/R2) 17.4K_s D101 10K_s C121 C106 C105 100P_s
1% mbrs340 470uf_21 470uf_21
VFB = 2.5V nominal 1% 1000P_s
3

2
C120 138194-000
+3.3V VOUT = 2.5V*(1 +

2
1000P_s
1

1K/2.8K) = 3.393V Low ESR Low ESR

2 8 C107 D D
See table 1 See table 1
3 7 1000P_s
U104 R110 C116 467639-001 R104
TL431CD R111 1K_s
1

6.3V X5R 1206 3.24K_s

2.8K_s 1%
6

C117 10U_c See table page 1. 1%

1%
0.1U_s
2

D
Collector tab of 2SD2118
must be heat sinked to
D
copper on PCB.

2 2

-5V Charge Pump (20 mA max)

467639-001
6.3V X5R 1206
U103B See table page 1.
+5V
74vhc14dt D102 -5V
C109 mbr0520lt
+2.5V Voltage Regulator (50 mA nominal) 3 4 1 2

2
+5V C108 467639-001
10U_c
D103 6.3V X5R 1206
U103A

14
74vhc14dt mbr0520lt 10U_c See table page 1.
R112 +3.3V U103C
74vhc14dt

1
100_s
R113 1 2
3

0_s 5 6
+2.5VREF 1 Q103
R114 mmbt2222a +2.5V
7
2

20_s 112004-014 D
Q104
2

1
2sa1162 U103D
74vhc14dt
D
3

9 8
D C110 R106
100P_s 100K_s

D
U103E
74vhc14dt

1 11 10 1

U103F
74vhc14dt

13 12
San Diego, California, USA. Taipei, Taiwan, R.O.C.
Title
PWR.SCH
Size Document Number File Name Rev
C 864684-049 A

Date: Friday, September 26, 2003 Sheet 5 of 14

A B C D E
 A B C D E

4 4

DC Input Power Supply Voltage Monitor

Power UP threshold = 8.536V nom.
Power DOWN threshold = 6.889V nom.
+12V_UNREG +3.3V

R152
R166 R157 R155 10K_s
3.3K_s 3.3K_s 20K_s R154 R153
1% 47.5K_s 100K_s D151
3

+2.5VREF bat54alt1 +3.3V

7 + +12V_UNREG
+2.5VREF PG1 POR_IRQB
1 2
6 -
3 R150
1

U150A 10K_s
12

3
2 8 LM339AD 1
3 7 R156 128008-010 2 R151 11 +
HARD_RESETB
U151 10K_s 3.3K_s 13 POR_RESETB

1
1% D150 3 +2.5VREF 10
TL431CD -
bat54alt1 C150
6

1 4700P_s U150D
EJTAG_RESETB

12
LM339AD

2
128008-010
D
D
3 3.3V Voltage Monitor R158 3
100K_s D
Power UP threshold = 2.989 V nom.
Power DOWN threshold = 2.894 V +3.3V C151
nom. +12V_UNREG 0.1U_s

R159 D
+3.3V 3.3K_s
3

R160
5 +
2 PG2
3.3K_s +2.5VREF 4 -
R161 U150B
20K_s LM339AD
12

1% 128008-010

1.2V Voltage Monitor

R162
Power UP threshold = 1.125 V nom. 100K_s
Power DOWN threshold = 1.113 V
nom.
+1.2V R163 +12V_UNREG
1K_s
3

R164 9 +
10K_s 14
2 +2.5VREF 2
1% 8 -
U150C
12

R165 LM339AD
8.06K_s 128008-010
1%

1 1

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
POR.SCH
Size Document Number File Name Rev
C 864684-049 A

Date: Friday, September 26, 2003 Sheet 6 of 14

A B C D E
 U200B Quake
SD_ADDR_[12:0]
SD_ADDR_0 U200D Quake
POR_RESETB T2 SYS_RSTI_N MI_MADDR00 AF6
T1 AE6 SD_ADDR_1
SYS_RESETB SYS_RSTO_N MI_MADDR01 SD_ADDR_2

QUAKE Digital CP
MI_MADDR02 AD6 CH3/4_SEL AD26 GPIO00 ATA_DATA00 AB2
SD_ADDR_3

QUAKE Digital I/O

MI_MADDR03 AF5 AD4 GPIO01 ATA_DATA01 AB4
AE5 SD_ADDR_4 M1 AC2
R201 33_s MI_MADDR04 SD_ADDR_5 GPIO02 ATA_DATA02
EBI_R/WB E1 CP_R_WN MI_MADDR05 AC5 PWR_LED R2 GPIO03 ATA_DATA03 AD1
R202 33_s E2 AD5 SD_ADDR_6 U5 AE1
EBI_RDB CP_RD_N MI_MADDR06 SD_ADDR_7 MSG_LED GPIO04 ATA_DATA04
D6 CP_DSACK_N MI_MADDR07 AC6 T5 GPIO05 ATA_DATA05 AE2
AB7 SD_ADDR_8 R5 AD3
MI_MADDR08 SD_ADDR_9 GPIO06 ATA_DATA06
D7 CP_DATA_STRB_N MI_MADDR09 AC7 P5 GPIO07 ATA_DATA07 AF3
+3.3V G5 AD7 SD_ADDR_10 V25 AC4
CP_BERR_N MI_MADDR10 SD_ADDR_11 GPIO08 ATA_DATA08
C8 CP_ADDR_STRB_N MI_MADDR11 AB8 V24 GPIO09 ATA_DATA09 AE3
E5 AC8 SD_ADDR_12 GPIO_11 is dedicated for F/W to determine the number of DRAM chips installed V23 AF2
CP_SIZE0 MI_MADDR12 GPIO10 ATA_DATA10
F5 CP_SIZE1 SD_DATA_[15:0] on a QUAKE platform. W26 GPIO11 ATA_DATA11 AF1
AE14 SD_DATA_0 W25 AD2
MI_MDBUS00 Default is 1 chip = pull down, for 2 chips a pullup is required GPIO12 ATA_DATA12
AF14 SD_DATA_1 W24 AC3
MI_MDBUS01 SD_DATA_2 GPIO13 ATA_DATA13
MC_IRQB T3 EXTI0 MI_MDBUS02 AE13 W23 GPIO14 ATA_DATA14 AC1
K3 AF13 SD_DATA_3 AC21 AB3
QUAKE has internal PU EXTI1 MI_MDBUS03 SD_DATA_4 GPIO15 ATA_DATA15
K4 EXTI2 MI_MDBUS04 AF12 AC15 GPIO16
for EXTI[4:0]. J5 AE12 SD_DATA_5 QUAKE has internal C10 AB1
EXTI3 MI_MDBUS05 SD_DATA_6 GPIO17 ATA_DRQ
C9 EXTI4 MI_MDBUS06 AF11 PD for V26 GPIO18 ATA_IOW AA4
R4 AE11 SD_DATA_7 GPIO[23:00]. U23 AA3
POR_IRQB NMI_N MI_MDBUS07 SD_DATA_8 GPIO19 ATA_IOR
MI_MDBUS08 AC11 B22 GPIO20 ATA_IOCHRDY AA2
EBI_ADDR_0 C4 AD11 SD_DATA_9 R3 AA1
EBI_ADDR_1 CP_ADDR00 MI_MDBUS09 SD_DATA_10 GPIO21 ATA_DACK
C3 CP_ADDR01 MI_MDBUS10 AC12 A22 GPIO22 ATA_INTRQ Y4
EBI_ADDR_2 C2 AD12 SD_DATA_11 D21
EBI_ADDR_3 CP_ADDR02 MI_MDBUS11 SD_DATA_12 GPIO23
C1 CP_ADDR03 MI_MDBUS12 AD13 ATA_DA0 Y1
EBI_ADDR_4 D4 AC13 SD_DATA_13 Y3
EBI_ADDR_5 CP_ADDR04 MI_MDBUS13 SD_DATA_14 ATA_DA1
D3 CP_ADDR05 MI_MDBUS14 AD14 ATA_DA2 Y2
EBI_ADDR_6 D2 AC14 SD_DATA_15 AE20
EBI_ADDR_7 CP_ADDR06 MI_MDBUS15 LK_SEL[3:0] are outputs. LK_SEL0
D1 CP_ADDR07 AF20 LK_SEL1 ATA_CS0 W4
EBI_ADDR_8 E4 AF7 LK_SEL4 has internal PD. AD19 W5
EBI_ADDR_9 CP_ADDR08 MI_BANK_O0 SD_BA_0 LK_SEL2 ATA_CS1
E3 CP_ADDR09 MI_BANK_O1 AE7 SD_BA_1 AE19 LK_SEL3
EBI_ADDR_10 A8 AC18
EBI_ADDR_11 CP_ADDR10 LK_SEL4 (656_IN_CLK)
B8 CP_ADDR11 MI_CS_N0 AD8 SD_CSB_0 CCIR656_A00 Y26
EBI_ADDR_12 A7 AE8 AF18 Y25
EBI_ADDR_13 CP_ADDR12 MI_CS_N1 LK_LD0 (656IN_D0) CCIR656_A01
B7 CP_ADDR13 AC17 LK_LD1 (656IN_D1) CCIR656_A02 Y24
EBI_ADDR_14 C7 AF8 QUAKE has internal AD17 Y23
EBI_ADDR_15 CP_ADDR14 MI_RAS_N SD_RASB LK_LD2 (656IN_D2) CCIR656_A03
A6 CP_ADDR15 MI_CAS_N AE9 SD_CASB PD for LK_LD[7:0] AE17 LK_LD3 (656IN_D3) CCIR656_A04 Y22
EBI_ADDR_16 B6 AF9 AF17 AA26
EBI_ADDR_17 CP_ADDR16 MI_WE_N SD_WEB LK_LD4 (656IN_D4) CCIR656_A05
C6 CP_ADDR17 AF16 LK_LD5 (656IN_D5) CCIR656_A06 AA25
EBI_ADDR_18 A5 AE16 AA24
EBI_ADDR_19 CP_ADDR18 LK_LD6 (656IN_D6) CCIR656_A07
B5 CP_ADDR19 AD16 LK_LD7 (656IN_D7) CCIR656_A08 AA22
EBI_ADDR_20 A4 AD10 AB26
EBI_ADDR_21 CP_ADDR20 MI_WMASK0 SD_LDM CCIR656_A09
B4 CP_ADDR21 MI_WMASK1 AB10 SD_UDM AF19 LK_KD0 CCIR656_A10 AB25
EBI_ADDR_22 A3 AF10 QUAKE has internal AD18 AB24
EBI_ADDR_23 CP_ADDR22 MI_DQS0 SD_LDQS_0 LK_KD1 CCIR656_A11
B9 CP_ADDR23 MI_DQS1 AC10 SD_UDQS_1 PD for LK_KD[3:0] AE18 LK_KD2 CCIR656_A12 AB23
EBI_ADDR_24 B3 AE10 AC19 AC26
EBI_ADDR_[24:0] CP_ADDR24 MI_DQS2 LK_KD3 CCIR656_A13
D9 CP_ADDR25 MI_DQS3 AB11 CCIR656_A14 AC25
CCIR656_A15 AC24
EBI_DATA_[15:0] MI_CKE AB9 SD_CLKE MANF_TXD D15 SCI_TXD0 CCIR656_ACLK AA23
EBI_DATA_0 F4 AC9 C15
EBI_DATA_1 CP_DATA00 MI_CLK SD_CLK MANF_RXD SCI_RXD0
F3 CP_DATA01 MI_CLK_N AD9 SD_CLKB
EBI_DATA_2 F2 AF21 R1
EBI_DATA_3 CP_DATA02 SCI_TXD1 CCIR656_B00
F1 CP_DATA03 AE21 SCI_RXD1 CCIR656_B01 P4
EBI_DATA_4 G4 QUAKE has internal PU P3
EBI_DATA_5 CP_DATA04 CCIR656_B02
G3 CP_DATA05
for SCI_RXD[3:0] AD20 SCI_TXD2 CCIR656_B03 P2
EBI_DATA_6 G2 AE26 EJTAG_TDO R205 33_s AC20 P1
EBI_DATA_7 CP_DATA06 TDO EJTAG_TDI J200 SCI_RXD2 CCIR656_B04
G1 CP_DATA07 TDI AD24 CCIR656_B05 N4
EBI_DATA_8 H4 AF26 EJTAG_TCK header_7pins_2rows A10 N3
EBI_DATA_9 CP_DATA08 TCK EJTAG_TMS SCI_TXD3 CCIR656_B06
H3 CP_DATA09 TMS AE25 B10 SCI_RXD3 CCIR656_B07 N2
EBI_DATA_10 H2 AD25 EJTAG_TRSTB N1
EBI_DATA_11 CP_DATA10 TRST_N QUAKE has internal PD/PU for TDI, 1 2 CCIR656_BCLK
H1 CP_DATA11 3 4 B13 USB_A_DATAP
EBI_DATA_12 J4 AF25 TCK, TMS & TRST_N. TDO is output QUAKE has internal PU A13 M2
EBI_DATA_13 CP_DATA12 EJTAG_SEL_N 5 6 USB_A_DATAN AUD_I2SO_DATA
J3 CP_DATA13 7 8 for USB inputs. C11 USB_A_PWR_ON_N AUD_I2SO_LRCLK M3
EBI_DATA_14 J2 B11 M4
EBI_DATA_15 CP_DATA14 9 10 USB_A_PWR_ERR_N AUD_I2SO_CLK
J1 CP_DATA15 EJTAG_RESETB 11 12
AF15 TP204 TP205 D13 C26
OUTENB_N 13 14 +3.3V USB_B_DATAP UO_POD_Q (QTX)
ROM_CSB A2 CP_CS_N0 TCC AC22 C13 USB_B_DATAN UO_POD_I (ITX) A26
FLASH1_CSB A1 CP_CS_N1 A12 USB_B_PWR_ON_N UO_POD_C (CTX) B24
C5 CP_CS_N2 D D11 USB_B_PWR_ERR_N UO_POD_E (ETX) B25
SRAMLB_CSB B2 CP_CS_N3 D
B1 L26 PHY_XTALI A11 B21
SRAMUB_CSB CP_CS_N4 QFE_XTI IR_OUT AUD_COMP_CLK
K1 K22 PHY_XTALO AC16 D20
CP_CS_N5 QFE_XTO IR_IN IR_IN AUD_COMP_LRCLK
EBI_CSB_6 K2 CP_CS_N6 AUD_COMP_DATA A21
H5 A20 CLK27_I
EBI_CSB_7 CP_CS_N7 CLK27_VCXO_I CLK27_O QUAKE has internal PD
EBI_CSB_8 D8 CP_CS_N8 CLK27_VCXO_O B20 AD23 GPT_INCAP0 AUD_MCLK C21
A9 D19 CLK27_PCR_DAC for GPT_INCAP[2:0], D10 E20
CP_BOOTSEL_CS0_N PCRDAC GPT_INCAP1 AUD_REQ_N
GPT_PWMA & GPT_PWMB. AD15 GPT_INCAP2
HSI_DATA0 A15
CLK54_OUT V1 HSI_DATA1 B15
SEL_FLASH1/ROMB CLK40_OUT R203 33_s MC_CLK40
SEL_FLASH1/ROMB CP_CLK40_OUT L1 MC_CLK40 AD21 GPT_PWMA
U4 CLK27_OUT AE15
CLK27_OUT GPT_PWMB
CP_CLK27_OUT D5 HSI_PKTDAT A19
AE23 I2C_SDA HSI_PKTSYN B19
R204 33_s MC_CLK27 AF23 C19
MC_CLK27 I2C_SCL HSI_PKTCLK
RP200
AE24 DMX_DBG_RXD
AF24 V4 1 8 INFO_DATA
DMX_DBG_TXD MCO_PKTDAT INFO_SYNC INFO_DATA
TP203 V3 2 7
27MHz MCO_PKTSYN INFO_CLK INFO_SYNC
MCO_PKTCLK V2 3 6 INFO_CLK
SPI_CLK R200 33_s U3 4 5
SPI_SCK
SPI_MISO T4 SPI_MISO
U1 C25 33_4_s
SPI_MOSI SPI_MOSI DO_POD_DATA (DRX)
MC_SPI_CSB U2 SPI_PCS0 DO_POD_CLK (CRX) D23
AC23 SPI_PCS1
QUAKE has internal PU AF4 SPI_PCS2
for SPI_PCS[3:0]. AE4 SPI_PCS3 MCI_PKTDAT W3 PKT_DATA
MCI_PKTSYN W2 PKT_SYNC
MCI_PKTCLK W1 PKT_CLK
D12 SFTM_PWRCLKP
27 MHz VCXO 35.84 MHz XO E12 SFTM_PWRCLKN MENC_PKTDAT L2
B12 SFTM_DIB_DATAP MENC_PKTSYN L3
Ground guard these components and all associated traces, including traces to Quake and Ground guard these components and all associated traces, including C12 L4
TP230 SFTM_DIB_DATAN MENC_PKTCLK
connect ground guard to digital ground. Place ground vias every 0.25 inches. traces to QUAKE and connect ground guard to analog ground. Place
ground vias every 0.25 inches.
TP206
R227 R226 R225 R224 D220 R222 Y220
4.7K_s 4.7K_s 4.7K_s 4.7K_s 1sv322 51_s 27mhz
CLK27_PCR_DAC 1 2 1 2 CLK27_I
R210
1

47K_s
1

C223 R223 C220

BER Test Header
1

C225 C224 1000P_s 100K_s 22P_s R220 PHY_XTALI

0.1U_s 0.1U_s C221 100K_s PHY_XTALO
2

0.01U_s
2

D +3.3V
R221 C212 Y210 C211
2

D D D 100_s 15P_s 35_84mhz_sm 15P_s L210 J201

D CLK27_O 2.7uH_c_1210 1
INFO_DATA 2
1

A A INFO_SYNC 3
C222 INFO_CLK 4
47P_s MC_CLK40 5
TP207
2

6
C210
D 68P_s D DNI San Diego, California, USA. Taipei, Taiwan, R.O.C.
Title
header_6_pins
A QUAKE_DIGITAL.SCH
Size Document Number File Name Rev
C A
864684-049
Date: Friday, September 26, 2003 Sheet 7 of 14
 5 4 3 2 1

ROM Socket
Daughter card
interface

+3.3V
TP351 BOOT BLOCK FLASH
J300 1
SEL_FLASH1/ROMB 1 2 EBI_ADDR_[24:1]
SEL_FLASH1/ROMB EBI_ADDR_10 EBI_ADDR_20
TP319 1 3 4 1 TP350
EBI_ADDR_11 ROM_CSB EBI_ADDR_24
TP320 1 5 6 ROM_CSB
EBI_ADDR_18 EBI_ADDR_13 EBI_ADDR_23 U300
TP317 1 7 8 1 TP345
EBI_ADDR_19 EBI_ADDR_3 EBI_ADDR_22 C4
TP318 1 9 10 1 TP344 A21 EBI_DATA_[15:0]
EBI_ADDR_17 EBI_ADDR_2 EBI_ADDR_21 C5
TP315 1 11 12 1 TP343 A20
D EBI_ADDR_15 EBI_ADDR_7 EBI_ADDR_20 A6 D
TP316 1 13 14 1 TP342 A19
EBI_ADDR_4 EBI_DATA_12 EBI_ADDR_19 B5 E2 EBI_DATA_15
TP313 1 15 16 1 TP341 A18 D15
EBI_ADDR_1 EBI_DATA_11 EBI_ADDR_18 B6 D2 EBI_DATA_14
TP314 1 17 18 1 TP340 A17 D14
EBI_ADDR_9 EBI_DATA_10 EBI_ADDR_17 D1 F3 EBI_DATA_13
TP311 1 19 20 1 TP339 A16 D13
EBI_ADDR_6 EBI_DATA_9 EBI_ADDR_16 C1 E4 EBI_DATA_12
TP312 1 21 22 1 TP338 A15 D12
EBI_ADDR_5 EBI_DATA_15 EBI_ADDR_15 B1 D4 EBI_DATA_11
TP309 1 23 24 1 TP337 A14 D11
EBI_RDB EBI_DATA_14 EBI_ADDR_14 A1 F6 EBI_DATA_10
TP310 1 25 26 1 TP336 A13 D10
EBI_DATA_8 EBI_DATA_13 EBI_ADDR_13 C2 E6 EBI_DATA_9
TP307 1 27 28 1 TP335 A12 D9
EBI_ADDR_14 EBI_ADDR_12 EBI_ADDR_12 A2 D6 EBI_DATA_8
TP308 1 29 30 1 TP334 A11 D8
EBI_ADDR_16 EBI_ADDR_8 EBI_ADDR_11 B2 F2 EBI_DATA_7
TP305 1 31 32 1 TP333 A10 D7
EBI_DATA_7 EBI_DATA_5 EBI_ADDR_10 C3 E3 EBI_DATA_6
TP306 1 33 34 1 TP332 A9 D6
EBI_DATA_6 EBI_DATA_4 EBI_ADDR_9 A3 D3 EBI_DATA_5
TP303 35 36 1 TP331 A8 D5
EBI_DATA_3 EBI_DATA_2 EBI_ADDR_8 A7 F4 EBI_DATA_4
TP304 37 38 1 TP330 A7 D4
EBI_DATA_1 EBI_ADDR_7 C6 E5 EBI_DATA_3
TP301 39 40 A6 D3
EBI_DATA_0 TP302 EBI_ADDR_6 B7 D5 EBI_DATA_2
TP352 41 42 1 A5 D2
EBI_ADDR_5 A8 F7 EBI_DATA_1
EBI_ADDR_4 A4 D1 EBI_DATA_0
hdr42_21x2_50_sm C7 A3 D0 E7
EBI_ADDR_3 B8
FLE-121-01-G-DV-A (SAMTEC) EBI_ADDR_2 A2
C8 A1
DNI: (Install only for the Proto, EBI_ADDR_1 D8 A5
D D A0 WP/ +3.3V
VCC F5
EPR and PPR) E1
SYS_RESETB VCCQ
Layout Note: Remapping connector SYS_RESETB B4 RP/ VPP A4

1
FLASH1_CSB FLASH1_CSB D7
signals is allowed for layout EBI_RDB CE/ C300
EBI_RDB F8 C302
EBI_R/WB OE/ 0.1U_s
optimization if necessary. EBI_R/WB B3 E8 0.01U_s
WE/ GND

2
F1

2
NOTE: All test pads GND The
should be placed at the placement of
bottom layer C302 should
Intel_GE28F320C3BD70
xxxxxx-xxx-xx D be near the
E1 and F5 of
U300.
TABLE 1: MEMORY OPTIONS

C
SIZE TYPE/VENDOR C
BOOT BLOCK(U300)
uBGA package
only
32 MBIT Intel_ GE28F320C3BD70
ST_M28W320ECB70_ZB1

SRAM

+3.3V

DNI
R311 10K_s EBI_DATA_0 R302 10K_s SRAM_VBATT
DNI SRAM_VBATT
R312 10K_s EBI_DATA_1 R303 10K_s

D6
E1
1

1
DNI U301
B B
R313 10K_s EBI_DATA_2 R304 10K_s R300 C301 C303 EBI_ADDR_1
DDR SDRAM SPEED SETTING A3

VCC1
VCC2
DNI 10K_s 0.1U_s 0.01U_s EBI_ADDR_2 A0
R314 10K_s EBI_DATA_3 R305 10K_s A4 A1

2
EBI_ADDR_3

2
121.5MHz => EBI_DATA_[3:2] = 10 The A5 A2
DNI EBI_ADDR_4 B3 G1 EBI_DATA_15
R315 10K_s EBI_DATA_4 R306 10K_s placement EBI_ADDR_5 A3 I/O15 EBI_DATA_14
B4 A4 I/O14 F1
DNI of C303 EBI_ADDR_6 C3 F2 EBI_DATA_13
R316 10K_s EBI_DATA_5 R307 10K_s EBI_ADDR_7 A5 I/O13 EBI_DATA_12
MIPS SPEED SETTING should be C4 A6 I/O12 E2
DNI EBI_ADDR_8 EBI_DATA_11
R317 10K_s EBI_DATA_6 R308 10K_s D D4 A7 I/O11 D2
near the EBI_ADDR_9 H2 C2 EBI_DATA_10
DNI 162MHz => EBI_DATA_[6..4] = 010 EBI_ADDR_10 A8 I/O10 EBI_DATA_9
R318 10K_s EBI_DATA_7 R309 10K_s D6 and E1 H3 A9 I/O9 C1
EBI_ADDR_11 H4 B1 EBI_DATA_8
of U301. EBI_ADDR_12 A10 I/O8 EBI_DATA_7
R319 10K_s EBI_DATA_8 R310 10K_s H5 A11 I/O7 G6
EBI_ADDR_13 G3 F6 EBI_DATA_6
EBI_ADDR_14 A12 I/O6 EBI_DATA_5
RP300 G4 A13 I/O5 F5
EBI_ADDR_15 F3 E5 EBI_DATA_4
EBI_DATA_9 1 8 EBI_ADDR_16 A14 I/O4 EBI_DATA_3
EBI_DATA_10 F4 A15 I/O3 D5
2 7 EBI_ADDR_17 E4 C6 EBI_DATA_2
EBI_DATA_11 3 6 A16 I/O2 EBI_DATA_1
EBI_DATA_12 D3 nc17 I/O1 C5
4 5 B6 EBI_DATA_0
EBI_RDB I/O0
10000_4 A2 /OE
SRAM_CSB B5 B2 SRAMUB_CSB
/CS1 /UB SRAMUB_CSB
A6 A1 SRAMLB_CSB
ncCS2 /LB SRAMLB_CSB
RP301 EBI_R/WB G5 /WE GND1 D1
1 8 H1 E6
EBI_DATA_13 EBI_DATA_[15..13] to be used by nc1 GND2

3
2 7 R301 H6
EBI_DATA_14 3 6 F/W to detect HW configurations. POR_RAM_ENB nc2
1 Q300 G2 E3
EBI_DATA_15 4 5 POR_RAM_ENB nc3 nc4
2sc2712
EBI_DATA_[15..13] 111 = Quake Installed
1K_s CY62137VLL
10000_4 EBI_DATA_[15..13] 000 = Quake RP Installed 481396-001-69 D

2
D

RESET CONFIGURATION:
D
cp_data00 RC: ebi_config Bit
A
cp_data01 RC: boot_config Bit A
cp_data02 RC: Memory Clock Speed Select Bus Bit 0
cp_data03 RC: Memory Clock Speed Select Bus Bit 1
cp_data04 RC: MIPS Clock Speed Select Bus Bit 0
cp_data05 RC: MIPS Clock Speed Select Bus Bit 1
cp_data06 RC: MIPS Clock Speed Select Bus Bit 2
cp_data07 RC: USB Normal Clock Source Select
cp_data08 RC: Internal clk27 Alternate Source Select San Diego, California, USA. Taipei, Taiwan, R.O.C.
Title
cp_data09 RC: MIPS After Reset Delay Enable
PLATFORM_FLASH & SRAM.SCH
cp_data10 RC: Staggered Reset Off Select
Size Document Number File Name Rev
cp_data11 RC: Slip ckt control C A
864684-049
cp_data12 RC: PLL By-Pass Select Date: Friday, September 26, 2003 Sheet 8 of 14
5 4 3 2 1
 5 4 3 2 1

RP400
SD_ADDR_[6..0] SD_ADDR_10 DDR_ADDR_10
SD_ADDR_10 1 16
SD_ADDR_0 2 15 DDR_ADDR_0
SD_ADDR_1
SD_ADDR_2
3
4
14
13
DDR_ADDR_1
DDR_ADDR_2
16 MBYTES UNIFIED DDR_SDRAM
SD_ADDR_3 5 12 DDR_ADDR_3
SD_ADDR_4 6 11 DDR_ADDR_4
SD_ADDR_6 7 10 DDR_ADDR_6 +2.5V
SD_ADDR_5 8 9 DDR_ADDR_5

33_8

1
1
467639-001
RP401 C409 C410 C411 C403 C404 C405 C401 6.3V X5R
DDR_LDQS_0 0.01U_s 1000P_s 1U_s 1000P_s 0.01U_s 0.1U_s 10U_c 1206 See
SD_LDQS_0 1 16
SD_LDQS_0

2
2
SD_LDM 2 15 DDR_LDM table page 1
SD_LDM
D SD_WEB 3 14 DDR_WEB D
SD_WEB
SD_CASB 4 13 DDR_CASB
SD_CASB SD_RASB 5 12 DDR_RASB D
SD_RASB
SD_CSB_0 6 11 DDR_CSB_0
SD_CSB_0
SD_BA_0 7 10 DDR_BA_0
SD_BA_0

15
18
33
55
61
SD_BA_1 DDR_BA_1

1
3

9
SD_BA_1 8 9 U400

VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDD

VDD
VDD
33_8 DDR_DATA_0 2
DDR_DATA_1 DQ0
4 DQ1
RP402 DDR_DATA_2 5
SD_DATA_[7..0] DDR_DATA_3 DQ2 DDR_ADDR_0
SD_DATA_0 DDR_DATA_0 7 DQ3 A0 29
1 16 DDR_DATA_4 DDR_ADDR_1
SD_DATA_1 DDR_DATA_1 8 DQ4 A1 30
2 15 DDR_DATA_5 DDR_ADDR_2
SD_DATA_2 DDR_DATA_2 10 DQ5 A2 31
3 14 DDR_DATA_6 DDR_ADDR_3
SD_DATA_3 DDR_DATA_3 11 DQ6 A3 32
4 13 DDR_DATA_7 DDR_ADDR_4
SD_DATA_4 DDR_DATA_4 13 DQ7 A4 35
5 12 DDR_DATA_8 DDR_ADDR_5
SD_DATA_5 DDR_DATA_5 54 DQ8 A5 36
6 11 DDR_DATA_9 DDR_ADDR_6
SD_DATA_6 DDR_DATA_6 56 DQ9 A6 37
7 10 DDR_DATA_10 DDR_ADDR_7
SD_DATA_7 DDR_DATA_7 57 DQ10 A7 38
8 9 DDR_DATA_11 DDR_ADDR_8
59 DQ11 A8 39
DDR_DATA_12 60 40 DDR_ADDR_9
33_8 DDR_DATA_13 DQ12 A9 DDR_ADDR_10
SD_ADDR_7 R408 33_s DDR_ADDR_7 62 DQ13 A10/AP 28 +2.5V
SD_ADDR_7 R409 DDR_DATA_14 63 41 DDR_ADDR_11
SD_ADDR_8 33_s DDR_ADDR_8 DQ14 A11
SD_ADDR_8 R410 DDR_DATA_15 65 42 DDR_ADDR_12
SD_ADDR_9 33_s DDR_ADDR_9 DQ15 A12
SD_ADDR_9 R411 33_s DDR_ADDR_11 17
SD_ADDR_11 NC (A13)
SD_ADDR_11 R412 33_s DDR_ADDR_12
SD_ADDR_12
SD_ADDR_12
+2.5V 8M x16 R401 C406
SD_DATA_[15..8] 1K_s 0.01U_s
R413 DDR_UDQS_1 51 Place caps near 10% 50V X7R
SD_DATA_8 33_s DDR_DATA_8 UDQS
R415 DDR_LDQS_0 16 U202 1%
SD_DATA_9 33_s DDR_DATA_9 LDQS
R416 DDR_WEB 21
SD_DATA_10 33_s DDR_DATA_10 WE (DDR_SDRAM)
R417 R402 R403 DDR_CASB 22 49 SD_VREF
SD_DATA_11 33_s DDR_DATA_11 CAS VREF
R418 10K_s 10K_s DDR_RASB 23
SD_DATA_12 33_s DDR_DATA_12 RAS
R419 R407 R405 DDR_CSB_0 24
SD_DATA_13 33_s DDR_DATA_13 CS

1
R420 121_s 121_s DDR_BA_0 26 R400
SD_DATA_14 33_s DDR_DATA_14 BA0
R421 DDR_BA_1 27 C400 1K_s
SD_DATA_15 33_s DDR_DATA_15 BA1
DDR_CLKE 44 0.01U_s 1%
DDR_CK D CKE 10% 50V X7R

2
C 45 CK
C
DDR_CKB 46
DDR_UDM CK
47 UDM
DDR_LDM 20
SD_CLK R414 20_s DDR_CK LDM D D
SD_CLK R404 R406 53
121_s 121_s C408 NC
SD_CLKB R428 20_s DDR_CKB NC 43
SD_CLKB 10P_s 19 25
DNU NC

VSSQ

VSSQ
VSSQ
VSSQ

VSSQ
50 14

VSS
VSS

VSS
DNU NC
C407
10P_s D
Place this cap

34
48
52
58
64
66
12
Place this cap

6
close to the U200 close to the
D
D (QUAKE)
U202 MICRON - MT46V8M16TG-6T
SD_CLKE R422 33_s DDR_CLKE D
SD_CLKE R423
SD_UDQS_1 33_s DDR_UDQS_1
SD_UDQS_1 R424 33_s
SD_UDM DDR_UDM
SD_UDM

LAYOUT NOTES:
1. DDR_DATA[15:0] lines and strobes should be the shortest (and most direct) trace lengths as possible.
2. CK & CKB traces again should be the shortest possible lengths, with CK & CKB being adjacent to each other on ALL layers.
3. DDR_ADDR[15:0], & control signals are not as critical as layout items 1 and 2.
4. NO data or data strobe traces should exceed 2 inches in length. (The 2 inches includes traces to and from series termination
resistors) Less critical signals should be less than 3 inches. Clock traces can be up to 3 inches, but should be as short as possible.
Route DQS and clock pair signal traces FIRST when laying out the board.
B 5. Trace length variations are as follows: B

Data, DQS signal traces have no more than 0.5 inch variation
Address, DQM, control signal traces have no more than 1.0 inch variation
Clock traces should be as closely matched as possible.
6. Clock traces should be on same layer(s) and should be spaced 5 mils from each other, with other signal traces spaced 10 mils away.
7. Number of vias for data and DQS lines should be restricted to maximum of 2 per signal trace. Other signals should be restricted to
no more than 3 vias per signal trace. Micro-vias (14 mil through hole) can be used for signals, with larger (20 mil minimum through
hole) used for power and grounds.
8. Trace widths for signals should be 5-6 mils. Power and ground signals should have minimum 10 mil traces from pins to vias (that drop
down to power/ground planes)
8a. DDR_VREF signal should be 20mil trace.
9. DDR section of board should keep all signals that are NOT part of the DDR interface outside of defined area on ALL layers.
10. Decoupling capacitors should be used in accordance with the DDR manufacturer's recommendations. Bulk bypass capacitors should be
located nearby DDR memory.
11. Power and ground pins should have dedicated traces to VIA, with adjacent power and ground pins using common trace only when
distance to via is less than .2 inch from any one pin/ball. In this case a more robust trace should be used to connect more than one
pin to the via. (15 mil trace minimum)

A A

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
DDR_SDRAM.SCH
Size Document Number File Name Rev
C A
864684-049
Date: Friday, September 26, 2003 Sheet 9 of 14
5 4 3 2 1
 5 4 3 2 1

+3.3V

Bypass

1
C900 C901 C902 C903 C904 C905 C906 C907 C908 C909 C915
4700P_s 0.1U_s 0.1U_s 4700P_s 0.1U_s 4700P_s 0.1U_s 47P_s 4700P_s 0.1U_s 47P_s

2
+3.3V D
D D

+3.3V

14
21
30
46
47
54
71
79
90
96
31
41
60
69
6
U900
R922

VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
10K_s 9 10
SYS_RESETB TVPC_DETECTB TVPC_SIO
SYS_RESETB 2 TVPC_CLOCK 8
TVPC_RESETB 11
D912 3 MC_RESETB 97 13
bat54alt1 RESETB TVPC_5V_SENSE
TVPC_3V_SENSE 12
POR_RESETB 1 SPI_CLK 1
POR_RESETB SPI_CLK MC_SPI_CSB SCLK
MC_SPI_CSB 2 SPL_CSB
SPI_MOSI 3 4 SPI_MISO
SPI_MOSI MOSI MISO SPI_MISO
RP901
+3.3V 5 4 22 TMROEB MC_IRQB
6 3 23 TMS MC1.7 UP_INTB 5 MC_IRQB
7 2 24 TCK
8 1 25 26 TD900
TDI TDO TDO
470_4
D
WRPROT_1 49 FUSE1 FUSE1RTN 50
WRPROT_3 51 FUSE0 FUSE0RTN 52

76 MIERROR
R903 R904 D
77 MCLKI MOERROR 45
470K_s 470K_s 78 44
MIVAL MCLKO
MOVAL 43
81 MDI7
82 MDI6
83 MDI5
D
C 84 MDI4 MDO7 40 C
85 MDI3 MDO6 39
D
86 MDI2 MDO5 38
87 MDI1 MDO4 37
INFO_DATA 88 36
INFO_DATA PKTDATAIN/MDI0 MDO3
MDO2 35 RP900
INFO_SYNC 89 34
INFO_SYNC PKTSTARTIN/MISTAT MDO1 MC_PKTDATA PKT_DATA
33 1 8 PKT_DATA
INFO_CLK PKTDATAOUT/MDO0 PKT_SYNC
92 2 7 PKT_SYNC
INFO_CLK MC_CLK40 PKTCLKIN/BITCLK PKT_CLK
94 3 6 PKT_CLK
MC_CLK40 MC_CLK27 SYNC_CLK MC_PKTSTART
100 32 4 5
MC_CLK27 CLK_27 PKTSTARTOUT/MOSTRT
+3.3V 99 28 MC_PKTCLK
CTRL_CLK_27 PKTCLKOUT 33_4_s
61 TAD7
62 TAD6
+3.3V CLK27M 63 R926 51_s POR_RAM_ENB
TAD5
TEST_PAD 64 TAD4 TESTOUT3 55
65 TAD3 TESTOUT2 56
66 57 R914
TAD2 TESTOUT1
1

67 58 4.7K_s
TAD1 TESTOUT0
68 TAD0
D901
1n5711 VB901 73
TESTPIN TESTCLK
74 TESTWRB PDUNDERB 18
SRAM_VBATT D
3

75 TESTSEL VSUPPLY 19 SRAM_VBATT

VBATT 16 VBATT
17 98

GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDBATT VBATT_EN
1
1

1
C911 MC1_7C

15
20
27
29
42

48
53
59
70
72
80
91
93
95
+ C910 0.1U_s C913 + C914

7
100uf_07 0.1U_s 10u_50v
2
1

Low Leakage Cap

2
D902 D911
2

2
1n4148w 1n4148w
D D
B D D B
D VB900 D
2

TESTPIN

BTV
3

BT905
3_0V_BR2032T3L_B
2

VB902 JET

TESTPIN
R906
VB903 620_s
TESTPIN

DNI
BTV BTV BTV BTV
3

A BT907 A
BT903 BT904 BT906 106007-002
3_0V_BR2335T3L_B 3_0V_BR2450A_GB 3_0V_BR2330A_GA
123002-020-99 414816-003-99
2
2

JET JET JET JET

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
SECURITY.SCH
Size Document Number File Name Rev
C A
864684-049
Date: Friday, September 26, 2003 Sheet 10 of 14

5 4 3 2 1
 A B C D E

+2.5V
AB5 AB12
AB6 AB13
Place bypass capacitors of +3.3v, +2.5v, and G22
+3.3V +1.2V near IC's pin on bottom side. J22
AB14
C427 C428 QUAKE pin numbers for each cap are AB21 E8 L22
0.1U_s 0.1U_s
AB15
indicated. AB22 E9 E15 N22 K5 V5
AB17 +1.2V
W22 E10 E18 R22 L5 Y5
AB18
C482 D

AB22
0.1U_s

G22

N22
R22
E10
E15
E18

L22
J22
C441 C442 C443 C444 C445 C446 C447 C448

E8
E9

K5
L5
U200C Quake 0.01U_s 0.1U_s 0.1U_s 0.01U_s 0.1U_s 0.01U_s 0.1U_s 0.01U_s
AB21 VDD12 V5

VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
4
+3.3V +3.3V D VDD12 4
AB18 VDD12 VDD12 W22
L415 AB17 VDD12 Y5
ferrite_0603 VDD12 D
A17 AB15 VDD12
AB14 VDD12 AA5 AB16 AB19 E6 E21 M5 U22 +3.3V
L402
(DAC B) VDD33
1 2 VDD33 AB16 AA5 AB20 E7 E11 E22 N5 V22
10uH_c_1008 L425
AB5 VDD25 QUAKE Power VDD33 AB19
AB6 VDD25 VDD33 AB20
ferrite_0603 C432 AB12 E6
0.1U_s VDD25 VDD33 C419 C420 C421 C422 C423 C424 C425 C426
AB13 VDD25 VDD33 E7
ANA_3.3V 1 2 E11 0.1U_s 0.01U_s 0.1U_s 0.1U_s 0.01U_s 0.01U_s 0.01U_s 0.1U_s
VDD33
D VDD33 E21
C440 D17 E22
0.1U_s QVD_AVDD_A VDD33
A17 QVD_AVDD_B VDD33 M5
C434 467639-001 DAC A, C & D not used. D
B18 QVD_AVDD_BIAS VDD33 N5
6.3V X5R D16 QVD_AVDD_C VDD33 U22
10U_c 1206 See A16 V22
+3.3V QVD_AVDD_D VDD33
table page
D
1 SDC_AVDD E13 SDC_AVDD SDC_AGND E14
+3.3V
A +3.3VA0 C20 XTAL_CLK27_PSUPA XTAL_CLK27_NSUPA E19

U200A Quake
D

8
7
6
5
+3.3VA1 M26 M22
L418 +3.3VA2 BTSC_ADC2_PSUPA BTSC_ADC2_NSUPA_SHA Signal Opitimize +3.3V RP410
N24 BTSC_ADC2_PSUPA_SHA BTSC_ADC2_NSUPA L23
ferrite_0603 1000_4
Place these parts near QUAKE Analog
1 2 +3.3VA3 K24 G23 QUAKE.

8
7
6
5
+3.3VA4 DI_ADC1_PSUPA_SHA DI_ADC1_NSUPA RP411

1
2
3
4
H26 DI_ADC1_PSUPA DI_ADC1_NSUPA_SHA J25 TNR_RFTE0 U24
C453 1000_4 U25
TNR_RFTD TUNER_SDA
L419 0.1U_s OOB_AGC K26 U26
+3.3VA5 IB_IF_POS DI_ADC1_VIP TNR_RFTCK TUNER_SCLK
ferrite_0603 R24 N23 RP412 K25
+3.3VA6 DO_ADC3_PSUPA_SHA DO_ADC3_NSUPA IB_IF_NEG DI_ADC1_VIN
P26 P22 470_4
DO_ADC3_PSUPA DO_ADC3_NSUPA_SHA

1
2
3
4
1 2 1 8
2 7 A23 DI_RFAGC_SDV UO_IOUTP F26 TX_DAC+
C454 +3.3VA7 K23 L25 3 6 A25 E23
QFE_XTAL_PSUPA QFE_XTAL_NSUPA DI_AGC_SDV UO_IOUTN TX_DAC-
L420 0.1U_s L24 4 5
ferrite_0603 QFE_ADC_ASUB
OOB_IF_POS R25 DO_ADC3_VIP
OOB_IF_NEG R26 DO_ADC3_VIN
3 1 2 +3.3VA8 F24 E25 C23 3
UO_DAC_PSUPA UO_DAC_ASUB QAM_AGCI DO_AAGC_SD
UO_DAC_BG_NSUPA E26 OOB_VCO_POS T25 DO_LO_BP
C455 C472 F25 E24 T24
UO_VBIAS UO_DAC_NSUPA OOB_VCO_NEG DO_LO_BN
L421 0.1U_s 1U_s C14 Place no traces or parts between
AUD_LEFT_POS AUDIO_LEFT_POS

1
ferrite_0603 D14
AUD_LEFT_NEG AUDIO_LEFT_NEG AUDIO_LEFT_POS/AUDIO_LEFT_NEG and
C456 C457 A14
AUD_RIGHT_POS AUDIO_RIGHT_POS
1 2 0.1U_s 0.1U_s B14 AUDIO_RIGHT_POS/AUDIO_RIGHT_NEG.
+3.3VA9 AUD_RIGHT_NEG AUDIO_RIGHT_NEG

2
T26 R23
C484 DO_LO_VBB DO_LO_BGND Keep traces close in length and
L422 0.1U_s +1.2VA1 T22 T23 AF22 route traces next to one another.
ferrite_0603 DO_LO_VDDB DO_LO_VSSB D AUD_I2SI_CLK
AE22
+1.2VA2 D22 C22 AD22
AUD_I2SI_LRCLK
E17
Surround each pair with DGND.
QFE_VPP QFE_PGND AUD_I2SI_DATA QVD_DV_A_P
1 2 R475 470_s B17 DIG_COMPOSITE
+1.2VA3 QVD_DV_B_P
G24 VDD_PLL VSS_PLL G25 QAM_AGCT QVD_DV_C_P E16 Surround video trace
C485 B16 DAC A, C & D not used.
L423 0.1U_s QVD_DV_D_P DIG_COMPOSITE with DGND.

1
ferrite_0603 +1.2VA4 D25 G26
UO_DAC_PSUPD UO_DAC_NSUPD C475
0.1U_s N25 BTSC_ADC2_VIP UO_PWR0_GATEB D26 US_CTL_CSB
1 2 N26 C24 US_CTL_CLK

2
+1.2VA5 BTSC_ADC2_VIN UO_PWR1_CLK
F22 UO_QUIET_PSUPD UO_QUIET_NSUPD D24 UO_PWR2_DATA A24 US_CTL_DATA
C486 B26
L424 0.1U_s UO_PWR3
VSS T16 A
ferrite_0603 D
L11 VSS VSS T15
L12 VSS VSS T14 J24 AVD_ADC1_VIP
1 2 L13 VSS VSS T13 J23 AVD_ADC1_VIN UO_RF_SD_OUT B23 TX_OEN
L14 VSS VSS T12
C487 L15 T11
0.1U_s VSS VSS
L16 VSS VSS R16
M11 VSS VSS R15 D18 AUD_DIGAUD DI_ADC1_VREFN J26
M12 VSS VSS R14 DI_ADC1_VREFP H22
L410 M13 R13 H23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ferrite_0603 VSS VSS DI_ADC1_VCM

M14 VSS VSS R12 (UO_IREFD)
F23 UO_DAC_BG_PSUPA
M15
M16
N11
N12
N13
N14
N15
N16

R11
P11
P12
P13
P14
P15
P16

1 2 BTSC_ADC2_VREFN M24
+1.2V H24 M23
C435 QFE_ADC_VBGOUT BTSC_ADC2_VREFP
BTSC_ADC2_VCM M25
L411 0.1U_s H25
ferrite_0603 QFE_EXT_IREF
D
C18 QVD_RBIAS DO_ADC3_VREFN P24
L401 1 2 R472 C473 R473 P23
2
10uH_c_1008 8.06K_s 0.1U_s 30.1K_s DO_ADC3_VREFP 2
A18 QVD_VREF DO_ADC3_VCM P25
C436 1% 1%
L412 0.1U_s C17
ANA_1.2V ferrite_0603 R474 C474 QVD_AVSS_BIAS
562_s 0.1U_s C16 C492 C481 C493 C463 C464 C465 C466 C467 C471
C450 1% QVD_AVSS_BIAS2
1 2
467639-001 1U_s 1U_s 1U_s 1U_s 1U_s 1U_s 1U_s 1U_s 1U_s
10U_c
6.3V X5R C437 VIDEO DAC CALCULATIONS
1206 See L413 0.1U_s
A Ioutfs = 17.4 mA with Rbias = 628 ohms
ferrite_0603
table page D
1 Choose Rbias = 562 ohms
1 2
A Rload = 75 ohms (see video page) A
C438
L414 0.1U_s Dwhite = 364 (9 bit value) NTSC
ferrite_0603 Dsync = 14 (9 bit value) NTSC
1 2 Vout p-p = Ioutfs * (628 ohms / Rbias) *
C439
Rload * ((Dwhite - Dsync)/511) = 1 Vp-p
0.1U_s

1 1

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
QUAKE_ANALOG.SCH
Size Document Number File Name Rev
864684-049 A
Custom
Date: Friday, September 26, 2003 Sheet 11 of 14
A B C D E
 5 4 3 2 1

Audio DAC Filter and Output Amp

+5V
R731 100K_s 1%
Video DAC Filter and Output Amp

1
C721 22P_s
1 2 C719
D D
0.1U_s
+5V

2
R727 D R729 U700A

8
8.25K_s 47.5K_s NJM4580 D
1% 1% 3 128006-129-26
AUDIO_LEFT_POS

1
+ DAC_AUD_LEFT R713 REMOD_VIDEO
1 LINE_OUT_LEFT

1
2 2 Vrms at 0 dBFS. 3.3K_s C702 R703
R728 C720 R730 - 0.1U_s 1.2K_s
8.25K_s 270P_s 47.5K_s -5V C739

3
1% 1% 100P_s

4
AUDIO_LEFT_NEG
1 Q702
D 2sc2712

1
Place no traces or parts between R732 100K_s 1% D R708
C718 L700 R702 R704 75_s

2
AUDIO_LEFT_POS and AUDIO_LEFT_NEG.

3
0.1U_s 6.8uH_c_0805 20_s 1K_s 1%
COMP_OUT
Keep traces close in length and route C723 22P_s Q701 1%

2
DIG_COMPOSITE 1 1
1 2 2sc2712
traces next to one another. Surround D C704 C707
the pair of traces with digital 10P_s 100P_s

2
1

1
R735 100K_s 1% 1 2
ground plane. R700 C700 C701 R701 Q700
102_s 270P_s 150P_s 280_s 2sc2712 D
C724 22P_s +5V 1% 1% R706

2
1 2 R705 887_s R707
510_s 1% 1K_s

R733 R736 U700B

8
8.25K_s D 47.5K_s NJM4580 -5V
1% 1% 128006-129-26 D D
AUDIO_RIGHT_POS 5 +
7 DAC_AUD_RIGHT R714
LINE_OUT_RIGHT
1

1
6 2 Vrms at 0 dBFS. 3.3K_s
R734 C725 R737 - C703
8.25K_s 270P_s 47.5K_s 1% C745 0.1U_s
1% -5V 100P_s
2

2
AUDIO_RIGHT_NEG
D
Place no traces or parts between R738 100K_s 1% D
C C
AUDIO_RIGHT_POS and AUDIO_RIGHT_NEG.
Keep traces close in length and route
C726 22P_s
traces next to one another. Surround 1 2
the pair of traces with digital ground
plane.

Video/Audio RF Modulator (Remod)

L803
4.7uH_c_0805 10%
REMOD_VIDEO 1 2

R806
150_s
RES\1%\0603 F800
3 1

3
tps4_5mb2 C810 Loop Filter must
2

R804 0.01U_s
R805 2 be as close as
B B
560_s 2K_POT possible to pins
A 118874-513-14
14&15
1

C808 R803
R807
A
10K_s
0.047U_s 2.2K_s
CH3/4_SEL

C815 C809 0.022U_s

0.1U_s
U800
R741 1 16 C807 L801 L800 R801 C800
2K_s 1% CHS SFS 0.01U_s 120nH_c_0603 150nH_c_0603 27_s 0.01U_s
A 2 PSS PLLFLT 15
DAC_AUD_LEFT REMOD_AUDIO Y800 4MHz C816 27P_s 3 13 1 2 1 2
LOP TVOUT REMOD_OUT
2 Vrms at 0 dBFS. 1.132 Vrms at 0 dBFS X7R 4 XTAL VIDEO 10
1

R810 R809 C805 9P_s C803 7P_s

R742 1K_s C820 0.1U_s 6 14 R802 R800 L804
A PREEM TVOVCC
2K_s 1% 2 7 11 470_s 470_s
DAC_AUD_RIGHT C821 AUDIO VCCA +5V
8 SPLFLT GND 5 3.3uH_c_1210
1000P_s 50K_POT C804 C802
2 Vrms at 0 dBFS. 9 PS/LO GND 12
36P_s 43P_s
R743 C818 Must be X7R
3

A A
1.3K_s 1U mc44bc375u L1119
A A A
1% 10uH_c_1008
C817
A
Lowpass filter, F3dB = 159 kHz 750P_s
5%, NPO
D C819 R808

1
0.022U_s 7.5K_s C822
A

1
C814 C813 C812 C1142 D800
+ 0.1U_s
smbj13
A 1000P_s 0.01U_s 0.1U_s
Change to 10uf_01

2
2
surface mount.
A MC44BC375U data sheet: 85% FM modulation at 1 kHz with 205 mVrms input at pin 7, with pre-emphasis. TDK part A
A
Pre-emphasis gain at 1 kHz = 0.87 dB. 100% modulation = +/- 25 kHz. NLFV25T-100K.
To achieve +/- 50 kHz FM modulation (200%) without pre-emphasis, the nominal input level at pin 7 is: A
A
2*(205 mVrms)*(0.87 dB)/(85%) = 534 mVrms.
The digital audio level at the top end of R853 must be greater than 534 mVrms in order to achieve alignment.
Target value = 566 mVrms for analog channel and 1132 mVrms for digital channel.

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
AUDIO_VIDEO.SCH
Size Document Number File Name Rev
C A
864684-049
Date: Friday, September 26, 2003 Sheet 12 of 14
5 4 3 2 1
 A B C D E

+5VA_OOB

+5V L1106
10uH_c_1008
+5VA_IB
QAM IF SAW Filter and AGC Amp

1
1
C1109 501442-002
C1107 C1108 + 10V Y5V 0805
0.1U_s 0.01U_s See table page 1.

2
10uf_01

2
60 MHz Lowpass Filter

2
4 4
L1104 L1102 L1100 IB_IF_POS
TP1104 C1104 R1101 1.5uH_c_0603 1.5uH_c_0603 1.5uH_c_0603 TP1100
A
0.01U_s 499_s 1% 10% 10% 10%

10

14

12
5
F1100 U1100 1 2 IB_IF_POS
TUNER_IF 1 3

VCC

DRV_AMP_VCC

AGC_VCC

VCC
QAM_IF+ IN CHIP

1
2 4 SAW_IF_POS 1 9 R1100
QAM_IF- ING POUT1 IF_IN+ IF_OUT-
5 C1103 C1102 C1101 C1100 1K_s
POUT2 SAW_IF_NEG C1105 R1102 5P_s 9P_s 9P_s 5P_s
16 IF_IN- IF_OUT+ 8 1%
0.01U_s 499_s 1%

2
x6964m 1 2 IB_IF_NEG
L1105 L1103 L1101
A
QAM_AGCI 11 LA7783 13 1.5uH_c_0603 1.5uH_c_0603 1.5uH_c_0603
AGC_IN AGC_OUT1 10% 10% 10%

1
3 469774-001-28 6 TP1101
C1110 AGC_SW AGC_OUT2 IB_IF_NEG
Inductors are TDK MLF1608 series
0.1U_s 4 DELAY_ADJ Table 1

2
TP1103
QAM_AGCI C1100C1101 Do not install

GND

GND

GND
A TP1102 C1102C1103 Do not install
AGND L1100L1101 0 ohm resistor
L1102L1103 0 ohm resistor

15
L1104L1105 0 ohm resistor

7
R1100 1000 ohms 1%
R1101 R1102 499 ohms 1%
A

+5VA_OOB

+5VA_OOB
3 3
149188-018

F1101
5 POUT2
OOB Tuner 4 POUT1 CHIP 2

3 SOUT IN 1

saf49_10mc220z
L1108
100nH_c_0603

L1109
A 100nH_c_0603
70 to 130 mhz LPF. Helps to

1
reduce LO leakage and also

1
reject signals above 130 R1103 C1121
51_s 0.01U_s C1120
MHz. 0.01U_s

2
C1133 C1131 Keep the bypass capacitors very

2
9P_s 5P_s R1104 close to the pins of the LA7784
A A

1
1 2 1 2 51_s
C1127

1
0.01U_s

19

20

21

22

14
4

8
L1112 C1124 C1123 C1122
220nH_c_0603 L1111 L1110 2 1000P_s 0.1U_s 0.1U_s

IF_IN1

IF_IN2

VCC_MIX_LO

VCC_LNA

VCC_LNA

VCC_POST_AMP
VCC_IF

VCC_DRIVER
A
100nH_c_0603 120nH_c_0603

2
26 MIX_OUT1
OOB_TAP 1 2
L1110 should be 27 MIX_OUT2
L1112 should be C1128
changed by new A
changed by new 0.01U_s
part number
part number 1 2 23 RF_IN1
1

1 2 24 TP1105
RF_IN2
1

C1130 R1105 C1129 U1101 C1125 OOB_IF_POS

C1134 C1132 6P_s 75_s 0.01U_s LA7784 0.1U_s
2 11P_s 2
12P_s
2

16 LO_IN1 471105-001-32 OUT1 12 1 2 OOB_IF_POS

2

A 17 LO_IN2 OUT2 13
A A
C1126
Note 3
0.1U_s
9 1 2 OOB_IF_NEG

NC_GND

NC_GND

NC_GND

NC_GND

NC_GND
AGC_IN
180 MHz Lowpass Filter

GND

GND

GND

GND

GND

GND
TP1106
R1109 L1117 L1115 L1113 C1135 OOB_IF_NEG
23.7_s 27nH_c_0603 27nH_c_0603 27nH_c_0603 0.01U_s TP1107

10

11

15

18

25

28
1% AGND
1

7
OOB_VCO_POS 1 2

C1140 C1139 C1138 C1137 R1107 See note 3

See note 3 27P_s 47P_s 47P_s 27P_s 49.9_s
1%
A
R1110 C1136
23.7_s 0.01U_s
1% 1 2
OOB_VCO_NEG
L1118 L1116 L1114
27nH_c_0603 27nH_c_0603 27nH_c_0603

Inductors are TDK MLG1608 series Notes :

TP1108
OOB_AGC 1. Use 0603 chip caps and resistors.
OOB_AGC 2. LA7784 Batwings must be connected to ground.
1

3. Keep these 2 traces very close to each other. Don't route

C1141
0.1U_s under bypass caps. Don't place any trace between them.
2

1 1
A

San Diego, California, USA. Taipei, Taiwan, R.O.C.

Title
AFE.SCH
Size Document Number File Name Rev
C 864684-049 A
Date: Friday, September 26, 2003 Sheet 13 of 14
A B C D E
 A B C D E
15.8, 1%
35.7,
1% +5V_TUNER

R519
C525 120_s
1000P_s L511
R520 C524 150nH_c_0603
1.2K_s 120P_s
A
1 2

1
Q501

1
L513 2sc5227_5
L512

3
120nH_c_0603 A
1 390nH_c_1008

2
4 4

A
C526

2
470P_s

R522 R521
OOB_TAP
4.7_s 470_s

C527
2P_s

A
S501

16
15
14
13
A

GND
GND
GND
GND
70 MHz Highpass Filter TUNER1
E500 TDEZ1X002A
C536 C534 C532
RF_conn 33P_s 22P_s 22P_s +5V_TUNER 1 GND GND 12
2 GND GND 11
1 RF_IN 3 10
GND GND
R501 1K_s 4 GND GND 9
QAM_AGCT 3 AGC OPEN 9

C535 C533 4 1 2
+5V

GND
GND
GND
GND
390P_s 150P_s Place close to C501 L500

1
0.1U_s 2 1uH_c_1008
GND
1

the ALPS TUNER

1
10 C500 A
GND 0.1U_s
R523 13 Diplexer shield

5
6
7
8
L517 GND

2
1M_2010 L516 14
100nH_c_1008 GND
120nH_c_1008 15
A GND
16 GND A
IF+ 12 QAM_IF+
2

A
A A R500
A SCLK 5
SDA SCL 150_s
6
42 MHz Lowpass Filter 7
SDA
C538 C540 AS
11

GND
3 27P_s 18P_s IF- QAM_IF- 3

A
8
L518 L519 L520 L521
390nH_c_1008 390nH_c_1008 270nH_c_1008 270nH_c_1008 A

1 2 1 2 1 2 1 2 UPSTREAM

1
A
C537 C539 C541 C542 L522
100P_s 100P_s 82P_s 39P_s
27uH_r

21
D500
smbj13

2
A

Place these parts near QUAKE. Place these parts near tuner IC. +5V +5V_TUNER
R504 470_s R502 470_s L523
R505 470_s R503 470_s SCLK 10uH_c_1008
TUNER_SCLK SDA
TUNER_SDA

1
467639-001
C558 + C557 C556 C555 C554 C553
C564 C563 C560 C559 6.3V X5R 10U_c 470u_10v 0.1U_s 1000P_s 1000P_s 1000P_s
1206

2
100P_s 100P_s 100P_s 100P_s

2
A A
2 D 2
R526
Option Table 1 0_s

R603 L608 L606 L604 C614 C613 C612 C611 R600 C603 C604
R604 L609 L607 L605 D A
Anadigics 35.7, 180nH 220nH 180nH 56pF 100pF 100pF 56pF 93.1, 15pF 270pF
ARA2018 1% 1%
Sanyo 13.0, 56nH 56nH 56nH 120pF 330pF 330pF 120pF 26.1, 6800 0.1uF
LA7791T 1% 1% pF
Microtune 15.8, 82nH 100nH 82nH 120pF 220pF 220pF 120pF 31.6, DNI 0.1uF Upstream Amp +5V_US JET
MT1530 1% 1% C602

+5V_US A
U600
la7791t
12 20 0.1U_s
/SHDN GND2
TX_OEN 18 TXEN A
C615 L608 L606 L604 R601 19
0.01U_s 56nH_c_0603 56nH_c_0603 56nH_c_0603 0_s VCC2
TX_DAC+ C608 0.01U_s 5 17
VIN+ NC C603 6800P_s
R600 16 SEE OPTION TABLE 1
VOUT+ A
C614 C613 C612 C611 26.1_s 1 T600 6
C616 120P_s 330P_s 330P_s 120P_s C609 0.01U_s 6
0.01U_s VIN- +5V_US C600
VOUT- 15 2 A
TX_DAC- 2 1000P_s
L609 L607 L605 VCC1 C604 0.1U_s UPSTREAM
VCM 14 3 4
56nH_c_0603 56nH_c_0603 56nH_c_0603 R602 4 13 458pt_1087
0_s GND1 NC SEE OPTION TABLE 1 463131-001
SEE OPTION TABLE 1 Inductors are TDK MLG1608 series 11 7 C601
NC DGND 0.1U_s
3 GND SCLK 10
R604 R603 1 9
13_s 13_s GND SDA A
/CS 8 A
1% 1% +5V_US
1 1
RP600
A A
1 8
1

SEE OPTION TABLE 1 2 7

US_CTL_CSB
3 6 C607 C606 C605
US_CTL_DATA
4 5 0.01U_s 0.01U_s 0.01U_s
US_CTL_CLK
+5V L610 +5V_US
2

10uH_c_1008 33_4_S
C610 DNI
A
0.1U_s
1

A Taipei, Taiwan R.O.C.

+ C617 San Diego, California, U.S.A.
470u_10v Title
TUNER_UPSTREAM.SCH
2

Document Number File Name Rev

A A
864684-049

Date: Friday, September 26, 2003 Sheet 14 of 14

A B C D E