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EEE C443/ EEE F313/ INSTR F313 – Analog & Digital VLSI Design
August-December, 2013
1. Introduction
Operational amplifiers (op amps) are an integral part of many analog and
mixed-signal systems. Op amps with vastly different levels of complexity are used to realize
functions ranging from dc bias generation to high-speed amplification filtering.
As a part of analog assignment, in this report we present the design and simulation of a
two-stage single ended output OP AMP (Folded cascode [differential amplifier + common
gate stage] + gain stage) with the biasing circuit for the following specifications
i. Gain ≥ 90 dB
ii. Unity Gain Bandwidth ≥ 100 MHz
iii. Phase margin ≈ 60°
2. Theoretical Expressions ( Details of Circuit realization)
Figure 2 Circuit Diagram of Two Stage Folded Cascode Single Ended Output
OPAMP
3. Simulation Setups and Plots
3.1. Gain and Unity-Gain Bandwidth (UGB)
The open loop phase margin was found to be 59.88° which falls in the range of stable
operation i.e. 45°-60°
Closed loop phase margin was found to be 59.23° during stability analysis which
falls within the range of stable operation i.e. 45 to 60 degrees. Consequently, the
opamp was found to operate in a stable manner during analysis at all corners
The Gain margin must be less than Phase Margin, also the Phase Margin should be
well above 50 degrees
tt – Corner (27° C, +3.3 V Supply)
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CMRR = 108.9 dB
3.5 Power Supply Rejection Ratio
PSRR = 80.11 dB
3.6 Slew Rate and Settling Time
A Transient pulse was given at both the inverting and non-inverting terminals
tt – Corner (27° C, +3.3 V Supply)
The Gain was observed to be 0 dB for AC Analysis thus confirming the unity gain buffer.
A Transient analysis was also performed to confirm the unity gain buffer operation.
It was observed the output peak to peak voltage and the input peak to peak voltage were
almost equal giving a gain of approximately one, confirming the unity gain buffer operation.
Results & Conclusions
Op-AMP Specifications Required Specifications Results
Gain ≥ 90 dB 105.4 dB
UGB ≥ 100 MHz 122.6 MHz
Phase Margin = 60° (approx.) 59.88°
PSRR -------------- 80.11 dB
CMRR -------------- 108.9 dB
Settling Time -------------- 554.472 ms
Slew Rate -------------- 1.83 V/µs
ICMR -------------- 2.3691 V
Output Swing -------------- 2.9295 V
Power ≤ 3 mW 2.8298 mW
Input Offset -------------- 380.6481 nV
Output Offset -------------- 70.881 mV
UGB gain -------------- 54.36 µdB