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1
of CMOS ICs - 3
Lecture# 08
VLSI Design
2 Basic Gate Designs
NAND 2-Input Gate
Design a CMOS schematic of 2-input NAND gate
VDD
a.b
a b
GND
3 Basic Gate Designs
OR 2-Input Gate
Design a CMOS schematic of 2-input OR gate
VDD
a+b
a b
GND
4 Class Exercise 1
3-Input NAND Gate
First design a CMOS schematic of 3-input NAND gate and then
design a CMOS layout of 3-input NAND gate.
VDD
a.b.c
a b c
GND
5 Class Example 1
3-Input OR Gate
First design a CMOS schematic of 3-input OR gate and then design
a CMOS layout of 3-input OR gate.
VDD
a+b+c
a b c
GND
6 Class Example 2
Design CMOS schematic and Layout of the equation
𝑓 𝑎 𝑏⋅𝑐
VDD
VDD
c b
a
f a+b.c
b
a
c c b a
GND
Gnd
7 Class Exercise 2
Design CMOS schematic and Layout of the equation
𝑔 𝑎⋅ 𝑏 𝑐
VDD
VDD
c a
b
g a . (b + c)
c b a
b c GND
Gnd
8 Stick Diagrams
𝑁 ⋅
r is effective radius
𝐴 is area of a single die
𝑑 is effective diameter
𝑑 is diameter of the wafer
𝑑 is wasted edge (due to rectangular sites)
13 Yield cont.
This procedure is slow and produces high quality oxides Silicon Wafer
Thermal oxide is native oxide, as it grows on the wafer
A faster method is to use water (as steam) instead of O 𝑥
Most oxide layers in VLSI are well above the wafer. So, thermal oxide
growth is not possible.
17 Material Growth & Deposition
Chemical Vapor Deposition (CVD) Oxide SiO2
CVD
oxide
Substrate