UART

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
-- Create Date: 14:30:08 04/08/2019
-- Design Name:
-- Module Name: PRAC3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PRAC3 is
Port ( clk : in STD_LOGIC;
Rx : in std_logic;
orx: out std_logic;
salida: out STD_LOGIC_VECTOR (7 downto 0);
Ena : out STD_LOGIC_VECTOR (3 downto 0));
end PRAC3;
architecture Behavioral of PRAC3 is
signal aux1 : std_logic_vector(7 downto 0);
component MATRIZZ is
Port ( clk_ds : in STD_LOGIC;
ABC : in std_logic_vector (7 downto 0);
display : out STD_LOGIC_VECTOR (7 downto 0);
Enable1 : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component UART is
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
o_RX_DV : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0)
);
end component;
begin
u1 : UART port map (i_Clk =>

clk,i_Rx_Serial=>Rx,o_Rx_Byte=>aux1,o_Rx_Dv=>orx);
u2 : MATRIZZ port map (clk_ds=>clk, ABC=>aux1,display=>salida , Enable1

=>Ena);
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:34:44 04/08/2019
-- Design Name:
-- Module Name: UART - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.numeric_std.all;

--library UNISIM;
entity UART is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
o_RX_DV : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0)
);
end UART;
architecture rh of UART is
type t_SM_Main is (s_Idle, s_RX_Start_Bit, s_RX_Data_Bits,
s_RX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_RX_Data_R : std_logic := '0';
signal r_RX_Data : std_logic := '0';
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_RX_Byte : std_logic_vector(7 downto 0) := (others => '0');
signal r_RX_DV : std_logic := '0';
begin
-- Purpose: Double-register the incoming data.
-- This allows it to be used in the UART RX Clock Domain.
-- (It removes problems caused by metastabiliy)
p_SAMPLE : process (i_Clk)

begin
if rising_edge(i_Clk) then
r_RX_Data_R <= i_RX_Serial;
r_RX_Data <= r_RX_Data_R;
end if;
end process p_SAMPLE;
-- Purpose: Control RX state machine
p_UART_RX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
r_RX_DV <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if r_RX_Data <= '0' then -- Start bit detected
r_SM_Main <= s_RX_Start_Bit;
else
r_SM_Main <= s_Idle;
end if;
-- Check middle of start bit to make sure it's still low
when s_RX_Start_Bit =>
if r_Clk_Count <= (g_CLKS_PER_BIT-1)/2 then
if r_RX_Data <= '0' then
r_Clk_Count <= 0; -- reset counter since we found the middle
r_SM_Main <= s_RX_Data_Bits;
else

end if;
else
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Start_Bit;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles to sample serial data
when s_RX_Data_Bits =>
if r_Clk_Count < g_CLKS_PER_BIT-1 then
else
r_Clk_Count <= 0;
r_RX_Byte(r_Bit_Index) <= r_RX_Data;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
else
r_Bit_Index <= 0;
r_SM_Main <= s_RX_Stop_Bit;
end if;
end if;
-- Receive Stop bit. Stop bit = 1
when s_RX_Stop_Bit =>
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_SM_Main <= s_RX_Stop_Bit;
else
r_RX_DV <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
r_RX_DV <= '0'
when others =>
end case;
end if;
end process p_UART_RX;
o_RX_DV <= r_RX_DV;
o_RX_Byte <= r_RX_Byte;
end rh;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:37:59 04/08/2019
-- Design Name:
-- Module Name: MATRIZZ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
entity MATRIZZ is
Port ( clk_ds : in STD_LOGIC;
ABC : in std_logic_vector (7 downto 0);
display : out STD_LOGIC_VECTOR (7 downto 0);
Enable1 : out STD_LOGIC_VECTOR (3 downto 0));
end MATRIZZ;
architecture Behavioral of MATRIZZ is
-- 12Mzh/24000=500Hz
constant max_refresh_count: INTEGER := 24000;
signal refresh_count: INTEGER range 0 to max_refresh_count;
signal refresh_state: STD_LOGIC_VECTOR(1 downto 0) := "00";
signal display_sel: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal disp_1,disp_2,disp_3,disp_4 : std_logic_vector (7 downto 0);
begin
with ABC select
disp_1 <= "11111111" when "00110000", --0
"00000000" when "00110001", --1
"10001111" when "00110010", --2
"10010001" when "00110011", --3
"11111000" when "00110100", --4
"11110001" when "00110101", --5
"11111111" when "00110110", --6
"10000000" when "00110111", --7
"11111111" when "00111000", --8
"11110000" when "00111001", --9
"11111111" when others;
with ABC select
disp_2 <= "10000001" when "00110000", --0
"00000000" when "00110001", --1
"10001001" when "00110010", --2
"10010001" when "00110011", --3

"00001000" when "00110100", --4
"10010001" when "00110101", --5
"10010001" when "00110110", --6
"10000000" when "00110111", --7
"10010001" when "00111000", --8
"10010000" when "00111001", --9
with ABC select
disp_3 <= "10000001" when "00110000", --0
"00000000" when "00110001", --1
"10001001" when "00110010", --2
"10010001" when "00110011", --3
"00001000" when "00110100", --4
"10010001" when "00110101", --5
"10010001" when "00110110", --6
"10000000" when "00110111", --7
"10010001" when "00111000", --8
"10010000" when "00111001", --9
with ABC select
disp_4 <= "11111111" when "00110000", --0
"11111111" when "00110001", --1
"11111001" when "00110010", --2
"11111111" when "00110011", --3
"11111111" when "00110100", --4
"10011111" when "00110101", --5
"10011111" when "00110110", --6
"11111111" when "00110111", --7
"11111111" when "00111000", --8

"11111111" when "00111001", --9
Enable1 <= display_sel;
gen_clock: process(clk_ds)
begin
if (rising_edge(clk_ds)) then
-- contador 500Hz (para refresco del display)
if refresh_count < max_refresh_count then
refresh_count <= refresh_count + 1;
else
refresh_state <= refresh_state + 1;
refresh_count <= 0;
end if;
end if;
end process;
show_display: process(refresh_state,disp_1, disp_2, disp_3, disp_4)
begin -- seleccion del display
case refresh_state is
when "00" =>
display_sel <= "1110"; -- display 0
when "01" =>
when "10" =>
when "11" =>

when others =>
display_sel <= "1111";
end case;
-- mostrar digitos
-- pGFEDCBA
case display_sel is
when "1110" =>
display <= disp_4; -- 3
when "1101" =>
when "1011" =>
when "0111" =>
when others =>
display <= "00000000";
end case;
end process;
end Behavioral;
#+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++#
# This file is a .ucf for ElbertV2 Development Board #
# To use it in your project : #
# * Remove or comment the lines corresponding to unused pins in the project #
# * Rename the used signals according to the your project #

#+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++#
#*******************************************************************************
*******************************************************************#
# UCF for ElbertV2 Development Board

#
#*******************************************************************************
*******************************************************************#
CONFIG VCCAUX = "3.3" ;
# Clock 12 MHz
NET "Clk" LOC = P129 | IOSTANDARD = LVCMOS33 | PERIOD = 12MHz;
################################################################################
####################
# VGA
################################################################################
####################
# NET "HSync" LOC = P93 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "VSync" LOC = P92 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "Blue[2]" LOC = P98 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "Blue[1]" LOC = P96 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "Green[2]" LOC = P102 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "Red[2]" LOC = P105 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# Micro SD Card
################################################################################
####################
# NET "CLK" LOC = P57 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "DAT0" LOC = P83 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "CMD" LOC = P84 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# Audio
################################################################################
####################
# NET "AUDIO_L" LOC = P88 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "AUDIO_R" LOC = P87 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# Seven Segment Display
################################################################################
####################
# NET "Display[0]" LOC = P117 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "Enable2" LOC = P124 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# LED
################################################################################
####################
# NET "LED[0]" LOC = P46 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# DP Switches
################################################################################
####################
# NET "DPSwitch[0]" LOC = P70 | PULLUP | IOSTANDARD = LVCMOS33 | SLEW = SLOW |
DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;
################################################################################
####################
# Switches
################################################################################
####################
# NET "Switch[0]" LOC = P80 | PULLUP | IOSTANDARD = LVCMOS33 | SLEW = SLOW |

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;

DRIVE = 12;
DRIVE = 12;
################################################################################
####################
# GPIO
################################################################################
####################
#############################################
#######################################################
# HEADER P1
################################################################################
####################
NET "Ena[0]" LOC = P31 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "Ena3[3]" LOC = P30 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "orx[4]" LOC = P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
# NET "IO_P1[5]" LOC = P29 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# HEADER P6
################################################################################
####################
NET "salida[0]" LOC = P19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# HEADER P2
################################################################################
####################
NET "Rx" LOC = P10 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
################################################################################
####################
# HEADER P4
################################################################################
####################
################################################################################
####################
# HEADER P5
################################################################################
####################
# Two input PINs of P5 Header IO_P5[1] and IO_P5[7].
# NET "IO_P5[1]" LOC = P123 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12 |

PULLUP;
# NET "IO_P5[7]" LOC = P140 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12 |

PULLUP;

UART

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UART

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----------------------------------------------------------------------------------

-- Create Date: 14:30:08 04/08/2019

-- Module Name: PRAC3 - Behavioral

-- Revision 0.01 - File Created

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

Port ( clk : in STD_LOGIC;

orx: out std_logic;

salida: out STD_LOGIC_VECTOR (7 downto 0);

Ena : out STD_LOGIC_VECTOR (3 downto 0));

architecture Behavioral of PRAC3 is

signal aux1 : std_logic_vector(7 downto 0);

Port ( clk_ds : in STD_LOGIC;

ABC : in std_logic_vector (7 downto 0);

display : out STD_LOGIC_VECTOR (7 downto 0);

Enable1 : out STD_LOGIC_VECTOR (3 downto 0));

o_RX_DV : out std_logic;

o_RX_Byte : out std_logic_vector(7 downto 0)

u1 : UART port map (i_Clk =>

u2 : MATRIZZ port map (clk_ds=>clk, ABC=>aux1,display=>salida , Enable1

-- Create Date: 14:34:44 04/08/2019

-- Module Name: UART - Behavioral

-- Revision 0.01 - File Created

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly

o_RX_DV : out std_logic;

o_RX_Byte : out std_logic_vector(7 downto 0)

type t_SM_Main is (s_Idle, s_RX_Start_Bit, s_RX_Data_Bits,

signal r_SM_Main : t_SM_Main := s_Idle;

signal r_RX_Data_R : std_logic := '0';

signal r_RX_Data : std_logic := '0';

signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;

signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total

signal r_RX_Byte : std_logic_vector(7 downto 0) := (others => '0');

signal r_RX_DV : std_logic := '0';

-- Purpose: Double-register the incoming data.

-- This allows it to be used in the UART RX Clock Domain.

-- (It removes problems caused by metastabiliy)

p_SAMPLE : process (i_Clk)

r_RX_Data_R <= i_RX_Serial;

r_RX_Data <= r_RX_Data_R;

end process p_SAMPLE;

-- Purpose: Control RX state machine

p_UART_RX : process (i_Clk)

when s_Idle =>

r_RX_DV <= '0';

if r_RX_Data <= '0' then -- Start bit detected

r_SM_Main <= s_RX_Start_Bit;

r_SM_Main <= s_Idle;

-- Check middle of start bit to make sure it's still low

when s_RX_Start_Bit =>

if r_Clk_Count <= (g_CLKS_PER_BIT-1)/2 then

if r_RX_Data <= '0' then

r_Clk_Count <= 0; -- reset counter since we found the middle

r_SM_Main <= s_RX_Data_Bits;

r_SM_Main <= s_Idle;

r_Clk_Count <= r_Clk_Count + 1;

r_SM_Main <= s_RX_Start_Bit;