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ADDER

Submitted

BACHELOR OF TECHNOLOGY

In

Submitted By

C. ANUSRI (15R11A0467)

D.SRINIDHI (15R11A0471)

B.L.N.A. KARTHIK (15R11A0466)

G.SreeLakshmi

Asst. Professor

GEETHANJALI COLLEGE OF ENGINEERING AND

TECHNOLOGY,

(UGC Autonomous)

(Approved by AICTE, Permanently Affiliated to JNTUH, Accredited by NBA, Accredited by

NAAC with “A” Grade and ISO 9000:2008 Certified)

Cheeryal (V), Keesara(M), Medchal Dt. Telangana – 501 301, INDIA

Mobile:9391199932, Landline:040-31001618, Fax:040-24220320

email:info@gcet.edu.in, Web: http://www.geethanjaliinstitutions.com

2015-2019

GEETHANJALI COLLEGE OF ENGINEERING AND

TECHNOLOGY

CERTIFICATE

This is to certify that the project report titled “Design of High Speed and low

power Carry skip adder” being submitted by C.Anusri,D. Srinidhi Reddy,

B.L.N.A. Karthik bearing hall ticket numbers 15R11A0467, 15R11A04671,

15R11A0466in partial fulfilment of the requirements for the award of the Degree of

Bachelor of Technology in Electronics & Communication Engineering is a record of

bona-fide work carried out under my guidance and supervision. The results embodied

in this report have not been submitted to any other University for the award of any

degree.

Assistant Professor HoD, ECE

ACKNOWLEDGEMENT

and Technology would like to convey heartfelt thanks to Dr. S. Udaya Kumar,

Principal of the college for the wonderful guidance and encouragement given to us to

move ahead in the execution of this project.

We are highly grateful to the great personality in the field of Electronics, none

other than Prof. B. Hari Kumar, Head of the Department of Electronics and

Communication Engineering of GCET for guiding and taking care of our career in

this field.

We are very happy for being guided by G.SreeLakshmi, Asst. professor for

his able guidance given to us to complete our technical work successfully.

Siva Kumar, Professor in-charge Dr./Mr.------------, Coordinator Dr./Mr.K.S.RAO-

and members of the Project Review Committee (PRC) for giving us an opportunity to

present the technical project work.

College of Engineering & Technology which was established by the high profile

intellectuals for the cause of Technical Education in modern era. We wish that

GCET sooner should become a deemed university and produce uncountable young

engineers and present them to the modern technical world.

With Regards

C. Anusri (15R11A0467)

D. Srinidhi (15R11A0471)

Contents Page no

Abstract i

List of Figures ii

Chapter 1 Introduction 1

Chapter 2 Test pattern generator 3

Classification of test pattern generator 4

Chapter 3 linear feedback shift register 10

Chapter 4 implementation 15

Chapter 5 simulation and synthesis 16

Writing test bench 17

Chapter 6 cadence 18

Chapter 7 steps for creating and executing program 22

Chapter 8 code for test pattern generation using standard LFSR 24

Code for test pattern generation using modular LFSR 29

Code for test pattern generation using cellular automated LFSR 34

Conclusion 39

Reference 40

ABSTRACT

adder (CSKA) architecture compared with the conventional one is

presented. The increment of speed is attained by implementing

concatenation and incrementation strategy to improve the efficiency of

the conventional CSKA (Conv-CSKA) architecture. Instead of make use

of multiplexer logic, the proposed architecture makes use of AND-OR-

Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry

skip logic. The structure possibly designed with fixed stage size style,

wherein the latter further improves the speed and power parameters of the

adder. The proposed architectures are evaluated by comparing their

speed, power, and area with those of other adders using 180-nm static

CMOS technology.

ii

List of figures Page no

Fig 3.2 LFSR implementation 7

Fig 3.3 test vector sequence 7

Fig 3.4 5-bit LFSR 8

Fig 3.5 standard LFSR 10

Fig 3.6modular LFSR 11

Fig 3.7 TPG architecture 12

Fig 3.8 LFSR and gray code tpg 13

Fig 8.1simulation of TPG using standard LFSR 27

Fig 8.2 synthesis of TPG using standard LFSR 28

Fig 8.3 1simulation of TPG using modular LFSR 32

Fig 8.4synthesis of TPG using modularLFSR 33

Fig 8.51simulation of TPG using cellular automata LFSR 37

Fig 8.6synthesis of TPG using cellular automata LFSR 38

CHAPTER 1

INTRODUCTION

quality in product functionality in both commercially and privately produced

products. The impact of testing affects areas of manufacturing as well as those

involved in design. Given this range of design involvement, how to go about best

achieving a high level of confidence in IC operation is a major concern. This desire to

attain a high quality level must be tempered with the cost and time involved in this

process.

If we build a product, fabricate and test it, and it fails the test, then there must be a

cause for the failure and maybe test was wrong or design was incorrect or fabrication

process was faulty.The increasing capability of being able to fabricate a very large

number of transistors on a single integrated-circuit chip and the complexity of the

possible systems has increased the difficulty of manual testing.

Engineering economy is the study of how engineers choose to optimize their designs

and construction methods to produce objects and systems that will optimize their

efficiency and hence satisfaction of their clients. The concepts such as analysis of

production and operational costs benefit versus cost analysis when applied to

electronic test, lead to justify design for testability [1].Engineers are concerned with

optimizing the technological efficiency. For large electronic systems, testing accounts

30% or more of the total cost. Testing is responsible for the quality of VLSI circuits.

Several trade-offs are often necessary to obtain the required quality level at minimum

cost. Costs include the cost of automatic test equipment (ATE), the cost of test

development (CAD tools, test vector generation, test programming).

Power dissipation is a challenging problem for today’s System-on-Chips

(SOCs) design and test. In general, the power dissipation of a system in test mode is

more than in normal mode. Four reasons are blamed for power increase during test .

• High switching activity due to nature of test patterns

• Parallel activation of internal cores during test

• Low correlation among test vectors

1

This extra average and peak power consumption can create problems such as

instantaneous power surge that cause circuit damage, formation of hot spots, difficulty

in performance verification, and reduction of the product field and lifetime[4]. Thus

special care must be taken to ensure that the power rating of circuits is not exceeded

during test application. Different types of techniques are presented in the literature to

control the power consumption. These mainly includes algorithms for test scheduling

with minimum power, techniques to reduce average and peak power, techniques for

reducing power during scan testing. Since off-chip communication between the FPGA

and a processor is bound to be slower than on-chip communication, in order to

minimize the time required for adjustment of the parameters.

Different techniques are available to reduce the switching activities of test pattern,

which reduce the power in test mode. For linear feedback shift register (LFSR), Giard

proposed a modified clock scheme in which only half of the D flip-flops works, thus

only half of the test pattern can be switched . There are different hardware pattern

generation approaches such as ROM, LFSR, Binary counters, Modified counters,

LFSR and ROM, Cellular automation, etc., LFSR is used to generate pseudo random

test it requires 1 million or more tests to obtain high fault coverage’s.. The Linear

feedback shift register (LFSR) pattern generator is most commonly used for pseudo

random pattern generation.

2

CHAPTER 2

Depending upon the desired fault coverage and the specific faults to be tested for, a

sequence of test vectors (test vector suite) is developed for the CUT. It is the function

of the TPG to generate these test vectors and apply them to the CUT in the correct

sequence. A ROM with stored deterministic test patterns, counters, linear feedback

shift registers are some examples of the hardware implementation styles used to

construct different types of TPGs.

Quality and economy are two major benefits of testing. The purpose of testing is to

weed out all bad products before they reach the user. The other main reason for a

proper test pattern will be the “Rule of Ten” in testing. The “Rule of Ten” tells that

the products returned from customers due to improper functioning will cause ten

times the cost of the original fabrication cost to re-test it.

3

Classification of Test Patterns:

There are several classes of test patterns. TPGs are sometimes classified according to

the class of test patterns that they produce. The different classes of test patterns are

briefly described below:

These test patterns are developed to detect specific faults and/or structural

defects for a given CUT. The deterministic test vectors are stored in a ROM

and the test vector sequence applied to the CUT is controlled by memory

access control circuitry. This approach is often referred to as the “stored test

patterns “approach.

Like deterministic test patterns, algorithmic test patterns are specific to a given

CUT and are developed to test for specific fault models. Because of the

repetition and/or sequence associated with algorithmic test patterns, they are

implemented in hardware using finite state machines (FSMs) rather than being

stored in a ROM like deterministic test patterns.

In this approach, every possible input combination for an N-input

combinational logic is generated. In all, the exhaustive test pattern set will

N

consist of 2 test vectors. This number could be really huge for large designs,

causing the testing time to become significant. An exhaustive test pattern

generator could be implemented using an N-bit counter.

In this approach the large N-input combinational logic block is partitioned into

smaller combinational logic sub-circuits. Each of the M-input sub-circuits

K

(M<N) is then exhaustively tested by the application all the possible 2 input

4

vectors. In this case, the TPG could be implemented using counters, Linear

Feedback Shift Registers (LFSRs) or Cellular Automata.

In large designs, the state space to be covered becomes so large that it is not

feasible to generate all possible input vector sequences, not to forget their

different permutations and combinations. An example befitting the above

scenario would be a microprocessor design. A truly random test vector

sequence is used for the functional verification of these large designs.

However, the generation of truly random test vectors for a BIST application is

not very useful since the fault coverage would be different every time the test

is performed as the generated test vector sequence would be different and

unique (no repeatability) every time.

These are the most frequently used test patterns in BIST applications. Pseudo-

random test patterns have properties similar to random test patterns, but in this

case the vector sequences are repeatable. The repeatability of a test vector

sequence ensures that the same set of faults is being tested every time a test

run is performed. Long test vector sequences may still be necessary while

making use of pseudo-random test patterns to obtain sufficient fault coverage.

In general, pseudo random testing requires more patterns than deterministic

ATPG, but much fewer than exhaustive testing. LFSRs and cellular automata

are the most commonly used hardware implementation methods for pseudo-

random TPGs.

The above classes of test patterns are not mutually exclusive. A BIST

application may make use of a combination of different test patterns – say pseudo-

random test patterns may be used in conjunction with deterministic test patterns so

as to gain higher fault coverage during the testing process.

5

CHAPTER 3

The Linear Feedback Shift Register (LFSR) is one of the most frequently

used TPG applications. This can be attributed to the fact that LFSR designs are more

area efficient than counters, requiring comparatively lesser combinational logic per

flip-flop. An LFSR can be implemented using internal or external feedback. The

former is also referred to as TYPE1 LFSR while the latter is referred to as TYPE2

LFSR. The two implementations are shown in Figure. The external feedback LFSR

best illustrates the origin of the circuit name – a shift register with feedback paths that

are linearly combined via XOR gates. Both the implementations require the same

amount of logic in terms of the number of flip-flops and XOR gates. In the internal

feedback LFSR implementation, there is just one XOR gate between any two flip-

flops regardless of its size. Hence, an internal feedback implementation for a given

LFSR specification will have a higher operating frequency as compared to its external

feedback implementation. For high performance designs, the choice would be to go

for an internal feedback implementation whereas an external feedback

implementation would be the choice where a more symmetric layout is desired (since

the XOR gates lie outside the shift register circuitry).

6

Fig: 3.2 LFSR Implementations.

one can deduce that the sequence of patterns generated, is a function of the initial state

of the LFSR, i.e. with what initial value it started generating the vector sequence. The

value that the LFSR is initialized with, before it begins generating a vector sequence

is referred to as the seed. The seed can be any value other than an all zeros vector. The

all zeros state is a forbidden state for an LFSR as it causes the LFSR to infinitely loop

in that state.

7

An n-bit LFSR is a n-bit length shift register with feedback to its input.

The Feedback is formed by X-OR ing or X-NOR ing the outputs of selected

stages of the shift register-referred to as ‘TAPS’-and then inputting this to the

least significant bit (stage 0).

The linear part of the term ‘LFSR’ derives from the fact that X-OR and X-

NOR are linear Functions. An Example of 5 bit LFSR is shown below.

This has taps at stages 1 and 4 with XOR feedback. Note also that the LS bit of the

shift register is, by convention, shown at the left hand side of the shift register, with

the output being taken from the MS bit at the right hand side.

sequence of length 2n-1 states (where n is the number of stages) if the LFSR is

of maximal length. The sequence will then repeat from the initial state for as long as

the LFSR is clocked. Assume that the example LFSR above is set to 1FH after

8

initialisation. The output of the feedback XOR gate will be 0 (since 1 XOR 1 = 0) and

the first clock edge will load 0 into stage 0. The following table shows the sequence:

0 1234 (0:4)

1 1111 1F

0 1111 0F

0 0111 07

1 0011 13

1 1001 19

0 1100 0C

1 0110 16

0 1011 0B

0 0101 05

1 0010 12

0 1001 09

0 0100 04

0 0010 02

0 0001 01

1 0000 10

0 1000 08

1 0100 14

0 1010 0A

1 0101 15

1 1010 1A

1 1101 1D

0 1110 0E

1 0111 17

1 1011 1B

0 1101 0D

0 0110 06

0 0011 03

1 0001 11

1 1000 18

1 1100 1C

1 1110 1E

Table 3.1: 5 bit LFSRsequence

After the initial state, the bit shifted into stage0 on each clock edge is the XOR of

stage4 and stage1. The LFSR passes through 31 states (25-1 = 31) and so is of maximal

length.

9

A low power test pattern generator has been proposed which consists of a modified

low power linear feedback shift register (LP-LFSR). The seed generated from (LP-

LFSR) is Ex-ORed with the single input changing sequences generated from gray

code generator, which effectively reduces the switching activities among the test

patterns.

Types of LFSRs

1) Standard LFSR

Figure1 shows a standard, external exclusive-OR. It consists of D flip-flops and linear

exclusive-OR gates. It is an external XOR LFSR because feedback network of XOR

gates feed externally from X0 to X (n-1). There are n flip-flops, so this is called an n-

stage LFSR. A properly designed LFSR can function as near exhaustive test pattern

generator, as it can cycle through 2(n-1) distinct states. The only emitted state being

all zeros in the flip-flop, this is known as maximal length LFSR.

Fig.3.5.Standard LFSR

2) Modular LFSR

The modular, internal exclusive-OR is described by a companion matrix TM = TST,

which is the transpose of TS. It is called an internal XOR LFSR because the feedback

10

XOR gates are located between adjacent flip-flops. The modular LFSR can run

somewhat faster than the standard LFSR, because it has at most one XOR gate delay

between adjacent flip-flops. However, this is usually not a serious consideration in

testing; because actual circuits always have more logic gates between flip-flops than

there are XOR gates in the feedback network of the external XOR LFSR.

Fig.3.6.Modular LFSR

It is highly desirable that the LFSR generate all possible patterns. The following

conditions are necessary to satisfy the requirement or to have a primitive polynomial

for the LFSR.

(i) The polynomial must be monic, which means that the coefficient of the highest

order x term of the characteristic polynomial must be 1.

(ii) The characteristic polynomial must divide the polynomial 1+x k for k = 2n-1, but

not for any smaller value of k.

Cellular Automata (CA) are excellent for pattern generation, because they have a

better randomness distribution than LFSRs. A cellular automaton is a cell collection

with regular connections. Each cell can only connect to its local neighbour's. The

connections are expressed as rules, which determine the next state based on the state

11

of the cells neighbour’s. If cell c can talk only with its neighbour’s, c-1 & c+1, then

the following rule, called rule 90(other rules are rule150), can be established based on

the following state transition table:

011 010 001 000

Xc(t+1) 0 10 1

1 0 1 0

Rule 90: 26 + 24 + 23 + 21 = 90

011 010 001 000

Xc(t+1) 1 0 01

0 1 1 0

Rule 150: 27 + 24 + 22 + 21 = 150

The less toggling pattern is generated by using transition controller. The transition

controller decreases the switching of sequent test pattern. The test pattern is formed

by re-alignment of the second half of the test pattern according with respect to the

next test test pattern. Interpolation of intercede pattern reduces the switching activity.

1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 0

→

1 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1

→

1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1

→

1 1 0 1 1 1 1 0 0 1 0 1 0 0 0 1

→

0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1

randomness.

12

Fig.3.8. LFSR and GRAY Code based Test Pattern Generator

Because of simplicity of the circuit and less area occupation, linear feedback shift

register [LFSR] is used at the maximum for generating test patterns. In this

architecture the generated test patterns have reduced switching activities. TPG

structure consists of linear feedback shift register (LP-LFSR), m-bit counter; gray

counter, NOR-gate structure and XOR-array.

13

The m-bit counter is initialized with Zeros and which generates 2m test

patterns in sequence. The m-bit counter and gray code generator are controlled by

common clock signal [CLK]. The output of m-bit counter is applied as input to gray

code generator and NOR-gate structure. When all the bits of counter output are Zero,

the NOR-gate output is one. Only when the NOR-gate output is one, the clock signal

is applied to activate the LFSR which generates the next seed. The seed generated

from LFSR is Exclusive–ORed with the data generated from gray code generator. The

patterns generated from the Exclusive–OR array are the final output patterns.

By using different LFSR architectures in the above TPG circuit, we can verify

the best LFSR in terms of low power, less switching activities and better randomness.

Here we have verified the TPG circuit by applying various LFSRs such as Standard

LFSR, Modular LFSR, primitive polynomial modular LFSR, Cellular automaton

based pattern generator and Low transition LFSR.

14

CHAPTER 4

IMPLEMENTATION

To validate the effectiveness of the proposed method, we select Test pattern

generator (TPG) using conventional linear feedback shift register [LFSR] for

comparison with various other LFSR architectures. Table 1 shows the power

consumption comparison between TPG Standard LFSR, Modular LFSR, primitive

polynomial modular LFSR, Cellular automaton based pattern generator and Low

transition LFSR after applying the generated patterns to the 8x8 Braun array

multipliers respectively. The generated test patterns from above two techniques are

used to test the synchronous pipelined 8x8 Braun array multipliers.

Simulation and analysis were carried out with candence tool. rc compiler was used for

the Power analysis. Theaverage test power consumption was compared with the test

pattern generator (TPG) using conventional LFSR. In table I, the average test power

consumption for the TPG using conventional LFSR and the average test power

consumption for the proposed LFSR are presented. The test patterns generated from

these LFSR’s are tested with 8x8 Braun array synchronous multiplier.

15

Chapter 5

SIMULATION

Simulation is a process in which the logic and functional VERIFICATION OF

ALGORITHM or design will be verified, by subjecting it to appropriate input test

stimulus.

SYNTHESIS

Synthesis is the process of constructing a gate level net list from a register-

transfer level model of a circuit described in Verilog HDL a synthesis system may as

an intermediate step, generate a net list that is comprised of register-transfer level

blocks such as flip-flops, arithmetic-logic-units, and multiplexers, interconnected by

wires. Synthesis is the implementation of the design in to the actual hardware.

Synthesis is actually targeting your functionally rather logically verified design to the

properly targeted technology like 90nm technology etc.

Once verified the design, it is need to target the design into hardware. So you

need to convert your RTL into gate level design. Synthesis is divided into three steps:

Translation, Optimization and Technology Mapping. Translation - RTL to gate-level

net lists. Optimization - technology-independent logic-level optimization to reduce

hardware for required functionality. Technology Mapping-technology-independent

net lists are transformed into technology-dependent ones. Synthesis tools do all these

steps. Designer needs to specify the optimization constraints, which the synthesis tool

tries to meet.

16

WRITING A TEST BENCH

A Test bench is a model that is used to exercise and verify the correctness of a

hardware model. A test bench has 3 main purposes:

2. To apply this stimulus to the entity under test and collect the output responses.

3. To compare output responses with expected values.

17

Chapter 6

CADENCE

There are a number of things to consider before beginning these lab exercises.

These labs were designed for use with Incisive Unified Simulator.

folder. Inside Work folder you can make modifications of the code locally without

affecting your Source code present inside Solutions directory.

These labs were designed to be run using Cadence Simulator and the synthesis

engine.

In this lab we will simulate the inverter code modeled using switch level by

the help of Incisive unified simulator.In this lab we will see how to perform

simulation in command mode using testbench without using GUI window.

18

2. You will need to copy each file present in solutions folder to

Workarea/Inverter location by using the below mentioned command :

cp -rf ../../Solutions/Inverter/*.

3.View the Code of Inverter and also the testbench for the same.

ncvloginverter.v –messages

ncvloginverter_test.v –MESS

Note: You can abbreviate options down to their shortest unique string and use

upper orLower case.

19

Elaborate the top level Design

ncelabinv_test -messages

ncelabinv_test -messages

The elaborator places the inv_test code and snapshot in the INCA_libs library.

Answer: The elaborator creates SIG (signature), HDLCODE (code), and SSS

(snapshot) objects.

20

5.Simulate the Top-Level Design

ncsiminv_test

You can simulate a design using the Incisive simulator. You will:

ncsimtrangate_test –gui

The -gui option opens the Console and Design Browser windows.

21

Chapter 7

5. Inroot@client window

8.write your program and its test bench then save it with extension..v

22

Simulate The Program

13.In the cadence window right click on testbench name and select “send to

waveform”.

Synthesis

14.2 Library

14.3 run.tcl

23

Chapter 8

moduleLP_TPGstand(Clk,Rst,CEna,Sel,TPG);

inputClk;

inputRst;

//input Din;

inputCEna;

inputSel;

output [15:0]TPG;

wire [15:0]LFSR;

wire [15:0]Count;

wire [15:0]gray;

wirenorout;

wireEna;

//assign LFSR2=~LFSR1;

standlfsr16 m0(LFSR,Clk,Rst,Ena,Sel);

counter m1(Clk,Rst,CEna,Count);

binary2gray m2(Clk, Rst, Count,gray);

assign TPG=gray^LFSR;

assignnorout=|Count;

assignEna=&norout;

endmodule

moduleLP_TPGstand_tb;

// Inputs

regClk;

regRst;

//reg Din;

regCEna;

regSel;

// Outputs

wire [15:0] TPG;

// Instantiate the Unit Under Test (UUT)

LP_TPGstanduut (

.Clk(Clk),

.Rst(Rst),

.CEna(CEna),

.Sel(Sel),

.TPG(TPG)

24

);

initial

begin

Clk = 1;Rst = 1;CEna=0;Sel = 1;

#5 Rst=0;CEna=1;

#200 $stop;

//#10 Rst=0;

end

always #5 Clk=~Clk;

//always #10 Sel=~Sel;

//always #30 Din=~Din;

endmodule

module counter(Clk,Rst,CEna,Count);

inputClk;

inputRst,CEna;

output [15:0] Count;

reg [15:0]Dreg;

assign Count=Dreg;

always @ (posedgeClk)

if(Rst)Dreg<=16'h00;

else if(CEna==1'b1) Dreg<=Dreg+1;

else Dreg<=Dreg;

endmodule

inputClk, Rst;

input [n-1:0] Count;

outputreg [n-1:0] gray;

always @ (posedgeClk)

begin

if (Rst)

gray = 16'b0;

else

gray = {Count[n-1],Count[n-1:1]^Count[n-2:0] };

end

endmodule

module standlfsr16(LFSR,Clk,Rst,Ena,Sel);

inputClk,Rst,Ena,Sel;

output [15:0]LFSR;

reg [15:0]q;

assign LFSR=q;

25

always@(posedgeClk)

if(Rst)

q<=(Sel==1'b0)?16'h00ff:16'hff00;

else if(Ena==1)

begin

q[0]<=q[1];

q[1]<=q[2];

q[2]<=q[3];

q[3]<=q[4];

q[4]<=q[5];

q[5]<=q[6];

q[6]<=q[7];

q[7]<=q[8];

q[8]<=q[9];

q[9]<=q[10];

q[10]<=q[11];

q[11]<=q[12];

q[12]<=q[13];

q[13]<=q[14];

q[14]<=q[15];

q[15]<=q[15]^q[14]^q[13]^q[12]^q[11]^q[10]^q[9]^q[8]^q[7]^q[6]^q[5]^q[4]^q[3]^q

[2]^q[1]^q[0];

end

endmodule

26

Fig 8.1: simulation of test pattern generator using standard LFSR

27

Fig 8.2:synthesis report of TPG using standard LFSR

28

Code for test pattern generator using modular LFSR

ModuleLP_TPGmod(Clk,Rst,CEna,Sel,TPG);

inputClk;

inputRst;

//input Din;

inputCEna;

inputSel;

output [15:0]TPG;

wire [15:0]LFSR;

wire [15:0]Count;

wire [15:0]gray;

wirenorout;

wireEna;

//assign LFSR2=~LFSR1;

modlfsr16 m0(LFSR,Clk,Rst,Ena,Sel);

counter m1(Clk,Rst,CEna,Count);

binary2gray m2(Clk, Rst, Count,gray);

assign TPG=gray^LFSR;

assignnorout=|Count;

assignEna=&norout;

endmodule

moduleLP_TPGmod_tb;

// Inputs

regClk;

regRst;

//reg Din;

regCEna;

regSel;

// Outputs

wire [15:0] TPG;

// Instantiate the Unit Under Test (UUT)

LP_TPGmoduut (

.Clk(Clk),

.Rst(Rst),

.CEna(CEna),

.Sel(Sel),

.TPG(TPG)

);

initial

begin

29

Clk = 1;Rst = 1;CEna=0;Sel = 1;

#5 Rst=0;CEna=1;

#200 $stop;

//#10 Rst=0;

end

always #5 Clk=~Clk;

//always #10 Sel=~Sel;

//always #30 Din=~Din;

endmodule

module counter(Clk,Rst,CEna,Count);

inputClk;

inputRst,CEna;

output [15:0] Count;

reg [15:0]Dreg;

assign Count=Dreg;

always @ (posedgeClk)

if(Rst)Dreg<=16'h00;

else if(CEna==1'b1) Dreg<=Dreg+1;

else Dreg<=Dreg;

endmodule

inputClk, Rst;

input [n-1:0] Count;

outputreg [n-1:0] gray;

always @ (posedgeClk)

begin

if (Rst)

gray = 16'b0;

else

gray = {Count[n-1],Count[n-1:1]^Count[n-2:0] };

end

endmodule

module modlfsr16(LFSR,Clk,Rst,Ena,Sel);

inputClk,Rst,Ena,Sel;

output [15:0]LFSR;

reg [15:0]q;

assign LFSR=q;

always@(posedgeClk)

if(Rst)

q<=(Sel==1'b0)?16'h00ff:16'hff00;

else if(Ena==1)

30

begin

q[0]<=q[15];

q[1]<=q[0]^q[15];

q[2]<=q[1]^q[15];

q[3]<=q[2]^q[15];

q[4]<=q[3]^q[15];

q[5]<=q[4]^q[15];

q[6]<=q[5]^q[15];

q[7]<=q[6]^q[15];

q[8]<=q[7]^q[15];

q[9]<=q[8]^q[15];

q[10]<=q[9]^q[15];

q[11]<=q[10]^q[15];

q[12]<=q[11]^q[15];

q[13]<=q[12]^q[15];

q[14]<=q[13]^q[15];

q[15]<=q[14]^q[15];

end

endmodule

31

Fig 8.3: simulation of TPG using modular LFSR

32

Fig 8.4:synthesisof TPG using modular LFSR

33

Code for pattern generator using Cellular Automata LFSR

moduleLP_TPGca(Clk,Rst,CEna,Sel,TPG);

inputClk;

inputRst;

//input Din;

inputCEna;

inputSel;

output [15:0]TPG;

wire [15:0]Dreg;

wire [15:0]Count;

wire [15:0]gray;

wirenorout;

wireEna;

//assign LFSR2=~LFSR1;

calfsr16 m0(Clk,Rst,Ena,Sel,Dreg);

counter m1(Clk,Rst,CEna,Count);

binary2gray m2(Clk, Rst, Count,gray);

assign TPG=gray^Dreg;

assignnorout=|Count;

assignEna=&norout;

endmodule

moduleLP_TPGca_tb;

// Inputs

regClk;

regRst;

//reg Din;

regCEna;

regSel;

// Outputs

wire [15:0] TPG;

// Instantiate the Unit Under Test (UUT)

LP_TPGcauut (

.Clk(Clk),

.Rst(Rst),

.CEna(CEna),

.Sel(Sel),

.TPG(TPG)

);

initial

34

begin

Clk = 1;Rst = 1;CEna=0;Sel = 1;

#5 Rst=0;CEna=1;

#200 $stop;

//#10 Rst=0;

end

always #5 Clk=~Clk;

//always #10 Sel=~Sel;

//always #30 Din=~Din;

endmodule

module counter(Clk,Rst,CEna,Count);

inputClk;

inputRst,CEna;

output [15:0] Count;

reg [15:0]Dreg;

assign Count=Dreg;

always @ (posedgeClk)

if(Rst)Dreg<=16'h00;

else if(CEna==1'b1) Dreg<=Dreg+1;

else Dreg<=Dreg;

endmodule

inputClk, Rst;

input [n-1:0] Count;

outputreg [n-1:0] gray;

always @ (posedgeClk)

begin

if (Rst)

gray = 16'b0;

else

gray = {Count[n-1],Count[n-1:1]^Count[n-2:0] };

end

endmodule

module calfsr16(Clk,Rst,Ena,Sel,Dreg);

inputClk,Rst,Ena,Sel;

//input Din;

outputreg [15:0]Dreg;

always @(posedgeClk)

begin

if(Rst)

Dreg<=(Sel==1'b0)?16'h00ff:16'hff00;

35

else if(Ena==1)

begin

Dreg[15]<= Dreg[14];

Dreg[14]<= Dreg[15]^Dreg[14]^Dreg[13];

Dreg[13]<= Dreg[14]^Dreg[12];

Dreg[12]<= Dreg[13]^Dreg[12]^Dreg[11];

Dreg[11]<= Dreg[12]^Dreg[10];

Dreg[10]<= Dreg[11]^Dreg[10]^Dreg[9];

Dreg[9]<= Dreg[10]^Dreg[8];

Dreg[8]<= Dreg[9]^Dreg[8]^Dreg[7];

Dreg[7]<= Dreg[8]^Dreg[6];

Dreg[6]<= Dreg[7]^Dreg[6]^Dreg[5];

Dreg[5]<= Dreg[6]^Dreg[4];

Dreg[4]<= Dreg[5]^Dreg[4]^Dreg[3];

Dreg[3]<= Dreg[4]^Dreg[2];

Dreg[2]<= Dreg[3]^Dreg[2]^Dreg[1];

Dreg[1]<= Dreg[2]^Dreg[0];

Dreg[0]<= Dreg[1];

end

end

endmodule

36

Fig 8.5:simulation of TPG using CA LFSR

37

Fig 8.6: synthesis of TPG using CA LFSR

38

Conclusion

Low power test pattern generator has been proposed which consists of a

modified low power linear Feedback shift Register. The seed generated LP-

LFSR is X-OR ed with output of grey code Generator, which effectively

reduces switching activities among the test patterns .

Thus this method significantly reduces power consumption with minimum no.

of switching activities using LP-LFSR in place of conventional LFSR.

Stand CA Mod

39

REFERENCE

& Mixed-signal VLSI Circuits – Micheal L Bushgnell,

VishwaniD.Agrawal.

[2] Y.Zorian, “A Distributed BIST control scheme for

complex VLSI devices,”

40

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