Proiect Structuri Hardware

Reconfigurabile

Student: Poterasu Ionut

Conf.univ.dr.ing. IONESCU LAURENTIU - MIHAI

Tema proiect:

Proiectarea unui sistem cu urmatoarele caracteristici:

- interfata intrare/iesire RS232 paralel;
- dimensiune date intrare/iesire de 12 biti;
- numarul total de date receptionate este de 12 biti;
- sistemul va efectua XOR cu cheia 333h.

333h = 0011 0011 0011(2)

Registru de intrare 12 biti:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity rpp8 is
port( clk: in std_logic;
d : in std_logic_vector (11 downto 0);
i : out std_logic_vector (11 downto 0));
end rpp8;
architecture rpp8_a of rpp8 is
begin
process(d,clk)
variable i_in : std_logic_vector (11 downto 0);
begin
 if clk'event and clk='1' then i_in := d;
end if;
i<=i_in;
end process;
end rpp8_a;

Modulul de procesare:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity procesare1 is
port(
clk: in std_logic;
data_in: in std_logic_vector(11 downto 0);
data_out: out std_logic_vector(11 downto 0);
activ_reset: out std_logic
);
end procesare1;
architecture procesare_a of procesare1 is
begin
process(clk,data_in)
variable rezultat: std_logic_vector(11 downto 0);
variable cheie: std_logic_vector(11 downto 0);
variable contor: integer := 0;
begin
cheie := x"333";
for i in 0 to 11 loop
rezultat(i) := data_in(i) xnor cheie(i);
end loop;
contor := contor + 1;
if contor = 12 then
activ_reset<='1';
else
activ_reset <='0';
end if;
data_out <= rezultat;
end process;
end architecture;
Registru final pe 12 biti:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity rpp8_fin is
port( clk: in std_logic;
d : in std_logic_vector (11 downto 0);
i : out std_logic_vector (11 downto 0);
reset : in std_logic
);
end rpp8_fin;
architecture rpp8_a of rpp8_fin is
begin
process(d,clk)
variable i_in : std_logic_vector (11 downto 0);
begin
if reset = '0' then
if clk'event and clk='1' then
i_in := d;
end if;
i<=i_in;
else
 i<="000000000000";
end if;
end process;
end rpp8_a;

Poarta XOR cu cheia 333h:

library IEEE;
use IEEE.std_logic_1164.all;

entity sistem is
port(
clk: IN std logic;
DATAIN: IN std_logic_vector(11 downto 0);
DATAOUT: OUT std_logic_vector(11 downto 0)
);
end sistem;

architecture sistem_a of sistem is

DATAOUT <= DATAIN XOR "0011 0011 0011";

end sistem_a;