A MBIST Controller based on JTAG Interface applied in Power Line

Chip

Yao Lu*, Yanxu Zhu, Ming Li

College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing 100124, China
* Email: 2015Iuyao@emails.bjut.edu.cn

Abstract JTAG is to defme a TAP (Access Port Test) inside the

device, and the internal nodes are tested by a dedicated
In this paper, a design of memory built-in self-test based JTAG test tool. The structure of JTAG is shown in Figure
on JTAG interface circuit applied in Power line 1, it contains test access port, tap controller, instruction
communication chip is implemented with SMIC 0. 18um register, data register and multiple choice module.
CMOS 1P5M process. The memory built-in self-test
circuit mainly includes JTAG interface and memory test
circuits. Test data and test instruction can be sent and
received through only 5 JTAG interface pins. It can also
�rapper
complete memory test with only 5 instructions so that it
will save more test cost. Furthermore, the faulty memory
can be positioned via the BIST controller and be output
through the JTAG port. The test results show that it can
run perfectly with 50MHz working clock.

1. Introduction

With the development of the integrated circuit entering

into the deep submicron stage, the cost of testing chip is
increasing, so the test technology is particularly critical.
In view of the current situation, how to solve the
problem of testing a large number of memory in the SOC
chip without increasing the number of pins on the chip is
the key point. This paper designed a MBIST controller
based on JTAG connector and implanted a certain
instruction set into the MBIST controller. Through the
relevant test instrument transmitting instructions and test
data, the designed controller can not only accomplish all
testing with only 5 test pins and but also accomplish the
testing of memorizers within the SOC chip, moreover, it
can locate the specific failure at the same time. This
design enhanced the test efficiency of memorizers to a
great extent, meanwhile, the controller can
Figure. 1 JTAG system chart
Through selecting the test mode by the TMS port, the
test vector is transmitted through the TDI port and
reaches the TAP controller at the same time, and then, it
controls the relevant circuit test. Finally, the results of
the test will be serial output through the TDO port [2].
The TAP controller is a synchronous state machine with
16 states, which can decode the received TMS and TCK
signals, and jump to the specified state, as shown in
Figure2.
be 'c
).-___________-----;
est-LOgic-

transplanted to other chips expediently, optimizing the

°C
reusability of our design. On the other hand, we saved
chip pins through reusing the JTAG connectors, and this
make it possible to economize the manufacture and
encapsulation costs.

2. JTAG interface

The full name of JTAG is "Joint Test Action Group", an

international standard test protocol, which is mainly used
for internal testing of the chip [ 1]. The basic principle of
Figure. 2 TAP Control State Machine

978-1-4673-9719-3/16/$31.00 ©20161EEE
3. Analysis of self-test interface based on RAM and In this design, five instructions are designed, as shown in
ROM
Table 1.

For the design of RAM self-test [3], its self-test sequence

diagram is shown in Figure 3. After reset, driven by Table l. Testing procedure
clock interface mbisCclk, the test starting interface
process name instruction date
tesCh will be pulled up. Under the control of the internal
MBIST, the logic memory will complete the self-test prepara MBTST SUML 8'h06 16'hBB08
based on fixed algorithm, when the test is completed, the tion ADDR
MBIST SUMH 8'h07 16'h0420
signalmbisCdone will be pulled up. If there is no fault in
ADDR
the memory, the signal mbistJail is low.
start MBIST CTRL 8'h03 16'h7FFF
ADDR
result MBTST DONE 8'h04 16'hOOOO
ADDR
MBTST FAIL 8'hOS 16'hOOOO
ADDR
Figure3. RAM sequence diagram

Meanwhile, the following registers have been set:

For the design of ROM self-test, its self-test sequence tesCdone [15:0J for storing the signal done of each
diagram as shown in Figure 4. When the test is memory; testJail [15:0J for storing the signal fail of
completed, the signal mbist_done will be pulled up, and each memory; tesCctrl [15:0J for storing the MBIST
then, based on the fixed algorithm and the binary data starting control signal; misr_data_l [15:0J and
stored in the internal storage, it will come into being a misr_data_h [15:0J for storing the test vector for ROM
32bit data. If the comparison between the actual self-test.
compression data and the ideal value is consistent, it The TOI and TOO ports in the diagram are serial input
means the memory test does not exist faults. port and serial output port, respectively. The received
level signal is divided into data and instruction. Their
format are shown in Figure 6 and Figure7, respectively.

Figure 4. ROM sequence diagram

4 Design of MBIST based on JTAG interface

Figure. 6 data format

This design is applied to a SOC chip, containing 6
memories, 1 ROM and S SRAM. Based on this situation,
C
the design structure diagram is shown in FigureS.

Figure.7 instruction format

The design flow of this paper:

Preparation of memory self-test, when the TAP state
machine is under the IDLE state, the TOO port will
serial output all the date from TDI port. When we send
instruction ir(8 'h06) , instruction [7:0J will be assigned
MEMOR
Y
with 8 'h06, because it is the instruction address of
MBIST SUML AOOR. When we send data

FigureS. mbist block diagram

dr(16 'hbb08) at the same time, the low 16 bits of the
data for the ROM self-test will be written to the internal
register misr_data_l [15:0j. Then we send instruction
ir(8 'h07) (the instruction address of
MBISLSUMH_ADDR) and data dr(16 'h042D), the
internal registermisr_data_l [15:0] will be assigned. It
means that the high 16 bits of the data for the ROM
self-test will be written to the internal registers.
Start of memory self-test, when we send instruction

ir(8 'h03), instruction [7:0] will be assigned with

8h '03(the instruction address of MBISLCTRL_ADDR).

Then we send dr(16 'hFFFF) to register tesCctrl[l5:0] ,
it will pull up the signal tesCh of all memory interfaces. Figure 10. actual measurement results

Display of test results, when we send instruction

ir(8 'h04) , JTDO will serial output the signal done of all

the memories. When the test equipment captured the

high state of signal done, it means the memory test has

been completed, then it will send the instruction ir(8 'h05)

and TDO will output the signal fail of all the registers.
Figure 1l. the photo of the chip
5 Simulation and test results

6 Summary
This design uses NC-verilog to complete the RTL
simulation and Design Compiler to complete synthesis
and IC Compiler to complete layout. Figure S is the In summary, a memory BIST controller based on JTAG

simulation results for the written data of ROM test data.
Figure 9 is the self-test of Boot memory test. Figure 10
shows the actual measurement results. Figure 11 shows
the photo of the chip.
interface is designed for chip mass production test. It can
accomplish the self-testing of memorizers with only 5
instructions and locate the specific failure of a certain

memorizer at the same time. The test instrument

transmits instructions to the JTDI pin of the chip and

detects the JTDO pin of this chip in the meantime, which

can capture the test data. The testing cost of the chip is

greatly reduced. In addition, through the simulation and

actual measurement, the controller achieved the designed

requirement perfectly under the 50MHz testing clock.

FigureS. the written data of ROM test data Acknowledgments

The authors would like to express gratitude to Mr. Wan,

Li Ming and Si Yu for their helpful suggestions.

References

[ 1] IEEE Standard 1149.6, IEEE Standards, April 2003

pAI2-422.
[2] Eklow, Parker, 2002 IEEE International Test

Conference, p.76-S2.
Figure 9. Boot memory test
[3] Mentor Graphics, MBTST Architect Process Guide.