module df(

input t,

input clk,

input reset,

output q

);

reg q=1'b0;

always @(posedge clk)

begin

if(reset==1)

q<=0;

else if(t)

q<=~q;

else

q<=q;

end

endmodule
module test(

);

reg d,clk,reset;

wire q;

df f1(d,clk,reset,q);

initial

clk=1'b0;

always # 1 clk=~clk;

initial

begin

reset=1'b1;

#10 reset=1'b0;

d=1'b0;

#10 d=1'b1;

#10 reset=1'b0;d=1'b0;

#10 d=1'b1;

#10 $finish;

end

endmodule