Ultra-Low Voltage Design for Interconnections
Chinwuba D. Ezekwe
Department of Electrical Engineering and Computer Sciences
University of California at Berkeley
chinwuba@eecs.berkeley.edu
Abstract—This paper is concerned with
high-speed, low-swing, off-chip signaling
circuits for Gb/s serial data communication. In
previous work, energy savings was limited by
power consumption in the transmitter primarily
due to the need to drive the termination
resistors at the prevailing signal swings and at
the receiver due to the need to have a wide
common-mode input range. This paper surveys
existing work with the view of reducing energy
consumption through proper choice of
transmitter and receiver architecture and
further reduction in signal swings. This is
possible without the loss of signal integrity
because the fundamental limit as dictated by
thermal noise is several orders of magnitude less
than the signal swings in present use.
I. INTRODUCTION
With the demand for ever increasing
microprocessor speeds comes an associated
demand for higher speed interface circuits. At high
frequencies, dielectric losses and impedance
mismatches, in addition to resistive losses, varying
dielectric constant, crosstalk and thermal noise,
cause high levels of distortion of the received
signal. Because of its relatively low dispersion and
attenuation characteristics, it is speculated that
optical links may be the answer to the high-speed
interconnect problem [1]. However, its use at
present comes at a significant expense and
inconvenience. Consequently conventional
electrical interconnects remain the method of
choice.
In recent years, low swing interface circuits
have received significant attention for both on-chip
and off-chip signaling as they allow for higher
transmission rates and lower power consumption
[2], [3]. These benefits come at the cost of signal
integrity due to the reduced noise margins. Signal
integrity is improved, however, by the use of
differential signaling, with its high common-mode
rejection, at the cost of more wiring space.
Because the data in a differential signal is
distinguished by the differential voltage polarity as
opposed to the absolute signal voltage level, the
signal swing can, in the ideal case, be reduced to a
minimal level to yield the ultimate in power
savings and transmission rates. In practice, further
swing reduction requires increased receiver
sensitivity, corresponding to increased receiver
power consumption.
In this paper, we review a number of existing
interface circuits and evaluate their effectiveness
for further swing reduction.
II. ULTRA-LOW VOLTAGE DESIGN
The resistance of board wires is sufficiently
low to be ignored. But, at the high transmission
rates under consideration, the effect of wire
inductance becomes quite significant. Essentially,
the wavelengths of the frequency components of
the transmitted signal become comparable to the
length of the wire such that an accurate modeling
of signal propagation must take the signal’s wave
nature into account. This requires that the wire be
considered a transmission line. To avoid signal
reflections, the line is terminated by its
characteristic impedance, typically 50Ω . It
becomes necessary sometime to add source
termination for improved signal integrity at the cost
of extra power dissipation. These main aspects of
high-speed low-swing signaling are shown in Fig.
1.
The characteristic impedance of the line
specifies the minimum current that must be sourced
and sunk by the transmitter given the sensitivity of
the receiver. Reducing this current, thus reducing
the signal swing, and providing it from a reduced
supply voltage will result in quadratic savings in
energy at the transmitter.
Transmitter Receiver
Z0
Vin Vout
RS RL
Vin Vout
Z0
Figure 1 Simplified schematic of a high-speed
differential link, with optional source termination
resistor.
 III. EXISTING LOW-SWING I/O CIRCUITS B. Static Driver with Reduced Supply
A. Current-Mode Driver The circuit shown in Fig. 3a is a well-known
on-chip level conversion circuit [7]. It consists of a
These are widely used in LVDS transmitters.
couple of inverters and achieves low swing by
They simply direct switched-polarity currents into
using a reduced supply voltage. It is possible to
the transmission line [4], [5]. This is accomplished
replace the PMOS pull-up transistors with NMOS
by the use of a current source, a current sink, and
transistors as shown in Fig. 3b to take advantage of
two NMOS and PMOS switches in bridge
their much lower drive resistance [8]. The low
configuration to steer current of the correct polarity
common-mode output level of these level
to each output. A variation on this theme involves
converters, which is about half of the reduced
the use of all-NMOS switches [6]. The utility of an
supply voltage, has limited their use to on-chip
all-NMOS switch setup is limited, however,
signaling where the absolute ground reference
especially if mid-rail common-mode outputs are
voltage is approximately the same everywhere.
desired because this significantly reduce the
With an AC coupled receiver, however, it becomes
overdrive voltage available for the top switches.
possible to take advantage of the quadratic gains in
At very high frequencies, single termination at
energy savings offered by these level converters.
the load may fail to provide sufficient signal
integrity. In this case, signals reflected from the
load to the source are reflected back to the load. Vddl
Under this condition, source termination is often
included to minimize the second reflection and
thereby improve signal integrity at the cost of extra
power dissipation [4]. Source termination can be
Vout Vin
purely differential, in which case the termination
resistor is tied between the two output nodes. With Vin Vout
this, common-mode signals reflected back from the
load are still fully reflected at the source back to
the load with some being converted to differential
mode noise due to source impedance mismatches
that are often quite significant. A differential
termination that is center-tapped to a stable low-
impedance source as shown in Fig. 2 greatly (a)
minimizes this problem [5]. Vddl
Vdd
Vbias , p
Vin Vin

Vout Vout
Vout Vin
Vin Vout
Vcm

(b)

Figure 3 (a) Static driver with reduced supply

Vbias ,n voltage. (b) All-NMOS driver with reduced supply
voltage.

Figure 2 Current-mode driver with center-tapped

source termination.
C. DC-Coupled Receiver
I-R drops on PCB traces may cause the
absolute ground reference voltage of chips on the
same PCB to vary across the board. For this reason,
DC-coupled receivers must be able to accept a
range of common-mode input levels. For example,
a typical LVDS receiver shown in Fig. 4 consists
of a PMOS differential pair with an infinite
differential impedance load [9]. PMOS inputs are
chosen over NMOS input because of the need to
accept common-mode input voltages that can
approach zero specified by the standard. Yet this
circuit violates the LVDS standard because the
PMOS devices enter the triode region, and
consequently lose significant gain, for common-
mode input levels that approach zero.
An approach to increase the common-mode
input range is to combine the PMOS input
differential pair with an NMOS input differential
pair to form a rail-to-rail input stage, and sum the
currents in a later stage to produce either a fully
differential [10] or a single-ended output [5].
Because of the need to have bias currents in both
PMOS and NMOS input devices, this approach is
likely to consume twice the power of a single
polarity input stage. However, it may be possible to
employ an adaptive biasing scheme in which bias
currents are adjusted by a feedback loop depending
on the common-mode input voltage to minimize
current wastage. If rail-to-rail capability is not
mandatory, a folded-cascode input stage in which
the drains of the input devices are so biased such
that the devices remain in the forward active-region
during extreme input excursions can be employed
[6].
Vbias
Via
Vib
Figure 4 DC-coupled receiver with infinite
impedance load.
D. AC-Coupled Receiver
AC coupling allows for far greater common-
mode range that is limited, in the ideal case, only
by the breakdown voltage of the on-chip coupling
capacitors. This approach has been used to realize a
1.8V receiver, fully compatible with the LVDS
standard [11]. This design used a passive biasing
network to set the DC common-mode voltage of
the input devices, but left the AC common-mode
voltage to vary with the input. This is undesired
because high frequency noise may drive the input
devices beyond their allowed common-mode input
range.
Fig. 5 shows the simplified schematic of
another receiver of this type with an active
common-mode biasing circuit [12]. It comprises of
a common-mode rejection/stabilization circuit
followed by a latch with a restricted voltage swing.
Note that termination resistors have been omitted
in the diagram but are present in the actual circuit.
The common-mode rejection circuit consists of
NMOS and PMOS infinite differential impedance
loads connected in parallel. Analysis shows that the
common-mode circuit is effectively a parallel
connection of eight diode-connected MOSFETS,
resulting in very low common-mode impedance.
On the other hand, the differential half-circuit (top
or bottom half) is the parallel connection of two
diode-connected transistors to two cross-coupled
transistors, with the cross-coupled transistors
forming a negative impedance that cancels that of
the diode connected transistors, resulting in very
high differential-mode impedance. This connection
effectively rejects common-mode signals at all
frequencies while passing differential-mode
signals. Apart from acting as a latch, the latch
serves to limit the excursion of the differential
voltage between nodes n1+ and n1− . Without the
latch, the impedance between those nodes is
infinite, so that the voltage across them is
inherently unstable. The latch limits the maximum
differential voltage to a manageable value. The
coupling capacitors have capacitance on the order
of the gate capacitance and thus have a minimal
impact on the termination impedance.
The authors claim a DC common-mode input
range of ±690V for a BiCMOS implementation
that achieves 8 Gb/s operation. In practice,
however, this common-mode range cannot be fully
exploited due to the need to limit ESD stress on the
termination resistors with ESD protection diodes. It
has been observed that ESD stress on on-chip
 Vcc

P+ P−

+
Cin+ n1+ icmc icmc nd+
n in

nin−
n1− nd−
Cin− N+
icmc N−
icmc

GND

Figure 5 AC-coupled receiver with common-mode voltage stabilization circuit followed by a latch.

termination resistors leads to significant increase in

termination impedance deviation due to
temperature and process variation with consequent
impact on signal integrity [13]. To minimize this
effect, ESD protection diodes that limit the input
swing must be included and on-chip resistors must
be sized properly so that the ESD protection
devices absorb most of the ESD stress.
Despite this practical limitation, this circuit
approach has the advantage that it can be used with
a minimum supply voltage since there is no
common-mode signal, while a higher supply
voltage is mandatory for DC coupled receivers as
well as AC coupled receivers lacking adequate
high-frequency common-mode rejection. This
directly translates into energy savings over other
methods.
V. SUMMARY
Several interface circuits have been proposed
and implemented. The decision to use DC coupled
receivers compels the use of current mode drivers.
Additionally, the receiver must meet the common-
mode input specification and so requires a supply
voltage large enough to accommodate the
headroom needs of the input devices, given the
common-mode input range. Properly designed
capacitively-coupled receivers, on the other hand,
have less headroom needs and thus require less
supply voltage. This combined with further
reduction in signal swing using a reduced supply
driver has the potential to yield quadratic gains in
energy savings.

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IV. PROPOSED WORK
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