Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
ESIEE, Paris
September 1996
SPRA347
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Abstract
This paper describes the teaching of Digital Signal Processors
(DSP) through classical lectures and a practical case study where
students have to implant a real time simplified FSK modem on a
TMS320C50.
Product Support
Students level
This teaching is delivered to ESIEE (French Grande ecole)
students 4 years after baccalaureat, and more precisely to
students of the Digital Communications specialization. These
students have already received lectures in Digital Signal
Processing (130h) and in Digital Communications (50h). The
same approach could be used with slight modifications to
postgraduate or undergraduate students with electronic
background.
Lectures
During the 8 hours lectures, 3 topics are developed:
q The general principles of Digital Signal Processors
q Fixed and floating point arithmetic
q Description of the TMS320C50 processor
Laboratories
The laboratories are dedicated to the study and the development
of a simplified FSK modem on a fixed point DSP TMS320C50.
During the laboratories, the students work in teams of 2 or 3
persons and they are supervised by two lecturers.
Evaluation
The evaluation is done by averaging 2 marks: the mark of the
practical case study (report and demonstration) and the mark of a
2 hour long written examination.
Documentation
The given documentation includes the copy of the lectures slides,
the TMS320C50 user’s guide and the instructions for the
laboratory.
The bit rate Fb is generated using the timer of the C50. The period
register PRD of the timer is loaded with the value Tb/Tc -1
rounded to the closest integer. Here Tb is equal to 1/1200 s and
Tc=50 ns, so the value of PRD is equal to 16666.
The obtained bit rate is equal to 1199,976 Hz.
The xn output samples are sent to the digital to analog converter at
the sampling rate 1/Te. This sampling rate is given by the clock on
the serial port where the DAC is connected. At each interruption
XINT (transmit interrupt from the serial port), a new sample Xn
must be written to the DXR register (transmit register of the serial
port).
The first term is a function of k only, its does not depend on time
as long as n and n-k belongs to the same bit. The second term
should be eliminated by the low pass filter.
So, after the low pass filter, as long as n and n-k belongs to the
same bit, the filtered signal will correspond to the constant
cos(2πF0kTe) or to the constant cos(2πF1kTe) depending on the
value of the received bit.
To maximize the efficiency of the demodulator, k must be chosen
in order to maximise the difference d(k):
Matlab is used to construct the above function d(k) and to find its
maximum for k smaller than 8 (8 is the number of sample by bit).
The best values are k = 7, then k = 4.
The value k = 4 is used in the demodulator, because it allows
longer time intervals corresponding to n and n-k on the same bit
period.
The low pass filter is a simple IIR filter (order 3 is enough) with a
cutoff frequency around 1200 Hz (bit rate).
Figure 2. Data sequence, modulated signal, output of the product s(n)s(n-k) and
demodulated signal
Main program
saving context.
if bit=l, ∆i=k1
saving context.
transferring the memory word OLJTDEMOD in the register DXR,
to send the demodulated signal to the DAC.
restoring context, enabling interrupts.
Motivation of students